Electronic device and manufacturing method thereof

Abstract

The invention provides an electronic device which comprises a substrate, a first metal layer and a second metal layer. The first metal layer is arranged on the substrate and comprises a first edge and a second edge. The second metal layer is arranged on the first metal layer, and the first metal layer is located between the substrate and the second metal layer. The first edge is not overlapped with the second metal layer, the second edge is overlapped with the second metal layer, the side angle of the first edge is different from that of the second edge, and the side angle of the second edge is larger than or equal to 30 degrees and smaller than or equal to 45 degrees. The invention also provides a manufacturing method of the electronic device.

Description

Technical Field

[0001] The present disclosure relates to an electronic device and a manufacturing method thereof, and in particular to a display device and a manufacturing method thereof. Background Art

[0002] Electronic devices including display panels, such as tablet computers, notebook computers, smartphones, monitors and TVs, have become an indispensable necessity in modern society. With the booming development of such portable electronic products, consumers have high expectations for the quality, functions or prices of these products.

[0003] However, these electronic devices still do not meet expectations in all aspects. For example, as the resolution increases and the pixel area decreases, how to improve the display quality and process yield is still one of the topics that the industry is currently working on. Summary of the invention

[0004] According to some embodiments of the present disclosure, an electronic device is provided, comprising a substrate, a first metal layer, and a second metal layer. The first metal layer is disposed on the substrate, and the first metal layer comprises a first edge and a second edge. The second metal layer is disposed on the first metal layer, and the first metal layer is located between the substrate and the second metal layer. The first edge does not overlap with the second metal layer, the second edge overlaps with the second metal layer, the side angle of the first edge is different from the side angle of the second edge, and the side angle of the second edge is greater than or equal to 30 degrees and less than or equal to 45 degrees.

[0005] According to some embodiments of the present disclosure, a method for manufacturing an electronic device is provided, comprising the following steps: providing a substrate; forming a first metal layer on the substrate, the first metal layer comprising a first edge and a second edge; performing a patterning process on the first metal layer; and forming a second metal layer on the first metal layer. The exposure dose of the patterning process in the area corresponding to the first edge is different from the exposure dose of the area corresponding to the second edge, so that the first metal layer has different profiles at the first edge and the second edge. The first edge does not overlap with the second metal layer, the second edge overlaps with the second metal layer, the side angle of the first edge is different from the side angle of the second edge, and the side angle of the second edge is greater than or equal to 30 degrees and less than or equal to 45 degrees.

[0006] In order to make the features and advantages of the present disclosure more obvious and understandable, some embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 Showing a schematic diagram of a top view structure of an electronic device according to some embodiments of the present disclosure;

[0008] Figure 2AShows a partial top view structural diagram of an electronic device according to some embodiments of the present disclosure;

[0009] Figure 2B Shows a partial top view structural diagram of an electronic device according to some embodiments of the present disclosure;

[0010] Figure 3A A schematic cross-sectional structure diagram of an electronic device corresponding to the section line AA' in FIG. 2 according to some embodiments of the present disclosure is shown;

[0011] Figure 3B A schematic cross-sectional structure diagram of an electronic device corresponding to the section line BB' in FIG. 2 according to some embodiments of the present disclosure;

[0012] FIG. 4A to FIG. 4G A schematic diagram showing a cross-sectional structure of an electronic device at an intermediate stage of a manufacturing process according to some embodiments of the present disclosure;

[0013] FIG. 5A to FIG. 5C A schematic diagram showing a cross-sectional structure of an electronic device at an intermediate stage of a manufacturing process according to some embodiments of the present disclosure;

[0014] FIG. 6A to FIG. 6C A schematic diagram of a cross-sectional structure of an electronic device at an intermediate stage of a manufacturing process according to some embodiments of the present disclosure is shown.

[0015]

Explanation of symbols

[0016] 10: Electronic devices

[0017] 102:Substrate

[0018] 104: Insulation layer

[0019] 110: Photoresist layer

[0020] 110a: Partial

[0021] 110b: Partial

[0022] 110bs: side surface

[0023] 112: Shield

[0024] 210: First metal layer

[0025] 210b: bottom surface

[0026] 210t: Top surface

[0027] 210s: side surface

[0028] 220: Second metal layer

[0029] 230: Electrode layer

[0030] A-A': Intersection

[0031] B-B': Intersection

[0032] d1, d1': first distance

[0033] d2: second distance

[0034] d3, d3': third distance

[0035] d4, d4': the fourth distance

[0036] E1: First Edge

[0037] E2: Second Edge

[0038] L1: First exposure step

[0039] L2: Second exposure step

[0040] P1: Area

[0041] P2: Area

[0042] W1: Bottom surface width

[0043] W2: Top surface width

[0044] θ1: side angle

[0045] θ2: side angle DETAILED DESCRIPTION

[0046] The following is a detailed description of the electronic device and its manufacturing method according to the embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only used as examples and are not limitations of the present disclosure. In addition, similar and / or corresponding numbers may be used in different embodiments to indicate similar and / or corresponding components to clearly describe the present disclosure. However, the use of these similar and / or corresponding numbers is only for the purpose of simply and clearly describing some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and / or structures discussed.

[0047] It should be understood that relative terms, such as "lower" or "bottom" or "upper" or "top", may be used in the embodiments to describe the relative relationship of one component to another component in the drawings. It is understood that if the device in the drawings is turned upside down, the component described on the "lower" side will become the component on the "upper" side. The embodiments of the present disclosure may be used in conjunction with the attached drawings. Figure 1It is also understood that the drawings of the present disclosure are also considered as part of the disclosure. It should be understood that the drawings of the present disclosure are not drawn to scale, and in fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0048] Furthermore, when a first material layer is mentioned as being located on or above a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0049] In addition, it should be understood that the ordinal numbers used in the specification and claims, such as "first", "second", etc., to modify components, do not imply or represent any previous ordinal numbers of the component (or components), nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The same words may not be used in the claims and the specification. For example, the first component in the specification may be the second component in the claims.

[0050] In some embodiments of the present disclosure, terms such as "connection", "interconnection", etc., related to bonding and connection, unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein another structure is disposed between the two structures. Such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection means.

[0051] In the text, the terms "about" and "substantially" usually mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The terms "a range is greater than or equal to a first value and less than or equal to a second value" or "a range is between a first value and a second value" mean that the range includes the first value, the second value, and other values ​​therebetween.

[0052] It should be understood that the following embodiments may replace, reorganize, or combine features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment may be used in any combination as long as they do not violate the spirit of the invention or conflict with each other.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0054] According to an embodiment of the present disclosure, an electronic device is provided, which includes a metal layer with different profiles in specific areas. Specifically, for example, the same metal layer can have different side angles in different areas, such as a smaller side angle at the overlap with another metal layer, thereby reducing the problem of electrostatic discharge (ESD) between metal layers and damaging the circuit structure or further improving the quality of displayed images. Furthermore, according to an embodiment of the present disclosure, a method for manufacturing the aforementioned electronic device is also provided, which can make the same metal layer have different profiles in different areas without increasing the number of shielding or the number of deposition and etching steps.

[0055] According to an embodiment of the present disclosure, the electronic device may include a display device, an antenna device, a light-emitting device, a sensing device, a splicing device, a touch-sensitive electronic device, a curved electronic device, or a non-rectangular electronic device, but is not limited thereto. The electronic device may, for example, include a liquid crystal, a light-emitting diode, a quantum dot (QD), fluorescence, phosphorescence, other suitable display media, or a combination of the foregoing, but is not limited thereto. The display device may be a non-self-luminous display device or a self-luminous display device. The electronic device may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode (LED) or a photodiode. The light-emitting diode may, for example, include an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device, and the sensing device may be a sensing device for sensing capacitance, light, heat or ultrasound, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the foregoing, but is not limited thereto. In addition, the electronic device may be a bendable or flexible electronic device. In addition, the appearance of the electronic device may be a rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device may have a peripheral system such as a drive system, a control system, a light source system, etc. to support a display device, an antenna device, a wearable device (for example, including an augmented reality (AR) or a virtual reality (VR) device), a vehicle-mounted device (for example, including a car windshield) or a splicing device. For the convenience of description, the following description will be based on the state of the electronic device as a display device, but the present disclosure is not limited thereto.

[0056] Please refer to Figure 1 , Figure 2A as well as Figure 2B , Figure 1 A schematic diagram of the structure of an electronic device 10 viewed from above is shown according to some embodiments of the present disclosure. Figure 2A as well as Figure 2B According to some embodiments of the present disclosure, Figure 1FIG. 1 is a schematic diagram of a partial top view of the structure of the electronic device 10 in the area A1 of FIG. 1 . It should be understood that for the sake of clarity, some components of the electronic device 10 are omitted in the figure, and only some components are schematically shown. Specifically, Figure 2A Only the substrate 102 and the first metal layer 210 of the electronic device 10 are shown. Figure 2B Only the substrate 102, the first metal layer 210, the second metal layer 220, and the electrode layer 230 of the electronic device 10 are shown. According to some embodiments, additional features may be added to the electronic device 10 described below.

[0057] like Figure 2A as well as Figure 2B As shown, the electronic device 10 may include a substrate 102, a first metal layer 210 and a second metal layer 220. The first metal layer 210 and the second metal layer 220 may be disposed on the substrate 102, the second metal layer 220 may be disposed on the first metal layer 210, and the first metal layer 210 may be located between the substrate 102 and the second metal layer 220.

[0058] According to some embodiments, the substrate 102 may be used as a driving substrate, and the electronic device 10 may include a driving circuit disposed on the substrate 102. The substrate 102 may include a rigid substrate or a flexible substrate. According to some embodiments, the material of the substrate 102 may include glass, quartz, sapphire, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), polydimethylsiloxane (PDMS), other suitable materials or a combination of the foregoing, but not limited thereto. According to some embodiments, the substrate 102 may include a flexible printed circuit (FPC). Furthermore, the driving circuit may include an active driving circuit and / or a passive driving circuit. According to some embodiments, the driving circuit may include a thin film transistor (TFT) (e.g., a switch transistor, a driving transistor, a reset transistor, or other thin film transistors), a data line, a scan line, a common electrode line, a touch signal line, a conductive pad, a dielectric layer, a capacitor or other lines, etc., but not limited thereto. In addition, the thin film transistor may be a top gate thin film transistor, a bottom gate thin film transistor, or a dual gate or double gate thin film transistor. According to some embodiments, the thin film transistor includes at least one semiconductor layer, and the semiconductor layer includes but is not limited to amorphous silicon, low-temp polysilicon (LTPS), metal oxide, other suitable materials or a combination of the foregoing, but not limited thereto. The metal oxide may include indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc tin oxide (IGZTO), other suitable materials or a combination of the foregoing, but not limited thereto.

[0059] According to some embodiments, the first metal layer 210 can be used as a shared electrode line, a scan line, a shading component, etc. In one embodiment, a relatively small side angle corresponds to a scan line. In one embodiment, a relatively large side angle corresponds to a shared electrode line and a shading component, but is not limited thereto. The shading component is, for example, a floating bar, but is not limited thereto. According to some embodiments, the material of the first metal layer 210 may include copper (Cu), silver (Ag), gold (Au), tin (Sn), aluminum (Al), molybdenum (Mo), tungsten (W), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), palladium (Pd), iridium (Ir), rhodium (Rh), alloys of the foregoing metals, other suitable metal conductive materials, or combinations of the foregoing, but are not limited thereto.

[0060] According to some embodiments, the second metal layer 220 may be used as a data line, but is not limited thereto. In the normal direction of the substrate 102 (e.g., the Z direction in the drawings), the second metal layer 220 may partially overlap with the first metal layer 210. According to some embodiments, the data lines and the scan lines may be interlaced with each other to define a plurality of pixel units (not shown). According to some embodiments, the material of the second metal layer 220 may include copper (Cu), silver (Ag), gold (Au), tin (Sn), aluminum (Al), molybdenum (Mo), tungsten (W), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), palladium (Pd), iridium (Ir), rhodium (Rh), alloys of the aforementioned metals, other suitable metal conductive materials, or combinations thereof, but are not limited thereto. Furthermore, the material of the second metal layer 220 may be the same as or different from that of the first metal layer 210.

[0061] Furthermore, the electronic device 10 may further include an electrode layer 230, and the electrode layer 230 may be disposed on the substrate 102, and the electrode layer 230 may be disposed on the first metal layer 210 and the second metal layer 220. In the normal direction of the substrate 102 (for example, the Z direction in the drawings), the electrode layer 230 may partially overlap with the first metal layer 210 and the second metal layer 220. According to some embodiments, the electrode layer 230 may be used as a pixel electrode, but is not limited thereto. According to some embodiments, the material of the electrode layer 230 may include a transparent conductive oxide (TCO), for example, may include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials or combinations thereof, but not limited thereto.

[0062] Next, please refer to Figure 2B , Figure 3A as well as Figure 3B , Figure 3A According to some embodiments of the present disclosure, corresponding to Figure 2B The cross-sectional structure diagram of the electronic device 10 is shown along the section line AA' in FIG. Figure 3B According to some embodiments of the present disclosure, corresponding to Figure 2B Schematic diagram of the cross-sectional structure of the electronic device 10 taken along the section line BB′ in FIG.

[0063] like Figure 3A as well as Figure 3B As shown, the electronic device 10 may further include an insulating layer 104, and the insulating layer 104 may be disposed on the first metal layer 210, and may be disposed between the first metal layer 210 and the second metal layer 220. According to some embodiments, the material of the insulating layer 104 may include silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), other suitable insulating materials, or a combination thereof, but is not limited thereto.

[0064] like Figure 2B As shown, the first metal layer 210 has an area P1 that does not substantially overlap with the second metal layer 220 and an area P2 that substantially overlaps with the second metal layer 220. Furthermore, the first metal layer 210 includes a first edge E1 and a second edge E2, the first edge E1 is located in the area P1, and the second edge E2 is located in the area P2. In other words, the first edge E1 does not overlap with the second metal layer 220, and the second edge E2 overlaps with the second metal layer 220. In addition, according to some embodiments, the area P2 where the first metal layer 210 and the second metal layer 220 overlap may be, for example, a scan line, and the area P1 where the first metal layer 210 does not overlap with the second metal layer 220 may be, for example, a shared electrode line. In some embodiments, the edge may be, for example, a boundary of each layer, or an area intersecting with or contacting other interfaces or other layers, but is not limited thereto. In some embodiments, the non-overlapping may mean, for example, that the projections of the first metal layer 210 and the second metal layer 220 do not overlap in the Z direction, or that there is a distance between the first metal layer 210 and the second metal layer 220 in the X or Y direction.

[0065] Furthermore, if Figure 3A as well as Figure 3B As shown, the side angle θ1 of the first edge E1 is different from the side angle θ2 of the second edge E2, and the side angle θ2 of the second edge E2 is greater than or equal to 30 degrees and less than or equal to 45 degrees (that is, 30 degrees ≤ side angle θ2 ≤ 45 degrees), or greater than or equal to 35 degrees and less than or equal to 40 degrees. According to some embodiments, the side angle θ1 of the first edge E1 is greater than the side angle θ2 of the second edge E2 (that is, side angle θ1>side angle θ2). According to some embodiments, the side angle θ1 of the first edge E1 is greater than or equal to 45 degrees and less than or equal to 75 degrees (that is, 45 degrees ≤ side angle θ1 ≤ 75 degrees), or greater than or equal to 50 degrees and less than or equal to 70 degrees, for example, 55 degrees, 60 degrees or 65 degrees, but not limited thereto.

[0066] As mentioned above, according to some embodiments, the side angle θ1 of the first edge E1 that does not overlap with the second metal layer 220 is greater than the side angle θ2 of the second edge E2 that overlaps with the second metal layer 220. For example, the first metal layer 210 has a larger side angle θ1 (relatively steep side profile) at the scanning line and a smaller side angle θ2 (relatively gentle side profile) at the shared electrode line. In particular, the above configuration can meet the electrical requirements of the first metal layer 210 in different regions. For example, the resistance value of the region of the first metal layer 210 corresponding to the first edge E1 can be smaller than the resistance value of the region corresponding to the second edge E2. In detail, since the side angle θ1 is larger at the shared electrode line, it can have a larger cross-sectional area or volume, thereby reducing the resistance value; further, since the side angle θ2 is smaller at the scanning line, it has a gentler side profile, thereby reducing the tip discharge caused by the smaller angle at the overlap or intersection of the first metal layer 210 and the second metal layer 220, thereby reducing the problem of electrostatic breakdown or damage to the circuit structure.

[0067] In addition, according to some embodiments, the first metal layer 210 also has a smaller side angle (not shown, the side profile is relatively gentle) in the area where it serves as a light shielding component or is adjacent to the electrode layer 230. In this way, the influence of the first metal layer 210 on the arrangement of the display medium (e.g., liquid crystal molecules) can be reduced, thereby improving the problem of uneven brightness (mura) of the displayed image. Furthermore, since the first metal layer 210 is less prone to electrostatic discharge when serving as a light shielding component, it can be regarded as having a second edge E2 (not shown).

[0068] Furthermore, the aforementioned side angle refers to the angle between the bottom surface 210 b and the side surface 210 s of the first metal layer 210 in the cross-sectional view.

[0069] It should be understood that according to the embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable methods may be used to measure the distance, spacing, angle between components, or the width or thickness of each component. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional image of a structure and measure the distance, spacing, angle between components, or the width or thickness of each component.

[0070] In addition, according to some embodiments, the side surface 210s of the first metal layer 210 has an arc-shaped profile (for example, the first metal layer 210 may have an arc-shaped top angle). In other words, the side surface 210s and the top surface 210t of the first metal layer 210 may not have a sharp angle, or the side surface 210s and the top surface 210t of the first metal layer 210 have a curvature at the junction. It is worth noting that this configuration can also reduce the risk of tip discharge in the first metal layer 210, thereby reducing the problem of electrostatic breakdown or damage to the circuit structure.

[0071] Next, please refer to FIG. 4A to FIG. 4G , FIG. 4A to FIG. 4G A schematic diagram of a cross-sectional structure of an electronic device at an intermediate stage of a manufacturing process is shown according to some embodiments of the present disclosure. It should be understood that, for the sake of clarity, some components of the electronic device are omitted in the accompanying drawings, and only some components are schematically shown. According to some embodiments, additional operating steps may be provided before, during and / or after the manufacturing method of the electronic device. According to some embodiments, some of the operating steps may be replaced or omitted, and the order of some of the operating steps may be interchangeable.

[0072] Specifically, FIG. 4A to FIG. 4G The patterning process of the first metal layer 210 is shown, and in particular, the photolithography process in the patterning process. According to some embodiments, the photolithography process may include photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying, etc., which will be described in detail below.

[0073] First, please refer to Figure 4A , a substrate 102 is provided, and a first metal layer 210 is formed on the substrate 102. Then, a patterning process is performed on the first metal layer 210. In detail, a photoresist layer 110 may be formed on the first metal layer 210, and a mask 112 may be formed on the photoresist layer 110 to define a pattern of the photoresist layer 110, for example, the mask 112 is used to shield a portion of the photoresist layer 110 to be removed. According to some embodiments, the patterning process uses an image reversal resist as the photoresist layer 110. Then, a first exposure step L1 may be performed on the photoresist layer 110.

[0074] According to some embodiments, the first metal layer 210 may be formed by a physical vapor deposition (PVD) process, an electroplating process, an electroless plating process, other suitable methods, or a combination thereof.

[0075] Please refer to Figure 4B, the mask 112 is removed, and the first exposure step L1 can transform the portion 110b of the photoresist layer 110 not blocked by the mask 112 (i.e., the exposed portion) into a soluble one, while the portion 110a of the photoresist layer 110 blocked by the mask 112 (i.e., the unexposed portion) is insoluble.

[0076] Next, please refer to Figure 4C The photoresist layer 110 may be subjected to a reversal bake so that a portion 110b of the photoresist layer 110 undergoes a cross-link reaction (the portion 110b after the cross-linking reaction is represented by dots in the figure) and becomes inert, while the unexposed portion 110a is still photoactive.

[0077] Next, please refer to Figure 4D A second exposure step L2 may be performed on the portion 110a and the portion 110b of the photoresist layer 110. The second exposure step L2 may be a flood exposure, that is, in the second exposure step L2, no mask is used.

[0078] Please refer to Figure 4E The second exposure step L2 can transform the portion 110a of the photoresist layer 110 (the portion not exposed in the first exposure step L1) into a soluble one, while the portion 110b of the photoresist layer 110 (the portion exposed in the first exposure step L1) remains insoluble. Then, steps such as development, cleaning, and drying can be performed to remove the portion 110a of the photoresist layer 110.

[0079] like Figure 4F as well as Figure 4G As shown, after the steps of developing, cleaning and drying, a portion 110b of the photoresist layer 110 (the portion exposed in the first exposure step L1) remains on the first metal layer 210, and the remaining portion 110b of the photoresist layer 110 can be used to perform an etching step on the first metal layer 210 (to be FIG. 5A to FIG. 5C and FIG. 6A to FIG. 6C part of the description).

[0080] It is worth noting that Figure 4F as well as Figure 4G The remaining portion 110b of the photoresist layer 110 in different embodiments is shown. According to some embodiments, the developed photoresist can have different states by adjusting the intensity of exposure. In detail, the profile of the remaining portion 110b of the photoresist layer 110 can be controlled by adjusting the exposure dose (e.g., adjusting the intensity or time) of the first exposure step L1. Figure 4FAs shown, the lower exposure dose makes the adhesion between the photoresist and the first metal layer 210 lower, so that the portion 110b of the photoresist layer 110 having a bottom surface width W1 smaller than the top surface width W2 can be obtained. Figure 4G As shown, a higher exposure dose can obtain a portion 110b of the photoresist layer 110 having a bottom surface width W1 substantially the same as a top surface width W2. According to some embodiments, the patterning process can use the same mask to simultaneously form portions 110b of the photoresist layer 110 having different profiles. According to some embodiments, a halftone mask or a gray tone mask can be used to allow the photoresist layer 110 to have different exposure doses in different regions.

[0081] Next, please refer to FIG. 5A to FIG. 5C , FIG. 5A to FIG. 5C The cross-sectional structure diagram of the electronic device at the intermediate stage of the manufacturing process according to some embodiments of the present disclosure is shown. It should be understood that for the sake of clarity, some components of the electronic device are omitted in the drawings, and only some components are schematically shown.

[0082] Specifically, FIG. 5A to FIG. 5C Display continuation Figure 4G The patterning process of the first metal layer 210 is performed, and in particular, the etching process in the patterning process. According to some embodiments, the patterning process uses a wet etching step. Figure 5A As shown, a portion 110b of the photoresist layer 110 whose bottom surface width W1 is substantially the same as the top surface width W2 is disposed on the first metal layer 210, and then a wet etching step is performed on the first metal layer 210. Figure 5B As shown, due to the isotropic etching characteristics of the wet etching step and the flow field effect, the side surface 210s of the first metal layer 210 can be recessed inward, for example, a first distance d1 is formed between the top surface 210t of the first metal layer 210 and the side surface 110bs of the portion 110b of the photoresist layer 110. Figure 5C As shown, as the wet etching step proceeds, the side surface 210s of the first metal layer 210 continues to be recessed inward, for example, so that the first distance d1 increases to the first distance d1', and also so that the bottom surface 210b of the first metal layer 210 and the side surface 110bs of the portion 110b of the photoresist layer have a second distance d2. According to some embodiments, the first distance d1' is greater than the first distance d1, and the first distance d1' is greater than the second distance d2. Furthermore, the side surface 210s of the first metal layer 210 and the bottom surface 210b have a relatively large side angle θ1.

[0083] Furthermore, the first distance d1 and the first distance d1′ refer to the maximum distance between the top surface 210t of the first metal layer 210 and the side surface 110bs of the portion 110b of the photoresist layer 110 in a direction perpendicular to the normal direction of the substrate 102 (e.g., the X direction in the drawings). The second distance d2 refers to the maximum distance between the bottom surface 210b of the first metal layer 210 and the side surface 110bs of the portion 110b of the photoresist layer 110 in a direction perpendicular to the normal direction of the substrate 102 (e.g., the X direction in the drawings).

[0084] Next, please refer to FIG. 6A to FIG. 6C , FIG. 6A to FIG. 6C The cross-sectional structure diagram of the electronic device at the intermediate stage of the manufacturing process according to some embodiments of the present disclosure is shown. It should be understood that for the sake of clarity, some components of the electronic device are omitted in the drawings, and only some components are schematically shown.

[0085] Specifically, FIG. 6A to FIG. 6C Display continuation Figure 4G The patterning process of the first metal layer 210 is performed, and in particular, the etching process in the patterning process. According to some embodiments, the patterning process uses a wet etching step. Fig. 6A As shown, a portion 110b of the photoresist layer 110 whose bottom surface width W1 is smaller than the top surface width W2 is disposed on the first metal layer 210, and then a wet etching step is performed on the first metal layer 210. Figure 6B As shown, due to the isotropic etching characteristics of the wet etching step and the flow field effect, the side surface 210s of the first metal layer 210 can be recessed inward, for example, a third distance d3 is provided between the top surface 210t of the first metal layer 210 and the side surface 110bs of the portion 110b of the photoresist layer 110, and a fourth distance d4 is provided between the bottom surface 210b of the first metal layer 210 and the side surface 110bs of the portion 110b of the photoresist layer. Figure 6C As shown, as the wet etching step proceeds, the side surface 210s of the first metal layer 210 continues to be recessed inward, for example, so that the third distance d3 increases to the third distance d3', and the fourth distance d4 also increases to the fourth distance d4'. According to some embodiments, the third distance d3' is greater than the third distance d3, the fourth distance d4' is greater than the fourth distance d4, and the third distance d3' is greater than the fourth distance d4'. Furthermore, the side surface 210s of the first metal layer 210 has a relatively small side angle θ2 with the bottom surface 210b.

[0086] Furthermore, the third distance d3 and the third distance d3′ refer to the maximum distance between the top surface 210t of the first metal layer 210 and the side surface 110bs of the portion 110b of the photoresist layer 110 in a direction perpendicular to the normal direction of the substrate 102 (e.g., the X direction in the drawings). The fourth distance d4 and the fourth distance d4′ refer to the maximum distance between the bottom surface 210b of the first metal layer 210 and the side surface 110bs of the portion 110b of the photoresist layer 110 in a direction perpendicular to the normal direction of the substrate 102 (e.g., the X direction in the drawings).

[0087] Based on the above, according to the embodiments of the present disclosure, the first metal layer 210 can have different profiles in different areas without increasing the number of masks or the number of deposition and etching steps. Figure 2B , the exposure dose of the aforementioned patterning process in the region P1 corresponding to the first edge E1 of the first metal layer 210 is different from the exposure dose of the region P2 corresponding to the second edge E2 of the first metal layer 210, so that the first metal layer 210 has different profiles at the first edge E1 and the second edge E2. Figure 4G as well as FIG. 5A to FIG. 5C ) may be greater than the exposure dose of the region P2 corresponding to the second edge E2 (as shown Figure 4F as well as FIG. 6A to FIG. 6C As shown), the side angle θ1 of the first edge E1 is greater than the side angle θ2 of the second edge E2. However, according to the characteristics of the photoresist material, according to some embodiments, the exposure dose of the area P1 corresponding to the first edge E1 may be less than the exposure dose of the area P2 corresponding to the second edge E2. As mentioned above, according to some embodiments, the side angle θ1 of the first edge E1 is greater than or equal to 45 degrees and less than or equal to 75 degrees (that is, 45 degrees ≤ side angle θ1 ≤ 75 degrees), or greater than or equal to 50 degrees and less than or equal to 70 degrees, for example, 55 degrees, 60 degrees or 65 degrees, but not limited thereto. According to some embodiments, the side angle θ2 of the second edge E2 is greater than or equal to 30 degrees and less than or equal to 45 degrees (that is, 30 degrees ≤ side angle θ2 ≤ 45 degrees), or greater than or equal to 35 degrees and less than or equal to 40 degrees.

[0088] According to some embodiments, different etching solutions may be selected in the wet etching steps corresponding to different areas to assist in forming different side angles. For example, an etching solution containing an etching inhibitor may be used at the first edge E1 that does not overlap with the second metal layer 220, while no etching inhibitor is added at the second edge E2 that overlaps with the second metal layer 220.

[0089] In addition, according to some embodiments, the second metal layer 220 may be formed on the first metal layer 210 after the patterning process of the first metal layer 210. According to some embodiments, the insulating layer 104 may be formed on the first metal layer 210 before the second metal layer 220 is formed, so that the insulating layer 104 is disposed between the first metal layer 210 and the second metal layer 220. In some embodiments, the material of the insulating layer 104 may include, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), epoxy resin, acrylic, bismaleimide, polyimide, or a combination thereof, but is not limited thereto.

[0090] According to some embodiments, the insulating layer 104 may be formed on the first metal layer 210 by a chemical vapor deposition process, a physical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof. Furthermore, the second metal layer 220 may be formed on the insulating layer 104 by a physical vapor deposition (PVD) process, an electroplating process, an electroless plating process, other suitable methods, or a combination thereof.

[0091] In summary, according to an embodiment of the present disclosure, the provided electronic device includes a metal layer with different profiles in specific areas. Specifically, different areas of the same metal layer (for example, scan lines, shared electrode lines, shading components, etc.) may have different side angles, so that the same metal layer in different areas can have appropriate electrical requirements according to different functions. In this way, the problem of electrostatic discharge (ESD) between metal layers damaging the circuit structure can be reduced or the quality of the displayed image can be further improved. Furthermore, according to an embodiment of the present disclosure, the provided method for manufacturing an electronic device can allow the same metal layer to have different profiles in different areas without increasing the number of shielding or the number of deposition and etching steps.

[0092] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. The features between the embodiments of the present disclosure can be mixed and matched as needed as long as they do not violate the spirit of the invention or conflict with each other. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. The scope of protection of the present disclosure shall be subject to the scope of the appended claims. Any embodiment or claim of the present disclosure does not need to achieve all the purposes, advantages and features disclosed in this disclosure.

Claims

1. An electronic device, characterized in that: include: a substrate; A first metal layer is disposed on the substrate, and the first metal layer includes a first edge and a second edge; as well as a second metal layer disposed on the first metal layer, wherein the first metal layer is located between the substrate and the second metal layer; The first edge does not overlap with the second metal layer, the second edge overlaps with the second metal layer, a side angle of the first edge is different from a side angle of the second edge, and the side angle of the second edge is greater than or equal to 30 degrees and less than or equal to 45 degrees.

2. The electronic device according to claim 1, wherein: The side angle of the first edge is greater than the side angle of the second edge.

3. The electronic device according to claim 1, wherein: The side angle of the first edge is greater than or equal to 45 degrees and less than or equal to 75 degrees.

4. The electronic device according to claim 1, wherein: The side surface of the first metal layer has an arc-shaped profile.

5. The electronic device according to claim 1, wherein: The first edge is located in a region of the first metal layer serving as a scan line.

6. The electronic device as claimed in claim 1, wherein: The second edge is located in a region of the first metal layer serving as a shared electrode line.

7. The electronic device as claimed in claim 1, characterized in that: The invention further comprises an insulating layer disposed between the first metal layer and the second metal layer.

8. The electronic device as claimed in claim 1, wherein: The resistance value of the area of ​​the first metal layer corresponding to the first edge is smaller than the resistance value of the area of ​​the first metal layer corresponding to the second edge.

9. A method for manufacturing an electronic device, characterized in that: include: providing a substrate; Forming a first metal layer on the substrate, the first metal layer comprising a first edge and a second edge; Performing a patterning process on the first metal layer; as well as forming a second metal layer on the first metal layer; The exposure dose of the patterning process in the area corresponding to the first edge is different from the exposure dose in the area corresponding to the second edge, so that the first metal layer has different profiles at the first edge and the second edge, wherein the first edge does not overlap with the second metal layer, the second edge overlaps with the second metal layer, a side angle of the first edge is different from a side angle of the second edge, and the side angle of the second edge is greater than or equal to 30 degrees and less than or equal to 45 degrees.

10. The method for manufacturing an electronic device according to claim 9, wherein: The patterning process uses the same mask.

11. The method for manufacturing an electronic device according to claim 9, wherein: The exposure dose of the area corresponding to the first edge is greater than the exposure dose of the area corresponding to the second edge.

12. The method for manufacturing an electronic device according to claim 9, wherein: The patterning process uses an image reversal resist.

13. The method for manufacturing an electronic device according to claim 9, wherein: The patterning process uses a wet etching step.

14. The method for manufacturing an electronic device according to claim 9, wherein: The side angle of the first edge is greater than the side angle of the second edge.

15. The method for manufacturing an electronic device according to claim 9, wherein: The side angle of the first edge is greater than or equal to 45 degrees and less than or equal to 75 degrees.

16. The method for manufacturing an electronic device according to claim 9, wherein: The first edge is located in a region of the first metal layer serving as a scan line.

17. The method for manufacturing an electronic device according to claim 9, wherein: The second edge is located in a region of the first metal layer serving as a shared electrode line.

18. The method for manufacturing an electronic device according to claim 9, wherein: The method further includes forming an insulating layer on the first metal layer, wherein the insulating layer is disposed between the first metal layer and the second metal layer.

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