Method for producing a silicon layer system having an electrical connection

Abstract

A method for manufacturing a silicon layer system (310) comprises the following steps: providing a carrier substrate having a surface, the carrier substrate being provided with an insulating layer formed on the surface; applying a first silicon layer on the insulating layer; structuring the first silicon layer for forming a trench in the first silicon layer, the trench extending at least partially through the first silicon layer; passivating the first silicon layer wherein the trench is filled, and forming a first passivation layer on a side of the first silicon layer facing away from the insulating layer; the first passivation layer is structured, a first sacrificial region and a functional region are formed in the first silicon layer, and the first sacrificial region is at least partially free of the first passivation layer on a side of the first silicon layer facing away from the insulating layer. Repeating these steps from the application, thereby forming sacrificial regions and functional regions in the further silicon layer; and removing all the sacrificial regions. Said steps are carried out in such a way that an electrical connection (390) is formed, which comprises at least one dedicated functional region, by means of which an electrical connection can be established between the two elements (380), said at least one dedicated functional region being exclusively used for the electrical connection (390).

Description

Technical Field

[0001] The present application relates to the field of silicon layer systems and to a method for producing a silicon layer system having an electrical connection. The present application also relates to a silicon layer system and a microelectromechanical device having such a silicon layer system. Background Art

[0002] DE 10 2015 206 996 A1 discloses the so-called EPyC process (EPyC: Epitaxial Polysilicon Cycle) for producing microelectromechanical structures of large vertical dimensions, which uses epitaxial polysilicon as functional and sacrificial material and builds up a layer structure of epitaxial polysilicon layers by repeated cycles. Documents US2014 / 0117469 A1 and US2018 / 0111823 A1 relate to the combination of MEMS (microelectromechanical system) and TSV (TSV: through-silicon via). Summary of the invention

[0003] According to the application, a method for producing a silicon layer system having an electrical connection, a corresponding silicon layer system and a microelectromechanical device having such a silicon layer system are proposed.

[0004] According to a first aspect of the present application, a method for producing a silicon layer system with electrical connections is provided, which silicon layer system can, for example, include structures for a microelectromechanical device such as MEMS. In this case, the method includes providing a carrier substrate, which can, for example, consist essentially of silicon. An insulating layer is formed on the surface of the carrier substrate, wherein the insulating layer itself is not part of the carrier substrate. This insulating layer serves for electrical and mechanical insulation between the substrate and the silicon layer of the following first EPyC cycle.

[0005] The insulating layer is preferably a silicon oxide layer and / or a silicon nitride layer. The insulating layer is preferably used as an etching stop layer for the subsequent etching of the silicon sacrificial layer. By using such an etching stop layer, a time-dependent etching process that is time-consuming and highly fluctuating can be eliminated. The insulating layer can be structured and / or can be structured before the subsequent steps are carried out, in particular in order to establish an electrical connection through the insulating layer.

[0006] A first silicon layer is applied to the insulating layer, for example by bonding, sputtering and / or preferably by growth, in particular epitaxial growth. In this case, epitaxial growth is carried out in particular at a temperature generally greater than 600° C., preferably greater than 900° C. The structuring of the insulating layer can be carried out before applying the first silicon layer and / or after removing the carrier substrate (i.e. from the reverse side). The applied first silicon layer can, for example, include or be, for example, a monocrystalline silicon layer, a polycrystalline silicon layer and / or an epitaxial polycrystalline silicon layer. In this case, a polycrystalline silicon layer that has been epitaxially grown, i.e. epitaxially grown under epitaxial growth conditions, is referred to as an epitaxial polycrystalline silicon layer. Such an epitaxial polycrystalline silicon layer usually has a thickness of more than 5 micrometers, usually several tens of micrometers.

[0007] Epitaxial growth on an insulating layer (e.g., a silicon oxide layer) can include the prior application of a polysilicon start layer on the insulating layer, which is performed, for example, by CVD polysilicon deposition (CVD: chemical vapor deposition), because polysilicon (polycrystalline silicon) cannot usually be grown epitaxially directly on the insulating layer. This also applies to the passivation layer discussed below. The areas not covered by the insulating layer or the passivation layer can be filled by CVD polysilicon deposition, thereby establishing electrical contact with the silicon layer to be grown subsequently. That is, a wiring layer is formed. However, direct epitaxy without a polysilicon start layer can also be achieved by selecting a process control method that automatically forms crystallization nuclei. In the context of the present application, the term "epitaxial growth" refers to two possible variants, namely indirect epitaxial growth with the use of a start layer that is to be at least partially applied in advance and direct epitaxial growth without a start layer.

[0008] The carrier substrate with the silicon layer applied on the insulating layer can also be provided directly in the form of an original silicon wafer such as an SOI silicon wafer (SOI: Silicon-on-Insulator). The layer thickness of the first silicon layer and the applied further silicon layer can be, for example, 0.5 micrometer to 100 micrometers, preferably 20 micrometers to 60 micrometers.

[0009] The first silicon layer is structured for forming a trench in the first silicon layer, wherein the trench at least partially extends through the first silicon layer. This structuring can be performed, for example, by reactive ion etching (RIE) and / or deep reactive-ion etching (DRIE) and / or, in particular in the case of relatively thin silicon layers, by a plasma etching process.

[0010] The first silicon layer is then passivated, wherein the trench is filled and a first passivation layer is formed on the side of the first silicon layer facing away from the insulating layer. The trench is filled by forming the first passivation layer in the trench. The passivation layer preferably covers substantially the entire surface of the first silicon layer including the trench. For passivation, methods such as thermal oxidation and / or tetraethyl orthosilicate deposition (TEOS deposition), silicon carbide deposition (SiC deposition), silicon carbonitride deposition (SiCN deposition), silicon nitride deposition (SiCN deposition), etc. can be used. x N y The invention relates to a passivation technique of silicon oxide deposition (SiON deposition) or silicon oxynitride deposition (SiON deposition). The areas of the silicon layer that should not be etched are protected from etching by the passivation layer. The areas of the silicon layer that can contact the etching medium used for etching (sacrificial areas) can be completely etched. The passivation layer can therefore serve as a lateral and vertical etching stop, i.e. it can have the same function as an insulating layer in this respect. Depending on the passivation technique used, the passivation layer can be composed of different materials, such as silicon oxide and / or silicon nitride. In the process for oxide etching, the part of the passivation layer composed of silicon nitride, for example, can be retained, which can then be used for electrical insulation during the operation of the layer system produced by this method.

[0011] The first passivation layer formed in this way is structured, wherein due to the structuring a first sacrificial region and a functional region are formed in the first silicon layer and the first sacrificial region is at least partially free of the first passivation layer on a side of the first silicon layer facing away from the insulation layer.

[0012] After the first passivation layer is structured, the above-mentioned application of the first silicon layer, such as epitaxial growth, structuring and passivation steps are repeated. The structuring of the first passivation layer is also repeated as described above. This repetition can occur multiple times, for example twice, three times, five times or ten times. Within the scope of this repetition, instead of the insulating layer, the application is performed on a structured passivation layer (i.e., the just outermost passivation layer). Thus, another silicon layer and another passivation layer are formed and structured. By forming and structuring the other silicon layer and the other passivation layer, another sacrificial area and another functional area are formed in the other silicon layer. At the same time, electrical connection and electrical insulation between specific areas of the silicon layer can be achieved by structuring the other passivation layer. Here, the layers stacked on each other can be precisely calibrated to each other. Each silicon layer can be structured and configured independently of other silicon layers. In particular, functional areas that mesh with each other and / or overlap with each other can also be achieved, especially in terms of vertical extension dimensions. The method also allows the free configuration of electrical connections and electrical insulation and mechanical connections and mechanical insulation in the functional area. Within the scope of this procedure, such areas without a passivation layer can be filled by means of CVD polysilicon deposition before the application of the next silicon layer in order to form a wiring layer. The starting layer can also be generated within the scope of the step of applying the next silicon layer by means of such CVD polysilicon deposition.

[0013] Here, the steps of applying, structuring and passivating the silicon layer (including the first silicon layer) and the step of structuring the passivation layer (including the first passivation layer) are carried out in the following manner: Here, an electrical connection is formed in the formed silicon layer system, which includes at least one dedicated functional area, wherein an electrical contact can be established between two elements inside and / or outside the silicon layer system via this electrical connection, wherein, in addition, the at least one dedicated functional area is only used for the electrical connection. Here, the dedicated functional area is a functional area formed by these method steps. The electrical connection formed in this way can be completely composed of dedicated functional areas that are only used for the electrical connection. The two elements can be internal elements and / or external elements. The internal element can be, for example, a functional area that is not specifically used for conducting current, that is, it can be a part of an electrode, an actuator and / or a sensor or an electrode, an actuator and / or a sensor itself. The external element can be, for example, an external current source and / or a signal source, such as a control electronics device, which has an external electrical connection connected to the silicon layer system, such as a wiring or a welding contact. Such an external electrical connection such as a wiring or a welding contact also forms an external element itself. That is, these elements generally relate to electrically functional elements. Finally, all sacrificial areas are removed, which is usually done using an etching process (silicon sacrificial layer etching).

[0014] Therefore, the present application proposes a method for forming an electrical connection in a silicon layer system of arbitrary extension. According to the present application, the method uses the EPyC process. For more details about the EPyC process, please refer to DE 10 2015 206 996 A1, which is hereby fully incorporated into the present application as a component of the present application.

[0015] In a preferred embodiment of the method according to the present application, the electrical connection portion is or includes an electrical connection portion extending vertically (perpendicular to the surface of the carrier substrate), wherein the vertically extending electrical connection portion is composed of or includes a plurality of dedicated functional areas stacked one above the other of the functional area, wherein the plurality of dedicated functional areas are only used for the electrical connection portion. The electrical connection portion may also be or include a horizontally extending electrical connection portion.

[0016] Here, the expressions "vertical" and "horizontal" are to be understood in conjunction with the surface of the carrier substrate on which the insulating layer is provided. A horizontally extending electrical connection is an electrical connection for conducting current horizontally, i.e. the direction of the current (current direction) differs from the essentially vertical direction, i.e. for example extends parallel to the surface of the carrier substrate or obliquely relative thereto. Thus, such a horizontally electrically extending electrical connection comprises a functional area dedicated to conducting current, which is in electrical contact with other functional areas or other elements inside and / or outside the silicon layer system, wherein these electrical contacts are not stacked one above the other in the vertical direction, but are offset from one another laterally. In particular, a functional area that is part of a horizontally extending electrical connection may also be part of a vertically extending electrical connection, for example in the case where the functional area has three or more electrical contacts to further surrounding functional areas, wherein two electrical contacts are arranged perpendicular to one another and the third electrical contact is offset from the two electrical contacts laterally.

[0017] Preferably, after removing all sacrificial areas, the first passivation layer and / or one or more of the further passivation layers (in some cases thereby exposing the grooves) and / or the insulating layer are also removed at least partially, for example to establish the desired mobility of the generated structure. This is advantageous in the following cases: By means of the method according to the present application, the functional areas are advantageously completely fixed relative to each other. For example, notches and / or gaps can be formed in one of the generated passivation layers and / or grooves can be exposed. The passivation layer can also be completely removed. This can include exposing the grooves. For example, the passivation layer or parts of the passivation layer can be removed by gas phase etching, plasma etching and / or wet etching. The passivation layer or parts of the passivation layer can thus be removed particularly easily.

[0018] Depending on the passivation technology used, the passivation layer can be composed of different materials, such as silicon oxide and / or silicon nitride. According to a preferred embodiment of the method, it is particularly advantageous that one of the passivation layers is at least partially formed by a first material, and one of the passivation layers and / or the insulating layer is at least partially formed by a second material. To achieve this, two different passivation technologies can be used to passivate the silicon layer, so that the passivation layer or a region of the passivation layer is formed by two different materials. For example, thermal oxidation and / or TEOS deposition can be used as a first passivation technology, and silicon nitride deposition can be used as a second passivation technology, so that the following passivation layers are formed, in which the first part is composed of silicon oxide and the second part is composed of silicon nitride. The following possibility is included here: the passivation layer is partially composed of silicon oxide and partially composed of silicon nitride. This embodiment of the method according to the present application makes it possible to achieve that in the case of a method for removing the part of the passivation layer composed of the first material (such as silicon oxide) correspondingly selected, the part of the passivation layer composed of the second material (such as silicon nitride) can be left. Electrical insulation between different functional areas can thus be ensured in a convenient and simple manner, since both silicon oxide and silicon nitride are dielectrics. With a process for etching oxides, for example, a portion of the passivation layer consisting of silicon nitride can remain, which can be used for electrical insulation during operation of the layer system produced by the method.

[0019] In an advantageous embodiment of the method of the present application, the carrier substrate is also removed. As a result, the resulting layer system can be used further independently of the carrier substrate. Preferably, this removal is carried out before removing all remaining sacrificial areas (usually by etching of the silicon sacrificial layer). The removal of the carrier substrate is preferably carried out by chemical mechanical polishing (CMP).

[0020] Preferably, at least one of the applied silicon layers, for example the first silicon layer and / or one of the further silicon layers, comprises a monocrystalline silicon layer, a polycrystalline silicon layer and / or an epitaxial polycrystalline silicon layer, or is such a silicon layer. Furthermore, the layer thickness of at least one of the applied silicon layers, for example the first silicon layer and / or the second silicon layer and / or one of the further silicon layers, can be, for example, 0.5 μm to 100 μm, preferably 20 μm to 60 μm. In MEMS, thin silicon layers are suitable, for example, as spring elements for vertical deflection. Thick silicon layers, on the other hand, are advantageous for producing electrode combs, for filling large volumes or for being removed again as sacrificial areas.

[0021] Preferably, the structuring for forming the trenches is achieved by means of trench processes such as reactive ion etching (RIE) and / or deep reactive ion etching (DRIE) and / or by means of a plasma etching process. Here, the plasma etching process is particularly suitable for thin layers (thickness of a few micrometers). For thicker layers, for example, DRIE can be used.

[0022] According to a preferred embodiment of the method of the present application, the structuring of the passivation layer is performed by a dry etching process and / or a wet etching process. Therefore, the passivation layer can be easily removed again without using a special etching process.

[0023] It is also advantageous that, after application of one of the silicon layers, the silicon layer is subjected to chemical mechanical polishing (CMP) and / or additional doping is performed at least locally by implantation and / or capping. This makes it possible to easily flatten the topological irregularities and height differences formed, especially in the case of epitaxial growth of the silicon layer. By means of the additional doping achieved by means of implantation or capping, the desired conductivity can be easily achieved in the silicon layer or in specific areas of the silicon layer. The grown silicon layer can be undoped, p-doped or n-doped. This approach is particularly suitable for achieving particularly good conductivity in the dedicated functional areas of the electrical connection to be formed.

[0024] Preferably, the sacrificial region is removed at least partially by plasma-free etching and / or plasma-assisted etching, i.e., by a silicon sacrificial layer etching process. In this way, the sacrificial region can be removed particularly easily. For example, such plasma-free etching can be performed by chlorine trifluoride (ClF3), chlorine fluoride (ClF), chlorine pentafluoride (ClF5), trifluorobromide (BrF3), pentafluorobromide (BrF5), iodine pentafluoride (IF5), iodine heptafluoride (IF7), sulfur tetrafluoride (SF4), xenon difluoride (XeF2) or similar substances. Plasma-assisted etching can be performed, for example, by fluorine plasma, chlorine plasma and / or bromine plasma. In particular, etching can also be based on a combination of plasma-free etching and plasma-assisted etching.

[0025] According to a second aspect of the present application, a silicon layer system is provided, for example for a microelectromechanical device including MEMS (such as a micromirror array), the silicon layer system preferably including a microelectromechanical structure manufactured using the method of the present application. The microelectromechanical device has an alternating sequence of structured silicon layers and structured passivation layers and an electrical connection, wherein the structured silicon layers have functional areas, and the electrical connection includes or consists of a dedicated functional area in the functional area. Here, an electrical contact between two elements inside and / or outside the silicon layer system can be established via the electrical connection, wherein the dedicated functional area is only used for the electrical connection.

[0026] In such a layer system, the electrical connection part can be a vertically extending electrical connection part or include a vertically extending electrical connection part, and the vertically extending electrical connection part is composed of or includes a plurality of dedicated functional areas stacked one above the other in the functional area, wherein the plurality of dedicated functional areas are only used for the electrical connection part. Alternatively or simultaneously, the electrical connection part can also be a horizontally extending electrical connection part or include a horizontally extending electrical connection part.

[0027] Finally, according to a third aspect of the present application, a micro-electromechanical device comprising the silicon layer system according to the present application is provided.

[0028] Advantages of this application

[0029] According to the method of the present application, a silicon layer system with electrical connections, in particular TSVs (TSV: through silicon vias), can be easily designed. A significant advantage of the method of the present application is its extremely high flexibility and variability.

[0030] The use of the method is therefore particularly advantageous when producing microelectromechanical structures for microelectromechanical devices, since this generally requires that the processes used for the circuit connections have a high degree of variability with regard to the dimensions of these circuit connections: the dimensions of the electrical connections and the insulating structures and their course must be flexibly selectable. This can be achieved with the method according to the present application. In this case, the method is particularly suitable for wiring structures and TSVs with large horizontal and vertical dimensions.

[0031] In this case, the method does not require complex intermediate steps for laying out the electrical connections. In particular, no additional lithography and / or structuring steps are required, as is the case, in particular, when producing individual TSVs. The method integrates the production of the actual silicon layer system (e.g., a microelectromechanical structure) with the formation of the desired electrical connections between the components. The process of the present application is also suitable for CMOS and high temperatures and is therefore particularly suitable for large-scale production, such as large-scale production of microelectromechanical systems. In particular, the high temperature resistance means that implantation steps (Eintreibschritte) and annealing (Annealing) are also not a problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Embodiments of the present application will be explained in more detail with reference to the accompanying drawings and the following description.

[0033] The accompanying drawings show:

[0034] Figure 1A and 1B A schematic cross-sectional illustration is shown for explaining the method according to the application for producing a silicon layer system having an electrical connection.

[0035] Figure 2A schematic flow chart is shown for explaining the method according to the present application for producing a silicon layer system having an electrical connection.

[0036] Figure 3 is a schematic diagram of an exemplary micro-electromechanical device according to the present application. DETAILED DESCRIPTION

[0037] In the following description of the embodiments of the present application, identical or similar elements are denoted by identical reference numerals, wherein a repeated description of these elements is omitted in individual cases. The drawings merely schematically illustrate the subject matter of the present application.

[0038] exist Figure 1A and 1B , a schematic cross-sectional illustration is shown for explaining an exemplary method according to the present application for producing a microelectromechanical structure. For the sake of clarity, the insulating layer and the passivation layer (inside and outside the drawn trench) are shown identically in the figure. All layers shown as two-dimensional objects in the figure also have a third spatial dimension and can also be structured along this third spatial dimension by the method of the present application, thereby achieving a very high flexibility.

[0039] Here, Figure 1A A provided carrier substrate 110 is shown. Also shown is an insulating layer 122 , which has been applied to the first surface 120 of the carrier substrate 110 and consists, for example, of silicon oxide.

[0040] On the insulating layer 122, a first silicon layer 150a has been applied, for example epitaxially grown, and then structured by the method of the present application. A trench 156a has been formed here, which extends through the first silicon layer 150a. By passivating the first silicon layer 150a, the trench 156a has been filled, and at the same time, a first passivation layer 154a has been formed on the side facing away from the insulating layer 122. The first passivation layer 154a has also been structured (notch 125a), wherein functional areas 152 and sacrificial areas 153 are formed in the first silicon layer 150a. This achieves that the sacrificial area 153 can be removed later by an etching process with an etching medium, wherein the area of ​​the silicon layer 150 that can contact the etching medium serves as the sacrificial area 153. Then the above-mentioned steps of applying 220, structuring 230 and passivating 240 of the first silicon layer 150a are repeated again. Here, another silicon layer 150b is applied on the first passivation layer 154a, and the notch 125a in the first passivation layer 154a has been filled. The other silicon layer 150b has been structured by another groove 156b. By passivation, these grooves 156b are filled, and another passivation layer 154b is also produced outside the groove 156b. Then the other passivation layer 154b is structured (notch 125b). Here, the two silicon layers 150a and 150b applied are represented by a common reference numeral 150, a common reference numeral 156 represents the filled groove, and a common reference numeral 154 represents the passivation layer outside the groove.

[0041] A further silicon layer 150 can be applied, structured and passivated, wherein the functional regions 152 and sacrificial regions 153 are defined by structuring the passivation layer 154. Figure 1B 1 shows a silicon layer system 100 having an electrical connection 190 produced by the method according to the present application, wherein Figure 1A In comparison, three further applied and structured silicon layers 150c , 150d , 150e with trenches 156 and correspondingly three further structured passivation layers 154c , 154d , 154e are shown.

[0042] Finally, in Figure 1B In the embodiment of the present invention, the carrier substrate 110 has been removed and the resulting structure can now be completely exposed by removing the sacrificial region 153, for example, by means of plasma-free and / or plasma-assisted etching. The region of the silicon layer 150 that can contact the etching medium used in the etching process (for example, via the notch 125e of the passivation layer 154e, i.e., the sacrificial region 153) is completely etched. If necessary, the passivation layer 154 (together with the exposed trench 156) and / or the insulating layer 122 ( Figure 1B(not shown), for example, in order to establish the desired mobility of the microelectromechanical structure. For example, gas phase etching, plasma etching or wet etching can be used to carry out such removal.

[0043] As in Figure 1B As shown in the upper sub-figure (side view, marked with S), electrical connections 190 can be formed by appropriately structuring the silicon layer 150. These electrical connections 190 may include dedicated functional areas 152. Figure 1B , an electrical connection 190 is specifically shown (visually shown as a plurality of arrows indicating the current flow direction of the electrical connection 190), which extends from a first electrical element 194 outside the silicon layer system 100 to a second electrical element 192 inside the silicon layer system 100. Here, the electrical connection 190 comprises a plurality of sections in which the current is conducted vertically and a plurality of sections in which the current is conducted horizontally, vertically and horizontally respectively referring to the surface 120 of the carrier substrate 110 which is removed at that time. More specifically, five functional areas 152v dedicated to current conduction are part of three vertically extending electrical connections 190v, and three functional areas 152h dedicated to current conduction are part of three horizontally extending electrical connections 190h. Here, the dedicated functional areas 152 are in electrical contact via the filled notches 191. These dedicated functional areas 152 jointly provide an electrical connection 190 between an external element 194 and an internal element 192, wherein the external element 194 can be, for example, a control electronics 198 with connecting lines 196. Here, the connecting line 196 itself is also an external element in the sense of the present application. In the example shown, the insulating layer 122 is removed at one location (notch 126) to connect the external element 194. The direction of the current is indicated by the arrow shape of the connecting line 196 of the electrical element 194. The internal element 192 is Figure 1B In the drawing, the internal element 192 is highlighted by another hatching for better recognition, for example, a sensor, an electrode and / or an actuator, which has been implemented by one or more functional areas 152 of the silicon layer system 100. For the sake of clarity, the internal element 192 is shown in FIG. Figure 1B The electrical connection 190 is shown only for the current direction toward the internal element 192, and the complete current loop is not shown. Figure 1B In the figure, it is shown that the internal element 192 is arranged in the outermost first silicon layer 150a, but this is purely for the purpose of illustrating the more complex possibilities of the electrical connection 190 and this situation usually does not occur in practical applications. That is, the present application is particularly advantageous in the following cases: simple direct access to the internal element 192 (such as access via the insulating layer 122 here) is not possible, that is, the internal element 192 to be coupled to the electrical connection 190 is located further inside the silicon layer system 100 to be produced.

[0044] Here, there is a dedicated functional area 152h in the top silicon layer 150e, which is only shown as two sub-areas 152h' and 152h". The cross-section of the top silicon layer 150e is shown in the lower sub-figure T, and its direction is marked with a dotted line / dash-dot line in the upper sub-figure S. As shown in the figure, the electrical connection portion 190 and its dedicated functional area 152 do not have to extend in a straight line, but can adopt any arbitrary shape. For ease of explanation, a dotted line S is drawn in the lower sub-figure, which indicates the position of the plane shown in the sub-figure S.

[0045] Figure 2 A schematic flow chart is shown for explaining an exemplary method according to the present application for producing a silicon layer system 100 with an electrical connection 190. After providing 210 a carrier substrate 110, a first silicon layer 150a is applied 220 to the surface 120 of the carrier substrate 110, for example by epitaxial growth. The first silicon layer 150a is then structured 230 by forming trenches 156, which extend at least partially through the first silicon layer 150a. After passivation 240 of the first silicon layer 150a with filling of the trenches 156, a first passivation layer 154a is also formed outside the trenches 156. This first passivation layer is located on the side of the first silicon layer 150a facing away from the insulating layer 122. In this case, the first passivation layer 154a produced in this way is structured in step 250 to define functional regions 152 and sacrificial regions 153. In this case, these steps for forming the applied, structured silicon layer 150 can be repeated any number of times. This is indicated by arrow 255 .

[0046] Here, steps 220 to 250 are respectively implemented to form an electrical connection part 190 including at least one dedicated functional area 152h, 152v, through which an electrical connection can be established between two elements 192, 194 inside and / or outside the silicon layer system 100, wherein the at least one dedicated functional area 152h, 152v is only used for the electrical connection part 190.

[0047] Once all desired silicon layers 150 have been applied, carrier substrate 110 is removed (step 260), and sacrificial region 153 is subsequently removed in step 270 using a process for silicon sacrificial layer etching. Optionally, vapor phase etching, plasma etching and / or wet etching may also be performed to at least partially remove passivation layer 154.

[0048] Figure 3A schematic diagram shows an exemplary microelectromechanical device 300 (e.g., a MEMS) according to the present application. The microelectromechanical device 300 has a silicon layer system 310, which is produced according to the method of the present application. The silicon layer system 310 comprises an alternating sequence 350 of structured silicon layers 150 with functional regions 152 and structured passivation layers 154. Furthermore, an electrical connection 390 is formed in the silicon layer system 310, which comprises dedicated functional regions 152h and 152v of the silicon layer 150, wherein electrical contact is made between an internal component 370 (e.g., an actuator implemented by the functional region 152 of the silicon layer system 310) and an external component 380 (e.g., a control electronics 198 with connecting lines 196) via the electrical connection 390. In this case, the dedicated functional regions 152h, 152v are used only for the electrical connection 390.

[0049] In the example shown, the electrical connection 390 includes a vertically extending electrical connection 390v and a horizontally extending electrical connection 390h. A circuit 360 including a plurality of electrical connections 390 can also be implemented by the silicon layer system 310, for example. The microelectromechanical device 300 is located on a carrier 320, which can include, for example, other electrical and electronic components for operating the microelectromechanical device 310.

[0050] The present application is not limited to the embodiments described herein and the aspects emphasized therein. On the contrary, numerous variations are possible within the scope of the claims that are within the grasp of a person skilled in the art.

Claims

1. A method for producing a silicon layer system (100, 310) having an electrical connection (190, 390), the method comprising the following steps: a. providing (210) a carrier substrate (110) having a surface (120), wherein the carrier substrate (110) is provided with an insulating layer (122) formed on the surface (120); b. applying (220) a first silicon layer (150a) onto the insulating layer (122); c. structuring (230) the first silicon layer (150a) for forming a trench (156) in the first silicon layer (150a), wherein the trench (156) at least partially extends through the first silicon layer (150a); d. passivating (240) the first silicon layer (150a), wherein the trench (156) is filled and a first passivation layer (154a) is formed on a side of the first silicon layer (150a) facing away from the insulating layer (122); e. Structuring (250) the first passivation layer (154a), wherein a first sacrificial region (153) and a functional region (152) are formed in the first silicon layer (150a), and the first sacrificial region (153) is at least partially free of the first passivation layer (154a) on a side of the first silicon layer (150a) facing away from the insulating layer (122); f. repeating steps b to e once or more times (255), wherein the applying (220) is respectively carried out on a structured passivation layer (154), and further silicon layers (150b, 150c, 150d, 150e) and further passivation layers (154b, 154c, 154d, 154e) are thereby formed and structured, thereby forming further sacrificial regions (153) and further functional regions (152) in the further silicon layers (150b, 150c, 150d, 150e); and g. after one or more repetitions (255) of steps b to e, removing (270) all sacrificial areas (153), In which steps b to f are implemented so as to form an electrical connection portion (190, 390) including at least one dedicated functional area (152h, 152v), through which electrical contact can be established between two elements (192, 194, 196, 370, 380) inside and / or outside the silicon layer system (100, 310), wherein the at least one dedicated functional area (152h, 152v) is only used for the electrical connection portion (190, 390).

2. The method according to claim 1, wherein: The electrical connection portion (190, 390) It is a vertically extending electrical connection portion (190v, 390v) or includes a vertically extending electrical connection portion, wherein the vertically extending electrical connection portion is composed of a plurality of dedicated functional areas (152v) stacked up and down of the functional area (152) or includes a plurality of dedicated functional areas stacked up and down of the functional area, wherein the plurality of dedicated functional areas (152v) are only used for the electrical connection portion (190v, 390v); and / or It is a horizontally extending electrical connection portion (190h, 390h) or includes a horizontally extending electrical connection portion.

3. The method according to claim 1 or 2, wherein: One of the passivation layers (154) is at least partially composed of a first material, and one of the passivation layers (154) and / or the insulating layer (122) is at least partially composed of a second material.

4. A method according to any one of the preceding claims, wherein: The carrier substrate (110) is removed (260) and preferably carried out before the sacrificial region (153) is removed (270) and / or by chemical mechanical polishing.

5. The method according to any one of the preceding claims, characterized in that The structuring (250) of the passivation layer (154) is performed by a dry etching process and / or a wet etching process.

6. A method according to any one of the preceding claims, wherein: After applying (220) one of the silicon layers (150), the silicon layer (150) is chemically mechanically polished and / or additionally doped at least locally by implantation and / or capping.

7. A method according to any one of the preceding claims, wherein: The sacrificial region (153) is removed (270) at least in part by plasma-free etching and / or plasma-assisted etching.

8. A silicon layer system (100, 310), preferably a silicon layer system produced according to the method of any one of claims 1 to 7, comprising an alternating sequence (350) of structured silicon layers (150) having functional areas (152) and structured passivation layers (154) and comprising an electrical connection (190, 390), the electrical connection comprising or consisting of a dedicated functional area (152h, 152v) of the functional area (152), in, The electrical connection (190, 390) enables electrical contact to be established between two elements (192, 194, 370, 380) inside and / or outside the silicon layer system (100, 310), wherein the dedicated functional area (152h, 152v) is used only for the electrical connection (190, 390).

9. The silicon layer system (100, 310) according to claim 8, wherein: The electrical connection portion (190, 390) a. It is a vertically extending electrical connection portion (190v, 390v) or includes a vertically extending electrical connection portion, wherein the vertically extending electrical connection portion is composed of a plurality of dedicated functional areas (152h, 152v) stacked up and down on the functional area (152) or includes a plurality of dedicated functional areas stacked up and down on the functional area, wherein the plurality of dedicated functional areas (152h, 152v) are only used for the electrical connection portion (190, 390); and / or b. It is a horizontally extending electrical connection portion (190h, 390h) or includes a horizontally extending electrical connection portion.

10. A micro-electromechanical device (300) comprising a silicon layer system (100, 310) according to claim 8 or 9.

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