Substrate and electronic device

Abstract

A substrate has a plurality of edges. The substrate comprises a device area and at least one binding area, and the binding area is close to any edge of the substrate relative to the device area. The substrate includes a substrate, a plurality of device groups, a plurality of signal line groups, and a plurality of conductive patterns. The plurality of device groups are located on one side of the substrate, and the plurality of device groups are located in the device region. The plurality of device groups are arranged along a first direction and a second direction, respectively. One device group includes at least one electronic component. One signal line group comprises a plurality of signal lines, any signal line extends from the binding area to the device area, and any signal line is electrically connected with one column of device groups arranged along the second direction. At least one conductive pattern of the plurality of conductive patterns is located in an area where one device group is located. And / or at least one conductive pattern in the plurality of conductive patterns is located in an area between two adjacent device groups. Wherein at least one signal line in the at least one signal line group is electrically connected with one conductive pattern.

Description

Substrates and electronic devices Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a substrate and an electronic device. Background Art

[0002] The substrate generally includes electronic components and signal lines, and the signal lines are electrically connected to the electronic components to achieve signal transmission.

[0003] Summary of the Invention

[0004] In one aspect, a substrate is provided. The substrate has multiple edges. The substrate includes a device region and at least one bonding region, the bonding region being closer to any edge of the substrate than the device region. The substrate includes a substrate, multiple device groups, multiple signal line groups, and multiple conductive patterns. The multiple device groups are located on one side of the substrate, and multiple device groups are located in the device region. The multiple device groups are arranged along a first direction and a second direction, respectively, intersecting the first and second directions and parallel to the substrate. A device group includes at least one electronic component. Multiple signal line groups are located on the same side of the substrate as the multiple device groups. A signal line group includes multiple signal lines, each extending along a second direction, and the multiple signal lines are spaced apart along the first direction. Any signal line extends from the bonding region to the device region, and any signal line is electrically connected to a row of device groups arranged along the second direction. Multiple conductive patterns are located on the same side of the substrate as the multiple device groups. At least one of the multiple conductive patterns is located within the region where a device group is located. And / or at least one of the multiple conductive patterns is located between two adjacent device groups. At least one signal line in at least one signal line group is electrically connected to a conductive pattern.

[0005] In some embodiments, the plurality of conductive patterns and the plurality of signal line groups are disposed on the same layer.

[0006] In some embodiments, the plurality of signal line groups include a first voltage line group including a plurality of first voltage lines, and the plurality of conductive patterns include a plurality of first conductive patterns electrically connected to at least one first voltage line in the first voltage line group.

[0007] In some embodiments, the substrate further includes a plurality of first bridge portions, and at least one first conductive pattern is electrically connected to a first voltage line through the first bridge portions.

[0008] In some embodiments, at least one of the plurality of first bridge portions is a jumper resistor.

[0009] In some embodiments, at least one first conductive pattern and a first voltage line form an integrated structure.

[0010] In some embodiments, at least two first conductive patterns are arranged along the first direction.

[0011] In some embodiments, at least two first conductive patterns arranged along the first direction constitute a first conductive pattern row, and a plurality of first conductive patterns constitute at least two first conductive pattern rows.

[0012] In some embodiments, there are two first conductive pattern rows, and the two first conductive pattern rows include different numbers of first conductive patterns. The length of any device group along the second direction is L. Along the second direction, one first conductive pattern row is closer to the bonding region than the other first conductive pattern row, and the spacing between the two first conductive pattern rows along the second direction ranges from 3L to 5L.

[0013] In some embodiments, the plurality of device groups include a first row of device groups, the first row of device groups being adjacent to the bonding region along the second direction, and at least one first conductive pattern row being located within the region where the first row of device groups is located.

[0014] In some embodiments, the plurality of first conductive patterns include a first type of first conductive pattern. One end of the first type of first conductive pattern is directly connected to an end of the bonding region proximal to the device region, and the other end of the first type of first conductive pattern is electrically connected to the first voltage line group. The number of the first type of first conductive patterns is a, where a is less than the number of first voltage lines in the first voltage line group, and a is a positive integer.

[0015] In some embodiments, a is no greater than half the number of first voltage lines in the first voltage line group.

[0016] In some embodiments, the plurality of signal line groups further include a second voltage line group including a plurality of second voltage lines, and the plurality of conductive patterns further include a plurality of second conductive patterns electrically connected to at least one second voltage line in the second voltage line group.

[0017] In some embodiments, the substrate further includes a plurality of second bridge portions, and at least one second conductive pattern is electrically connected to a second voltage line through the second bridge portions.

[0018] In some embodiments, at least one of the plurality of second bridge sections is a jumper resistor.

[0019] In some embodiments, at least one second conductive pattern and a second voltage line form an integrated structure.

[0020] In some embodiments, at least two second conductive patterns are arranged along the first direction.

[0021] In some embodiments, at least two second conductive patterns arranged along the first direction constitute a second conductive pattern row, and a plurality of second conductive patterns constitute at least two second conductive pattern rows.

[0022] In some embodiments, there are two second conductive pattern rows, and the two second conductive pattern rows include different numbers of second conductive patterns. The length of any device group along the second direction is L. Along the second direction, one second conductive pattern row is closer to the bonding region than the other second conductive pattern row, and the spacing between the two second conductive pattern rows along the second direction ranges from 3L to 5L.

[0023] In some embodiments, the plurality of device groups include a first row of device groups, the first row of device groups being adjacent to the bonding region along the second direction, and the at least one second conductive pattern row being located in the region where the first row of device groups is located.

[0024] In some embodiments, the plurality of second conductive patterns include a first type of second conductive pattern. One end of the first type of second conductive pattern is directly connected to an end of the bonding region proximal to the device region, and the other end of the first type of second conductive pattern is electrically connected to the second voltage line group. The number of the first type of second conductive patterns is b, where b is less than the number of second voltage lines in the second voltage line group, and b is a positive integer.

[0025] In some embodiments, Y is no greater than half the number of the second voltage lines in the second voltage line group.

[0026] In some embodiments, the substrate further includes a plurality of third bridge portions and a plurality of fourth bridge portions, wherein at least two first conductive patterns are electrically connected via the third bridge portions, and / or at least two second conductive patterns are electrically connected via the fourth bridge portions.

[0027] In some embodiments, at least two first voltage lines in the same first voltage line group are connected to each other on a side away from the binding region along the second direction. And / or, at least two second voltage lines in the same second voltage line group are connected to each other on a side away from the binding region along the second direction.

[0028] In some embodiments, the width of the first voltage line along the first direction ranges from 0.5 mm to 1 mm, and / or the width of the second voltage line along the first direction ranges from 0.5 mm to 1 mm.

[0029] In some embodiments, any first voltage line is located along the first direction on a first side of a column of device groups electrically connected to the first voltage line, and any second voltage line is located along the first direction on a second side of a column of device groups electrically connected to the second voltage line.

[0030] In some embodiments, there are multiple bonding areas, and multiple signal lines in one signal line group are electrically connected to one bonding area in the multiple bonding areas.

[0031] In some embodiments, the substrate further includes an electrostatic loop and a circuit board. The electrostatic loop is disposed around the plurality of device groups and is electrically connected to the binding area. The circuit board is electrically connected to the binding area.

[0032] In another aspect, an electronic device is provided, which includes the substrate as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0034] FIG1A is a structural diagram of an electronic device according to some embodiments;

[0035] FIG1B is a structural diagram of an electronic device according to some other embodiments;

[0036] FIG2A is a structural diagram of a substrate according to some embodiments;

[0037] FIG2B is a structural diagram of a substrate according to some other embodiments;

[0038] FIG2C is a structural diagram of a device group according to some embodiments;

[0039] FIG2D is a structural diagram of a driver chip and a device group according to some embodiments;

[0040] FIG2E is a structural diagram of a driver chip and a device group according to some other embodiments;

[0041] FIG2F is a structural diagram of a substrate according to yet other embodiments;

[0042] FIG2G is a structural diagram of a substrate according to yet other embodiments;

[0043] FIG3A is a structural diagram of a substrate according to yet other embodiments;

[0044] FIG3B is a structural diagram of a substrate according to yet other embodiments;

[0045] FIG3C is a structural diagram of a substrate according to yet other embodiments;

[0046] FIG3D is a structural diagram of a substrate according to yet other embodiments;

[0047] FIG3E is a structural diagram of a substrate according to yet other embodiments;

[0048] FIG3F is a structural diagram of a substrate according to yet other embodiments;

[0049] FIG4A is a structural diagram of a substrate according to yet other embodiments;

[0050] FIG4B is a structural diagram of a substrate according to yet other embodiments;

[0051] FIG4C is a structural diagram of a substrate according to yet other embodiments;

[0052] FIG5A is a structural diagram of a substrate according to yet other embodiments;

[0053] FIG5B is a structural diagram of a substrate according to yet other embodiments;

[0054] FIG5C is a structural diagram of a substrate according to yet other embodiments;

[0055] FIG5D is a structural diagram of a substrate according to yet other embodiments;

[0056] FIG5E is a structural diagram of a substrate according to yet other embodiments;

[0057] FIG6A is a structural diagram of a substrate according to yet other embodiments;

[0058] FIG6B is a structural diagram of a substrate according to yet other embodiments;

[0059] FIG6C is a structural diagram of a substrate according to yet other embodiments;

[0060] FIG7A is a structural diagram of a substrate according to yet other embodiments;

[0061] FIG7B is a partial enlarged view of area 1 in FIG7A ;

[0062] FIG8A is a structural diagram of a substrate according to yet other embodiments;

[0063] FIG8B is a partial enlarged view of area 2 in FIG8A ;

[0064] FIG8C is a partial enlarged view of area 3 in FIG8A ;

[0065] FIG8D is a partial enlarged view of area 4 in FIG8A . DETAILED DESCRIPTION

[0066] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0067] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0068] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0069] When describing some embodiments, the term "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0070] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0071] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0072] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0073] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0074] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0075] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0076] FIG. 1A is a structural diagram of an electronic device according to some embodiments.

[0077] As shown in FIG1A , an embodiment of the present disclosure provides an electronic device 200. In some examples, the electronic device 200 may be a product with an image display function. For example, the electronic device 200 may be used to display static images, such as pictures or photos. The electronic device 200 may also be used to display dynamic images, such as videos or game screens.

[0078] In some examples, the electronic device 200 can be a laptop computer, a mobile phone, a wireless device, a personal data assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a watch, a clock, a calculator, a television monitor, a flat-panel display, a computer monitor, an automobile display (e.g., an odometer display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photograph, an electronic billboard or sign, a projector, packaging and aesthetic structures (e.g., a display of an image for a piece of jewelry), etc.

[0079] In other examples, the electronic device 200 may also be a product without an image display function.

[0080] The embodiments of the present disclosure do not further limit the electronic device 200 . The following description will be given by taking the electronic device 200 as a product with an image display function as an example.

[0081] FIG1B is a structural diagram of an electronic device according to some other embodiments.

[0082] 1B , in some embodiments, the electronic device 200 may include a substrate 100 and a display panel 210. For example, the substrate 100 is configured to emit light outward, and the display panel 210 is located on the light-emitting side of the substrate 100 and is configured to display image information.

[0083] In some examples, the display panel 210 is a liquid crystal display panel, and the substrate 100 is used to provide backlight for the display panel 210 .

[0084] In some examples, the substrate 100 can be configured to emit white light or blue light. The display panel 210 can filter or convert the light emitted by the substrate 100 to generate red light, green light, and blue light, enabling the electronic device 200 to display full-color images.

[0085] The display panel 210 is described below by taking the display panel 210 as a liquid crystal display panel as an example.

[0086] In some examples, as shown in FIG1B , the display panel 210 includes an array substrate 216, an opposing substrate 214, and a liquid crystal layer 212 located between the array substrate 216 and the opposing substrate 214. It will be appreciated that light emitted from the substrate 100 can pass through the array substrate 216 and illuminate the liquid crystal layer 212. The liquid crystal layer 212 includes liquid crystal molecules, and by controlling the deflection angle of the liquid crystal molecules, the intensity of light that passes through the liquid crystal layer 212 and illuminates the opposing substrate 214 can be controlled, thereby enabling the electronic device 200 to display images.

[0087] In some examples, when substrate 100 is configured to emit white light, counter substrate 214 may include a red filter, a green filter, and a blue filter. By controlling the intensity of light incident on the red, green, and blue filters, different intensities of red, green, and blue light can be generated, enabling electronic device 200 to display color images.

[0088] In other examples, when substrate 100 is configured to emit blue light, counter substrate 214 may include a color conversion film. For example, the color conversion film may be a quantum dot film. Blue light irradiated by the red quantum dot film is converted to red light. Blue light irradiated by the green quantum dot film is converted to green light. The red and green light converted by the quantum dot film, when mixed with the blue light emitted by substrate 100, enables electronic device 200 to achieve full-color graphic display.

[0089] In some examples, the display panel 210 includes a common electrode and a plurality of pixel electrodes. An electric field can be formed between the common electrode and each pixel electrode. By controlling the voltage value of each pixel electrode, the intensity of the electric field formed between the common electrode and each pixel electrode can be controlled, thereby controlling the deflection angle of the liquid crystal molecules in the liquid crystal layer 212, that is, controlling the intensity of light passing through the liquid crystal layer 212.

[0090] In some examples, the pixel electrode may be disposed on the array substrate 216 . The common electrode may be disposed on the array substrate 216 or the counter substrate 214 .

[0091] Figure 2A is a structural diagram of a substrate according to some embodiments. Figure 2B is a structural diagram of a substrate according to other embodiments. Figure 2C is a structural diagram of a device group according to some embodiments. Figure 2D is a structural diagram of a driver chip and a device group according to some embodiments. Figure 2E is a structural diagram of a driver chip and a device group according to other embodiments. Figure 2F is a structural diagram of a substrate according to still other embodiments. Figure 2G is a structural diagram of a substrate according to still other embodiments. The following describes substrate 100 with reference to Figures 2A to 2G.

[0092] In some embodiments, as shown in FIG2A and FIG2B , the substrate 100 has a plurality of edges P. It is understood that the edges P of the substrate 100 can be straight segments or curved segments. In some examples, as shown in FIG2A and FIG2B , the substrate 100 can be square or rectangular, that is, the substrate 100 can have four edges P.

[0093] In other examples, the substrate 100 may also be a polygon or other irregular shapes, etc. The embodiment of the present disclosure does not further limit the shape of the substrate 100 and the number of edges P of the substrate 100.

[0094] As shown in FIG. 2A and FIG. 2B , the substrate 100 includes a device area AA and at least one bonding area BB. The bonding area BB is closer to any edge P of the substrate 100 relative to the device area AA.

[0095] It is understandable that the bonding area BB is adjacent to one side edge of the device area AA and is adjacent to one side edge of the device area AA adjacent to the bonding area BB. It should be noted that in the drawings of the present disclosure, taking Figures 2A and 2B as examples, the edges of the device area AA and the bonding area BB shown in the dashed boxes are spaced apart from each other only to clearly distinguish the device area AA from the bonding area BB, and do not further define the edge positions of the device area AA and the bonding area BB.

[0096] The bonding area BB is closer to any edge P of the substrate 100 relative to the device area AA. That is, the bonding area BB may be located between the device area AA and any edge P.

[0097] In some examples, the bonding area BB is located on one side of the device area AA along the second direction Y. For example, the second direction Y can be a vertical direction.

[0098] In some examples, as shown in FIG2A , the number of binding areas BB may be one. In other examples, as shown in FIG2B , the number of binding areas BB may be multiple. For example, the number of binding areas BB may be two, three, or four.

[0099] It can be understood that, as shown in FIG. 2B , when there are multiple binding areas BB, the multiple binding areas BB are located on the same side of the device area AA, that is, the multiple binding areas BB are all arranged on the same edge P.

[0100] In some examples, as shown in FIG2B , the plurality of binding areas BB may be spaced apart along a first direction X. For example, the first direction X may be a horizontal direction, and the first direction X may be perpendicular to the second direction Y. It is understood that the plurality of binding areas BB may be spaced apart at the same distance, or the spacing between any two adjacent binding areas BB in the plurality of binding areas BB may be different.

[0101] As shown in Figures 2A and 2B, substrate 100 includes a substrate 101 and multiple device groups 110. Multiple device groups 110 are located on one side of substrate 101, and multiple device groups 110 are located in device area AA. Multiple device groups 110 are arranged along a first direction X and a second direction Y, respectively. The first direction X and the second direction Y intersect and are parallel to substrate 101. Each device group 110 includes at least one electronic component 120.

[0102] In some examples, substrate 101 is a rigid substrate. In other examples, substrate 101 is a flexible substrate. Exemplary materials for substrate 101 include plastic, FR-4 grade material, resin, glass, quartz, polyimide (PI), or polymethyl methacrylate (PMMA).

[0103] It is understood that the multiple device groups 110 are located on the same side of the substrate 101 and in the device area AA. In some examples, the multiple device groups 110 are spaced apart along the first direction X, and the spacing between two adjacent device groups 110 along the first direction X is the same or approximately the same. The multiple device groups 110 are spaced apart along the second direction Y, and the spacing between two adjacent device groups 110 along the second direction Y is the same or approximately the same. In this way, as shown in Figures 2A and 2B, the multiple device groups 110 can be arranged in rows along the first direction X and in columns along the second direction Y. It is understood that the multiple rows of device groups 110 are spaced apart along the second direction Y, and the multiple columns of device groups 110 are spaced apart along the first direction X.

[0104] It should be noted that in the drawings of the specification of the present disclosure, in order to clearly show the structure of the substrate 100, only four rows and three columns of device groups 110 (for example, Figure 2A) or four rows and six columns of device groups 110 (for example, Figure 2B) are shown, and no further limitation is imposed on the number and arrangement of the device groups 110 in the embodiments of the present disclosure.

[0105] It can be understood that one device group 110 may include one electronic component 120 or multiple electronic components 120 .

[0106] In some examples, when a device group 110 includes multiple electronic components 120, the multiple electronic components 120 can be components of the same type or different types. For example, when the substrate 100 is used to emit light, the electronic components 120 can be light-emitting devices. The multiple light-emitting devices included in a device group 110 can be used to emit light of the same color, and the multiple light-emitting devices included in a device group 110 can also be used to emit light of multiple different colors. Alternatively, among the multiple electronic components 120 included in a device group 110, a portion (one or more) are light-emitting devices for emitting light, while another portion (one or more) are other components (such as sensor chips, etc.) to achieve other functions.

[0107] In some examples, as shown in Figures 2A and 2B, a device group 110 may include six electronic components 120. In other examples, as shown in Figure 2C, a device group 110 may also include four electronic components 120. In still other examples, a device group 110 may also include two, three, or five electronic components 120. It is understandable that the number of electronic components 120 included in different device groups 110 may be the same or different. The embodiments of the present disclosure do not further limit the number of electronic components 120 in a device group 110.

[0108] In some examples, as shown in Figures 2A and 2B, when a device group 110 includes multiple electronic components 120, the multiple electronic components 120 can be arranged in a matrix form, that is, the multiple electronic components 120 can be arranged at the four vertices of a rectangle or a square, thereby improving the regularity of the arrangement of the multiple electronic components 120.

[0109] In other examples, when a device group 110 includes multiple electronic components 120, the multiple electronic components 120 in the device group 110 may be arranged at the vertices of a hexagon, octagon, or other irregular shape. Alternatively, the multiple electronic components 120 in the device group 110 may be arranged in a circular or elliptical shape to meet different usage requirements.

[0110] In some examples, as shown in FIG. 2C , the plurality of electronic components 120 in the device group 110 are electrically connected via connection lines 112 .

[0111] For example, multiple electronic components 120 in a device group 110 can be connected in series via the connecting wires 112. In this way, by providing an electrical signal to any electronic component 120 in a device group 110, it is possible to provide electrical signals to all electronic components 120 in the device group 110, thereby improving the wiring convenience of the substrate 100.

[0112] As can be seen from the above, in some examples, the substrate 100 can be used to provide a light source. In this case, the electronic component 120 can be a light-emitting device. For example, the electronic component 120 can be a light-emitting diode (LED).

[0113] In some examples, the electronic component 120 can be any one of a traditional LED, a sub-millimeter light emitting diode (full name: Mini Light Emitting Diode, English abbreviation: Mini LED) or a micro light emitting diode (full name: Micro Light Emitting Diode, English abbreviation: Micro LED).

[0114] For example, a traditional LED is an LED with a size greater than or equal to 500 μm. A Mini LED is an LED with a size greater than or equal to 100 μm and less than 500 μm. A Micro LED is an LED with a size less than 100 μm. In some examples, a Micro LED can be less than or equal to 50 μm.

[0115] In some examples, the electronic components 120 in each device group 110 can be used to emit light of the same color, for example, the electronic components 120 in each device group 110 are all used to emit white light, or the electronic components 120 in each device group 110 are all used to emit blue light, so that the substrate 100 can emit light of a specific color.

[0116] In some examples, the electronic components 120 in a device group 110 have the same luminance. The luminance of the electronic components 120 in different device groups 110 can be the same or different. By controlling the luminance of the electronic components 120 in different device groups 110, the brightness of different areas of the substrate 100 can be controlled to meet different usage requirements.

[0117] As can be seen from the above, in some embodiments, the electronic device 200 includes a substrate 100 and a display panel 210. In this case, the substrate 100 can be used to provide a light source. In other embodiments, the electronic device 200 may not include the display panel 210, but only include the substrate 100. In this case, the substrate 100 is used to display image information, and the electronic components 120 in each device group 110 can emit light of different colors.

[0118] For example, when the substrate 100 is used to display image information, a portion (one or more) of the device groups 110 are configured to emit red light, another portion (one or more) of the device groups 110 are configured to emit green light, and another portion (one or more) of the device groups 110 are configured to emit blue light. By controlling the luminous intensity of the electronic components 120 in different device groups 110, different intensities of red light, green light, and blue light can be obtained, enabling the electronic device 200 to achieve full-color image display.

[0119] The embodiments of the present disclosure are described by taking as an example that the substrate 100 uses glass as the substrate 101 , uses Mini LED as the electronic component 120 , and the substrate 100 serves as a light source providing component of the electronic device 200 .

[0120] In some examples, as shown in FIG2A and FIG2B , the substrate 100 further includes multiple signal line groups 130. The multiple signal line groups 130 and the multiple device groups 110 are located on the same side of the substrate 101. Each signal line group 130 includes multiple signal lines 131. The multiple signal lines 131 extend along the second direction Y and are arranged in intervals along the first direction X. Each signal line 131 extends from the bonding area BB to the device area AA and is electrically connected to a column of device groups 110 arranged along the second direction Y.

[0121] It can be understood that the lengths of multiple signal lines 131 are not exactly the same. The length of some signal lines along the second direction Y is basically equal to the length of a column of device groups along the second direction Y, while the length of another part of the signal lines along the second direction Y is less than the length of a column of device groups along the second direction Y.

[0122] It can be understood that the plurality of signal line groups 130 and the plurality of device groups 110 are located on the same side of the substrate 101 , so that the signal lines 131 in the signal line groups 130 can be electrically connected to the device groups 110 .

[0123] In some examples, multiple signal line groups 130 are disposed on the same layer, that is, multiple signal line groups 130 are disposed on the same conductive layer. It is understandable that in addition to the multiple signal line groups 130, other traces may also be disposed on the conductive layer.

[0124] In other examples, the signal lines 131 in the plurality of signal line groups 130 may be disposed on different conductive layers. For example, the signal lines 131 in the plurality of signal line groups 130 may be disposed on two conductive layers respectively.

[0125] Understandably, disposing multiple signal line groups 130 on different conductive layers provides greater routing flexibility for signal lines 131. However, if two signal lines 131 on different conductive layers have overlapping orthographic projections on substrate 101, short circuits are likely to occur, affecting the yield of substrate 100. Furthermore, since substrate 100 includes at least two conductive layers, the number of steps required to prepare substrate 100 increases, raising the production cost of substrate 100.

[0126] It can be understood that the arrangement of multiple signal line groups 130 on the same layer can reduce the steps of patterning the conductive layer, thereby simplifying the preparation process of the substrate 100, reducing the number of masks (full name in English: Mask), reducing the cost of the substrate 100, and also reducing the occurrence of adverse failures such as short circuits in the substrate 100, thereby improving the yield of the substrate 100.

[0127] The embodiment of the present disclosure is described by taking the case where multiple signal line groups 130 are arranged on the same layer as an example.

[0128] In some examples, the substrate 100 includes an insulating layer located on a side of the conductive layer away from the substrate 101 and covering the conductive layer. That is, the insulating layer can cover the plurality of signal line groups 130 disposed on the conductive layer and other conductive structures disposed on the conductive layer.

[0129] A signal line group 130 includes multiple signal lines 131. It is understood that the signal lines 131 are used to transmit signals, such as analog electrical signals or digital electrical signals. In some examples, the multiple signal line groups 130 can be used to transmit different signals or the same signal. Each signal line 131 in a signal line group 130 is used to transmit the same signal.

[0130] In some examples, the signal line 131 is made of metal or metal alloy. For example, the material of the signal line 131 may include copper or aluminum, etc., to improve the conductivity of the signal line 131.

[0131] In some examples, the number of signal lines 131 included in each signal line group 130 may be the same or different. The intervals between any two adjacent signal lines 131 in a signal line group 130 along the first direction X may be the same or different.

[0132] In some examples, the binding area BB is provided with bonding pins (not shown in the figure). The number of the bonding pins can be multiple, and the multiple binding pins are spaced apart along the first direction X. The signal line 131 is electrically connected to the binding pins in the binding area BB.

[0133] For example, as shown in FIG2A and FIG2B , one end of any signal line 131 is electrically connected to a binding pin in the binding area BB, and the other end extends along the second direction Y (or along the first direction X and the second direction Y) to extend from the binding area BB to the device area AA, and is electrically connected to a column of device groups 110 arranged along the second direction Y. It is understandable that the signal line 131 can be directly electrically connected to the electronic components 120 in the device group 110, or can be electrically connected to the electronic components 120 in the device group 110 through other components or conductive patterns.

[0134] In some examples, at least one signal line 131 is disposed between two columns of device groups 110 spaced apart along the first direction X to improve area utilization of the substrate 101 .

[0135] In some examples, as shown in FIG2A , there is one binding area BB, and multiple binding pins are provided within the binding area BB. For example, different signal line groups 130 are electrically connected to different binding pins to reduce mutual interference during signal transmission. Multiple signal lines 131 in the same signal line group 130 can be electrically connected to one binding pin or to multiple binding pins.

[0136] In some examples, when there is only one bonding area BB, the number of signal lines 131 in a signal line group 130 is the same as the number of columns in which the device groups 110 are arranged. That is, as shown in FIG2A , when multiple device groups 110 are arranged in three columns along the second direction Y, a signal line group 130 includes three signal lines 131. It will be appreciated that the three signal lines 131 in a signal line group 130 can be electrically connected to three bonding pins or to one bonding pin.

[0137] In other examples, as shown in FIG. 2B , there are multiple bonding areas BB, and multiple signal lines 131 in one signal line group 130 are electrically connected to one bonding area BB in the multiple bonding areas BB.

[0138] 2B , the signal line group 130 includes a first signal line group 130a, a second signal line group 130b, and a third signal line group 130c. The first signal line group 130a includes a first signal line 131a, the second signal line group 130b includes a second signal line 131b, and the third signal line group 130c includes a third signal line 131c.

[0139] It should be noted that the first signal line group 130a, the second signal line group 130b, and the third signal line group 130c are merely used to distinguish the three signal line groups 130 connected to different binding areas BB, and do not further define the signal line groups 130. The first signal line 131a, the second signal line 131b, and the third signal line group 130c are merely used to distinguish the signal lines 131 in the first signal line group 130a, the second signal line group 130b, and the third signal line group 130c, and do not further define the signal lines 131.

[0140] In some examples, the first signal line group 130 a , the second signal line group 130 b , and the third signal line group 130 c are used to transmit the same signal.

[0141] 2B , the binding area BB includes a first binding area BB1, a second binding area BB2, and a third binding area BB3. It should be noted that the first binding area BB1, the second binding area BB2, and the third binding area BB3 are only used to distinguish three different binding areas BB and do not further define the binding area BB.

[0142] For example, as shown in FIG2B , the plurality of first signal lines 131a in the first signal line group 130a are electrically connected to the bonding pins in the first bonding area BB1. The plurality of second signal lines 131b in the second signal line group 130b are electrically connected to the bonding pins in the second bonding area BB2. The third signal line 131c in the third signal line group 130c is electrically connected to the bonding pins in the third bonding area BB3. In this way, the plurality of signal lines 131 in a signal line group 130 can be electrically connected to one bonding area BB among the plurality of bonding areas BB.

[0143] Such an arrangement enables different binding areas BB to transmit signals to different signal line groups 130 , thereby reducing mutual interference generated during signal transmission and improving the reliability of the substrate 100 .

[0144] In some examples, as shown in FIG2B , a signal line 131 (e.g., first signal line 131a) in a signal line group 130 (e.g., first signal line group 130a) is electrically connected to a bonding pin within a bonding area BB (e.g., first bonding area BB1) adjacent to the signal line group 130. This reduces the length of the signal line 131, lowers the voltage drop across the signal line 131, and improves signal transmission reliability. Furthermore, this reduces the material usage of the signal line 131, thereby lowering the cost of the substrate 100.

[0145] In some examples, as shown in FIG2A , substrate 100 further includes a first driver chip 103. First driver chip 103 is electrically connected to at least one device group 110. That is, in some examples, as shown in FIG2D , first driver chip 103 is electrically connected to only one device group 110. In other examples, as shown in FIG2E , first driver chip 103 is electrically connected to four device groups 110 sequentially arranged along second direction Y.

[0146] It is understandable that one signal line 131 may be electrically connected to the first driving chip 103 , or electrically connected to one device group 110 or multiple device groups 110 .

[0147] In some examples, multiple device groups 110 arranged along the second direction Y are electrically connected to one first driver chip 103. In other examples, multiple device groups 110 arranged along the second direction Y are electrically connected to multiple first driver chips 103, respectively. For example, when multiple device groups 110 arranged along the second direction Y are electrically connected to multiple first driver chips 103, respectively, the multiple first driver chips 103 electrically connected to a column of device groups 110 are spaced apart along the second direction Y.

[0148] In some examples, as shown in Figures 2F and 2G, the device area AA includes a central area AA1 and an edge area AA2, and the edge area AA2 surrounds the central area AA1. Multiple device groups 110 are located in the central area AA1, and a portion (one or more) of the signal lines 131 can be located only in the edge area AA2, while another portion (one or more) of the signal lines 131 can be located in the edge area AA2 and the central area AA1. It will be understood that in order to clearly illustrate the positional relationship between a signal line group and the bridge portion, some components and other signal lines on the substrate are omitted in Figures 2F and 2G.

[0149] As shown in FIG2G , the edge region AA2 located between the central region AA1 and the bonding region BB along the second direction Y can be defined as the lower edge region AA22; and the two edge regions adjacent to the lower edge region AA22 along the second direction Y and located on both sides of the central region AA along the first direction X can be defined as the side edge regions AA21. In other words, the edge region AA2 includes the side edge regions AA21 and the lower edge region AA22. For example, the lower edge region AA22 can also be referred to as the fan-out region.

[0150] For example, as shown in Figures 2F and 2G, multiple signal lines 131 extend along the second direction Y (or along the first direction X and the second direction Y) via the binding area BB to the lower edge area AA22. A portion (one or more, such as the fifth signal line 131e shown in Figure 2F) of the signal lines 131 extend from the lower edge area AA22 to the side edge area AA21 and are electrically connected to a column of device groups 110. That is, the fifth signal line 131e is located in the edge area AA2. Another portion (one or more, such as the fourth signal line 131d shown in Figure 2F) of the signal lines 131 extend from the lower edge area AA22 to the device area AA and are electrically connected to a column of device groups 110.

[0151] It should be noted that, in the embodiment of the present disclosure, the fourth signal line 131d and the fifth signal line 131e are only used to distinguish the signal line 131 located in the device area AA and electrically connected to the device group 110, and the signal line 131 located in the side edge area AA21 and electrically connected to the device group 110, and no further limitation is imposed on the signal line 131.

[0152] Since the length of the signal line 131 extending along the second direction Y is related to the length dimension of the substrate 100 along the second direction Y, in some implementations, in order to minimize the inherent voltage drop (full name: IR Drop) of the signal line 131 as much as possible, the resistance of the signal line 131 can be reduced by increasing the width of the signal line 131 along the first direction X or increasing the thickness of the signal line 131.

[0153] For example, taking a 55-inch substrate 100 as an example, the width of the side edge area AA21 along the first direction X is approximately 4.125 mm, and the width of the lower edge area AA22 along the second direction Y is approximately 4.62 mm. To ensure that the voltage drop of the signal line 131 meets the requirements, the width of a portion (one or more) of the signal lines 131 along the first direction X needs to be set between 2 mm and 15 mm.

[0154] For example, as shown in FIG2F , the width of the fifth signal line 131e along the first direction X needs to be greater than 3 mm (e.g., greater than 3.5 mm). Furthermore, in addition to the fifth signal line 131e, other signal lines 131 are typically provided within the side edge area AA21. In other words, increasing the width of the signal line 131 along the first direction X to reduce voltage drop increases the difficulty of wiring within the side edge area AA21 and increases the width of the side edge area AA21 along the first direction X, hindering the realization of a narrow bezel for the substrate 100.

[0155] On the other hand, increasing the thickness of the signal line 131 to reduce the voltage drop will increase the amount of material used for the signal line 131 and increase the manufacturing cost of the substrate 100 .

[0156] FIG3A is a structural diagram of a substrate according to yet other embodiments. FIG3B is a structural diagram of a substrate according to yet other embodiments. FIG3C is a structural diagram of a substrate according to yet other embodiments. FIG3D is a structural diagram of a substrate according to yet other embodiments. FIG3E is a structural diagram of a substrate according to yet other embodiments. FIG3F is a structural diagram of a substrate according to yet other embodiments.

[0157] Based on this, as shown in Figures 3A to 3F , in an embodiment of the present disclosure, the substrate 100 includes, in addition to a substrate 101, multiple device groups 110, and multiple signal line groups 130, multiple conductive patterns 170. It will be appreciated that the above embodiments of the present disclosure have already provided examples for the substrate 101, multiple device groups 110, and multiple signal line groups 130, and will not be further described here. The multiple conductive patterns 170 will now be described with reference to Figures 3A to 3F .

[0158] In some examples, as shown in Figures 3A and 3B, multiple conductive patterns 170 and multiple device groups 110 are located on the same side of the substrate 101. At least one conductive pattern 170 among the multiple conductive patterns 170 is located within a region where one device group 110 is located, and / or at least one conductive pattern 170 among the multiple conductive patterns 170 is located between two adjacent device groups 110. At least one signal line 131 in at least one signal line group 130 is electrically connected to one conductive pattern 170.

[0159] It will be understood that a device group 110 includes multiple electronic components 120, and the region within which a device group 110 is located refers to a closed virtual region formed by connecting the boundaries of the outermost electronic components 120 of the device group in a clockwise or counterclockwise direction. In some examples, when the multiple electronic components 120 in a device group 110 are arranged in a matrix, the region within which a device group 110 is located is rectangular, and the multiple electronic components 120 in the device group 110 are all located within the rectangular region.

[0160] In other examples, when a device group 110 includes only one electronic component 120 , the area where the device group 110 is located is also a rectangular area surrounding the electronic component 120 .

[0161] As will be appreciated, conductive pattern 170 is capable of conducting electricity. In some examples, the material of conductive pattern 170 includes copper or aluminum to improve the conductivity of conductive pattern 170. For example, conductive pattern 170 can be rectangular, convex polygonal, or other irregular shapes. The shapes of each conductive pattern 170 can be the same or different.

[0162] The plurality of conductive patterns 170 and the plurality of device groups 110 are located on the same side of the substrate 101. As can be seen from the above description, the plurality of signal line groups 130 and the plurality of device groups 110 are also located on the same side of the substrate 101. That is, the plurality of conductive patterns 170, the plurality of signal line groups 130, and the plurality of device groups 110 are all located on the same side of the substrate 101. This allows the conductive patterns 170 to be electrically connected to the signal lines 131.

[0163] In some examples, the plurality of conductive patterns 170 and the plurality of signal line groups 130 may be provided on the same layer to simplify the preparation process of the substrate 100 and reduce the production cost of the substrate 100. In other examples, the plurality of conductive patterns 170 and the plurality of signal line groups 130 may also be provided on different layers to reduce mutual interference therebetween.

[0164] In some examples, the plurality of conductive patterns 170 are all located in the device area AA. In other examples, the plurality of conductive patterns 170 are located in the device area AA and the bonding area BB.

[0165] In some examples, as shown in FIG. 3A and FIG. 3B , at least one conductive pattern 170 among the plurality of conductive patterns 170 is located in a region where one device group 110 is located.

[0166] 3A and 3B , at least one conductive pattern 170 among the plurality of conductive patterns 170 may also be located in a region between two adjacent device groups 110. For example, at least one conductive pattern 170 may be located in a region between two adjacent device groups 110 along the second direction Y, and at least one conductive pattern 170 may also be located in a region between two adjacent device groups 110 along the first direction X.

[0167] As can be understood, as shown in Figures 3A and 3B , any conductive pattern 170 can avoid the electronic components 120, the connecting wires 112 that electrically connect two adjacent electronic components 120, and the multiple signal line groups 130. That is, the orthographic projection of the conductive pattern 170 on the substrate 101 is located outside the orthographic projection of the electronic components 120 on the substrate 101, the orthographic projection of the connecting wires 112 on the substrate 101, and the orthographic projection of the multiple signal line groups 130 on the substrate 101. This configuration can reduce mutual interference between the conductive pattern 170 and the device group 110 and the signal line group 130, thereby improving the reliability of the substrate 100.

[0168] It can be understood that since at least one conductive pattern 170 is located in the area where a device group 110 is located, and / or at least one conductive pattern 170 is located in the area between two adjacent device groups 110, at least one signal line 131 in at least one signal line group 130 can be electrically connected to a conductive pattern 170.

[0169] In some examples, as shown in FIG3C , each signal line 131 in each signal line group 130 is electrically connected to the conductive pattern 170. In other examples, one signal line 131 in each signal line group 130 is electrically connected to the conductive pattern 170. In still other examples, one signal line 131 in a signal line group 130 is electrically connected to the conductive pattern 170. It is understood that the conductive pattern 170 and the signal line 131 can be electrically connected directly or through other components or traces.

[0170] 3A and 3B , at least two signal lines 131 in the same signal line group 130 may be electrically connected to the same conductive pattern 170 . It is understood that signal lines 131 in different signal line groups 130 may be electrically connected to different conductive patterns 170 .

[0171] As can be understood, since the conductive pattern 170 is electrically conductive, electrically connecting at least one signal line 131 in at least one signal line group 130 to a conductive pattern 170 allows the conductive pattern 170 to compensate for the voltage drop on the signal line 131. In other words, electrically connecting the conductive pattern 170 to the signal line 131 can reduce the resistance of the signal transmission path (i.e., the electrically connected signal line 131 and the conductive pattern 170), reduce the voltage drop on the signal transmission path (i.e., the electrically connected signal line 131 and the conductive pattern 170), and thus reduce the voltage drop on the signal line 131. This can reduce signal loss during transmission, improve signal transmission reliability, and enhance the luminous efficiency of the electronic component 120.

[0172] It can be understood that after the conductive pattern 170 is electrically connected to the signal line 131, the voltage drop of the signal line 131 can be reduced. Therefore, even if the width of the signal line 131 along the first direction X is set to be smaller, or the thickness of the signal line 131 is set to be smaller, the compensation effect of the conductive pattern 170 can still ensure that the voltage drop of the signal line 131 can meet the requirements.

[0173] That is, by providing the conductive pattern 170 electrically connected to the signal line 131, on the one hand, the width of the signal line 131 along the first direction X is reduced, thereby reducing the space occupied by the signal line 131 on the substrate 101 and improving the wiring convenience of the substrate 100. On the other hand, it is also helpful to reduce the thickness of the signal line 131, thereby reducing the amount of material used for the signal line 131 and reducing the cost of the substrate 100.

[0174] In addition, as shown in Figure 3C, when the signal line 131 (for example, the fifth signal line 131e) located in the side edge area AA21 is electrically connected to the conductive pattern 170, the width of the signal line 131 along the first direction X is reduced, and the space occupied by the signal line 131 in the side edge area AA21 can also be reduced, thereby facilitating the reduction of the width of the side edge area AA21 and facilitating the realization of a narrow frame (side frame) of the substrate 100.

[0175] Moreover, when the signal line 131 (for example, the fifth signal line 131e) located in the side edge area AA21 is electrically connected to the conductive pattern 170, the voltage drop of the signal line 131 in the side edge area AA21 can be reduced, thereby improving the electrical performance of the signal line 131 in the side edge area AA21.

[0176] It can be understood that when the area of ​​the substrate 101 is determined, the narrower the border of the substrate 100, the greater the number of device groups 110 that can be arranged. When the electronic components 120 included in the device group 110 are light-emitting elements, the greater the overall brightness of the substrate 100, which can improve the performance of the substrate 100.

[0177] Furthermore, since the conductive pattern 170 can avoid the device group 110 and the signal line group 130 , etc., the provision of the conductive pattern 170 does not affect the function of the substrate 100 , thereby improving the reliability of the substrate 100 .

[0178] As can be seen from the above, the multiple electronic components 120 in the device group 110 are electrically connected via the connecting wires 112. In some examples, as shown in FIG3C , the multiple connecting wires 112 in a device group 110 are spaced apart. The electronic component 120 includes two pins, one pin is welded to one end of one connecting wire 112, and the other pin is welded to one end of the other connecting wire 112. In this way, as shown in FIG2F , after being welded to the connecting wires 112, the electronic component 120 can be located within the region Q (see FIG3A and FIG3B for the positional relationship diagram of the electronic component 120 and the connecting wire 112 after being welded).

[0179] It can be understood that, except for the area where the connecting wire 112 is connected to the pin, which is exposed by the insulating layer, the other areas are covered by the insulating layer.

[0180] In some embodiments, the plurality of conductive patterns 170 and the plurality of signal line groups 130 are disposed on the same layer.

[0181] Understandably, "same layer" refers to a single film-forming process used to form the entire layer structure, followed by a patterning process to create specific patterns in different areas. Depending on the specific pattern, the patterning process may include at least one exposure, development, or etching process, and each specific pattern may be continuous or discontinuous, and may also have different heights or thicknesses.

[0182] In some examples, the plurality of conductive patterns 170 and the plurality of signal line groups 130 may be formed in the same layer and made of the same material, thereby simplifying the preparation process of the substrate 100 and reducing production costs.

[0183] The following is an example of a method for preparing the substrate 100 .

[0184] In some examples, the substrate 101 is made of glass. For example, a magnetron sputtering process can be used to form a buffer layer on one side of the substrate 101. For example, the buffer layer can be made of at least one of tungsten, titanium, nickel, aluminum, a nickel alloy, and a titanium-tungsten alloy.

[0185] A conductive layer is formed on the side of the buffer layer away from the substrate 101. For example, the conductive layer comprises copper. In some examples, a magnetron sputtering process can be used to form the conductive layer on the side of the buffer layer away from the substrate 101. In other examples, an electroplating process can be used to form the conductive layer on the side of the buffer layer away from the substrate 101. In still other examples, a magnetron sputtering process and an electroplating process can be used to form the conductive layer on the side of the buffer layer away from the substrate 101.

[0186] The conductive layer is patterned through processes such as cleaning, coating, baking, imaging, developing, hard baking, etching and stripping to form multiple signal line groups 130 and multiple conductive patterns 170.

[0187] An insulating layer is formed on a side of the patterned conductive layer away from the substrate 101. The insulating layer can cover the conductive layer to provide electrical isolation. For example, the insulating layer can be formed using a magnetron sputtering process, or chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0188] It can be understood that multiple conductive patterns 170 and multiple signal line groups 130 are arranged on the same layer. On the one hand, it can simplify the process steps when patterning the conductive layer, reduce the number of masks, and reduce the BOM (full name: Bill of Material, English abbreviation: BOM) cost, thereby reducing the production cost of the substrate 100.

[0189] On the other hand, the multiple conductive patterns 170 and the multiple signal line groups 130 are arranged on the same layer, which can increase the area of ​​the orthographic projection of the conductive structure on the conductive layer (eg, the signal line group 130 and the conductive patterns 170 ) on the substrate 101 .

[0190] For example, when the conductive pattern 170 is not provided, the area of ​​the orthographic projection of the conductive structure (the plurality of signal line groups 130) on the conductive layer on the substrate 101 is approximately 20% of the area of ​​the substrate 101. However, after the conductive pattern 170 is provided, the area of ​​the orthographic projection of the conductive structure (the plurality of signal line groups 130 and the plurality of conductive patterns 170) on the conductive layer on the substrate 101 is approximately 75% of the area of ​​the substrate 101.

[0191] That is, taking the conductive layer material as Cu as an example, multiple conductive patterns 170 and multiple signal line groups 130 are arranged on the same layer, which can increase the ratio of the area of ​​Cu in the conductive layer to the area of ​​the substrate 101 from about 20% to about 75%, thereby increasing the area of ​​Cu in the conductive layer, thereby reducing the amount of etching solution used in the etching process and reducing the cost of the substrate 100.

[0192] 3A and 3B , the substrate 100 further includes a plurality of bridges 140. The plurality of bridges 140 and the plurality of device groups 110 are located on the same side of the substrate 101, and at least one bridge 140 is located in the device area AA.

[0193] As will be appreciated, the bridge portion 140 functions as a conductor. In some examples, the bridge portion 140 is made of a conductive material, such as copper or aluminum. In other examples, the bridge portion 140 may also be an electrical component, such as a resistor or capacitor. As will be appreciated, the multiple bridge portions 140 may be identical or different.

[0194] It can be understood that the bridges 140 and the device groups 110 are located on the same side of the substrate 101 . That is, the bridges 140 , the device groups 110 , the conductive patterns 170 and the signal line groups 130 are located on the same side of the substrate 101 .

[0195] It can be understood that at least one bridge portion 140 is located in the device area AA, so that the at least one bridge portion 140 can be electrically connected to the conductive pattern 170 and / or the at least one bridge portion 140 can be electrically connected to the signal line 131 .

[0196] As can be seen from the above, the multiple conductive patterns 170 and the multiple signal line groups 130 are arranged on the same layer. In some examples, the multiple bridges 140 are located on a side of the multiple conductive patterns 170 and the multiple signal line groups 130 away from the substrate 101, thereby preventing the bridges 140 from affecting the signal lines 131 and the conductive patterns 170.

[0197] In some examples, a protective layer is provided on a side of the plurality of bridge portions 140 away from the substrate 101 . The protective layer can cover the plurality of bridge portions 140 to perform electrical isolation and also protect the plurality of bridge portions 140 .

[0198] In some embodiments, as shown in FIG. 3A and FIG. 3B , the plurality of signal line groups 130 include a first voltage line group 150 , and the first voltage line group 150 includes a plurality of first voltage lines 151 .

[0199] In some examples, the first voltage line 151 is used to power the electronic components 120 in each device group 110. For example, as shown in Figures 3A and 3B , one end of the first voltage line 151 is electrically connected to the bonding pins in the bonding area BB, and the other end extends to the device area AA and is electrically connected to a column of device groups 110 arranged along the second direction Y. In other words, the device groups 110 arranged in the column along the second direction Y share one first voltage line 151.

[0200] In some examples, as shown in FIG3A and FIG3B , a first voltage line 151 in the first voltage line group 150 may be located in the side edge region AA21 , so that the first voltage line 151 can be electrically connected to a column of device groups 110 adjacent to the side edge region AA21 along the first direction X.

[0201] In some examples, as shown in FIG. 3D , the substrate 100 further includes a circuit board 107 , and the circuit board 107 is electrically connected to the bonding area BB.

[0202] For example, as shown in FIG3D , circuit board 107 includes a flexible printed circuit (FPC) 105 and a printed circuit board (PCB) 106. One end of FPC 105 is bonded to binding pins within a bonding area BB, and the other end is bonded to PCB 106, enabling signal transmission between multiple signal line groups 130 and PCB 106, thereby driving multiple device groups 110.

[0203] In some examples, the power supply outside the substrate 100 is electrically connected to the first voltage line 151 through the printed circuit board 106 and the binding pins, so that the power supply can power the electronic components 120 in a column of device groups 110 through the first voltage line 151, thereby enabling the electronic components 120 to emit light.

[0204] In some examples, as shown in FIG. 3A and FIG. 3B , the plurality of signal line groups 130 further include a second voltage line group 160 , and the second voltage line group 160 includes a plurality of second voltage lines 161 .

[0205] In some examples, a second voltage line (full name: Ground, abbreviated as GND) 161 is used to ground the first driver chip 103. For example, as shown in Figures 3A and 3B , one end of the second voltage line 161 is electrically connected to a binding pin in the binding area BB, and the other end extends to the device area AA and is electrically connected to the first driver chip 103. As can be seen from the above, the first driver chip 103 is electrically connected to the device group 110. In this way, the second voltage line 161 can be electrically connected to the device group 110 through the first driver chip 103.

[0206] In some examples, as shown in FIG. 3A and FIG. 3B , a second voltage line 161 in the second voltage line group 160 may be located in the side edge region AA21 , so that the second voltage line 161 can be electrically connected to a column of device groups 110 adjacent to the side edge region AA21 along the first direction X.

[0207] In some examples, as shown in FIG3E , the first driver chip 103 includes a first output port CH1, a second output port CH2, a third output port CH3, and a fourth output port CH4. The first output port CH1, the second output port CH2, the third output port CH3, and the fourth output port CH4 are electrically connected to four device groups 110, respectively, so that one first driver chip 103 can be electrically connected to four device groups 110.

[0208] 3D and 3E , the substrate 100 further includes a second driver chip 104 . For example, the second driver chip 104 may be disposed on a printed circuit board 106 .

[0209] In some examples, the second driver chip 104 is a Tx IC (Transmit Integrated Circuit), and the first driver chip 103 is an Rx IC (Receive Integrated Circuit). Signals emitted by the second driver chip 104 are transmitted to the first driver chip 103 via binding pins and a signal line group 130 (e.g., a second voltage line group 160), thereby driving the device group 110.

[0210] In some examples, as shown in FIG3E , the second driver chip 104 has a first ground port GNDa and a second ground port GNDb. The first driver chip 103 also has a first ground port GND1 and a second ground port GND2. The second voltage line 161 includes a first second voltage line 161a and a second voltage line 161b.

[0211] As shown in FIG3E , one end of the first second voltage line 161a is electrically connected to the first ground port GNDa of the second driver chip 104 via a binding pin in the binding area BB. The other end of the first second voltage line 161a is electrically connected to the first ground port GND1 of the first driver chip 103. One end of the second second voltage line 161b is electrically connected to the second ground port GNDb of the second driver chip 104 via a binding pin in the binding area BB. The other end of the second second voltage line 161b is electrically connected to the second ground port GND2 of the first driver chip 103.

[0212] It should be noted that the first second voltage line 161 a and the second second voltage line 161 b are only used to distinguish the two second voltage lines 161 , and do not further limit the second voltage line 161 .

[0213] In other examples, the first driver chip 103 may also include only one ground port. In this case, one end of a second voltage line 161 is electrically connected to the ground port of the second driver chip 104 through the binding pin of the binding area BB, and the other end is electrically connected to the ground port of the first driver chip 103 to ground the first driver chip 103.

[0214] In some examples, as shown in FIG. 3E , when a column of device groups 110 arranged along the second direction Y is electrically connected to multiple first driver chips 103 , the multiple first driver chips 103 electrically connected to the same column of device groups 110 may share one second voltage line 161 .

[0215] As shown in FIG. 3A and FIG. 3B , the plurality of conductive patterns 170 includes a plurality of first conductive patterns 171 , and the plurality of first conductive patterns 171 are electrically connected to at least one first voltage line 151 in the first voltage line group 150 .

[0216] In some examples, one first voltage line 151 in the first voltage line group 150 is electrically connected to the first conductive pattern 171 . In other examples, all of the first voltage lines 151 in the first voltage line group 150 are electrically connected to the first conductive pattern 171 .

[0217] In some examples, as shown in FIG. 3A and FIG. 3B , at least two first voltage lines 151 are electrically connected to the same first conductive pattern 171 .

[0218] As can be seen from the above, the first voltage line 151 is used to provide a constant voltage high-level signal to the electronic components 120 in each device group 110. Therefore, the width of the first voltage line 151 along the first direction X is generally large. Thus, providing the first conductive pattern 171 electrically connected to at least one first voltage line 151 in the first voltage line group 150 can, on the one hand, improve the transmission reliability of the power supply signal, thereby improving the luminous efficiency of the electronic component 120. On the other hand, it helps to reduce the width of the first voltage line 151 along the first direction X, thereby improving the wiring convenience of the substrate 100. Furthermore, it also helps to reduce the thickness of the first voltage line 151, thereby reducing the material consumption of the first voltage line 151 and reducing the cost of the substrate 100.

[0219] As shown in Figures 3A and 3B, one of the first voltage lines 151 in the first voltage line group 150 can be located in the side edge area AA21. For example, the first conductive pattern 171 can be electrically connected to the first voltage line 151 located in the side edge area AA21 to reduce the width of the first voltage line 151 located in the side edge area AA21 along the first direction X, thereby facilitating the reduction of the width of the side edge area AA21 along the first direction X, and facilitating the realization of a narrow frame (side frame) of the substrate 100.

[0220] In some embodiments, the width of the first voltage line 151 along the first direction X ranges from 0.5 mm to 1 mm.

[0221] It can be understood that when the conductive pattern 170 is not provided, in order to meet the voltage drop requirement, the width of the first voltage line 151 along the first direction X ranges from 2 mm to 15 mm.

[0222] In the embodiment of the present disclosure, a first conductive pattern 171 is electrically connected to the first voltage line 151, so that the first conductive pattern 171 can compensate for the voltage drop of the first voltage line 151, which is beneficial to reducing the width of the first voltage line 151 along the first direction X, so that the value range of the width of the first voltage line 151 along the first direction X can be reduced to 0.5 mm to 1 mm, which is beneficial to achieving a narrow frame of the substrate 100.

[0223] It is understandable that the width of the first voltage line 151 along the first direction X is set to a value range of 0.5 mm to 1 mm, which prevents the width of the first voltage line 151 along the first direction X from being too large (for example, greater than 1 mm), thereby facilitating a narrow frame of the substrate 100. In addition, the width of the first voltage line 151 along the first direction X is prevented from being too small (for example, less than 0.5 mm), thereby improving the transmission reliability of the constant voltage high-level signal.

[0224] In some examples, the width of the first voltage line 151 along the first direction X may range from 0.6 mm to 0.9 mm or from 0.7 mm to 0.8 mm, etc. For example, the width of the first voltage line 151 along the first direction X may range from 0.6 mm to 0.9 mm or from 0.7 mm to 0.8 mm, etc.

[0225] It can be understood that the widths of the plurality of first voltage lines 151 along the first direction X may be the same or different.

[0226] In some embodiments, as shown in FIG. 3A and FIG. 3B , the plurality of conductive patterns 170 includes a plurality of second conductive patterns 172 , and the plurality of second conductive patterns 172 is electrically connected to at least one second voltage line 161 in the second voltage line group 160 .

[0227] In some examples, one second voltage line 161 in the second voltage line group 160 is electrically connected to the second conductive pattern 172 . In other examples, all of the second voltage lines 161 in the second voltage line group 160 are electrically connected to the second conductive pattern 172 .

[0228] In some examples, as shown in FIG. 3A and FIG. 3B , at least two second voltage lines 161 are electrically connected to the same second conductive pattern 172 .

[0229] As can be seen from the above, the second voltage line 161 is used to ground the first driver chip 103. Therefore, the width of the second voltage line 161 along the first direction X is generally large. Thus, providing the second conductive pattern 172 electrically connected to at least one second voltage line 161 in the second voltage line group 160 can, on the one hand, improve the transmission reliability of the power supply signal. On the other hand, it helps to reduce the width of the second voltage line 161 along the first direction X, thereby improving the wiring convenience of the substrate 100. Furthermore, it also helps to reduce the thickness of the second voltage line 161, thereby reducing the material consumption of the second voltage line 161 and reducing the cost of the substrate 100.

[0230] As shown in Figures 3A and 3B, one of the second voltage lines 161 in the second voltage line group 160 can be located in the side edge area AA21. For example, the second conductive pattern 172 can be electrically connected to the second voltage line 161 located in the side edge area AA21 to reduce the width of the second voltage line 161 located in the side edge area AA21 along the first direction X, thereby facilitating the reduction of the width of the side edge area AA21 along the first direction X, and facilitating the realization of a narrow frame (side frame) of the substrate 100.

[0231] In some embodiments, the width of the second voltage line 161 along the first direction X ranges from 0.5 mm to 1 mm.

[0232] It can be understood that when the conductive pattern 170 is not provided, in order to meet the voltage drop requirement, the width of the second voltage line 161 along the first direction X ranges from 2 mm to 15 mm.

[0233] In the embodiment of the present disclosure, a second conductive pattern 172 is provided to be electrically connected to the second voltage line 161, so that the second conductive pattern 172 can compensate for the voltage drop of the second voltage line 161, which is beneficial to reducing the width of the second voltage line 161 along the first direction X, so that the value range of the width of the second voltage line 161 along the first direction X can be reduced to 0.5 mm to 1 mm, which is beneficial to achieving a narrow frame of the substrate 100.

[0234] It is understood that the width of the second voltage line 161 along the first direction X is set to a value range of 0.5 mm to 1 mm, which prevents the width of the second voltage line 161 along the first direction X from being too large (for example, greater than 1 mm), thereby facilitating a narrow frame of the substrate 100. In addition, the width of the second voltage line 161 along the first direction X is prevented from being too small (for example, less than 0.5 mm), thereby improving the transmission reliability of the electrical signal.

[0235] In some examples, the width of the second voltage line 161 along the first direction X may range from 0.6 mm to 0.9 mm or from 0.7 mm to 0.8 mm, etc. For example, the width of the second voltage line 161 along the first direction X may range from 0.6 mm to 0.9 mm or from 0.7 mm to 0.8 mm, etc.

[0236] It is understandable that the widths of the second voltage lines 161 along the first direction X may be the same or different. The width of the first voltage line 151 along the first direction X may be the same as or different from the width of the second voltage line 161 along the first direction X.

[0237] In some embodiments, as shown in FIG. 3A and FIG. 3B , a first voltage line 151 electrically connected to a column of device groups 110 and a second voltage line 161 electrically connected to the column of device groups 110 are spaced apart along the first direction X.

[0238] In some examples, as shown in FIG. 3A and FIG. 3B , a first voltage line 151 is located on one side of the central area AA1 along the first direction X, and a second voltage line 161 is located on a side of the central area AA1 away from the first voltage line 151 along the first direction X.

[0239] 3A and 3B , any first voltage line 151 is located along the first direction X on a first side of a column of device groups 110 electrically connected to the first voltage line 151. It is understood that the first side may be either side of the column of device groups 110 along the first direction X.

[0240] In some examples, as shown in FIG3A and FIG3B , the first voltage line 151 and the first driver chip 103 electrically connected to the same column of device groups 110 are located on opposite sides of the column of device groups 110 along the first direction X. For example, a first end of the device group 110 is electrically connected to the first driver chip 103, and a second end is electrically connected to the first voltage line 151, and the first end and the second end are arranged opposite each other along the first direction X, so that the first voltage line 151 and the first driver chip 103 electrically connected to the same column of device groups 110 can be located on opposite sides of the column of device groups 110 along the first direction X.

[0241] 3A and 3B , any second voltage line 161 is located along the first direction X on the second side of a column of device groups 110 electrically connected to the second voltage line 161. It is understood that the second side may be either side of the column of device groups 110 along the first direction X.

[0242] As can be seen from the above, any first voltage line 151 is located along the first direction X on a first side of a column of device groups 110 electrically connected to the first voltage line 151. In some examples, the first side and the second side are opposite sides of a column of device groups 110 along the first direction X. That is, as shown in Figures 3A and 3B, the first voltage line 151 and the second voltage line 161 electrically connected to a column of device groups 110 are located on both sides of the column of device groups 110 along the first direction X. This arrangement reduces the mutual influence between the first voltage line 151 and the second voltage line 161.

[0243] In some examples, as shown in FIG. 3A and FIG. 3B , the second voltage line 161 and the first driving chip 103 electrically connected to the same column of device groups 110 are located on the same side of the column of device groups 110 along the first direction X.

[0244] As can be seen from the above, the substrate 100 includes a plurality of bridges 140. In some embodiments, as shown in FIG3A and FIG3B, the substrate 100 further includes a plurality of first bridges 141, and at least one first conductive pattern 171 is electrically connected to a first voltage line 151 via the first bridge 141.

[0245] For example, as shown in Figures 3A and 3B, one end of the first bridge portion 141 is electrically connected to the first conductive pattern 171, and the other end is electrically connected to the first voltage line 151, so that at least one first conductive pattern 171 can be electrically connected to the first voltage line 151 through the first bridge portion 141.

[0246] As can be seen from the above, the insulating layer can cover the conductive layer (that is, the insulating layer can cover the multiple signal line groups 130 and the multiple conductive patterns 170) to provide electrical isolation. In some examples, after forming the insulating layer, a first through-hole can be opened in the insulating layer, and the first bridge portion 141 is electrically connected to the first conductive pattern 171 and the first voltage line 151 through the first through-hole.

[0247] It can be understood that by setting the first bridging portion 141, even if other conductive structures (such as other signal lines 131) are set between the first conductive pattern 171 and the first voltage line 151, the first bridging portion 141 can electrically connect the two, thereby improving the wiring flexibility of the substrate 100 and meeting different usage requirements.

[0248] Furthermore, by adjusting the width and thickness of the first bridge portion 141, the current carrying capacity of the first bridge portion 141 can be adjusted. In some examples, the width and thickness of the first bridge portion 141 can be increased to provide a greater current carrying capacity. In other examples, the width and thickness of the first bridge portion 141 can be reduced to provide a smaller current carrying capacity, thereby meeting different usage requirements and improving the applicability of the substrate 100.

[0249] In some embodiments, as shown in FIG. 3A and FIG. 3B , at least one first conductive pattern 171 and one first voltage line 151 form an integral structure.

[0250] It is understandable that the first conductive pattern 171 and the first voltage line 151 form an integral structure, that is, the first conductive pattern 171 and the first voltage line 151 are directly electrically connected, and no other conductive structure (such as the first bridge portion 141 ) is disposed therebetween.

[0251] Providing at least one first conductive pattern 171 and a first voltage line 151 to form an integrated structure can improve the reliability of the electrical connection between the first conductive pattern 171 and the first voltage line 151, and eliminates the need to provide other conductive structures, thereby simplifying the structure of the substrate 100 and reducing the cost of the substrate 100.

[0252] It can be understood that when multiple first conductive patterns 171 are electrically connected to the first voltage line 151, a part (one or more) of the first conductive patterns 171 can be electrically connected to the first voltage line 151 through the first bridging portion 141, and another part (one or more) of the first conductive patterns 171 can form an integrated structure with the first voltage line 151.

[0253] In some embodiments, as shown in FIG. 3A and FIG. 3B , the substrate 100 further includes a plurality of second bridge portions 142 , and at least one second conductive pattern 172 is electrically connected to one second voltage line 161 through the second bridge portion 142 .

[0254] 3A and 3B , one end of the second bridge portion 142 is electrically connected to the second conductive pattern 172 , and the other end is electrically connected to the second voltage line 161 , so that at least one second conductive pattern 172 can be electrically connected to the second voltage line 161 through the second bridge portion 142 .

[0255] As can be seen from the above, the insulating layer can cover the conductive layer (that is, the insulating layer can cover the multiple signal line groups 130 and the multiple conductive patterns 170) to provide electrical isolation. In some examples, after the insulating layer is formed, a second through hole can be opened in the insulating layer, and the second bridge portion 142 is electrically connected to the second conductive pattern 172 and the second voltage line 161 through the first through hole.

[0256] It can be understood that by setting the second bridging portion 142, even if other conductive structures (such as other signal lines 131) are set between the second conductive pattern 172 and the second voltage line 161, the second bridging portion 142 can electrically connect the two, thereby improving the wiring flexibility of the substrate 100 and meeting different usage requirements.

[0257] Furthermore, by adjusting the width and thickness of the second bridging portion 142, the current carrying capacity of the second bridging portion 142 can be adjusted. In some examples, the width and thickness of the second bridging portion 142 can be increased to provide a greater current carrying capacity. In other examples, the width and thickness of the second bridging portion 142 can be reduced to provide a smaller current carrying capacity, thereby meeting different usage requirements and improving the applicability of the substrate 100.

[0258] As can be seen from the above, two adjacent electronic components 120 are electrically connected via the connecting wire 112. In some examples, the connecting wire 112 is also provided in the conductive layer, that is, the connecting wire 112 is provided in the same layer as the plurality of signal line groups 130 and the plurality of conductive patterns 170 (including the first conductive pattern 171 and the second conductive pattern 172). A third through hole is also provided in the insulating layer, exposing a portion of the connecting wire 112. The exposed surface area of ​​the connecting wire 112 constitutes a pad, electrically connecting the pins of the electronic component 120 to the pad. Multiple electronic components 120 in a device group 110 can be connected in series via the connecting wire 112.

[0259] The following is an example of a method for opening through holes (including a first through hole, a second through hole, and a third through hole) in an insulating layer.

[0260] In some examples, a photoresist layer can be formed on the side of the insulating layer away from the conductive layer through processes such as coating, imaging, and development. The photoresist layer is patterned through an etching process to expose the insulating layer at the locations where holes are to be opened. The exposed insulating layer is then removed through an etching process to form through-holes (including the first through-hole, the second through-hole, and the third through-hole).

[0261] In some examples, after the insulating layer is patterned, the electronic component 120 can be soldered to the pad first, and then the bridging portion 140 (including the first bridging portion 141 and the second bridging portion 142) can be electrically connected to the signal line 131 (including the first voltage line 151 and the second voltage line 161) and the conductive pattern 170 (including the first conductive pattern 171 and the second conductive pattern 172).

[0262] In some embodiments, as shown in FIG. 3F , at least one second conductive pattern 172 and one second voltage line 161 form an integrated structure.

[0263] It is understandable that the second conductive pattern 172 and the second voltage line 161 form an integral structure, that is, the second conductive pattern 172 and the second voltage line 161 are directly electrically connected, and no other conductive structure (such as the first bridge portion 141 ) is disposed therebetween.

[0264] Providing at least one second conductive pattern 172 and a second voltage line 161 to form an integrated structure can improve the reliability of the electrical connection between the second conductive pattern 172 and the second voltage line 161, and eliminates the need to provide other conductive structures, thereby simplifying the structure of the substrate 100 and reducing the cost of the substrate 100.

[0265] It can be understood that when multiple second conductive patterns 172 are electrically connected to the second voltage line 161, a part (one or more) of the second conductive patterns 172 can be electrically connected to the second voltage line 161 through the first bridging portion 141, and another part (one or more) of the second conductive patterns 172 can form an integrated structure with the second voltage line 161.

[0266] In some embodiments, at least one of the plurality of bridge portions 140 is a jumper resistor.

[0267] It is understood that a jumper resistor is a special-purpose resistor with a very small resistance value, not completely zero. In some examples, an automatic placement machine or an automatic insertion machine can be used to place the jumper resistor between two points on the substrate 100 that cannot be directly connected by a line to achieve an electrical connection between the two points.

[0268] In some examples, all of the multiple bridge portions 140 may be jumper resistors. In other examples, a portion (one or more) of the multiple bridge portions 140 may be jumper resistors.

[0269] It is understandable that configuring at least one of the multiple bridge portions 140 as a jumper resistor can improve the processing convenience of the substrate 100 and reduce the cost of the substrate 100. In addition, since the resistance of the jumper resistor is very small, the voltage drop is small, thereby improving the transmission reliability of the signal.

[0270] In some embodiments, at least one of the plurality of first bridge portions 141 is a jumper resistor.

[0271] This configuration can improve the processing convenience of the substrate 100 and reduce the cost of the substrate 100. In addition, since the resistance of the jumper resistor is very small, the voltage drop is small, thereby improving the transmission reliability of the signal.

[0272] In some examples, all of the first bridge portions 141 may be jumper resistors. In other examples, a portion (one or more) of the first bridge portions 141 may be jumper resistors.

[0273] In some embodiments, at least one of the plurality of second bridge portions 142 is a jumper resistor.

[0274] This configuration can improve the processing convenience of the substrate 100 and reduce the cost of the substrate 100. In addition, since the resistance of the jumper resistor is very small, the voltage drop is small, thereby improving the transmission reliability of the signal.

[0275] In some examples, all of the second bridge portions 142 may be jumper resistors. In other examples, a portion (one or more) of the second bridge portions 142 may be jumper resistors.

[0276] As can be seen from the above, the plurality of signal line groups 130 include a first voltage line group 150 and a second voltage line group 160. The following describes other signal line groups 130 in the plurality of signal line groups 130 with reference to FIG3D and FIG3E.

[0277] In some examples, as shown in FIG. 3D and FIG. 3E , the plurality of signal line groups 130 further include a power line group 135 , and the power line group 135 includes a plurality of power lines 132 .

[0278] In some examples, a power line (Volt Current Condenser, VCC) 132 is used to power the first driver chip 103. For example, as shown in FIG3D and FIG3E , one end of the power line 132 is electrically connected to the binding pins in the binding area BB, and the other end extends to the device area AA and is electrically connected to the first driver chip 103. As can be seen from the above, the first driver chip 103 is electrically connected to the device group 110, so that the power line 132 can be electrically connected to the device group 110 through the first driver chip 103.

[0279] In some examples, as shown in FIG3E , the first driver chip 103 has a power port Vcc. One end of a power line 132 is electrically connected to a power supply external to the substrate 100 via a binding pin and the printed circuit board 106 , and the other end is electrically connected to the power port Vcc of the first driver chip 103 , so that the power line 132 can provide power to the first driver chip 103 .

[0280] In some examples, as shown in FIG3D and FIG3E , any power line 132 is located along the first direction X on the second side of a column of device groups 110 electrically connected to the power line 132. That is, the power line 132 and the second voltage line 161 electrically connected to the same column of device groups 110 are located along the first direction X on the same side of the column of device groups 110.

[0281] In some examples, as shown in FIG. 3D and FIG. 3E , the plurality of signal line groups 130 further include a data line group 136 , and the data line group 136 includes a plurality of data lines 133 .

[0282] In some examples, data line (full name: Data) 133 is used to transmit data signals. For example, as shown in Figures 3D and 3E , one end of data line 133 is electrically connected to a binding pin in binding area BB, and the other end extends to device area AA and is electrically connected to first driver chip 103. As can be seen from the above, first driver chip 103 is electrically connected to device group 110, allowing data line 133 to be electrically connected to device group 110 through first driver chip 103.

[0283] In some examples, as shown in Figures 3D and 3E , the first driver chip 103 has a data port Dip, and the second driver chip 104 has a first data port Dip1 through an Nth data port DipN. One end of a data line 133 is electrically connected to the first data port Dip1 of the second driver chip 104 via a binding pin and printed circuit board 106, and the other end is electrically connected to the data port Dip of one or more first driver chips 103 electrically connected to a column of device groups 110. Another data line 133 has one end electrically connected to the second data port Dip2 of the second driver chip 104 via a binding pin and printed circuit board 106, and the other end is electrically connected to the data port Dip of one or more first driver chips 103 electrically connected to another column of device groups 110, and so on, up to the Nth data port DipN. It will be understood that N is a positive integer. In some examples, the value of N is equal to the number of columns of device groups 110 arranged along the second direction Y.

[0284] In some examples, as shown in FIG3D and FIG3E , any data line 133 is located along the first direction X on the second side of a column of device groups 110 electrically connected to the data line 133. That is, the data line 133 and the second voltage line 161 electrically connected to the same column of device groups 110 are located along the first direction X on the same side of the column of device groups 110.

[0285] In some examples, as shown in FIG3D and FIG3E , there are multiple first driver chips 103 electrically connected to a column of device groups 110. For example, the multiple first driver chips 103 electrically connected to a column of device groups 110 include a first first driver chip 103a, a second first driver chip 103b, a third first driver chip 103c, a fourth first driver chip 103d, and so on, up to the mth first driver chip 103m. It is understood that the multiple first driver chips 103 are cascaded.

[0286] 3E , the first first driver chip 103 a to the mth first driver chip 103 m are sequentially away from the binding area BB along the second direction Y. It can be understood that m is greater than 4 and is a positive integer.

[0287] It should be noted that the first first driver chip 103a, the second first driver chip 103b, the third first driver chip 103c, the fourth first driver chip 103d, and so on to the mth first driver chip 103m are only used to distinguish the multiple first driver chips 103 electrically connected to a column of device groups 110, and do not further limit the first driver chip 103.

[0288] In some examples, as shown in Figures 3D and 3E , the plurality of signal line groups 130 further include an input / output line group 137, which includes input / output lines (also called addressing signal lines) 134. For example, as shown in Figures 3D and 3E , the input / output lines 134 include input lines 1341 and output lines 1342.

[0289] 3E , the second driver chip 104 has an input port DiN and an output port DoN. The first driver chip 103 has an input port Dis and an output port Dos.

[0290] For example, as shown in FIG3E , there are multiple input lines 1341. One end of one input line 1341 is electrically connected to the input port DiN of the second driver chip 104 via a binding pin, and the other end is electrically connected to the input port Dis of the first first driver chip 103a. Another input line 1341 has one end electrically connected to the output port Dos of the first first driver chip 103a, and the other end is electrically connected to the input port Dis of the second first driver chip 103b. Yet another input line 1341 has one end electrically connected to the output port Dos of the second first driver chip 103b, and the other end is electrically connected to the input port Dis of the third first driver chip 103c. This continues in this manner, all the way to the mth first driver chip 103m that is farthest from the binding area BB along the second direction Y.

[0291] For example, as shown in FIG3E , the output terminal Dos of the mth first driver chip 103m is electrically connected to the bonding pin in the bonding area BB via the output line 1342. That is, multiple first driver chips 103 electrically connected to a column of device groups 110 are cascaded via the input line 1341 and the output line 1342.

[0292] In this way, the signal output by the second driver chip 104 can be transmitted to the multiple first driver chips 103 through the input line 1341 and then fed back to the second driver chip 104 through the output line 1342 , so that the second driver chip 104 can drive the multiple first driver chips 103 .

[0293] In some examples, as shown in Figures 3D and 3E, any input / output line 134 is located along the first direction X on the second side of a column of device groups 110 electrically connected to the input / output line 134, that is, the input / output line 134 and the second voltage line 161 electrically connected to the same column of device groups 110 are located on the same side of the column of device groups 110.

[0294] In some examples, as shown in FIG. 3D and FIG. 3E , the input / output line 134 surrounds the second voltage line 161 to save wiring space and improve area utilization of the substrate 101 .

[0295] In some examples, as shown in Figures 3D and 3E, along a column of device groups 110 to a first driver chip 103 electrically connected to the column of device groups 110, the first voltage line 151, the power line 132, the data line 133, the input line 1341, the second voltage line 161, and the output line 1342 are arranged in sequence.

[0296] 3D and 3E , the substrate 100 further includes an electrostatic loop 108. The electrostatic loop 108 surrounds the plurality of device groups 110 and is electrically connected to the bonding area BB.

[0297] For example, both ends of the electrostatic loop 108 are electrically connected to the binding pins in the binding area BB. In this way, the electrostatic loop 108 can not only surround the multiple device groups 110, but also surround the multiple signal line groups 130 electrically connected to the multiple device groups 110.

[0298] It can be understood that the electrostatic loop 108 can release static electricity, thereby protecting the multiple device groups 110 and the multiple signal line groups 130 and improving the reliability of the substrate 100 .

[0299] It can be understood that the arrangement order of the binding pins in the binding area BB along the first direction X is the same as the arrangement order of the electrostatic loop 108, the first voltage line 151, the power line 132, the data line 133, the input line 1341, the second voltage line 161 and the output line 1342 along the first direction.

[0300] This arrangement can shorten the distance between the signal line 131 and the electrostatic loop 108 and the binding pins, thereby shortening the length of the wiring (including the signal line 131 and the electrostatic loop 108), reducing the voltage drop of the wiring (including the signal line 131 and the electrostatic loop 108), and improving the reliability of the substrate 100. It can also reduce material usage and reduce costs.

[0301] As can be seen from the above, by electrically connecting at least one signal line 131 in at least one signal line group 130 to one conductive pattern 170 , the voltage drop of the signal line 131 can be reduced.

[0302] The voltage drops of the first voltage line 151 , the second voltage line 161 , and the power line 132 when the conductive pattern 170 is provided and when the conductive pattern 170 is not provided are exemplified below with reference to Table 1.

[0303] Table 1

[0304]

[0305] As shown in Table 1, taking the conductive layer material as Cu as an example, simulation tests were performed on the first voltage line group 150 , the second voltage line group 160 and the power line group 135 .

[0306] Table 1 shows the resistance values ​​and voltage drops of the longest first voltage line 151 in the first voltage line group 150, the longest second voltage line 161 in the second voltage line group 160, and the longest power line 132 in the power line group 135. For example, in both cases where the conductive pattern 170 is not provided and where the conductive pattern 170 is provided, the lengths of the first voltage line 151 and the second voltage line 161 are the same, and the lengths of the power line 132 are the same. Furthermore, in both cases where the conductive pattern 170 is not provided and where the conductive pattern 170 is provided, the width of the first voltage line 151 along the first direction X is approximately 4 mm, the width of the second voltage line 161 along the first direction X is approximately 3.3 mm, and the width of the power line 132 along the first direction X is approximately 0.34 mm. That is, in both cases where the conductive pattern 170 is not provided and where the conductive pattern 170 is provided, the widths of the first voltage line 151, the second voltage line 161, and the power line 132 along the first direction X are the same. On this basis, by controlling the thickness of the three, different resistance values ​​and voltage drops were obtained.

[0307] As shown in Table 1, when the conductive pattern 170 is not provided, the resistance of the first voltage line 151, the second voltage line 161, and the power line 132 are all relatively high, resulting in a large voltage drop. For example, the voltage drop of the first voltage line 151 reaches 0.2632V, the voltage drop of the second voltage line 161 reaches 0.3122V, and the voltage drop of the power line 132 reaches 0.1439V. Furthermore, the sum of the voltage drops of the second voltage line 161 and the power line 132 reaches 0.4561V.

[0308] Typically, the voltage drop of the first voltage line 151 needs to be less than 0.5 V, the voltage drop of the second voltage line 161 needs to be less than 0.4 V, and the sum of the voltage drop of the second voltage line 161 and the voltage drop of the power line 132 needs to be less than 0.45 V. It is understandable that since the second voltage line 161 is used to ground the first driver chip 103, and the power line 132 is used to power the first driver chip 103, if the voltage drop of the second voltage line 161 and the voltage drop of the power line 132 are too large (for example, greater than 0.45 V), the power consumption of the first driver chip 103 will increase, causing the temperature of the first driver chip 103 to rise, and affecting the reliability of the first driver chip 103.

[0309] As can be seen from Table 1, when the conductive pattern 170 is not provided, even if the thickness of Cu is large (for example, 4.5 μm), the sum of the voltage drop of the second voltage line 161 and the voltage drop of the power line 132 is 0.4561 V, which still cannot meet the requirements, thereby reducing the reliability of the first driver chip 103.

[0310] In the embodiment of the present disclosure, the conductive pattern 170 is electrically connected to the signal line 131 (eg, the first voltage line 151 and the second voltage line 161 ), so that the conductive pattern 170 can compensate for the voltage drop of the signal line 131 .

[0311] For example, as shown in Table 1, after the first conductive pattern 171 is electrically connected to the first voltage line 151 and the second conductive pattern 172 is electrically connected to the second voltage line 161, the voltage drop of the first voltage line 151 can be reduced to 0.3392 V, the voltage drop of the second voltage line 161 can be reduced to 0.2218 V, and the sum of the voltage drop of the second voltage line 161 and the voltage drop of the power line 132 can be reduced to 0.3452 V. In other words, by providing the conductive pattern 170, even if the thickness of Cu is small (for example, 3.6 μm), the voltage drop can meet the requirements, reducing the amount of Cu used and lowering the cost of the substrate 100.

[0312] As can be seen from the above, the input / output lines 134 include input lines 1341 and output lines 1342. In some examples, as shown in FIG3D , the input / output lines 134 include first input / output lines 134a. The first input / output lines 134a are located in the side edge region AA21 and electrically connect a column of device groups 110 adjacent to the side edge region AA2 along the first direction X. For example, the first input / output lines 134a include first input lines 1341a and first output lines 1342a.

[0313] In some examples, as shown in FIG3D , the first output line 1342a extends through the side edge area AA21 to the central area AA1 and is electrically connected to the other output lines 1342. In this way, the first output line 1342a does not need to occupy the space of the side edge area AA21, which helps to reduce the width of the side edge area AA21, thereby facilitating a narrow frame (side frame) of the substrate 100.

[0314] In some examples, the first output line 1342 a extends to the central area AA1 and electrically connects the output lines 1342 adjacent to the first output line 1342 a along the first direction X.

[0315] Figure 4A is a structural diagram of a substrate according to some further embodiments. Figure 4B is a structural diagram of a substrate according to some further embodiments. Figure 4C is a structural diagram of a substrate according to some further embodiments.

[0316] As can be seen from the above, providing the conductive pattern 170 (including the first conductive pattern 171 and the second conductive pattern 172) electrically connected to the signal line 131 (for example, the first voltage line 151 and the second voltage line 161) can reduce the width of the signal line 131 along the first direction X, thereby facilitating the reduction of the width of the side edge area AA21 of the substrate 100 and facilitating the realization of a narrow frame of the substrate 100. The substrate 100 will be further described with reference to Figures 4A to 4C.

[0317] In some implementations, as shown in FIG4A , the signal lines 131 (e.g., the first voltage line 151 and the second voltage line 161) within the device area AA need to extend along the first direction X and the second direction Y within the lower edge area AA22 in order to be electrically connected to the binding pins within the binding area BB. It is understandable that extending the signal lines 131 along the first direction X within the lower edge area AA22 increases the space occupied by the signal lines 131 within the lower edge area AA22. Furthermore, when the number of signal lines 131 is large, the wiring difficulty within the lower edge area AA22 increases, which is not conducive to achieving a narrow bezel (lower bezel) for the substrate 100.

[0318] In some implementations, as shown in FIG4B , the binding area BB includes a pin area BBa and a floating binding area BBb. It can be understood that the binding pin is set in the pin area BBa, and a dummy pin (full name in English: Dummy Pin) is set in the floating binding area BBb. By setting the dummy pin, the setting position of the binding pin (full name in English: Pin Map) can be adjusted, shortening the distance between the signal line 131 and the binding pin electrically connected to the signal line 131, thereby shortening the length of the signal line 131 extending along the first direction X in the lower edge area AA22.

[0319] In related art, the binding area BB includes a plurality of binding pins arranged at equal intervals along a first direction X. Each signal line group 130 is electrically connected to a portion of the binding pins in the binding area BB. The binding area BB includes a first binding area BB1, a second binding area BB2, and a third binding area BB3. The first binding area BB1, the second binding area BB2, and the third binding area BB3 are respectively connected to different signal line groups 130. The first binding area BB1, the second binding area BB2, and the third binding area BB3 are arranged continuously along the first direction X. The inventors of the present disclosure discovered that, as shown in FIG4C , the first binding area BB1 is electrically connected to the first signal line group 130a. If the center axis of the first signal line group 130a along the second direction Y is far away from the center axis of the first binding area BB1 along the second direction Y in the first direction X, the signal line 131 needs to extend a distance along the first direction X within the lower edge area AA22 before it can be connected to the first binding area BB1, which is not conducive to achieving a narrow frame of the substrate 100. If the center axis of the signal line group 130 (for example, the first signal line group 130a) electrically connected to a certain binding area BB (for example, the first binding area BB1) along the second direction Y is set as close as possible to the center axis of the binding area BB (for example, the first binding area BB1) along the second direction Y in the first direction X, then a floating binding area BBb that is not connected to any signal line needs to be set between different binding pins in the binding area BB. When there are many signal lines 131, the number of binding pins is large, so there is insufficient space to set a large number of floating binding areas BBb, resulting in the signal lines 131 still needing to extend a long distance along the first direction X in the lower edge area AA22, which is not conducive to achieving a narrow frame of the substrate 100.

[0320] It can be seen that the method of setting the floating binding area BBb has poor applicability and cannot effectively solve the problem of the wide width of the bottom frame of the substrate 100.

[0321] Figure 5A is a structural diagram of a substrate according to some further embodiments. Figure 5B is a structural diagram of a substrate according to some further embodiments. Figure 5C is a structural diagram of a substrate according to some further embodiments. Figure 5D is a structural diagram of a substrate according to some further embodiments.

[0322] In some embodiments, as shown in FIG. 5A and FIG. 5B , at least two first conductive patterns 171 are arranged along the first direction X.

[0323] It is understandable that in the first voltage line group 150, at least two first voltage lines 151 can be electrically connected to the same first conductive pattern 171. Therefore, at least two first conductive patterns 171 are arranged along the first direction X, so that multiple first voltage lines 151 can be electrically connected through at least two first conductive patterns 171 arranged along the first direction X.

[0324] It can be understood that providing multiple first voltage lines 151 electrically connected via at least two first conductive patterns 171 arranged along the first direction X can reduce the voltage drop of the first voltage lines 151, thereby reducing the thickness of the first voltage lines 151 and reducing the cost of the substrate 100. Furthermore, the multiple first voltage lines 151 are electrically connected via at least two first conductive patterns 171. In this way, by electrically connecting any one of the multiple electrically connected first voltage lines 151 to the bonding area BB, signals can be transmitted between the bonding pin and the multiple electrically connected first voltage lines 151, thereby improving the wiring convenience of the substrate 100.

[0325] 5A and 5B , the first conductive pattern 171 includes a second-type first conductive pattern 171 b located in the center area AA1 . The first voltage lines 151 are electrically connected via the second-type first conductive patterns 171 b arranged along the first direction X.

[0326] It can be understood that because the second-type first conductive pattern 171b is located in the central area AA1, the multiple first voltage lines 151 can be electrically connected sequentially within the central area AA1. In other words, the multiple first voltage lines 151 do not need to be electrically connected to the binding area BB separately within the lower edge area AA22. Instead, they can be electrically connected to each other in the central area AA1 via the second-type first conductive pattern 171b, and then electrically connected to the binding pins within the binding area BB through one or more electrical structures (such as the conductive pattern 170 and the bridge portion 140) (fewer than the number of first voltage lines 151).

[0327] As a result, the multiple first voltage lines 151 no longer need to extend along the first direction X within the lower edge area AA22, facilitating a reduction in the width of the lower edge area AA22 and achieving a narrower bezel (lower bezel) for the substrate 100. Furthermore, there is no need to adjust the positions of the binding pins connected to the first voltage line group 150, simplifying the substrate 100 manufacturing process. Furthermore, by providing the second-type first conductive pattern 171b to electrically connect the multiple first voltage lines 151, a narrow bezel for the substrate 100 is achieved, providing high adaptability and meeting diverse wiring requirements.

[0328] In some examples, after the plurality of first voltage lines 151 are electrically connected, they are electrically connected to at least one binding pin via a conductive structure (e.g., the first conductive pattern 171 or the first bridge portion 141). It is understood that the central axis along the second direction Y of the region where the at least one binding pin connected to the first voltage line group 150 to which the plurality of first voltage lines 151 belong is located substantially coincides with the central axis along the second direction Y of the conductive structure.

[0329] In some embodiments, as shown in FIG. 5C and FIG. 5D , at least two second conductive patterns 172 are arranged along the first direction X.

[0330] It is understandable that in the second voltage line group 160, at least two second voltage lines 161 can be electrically connected to the same second conductive pattern 172. Therefore, at least two second conductive patterns 172 are arranged along the first direction X, so that the plurality of second voltage lines 161 can be electrically connected through at least two second conductive patterns 172 arranged along the first direction X.

[0331] It can be understood that providing multiple second voltage lines 161 electrically connected via at least two second conductive patterns 172 arranged along the first direction X can reduce the voltage drop of the second voltage lines 161, thereby reducing the thickness of the second voltage lines 161 and reducing the cost of the substrate 100. Furthermore, the multiple second voltage lines 161 are electrically connected via at least two second conductive patterns 172. In this way, by electrically connecting any one of the multiple electrically connected second voltage lines 161 to the bonding area BB, signals can be transmitted between the bonding pin and the multiple electrically connected second voltage lines 161, thereby improving the wiring convenience of the substrate 100.

[0332] 5C and 5D , the second conductive patterns 172 include second-type second conductive patterns 172 b located in the center area AA1 . The second voltage lines 161 are electrically connected via the second-type second conductive patterns 172 b arranged along the first direction X.

[0333] Understandably, due to the central area AA1 of the second-type second conductive pattern 172b, the multiple second voltage lines 161 can be electrically connected sequentially within the central area AA1. That is, the multiple second voltage lines 161 do not need to be electrically connected to the binding area BB individually within the lower edge area AA22. Instead, the multiple second voltage lines 161 can be electrically connected to each other in the central area AA1 via the second-type second conductive pattern 172b, and then electrically connected to the binding pins within the binding area BB via one or more (fewer than the number of first voltage lines 151) electrical structures (e.g., the conductive pattern 170 and the bridge portion 140).

[0334] As a result, the multiple second voltage lines 161 no longer need to extend along the first direction X within the lower edge area AA22, facilitating a reduction in the width of the lower edge area AA22 and achieving a narrower bezel (lower bezel) for the substrate 100. Furthermore, there is no need to adjust the positions of the binding pins connected to the second voltage line group 160, simplifying the substrate 100 manufacturing process. Furthermore, by providing a second-type second conductive pattern 172b to electrically connect the multiple second voltage lines 161, a narrow bezel for the substrate 100 is achieved, providing high adaptability and meeting diverse wiring requirements.

[0335] In some examples, after the plurality of second voltage lines 161 are electrically connected, they are electrically connected to at least one binding pin via a conductive structure (e.g., the second conductive pattern 172 or the second bridge portion 142). It is understood that the central axis along the second direction Y of the region where the at least one binding pin connected to the second voltage line group 160 to which the plurality of second voltage lines 161 belong is located substantially coincides with the central axis along the second direction Y of the conductive structure.

[0336] In some embodiments, as shown in FIG. 5B , at least two first conductive patterns 171 arranged along the first direction X constitute a first conductive pattern row 181 , and a plurality of first conductive patterns 171 constitute at least two first conductive pattern rows 181 .

[0337] It can be understood that the number of first conductive patterns 171 included in the at least two first conductive pattern rows 181 may be the same or different.

[0338] In some examples, at least two first conductive pattern rows 181 are respectively electrically connected to multiple first voltage lines 151 in the first voltage line group 150. In other examples, a portion (two or more) of the first voltage lines 151 in the first voltage line group 150 are electrically connected through one first conductive pattern row 181, and another portion (two or more) of the first voltage lines 151 are electrically connected through another first conductive pattern row 181.

[0339] In some examples, at least two first conductive pattern rows 181 are spaced apart along the second direction Y. In other examples, at least two first conductive pattern rows 181 are spaced apart along the first direction X.

[0340] It can be understood that the plurality of first conductive patterns 171 are arranged to form at least two first conductive pattern rows 181 , so that the plurality of first voltage lines 151 can be electrically connected through the at least two first conductive pattern rows 181 , thereby improving the wiring flexibility of the substrate 100 .

[0341] In some embodiments, as shown in FIG. 5B , the number of first conductive pattern rows 181 is two, and the number of first conductive patterns 171 included in the two first conductive pattern rows 181 is different.

[0342] Understandably, the shapes and sizes of the first conductive patterns 171 within the same first conductive pattern row 181 can vary, and are not limited here. Some (one or more) first conductive patterns 171 within the same first conductive pattern row 181 directly contact and form an integral structure with adjacent first voltage lines 151, while other (one or more) first conductive patterns 171 are spaced apart from the first voltage lines 151 and connected via first bridges 141.

[0343] With this configuration, different numbers of first conductive patterns 171 can be included in different first conductive pattern rows 181 according to usage requirements, thereby improving the wiring flexibility of the substrate 100 .

[0344] In some embodiments, as shown in FIG5B , the length of any device group 110 along the second direction Y is L. Along the second direction Y, one first conductive pattern row 181 (e.g., the first conductive pattern row 181a in FIG5B ) is closer to the bonding area BB than another first conductive pattern row 181 (e.g., the first conductive pattern row 181b in FIG5B ), and along the second direction Y, the interval between the two first conductive pattern rows 181 (the first conductive pattern row 181a and the first conductive pattern row 181b) is in the range of 3L to 5L.

[0345] It is understandable that the first conductive pattern row 181a and the first conductive pattern row 181b are merely used to distinguish between two first conductive pattern rows 181 spaced apart along the second direction Y, and do not further define the first conductive pattern row 181. Since the length of any device group 110 along the second direction Y is L, three to five device groups 110 are spaced apart between the first conductive pattern row 181a and the first conductive pattern row 181b.

[0346] This arrangement prevents the spacing between the first conductive pattern rows 181a and 181b along the second direction Y from being too small (e.g., less than 3L). This also prevents the multiple first conductive patterns 171 from being arranged too densely, which could lead to excessive current in a portion of the substrate 100 and cause local overheating of the substrate 100. Furthermore, the arrangement prevents the spacing between the first conductive pattern rows 181a and 181b along the second direction Y from being too large (e.g., greater than 5L), which could affect the first conductive patterns 171's ability to compensate for the voltage drop of the first voltage line 151.

[0347] That is, setting the spacing between the first conductive pattern row 181a and the first conductive pattern row 181b to a value ranging from 3L to 5L can improve thermal uniformity at different locations on the substrate 100, prevent local overheating of the substrate 100, and thus improve the reliability of the substrate 100. Furthermore, the first conductive pattern 171 can improve the compensation effect of the voltage drop of the first voltage line 151, thereby reducing the voltage drop of the first voltage line 151. In some examples, the spacing between the first conductive pattern row 181a and the first conductive pattern row 181b can be 3L, 4L, or 5L, etc.

[0348] In some embodiments, as shown in FIG. 5D , at least two second conductive patterns 172 arranged along the first direction X constitute a second conductive pattern row 182 , and a plurality of second conductive patterns 172 constitute at least two second conductive pattern rows 182 .

[0349] It can be understood that the number of second conductive patterns 172 included in the at least two second conductive pattern rows 182 may be the same or different.

[0350] In some examples, at least two second conductive pattern rows 182 are respectively electrically connected to multiple second voltage lines 161 in the second voltage line group 160. In other examples, a portion (two or more) of the second voltage lines 161 in the second voltage line group 160 are electrically connected through one second conductive pattern row 182, and another portion (two or more) of the second voltage lines 161 are electrically connected through another second conductive pattern row 182.

[0351] In some examples, at least two second conductive pattern rows 182 are spaced apart along the second direction Y. In other examples, at least two second conductive pattern rows 182 are spaced apart along the first direction X.

[0352] It can be understood that the plurality of second conductive patterns 172 are arranged to form at least two second conductive pattern rows 182 , so that the plurality of second voltage lines 161 can be electrically connected through the at least two second conductive pattern rows 182 , thereby improving the wiring flexibility of the substrate 100 .

[0353] In some embodiments, as shown in FIG. 5D , there are two second conductive pattern rows 182 , and the two second conductive pattern rows 182 include different numbers of second conductive patterns 172 .

[0354] Understandably, the shapes and sizes of the second conductive patterns 172 within the same second conductive pattern row 182 can vary, and are not limited here. Some (one or more) second conductive patterns 172 within the same second conductive pattern row 182 directly contact and form an integral structure with adjacent second voltage lines 161, while other (one or more) second conductive patterns 172 are spaced apart from the second voltage lines 161 and connected via second bridges 142.

[0355] With this configuration, different numbers of second conductive patterns 172 can be included in different second conductive pattern rows 182 according to usage requirements, thereby improving the wiring flexibility of the substrate 100 .

[0356] In some embodiments, as shown in FIG5D , the length of any device group 110 along the second direction Y is L. Along the second direction Y, one second conductive pattern row 182 (e.g., second conductive pattern row 182a in FIG5D ) is located closer to the bonding area BB than another second conductive pattern row 182 (e.g., second conductive pattern row 182b in FIG5D ), and along the second direction Y, the interval between two second conductive pattern rows 182 (second conductive pattern row 182a and second conductive pattern row 182b) is in the range of 3L to 5L.

[0357] It is understandable that the second conductive pattern row 182a and the second conductive pattern row 182b are merely used to distinguish two second conductive pattern rows 182 spaced apart along the second direction Y, and do not further define the second conductive pattern rows 182. Since the length of any device group 110 along the second direction Y is L, three to five device groups 110 are spaced apart between the second conductive pattern row 182a and the second conductive pattern row 182b.

[0358] This arrangement prevents the spacing between the second conductive pattern rows 182a and 182b along the second direction Y from being too small (e.g., less than 3L). This also prevents the multiple second conductive patterns 172 from being arranged too densely, which could lead to excessive current in a portion of the substrate 100 and localized overheating of the substrate 100. Furthermore, it prevents the spacing between the second conductive pattern rows 182a and 182b along the second direction Y from being too large (e.g., greater than 5L), which could affect the second conductive patterns 172's ability to compensate for the voltage drop of the second voltage line 161.

[0359] That is, setting the interval between the second conductive pattern row 182a and the second conductive pattern row 182b to a value within the range of 3L to 5L can improve the thermal uniformity at different locations of the substrate 100, prevent local overheating of the substrate 100, and thus improve the reliability of the substrate 100. Furthermore, the second conductive pattern 172 can improve the compensation effect for the voltage drop of the second voltage line 161, thereby reducing the voltage drop of the second voltage line 161.

[0360] In some examples, the interval between the second conductive pattern row 182a and the second conductive pattern row 182b may be 3L, 4L, or 5L, etc.

[0361] It can be understood that the distance between the second conductive pattern row 182a and the second conductive pattern row 182b may be the same as or different from the distance between the first conductive pattern row 181a and the first conductive pattern row 181b.

[0362] FIG. 5E is a structural diagram of a substrate according to yet other embodiments.

[0363] 5E , the plurality of device groups 110 include a first row of device groups 111 , which are adjacent to the bonding region BB along the second direction Y. It is understood that the first row of device groups 111 is the row of device groups 110 that is closest to the bonding region BB along the second direction Y among the plurality of device groups 110 .

[0364] In some examples, at least one first conductive pattern row 181 is located in the region where the first row device group 111 is located. That is, the multiple first conductive patterns 171 in at least one first conductive pattern row 181 are located in the region where each device group 110 in the first row device group 111 is located.

[0365] Such a configuration can shorten the distance between the first conductive pattern row 181 and the binding area BB, thereby improving the convenience of electrical connection between the first conductive patterns 171 in the first conductive pattern row 181 and the binding area BB.

[0366] As can be seen from the above, the first conductive pattern row 181 a is closer to the binding area BB than the first conductive pattern row 181 b , that is, the first conductive pattern row 181 a may be located in the area where the first row of device groups 111 is located.

[0367] In some embodiments, as shown in FIG. 5E , at least one second conductive pattern row 182 is located in the region where the first row device group 111 is located.

[0368] At least one second conductive pattern row 182 is located in the region where the first row device group 111 is located. That is, the plurality of second conductive patterns 172 in at least one second conductive pattern row 182 are located in the region where the device groups 110 in the first row device group 111 are located.

[0369] Such a configuration can reduce the distance between the second conductive pattern row 182 and the binding area BB, thereby improving the convenience of electrical connection between the second conductive patterns 172 in the second conductive pattern row 182 and the binding area BB.

[0370] As can be seen from the above, the second conductive pattern row 182a is closer to the binding area BB than the second conductive pattern row 182b. That is, the second conductive pattern row 182a may be located in the area where the first row device group 111 is located.

[0371] In some examples, as shown in FIG. 5E , when the second conductive pattern row 182 is located in the region where the first row device group 111 is located, the first conductive pattern row 181 is located along the second direction Y on a side of the second conductive pattern row 182 away from the bonding area BB.

[0372] As can be seen from the above, in some examples, after being electrically connected in the central area AA1 , the plurality of signal lines 131 (including the first voltage line 151 and the second voltage line 161 ) are electrically connected to the binding pins in the binding area BB.

[0373] The following is an example of how the multiple signal lines 131 are electrically connected to the binding pins in the binding area BB.

[0374] Referring again to FIG. 5C and FIG. 5D , in some embodiments, at least one signal line 131 in at least one signal line group 130 is electrically connected to the bonding area BB through the conductive pattern 170 .

[0375] In some examples, as shown in Figures 5C and 5D, at least two signal lines 131 (e.g., first voltage lines 151) in a signal line group 130 (e.g., first voltage line group 150) are electrically connected and then electrically connected to the binding pins in the binding area BB through the conductive pattern 170.

[0376] It is understandable that electrically connecting at least two signal lines 131 can reduce the voltage drop of the signal lines 131, thereby reducing the thickness of the signal lines 131. Furthermore, after the at least two signal lines 131 are electrically connected, they are then electrically connected to the binding pins in the binding area BB via the conductive pattern 170, thereby improving the convenience of the electrical connection between the at least two signal lines 131 and the binding pins.

[0377] In other examples, one signal line 131 in one signal line group 130 is electrically connected to a binding pin in the binding area BB through the conductive pattern 170 , thereby meeting different usage requirements and improving the flexibility of the substrate 100 .

[0378] It can be understood that electrically connecting at least one signal line 131 in at least one signal line group 130 to the binding area BB can improve the reliability of the electrical connection between the signal line 131 and the binding pin, reduce voltage drop, and thus improve the reliability of the substrate 100.

[0379] 5E , the plurality of first conductive patterns 171 include a first-type first conductive pattern 171 a . One end of the first-type first conductive pattern 171 a is directly connected to an end of the bonding area BB near the device area AA, and the other end of the first-type first conductive pattern 171 a is electrically connected to the first voltage line group 150 .

[0380] It is understood that the first-type first conductive pattern 171a can extend from the bonding area BB to the device area AA. One end of the first-type first conductive pattern 171a is directly connected to the end of the bonding area BB near the device area AA. In other words, one end of the first-type first conductive pattern 171a is directly electrically connected to the end of the bonding area BB near the device area AA, with no other conductive structure disposed therebetween. It is understood that the first-type first conductive pattern 171a can be electrically connected to multiple bonding pins within the bonding area BB.

[0381] The other end of the first-type first conductive pattern 171 a is electrically connected to the first voltage line group 150 . That is, the other end of the first-type first conductive pattern 171 a is electrically connected to the plurality of first voltage lines 151 in the first voltage line group 150 .

[0382] As can be seen from the above, in some examples, as shown in FIG5B , the plurality of first voltage lines 151 in the first voltage line group 150 are electrically connected via the second-type first conductive pattern 171 b. For example, one end of the first-type first conductive pattern 171 a away from the bonding area BB is electrically connected to the second-type first conductive pattern 171 b, such that the first-type first conductive pattern 171 a can electrically connect the plurality of first voltage lines 151 to the bonding pins.

[0383] It can be understood that since the conductive pattern 170 (including the first type first conductive pattern 171a) has a strong current carrying capacity, the first voltage line group 150 is electrically connected to the binding pin in the binding area BB through the first type first conductive pattern 171a, thereby improving the reliability of the electrical connection between the first voltage line group 150 and the binding pin.

[0384] In some embodiments, the number of the first-type first conductive patterns 171 a is a, where a is less than the number of the first voltage lines 151 in the first voltage line group 150, and a is a positive integer.

[0385] It can be understood that the number a of the first-type first conductive patterns 171a is set to be less than the number of the first voltage lines 151. That is, after the multiple first voltage lines 151 are electrically connected to the second-type first conductive patterns 171b located in the device area AA, they can be electrically connected to the bonding area BB through the first-type first conductive patterns 171a, which are less in number than the first voltage lines 151. On the one hand, this can reduce the number of bonding pins electrically connected to the first voltage lines 151, thereby reducing the width of the flexible circuit board 105 along the first direction X and reducing costs. On the other hand, it can simplify the structure of the substrate 100 and improve the wiring convenience of the substrate 100.

[0386] In some examples, the value of a may be 2. That is, the plurality of first voltage lines 151 in the first voltage line group 150 are electrically connected to the bonding pins in the bonding area BB through the two first-type first conductive patterns 171 a.

[0387] In some other examples, the value of a may be 1. That is, the plurality of first voltage lines 151 in the first voltage line group 150 are electrically connected to the bonding pins in the bonding area BB through a first-type first conductive pattern 171 a .

[0388] In some embodiments, a is no greater than half the number of the first voltage lines 151 in the first voltage line group 150 .

[0389] It can be understood that a is greater than half the number of first voltage lines 151 in the first voltage line group 150, that is, a is less than or equal to half the number of first voltage lines 151. This configuration can reduce the number of first-type first conductive patterns 171a, thereby reducing the number of binding pins electrically connected to the first voltage lines 151, reducing the width of the flexible circuit board 105 along the first direction X, and reducing the cost of the substrate 100.

[0390] In some examples, when the value of a is small (for example, when the value of a is 1 or 2), the width of the first type first conductive pattern 171a along the first direction X can be increased, so that the first type first conductive pattern 171a can be bound and connected to a larger number of binding pins to reduce the current value on the first type first conductive pattern 171a, reduce the heat dissipation of the first type first conductive pattern 171a, and improve the reliability of the substrate 100.

[0391] 5E , the plurality of second conductive patterns 172 include a first-type second conductive pattern 172 a . One end of the first-type second conductive pattern 172 a is directly connected to an end of the bonding area BB near the device area AA, and the other end of the first-type second conductive pattern 172 a is electrically connected to the second voltage line group 160 .

[0392] It is understood that the first-type second conductive pattern 172a can extend from the bonding area BB to the device area AA. One end of the first-type second conductive pattern 172a is directly connected to the end of the bonding area BB near the device area AA0. In other words, one end of the first-type second conductive pattern 172a is directly electrically connected to the end of the bonding area BB near the device area AA, with no other conductive structure disposed therebetween. It is understood that the first-type second conductive pattern 172a can be electrically connected to multiple bonding pins within the bonding area BB.

[0393] The other end of the first-type second conductive pattern 172 a is electrically connected to the second voltage line group 160 . That is, the other end of the first-type second conductive pattern 172 a is electrically connected to the plurality of second voltage lines 161 in the second voltage line group 160 .

[0394] As can be seen from the above, in some examples, as shown in FIG5D , the plurality of second voltage lines 161 in the second voltage line group 160 are electrically connected via the second-type second conductive pattern 172 b. For example, an end of the first-type second conductive pattern 172 a away from the bonding area BB is electrically connected to the second-type second conductive pattern 172 b, such that the first-type second conductive pattern 172 a can electrically connect the plurality of second voltage lines 161 to the bonding pins.

[0395] It can be understood that since the conductive pattern 170 (including the first-type second conductive pattern 172a) has a strong current-carrying capacity, the second voltage line group 160 is electrically connected to the binding pin in the binding area BB through the first-type second conductive pattern 172a, thereby improving the reliability of the electrical connection between the second voltage line group 160 and the binding pin.

[0396] In some embodiments, the number of the first-type second conductive patterns 172 a is b, where b is less than the number of the second voltage lines 161 in the second voltage line group 160 , and b is a positive integer.

[0397] It can be understood that the number a of the first-type second conductive patterns 172a is smaller than the number of the second voltage lines 161. That is, after being electrically connected to the second-type second conductive patterns 172b located in the device area AA, the plurality of second voltage lines 161 can be electrically connected to the bonding area BB via the first-type second conductive patterns 172a, which is smaller in number than the second voltage lines 161. This can, on the one hand, reduce the number of bonding pins electrically connected to the second voltage lines 161, thereby reducing the width of the flexible circuit board 105 along the first direction X and reducing costs. On the other hand, it can simplify the structure of the substrate 100 and improve the wiring convenience of the substrate 100.

[0398] In some examples, the value of b may be 2. That is, the plurality of second voltage lines 161 in the second voltage line group 160 are electrically connected to the bonding pins in the bonding area BB through the two first-type second conductive patterns 172 a.

[0399] In some other examples, the value of b may be 1. That is, the plurality of second voltage lines 161 in the second voltage line group 160 are electrically connected to the bonding pins in the bonding area BB through a first-type second conductive pattern 172 a .

[0400] It can be understood that the value of a and the value of b can be the same or different.

[0401] In some embodiments, b is no greater than half the number of the second voltage lines 161 in the second voltage line group 160 .

[0402] It can be understood that b is greater than half the number of second voltage lines 161 in the second voltage line group 160, that is, b is less than or equal to half the number of second voltage lines 161. This configuration can reduce the number of first-type second conductive patterns 172a, thereby reducing the number of binding pins electrically connected to the second voltage lines 161, reducing the width of the flexible circuit board 105 along the first direction X, and reducing the cost of the substrate 100.

[0403] In some examples, when the value of b is small (for example, when the value of b is 1 or 2), the width of the first-type second conductive pattern 172a along the first direction X can be increased, so that the first-type second conductive pattern 172a can be bound and connected to a larger number of binding pins to reduce the current value on the first-type second conductive pattern 172a, reduce the heat dissipation of the first-type second conductive pattern 172a, and improve the reliability of the substrate 100.

[0404] In some examples, the first-type first conductive patterns 171 a and the first-type second conductive patterns 172 a are spaced apart to avoid local overheating of the substrate 100 and improve heat uniformity at different locations of the substrate 100 .

[0405] 3A and 3B , it can be seen from the above that the substrate 100 includes a plurality of bridges 140 . In some embodiments, the substrate 100 further includes a plurality of third bridges 143 , and at least two first conductive patterns 171 are electrically connected via the third bridges 143 .

[0406] It can be understood that two first conductive patterns 171 spaced apart along the first direction X can be electrically connected via the third bridge portion 143 , and two first conductive patterns 171 spaced apart along the second direction Y can also be electrically connected via the third bridge portion 143 .

[0407] By providing the third bridge portion 143 , the first conductive patterns 171 arranged at intervals can be connected via the third bridge portion 143 , thereby improving the wiring flexibility of the substrate 100 .

[0408] It is understood that by adjusting the width and thickness of the third bridging portion 143, the current carrying capacity of the third bridging portion 143 can be adjusted. In some examples, the third bridging portion 143 can be configured to have a larger width and thickness to improve the current carrying capacity of the third bridging portion 143. In other examples, the third bridging portion 143 can be configured to have a smaller width and thickness to meet different usage requirements.

[0409] In some examples, a fourth through hole is further formed in the insulating layer to expose a portion of the surface of the first conductive pattern 171 , and the third bridge portion 143 is electrically connected to the exposed surface areas of at least two first conductive patterns 171 .

[0410] In some embodiments, as shown in FIG. 3A and FIG. 3B , the substrate 100 further includes a plurality of fourth bridge portions 144 , and at least two second conductive patterns 172 are electrically connected via the fourth bridge portions 144 .

[0411] It can be understood that two second conductive patterns 172 spaced apart along the first direction X can be electrically connected via the fourth bridge portion 144 , and two second conductive patterns 172 spaced apart along the second direction Y can also be electrically connected via the fourth bridge portion 144 .

[0412] By providing the fourth bridge portion 144 , the second conductive patterns 172 arranged at intervals can be connected via the fourth bridge portion 144 , thereby improving the wiring flexibility of the substrate 100 .

[0413] It is understood that by adjusting the width and thickness of the fourth bridging portion 144, the current carrying capacity of the fourth bridging portion 144 can be adjusted. In some examples, the fourth bridging portion 144 can be configured to have a larger width and thickness to increase the current carrying capacity of the fourth bridging portion 144. In other examples, the fourth bridging portion 144 can be configured to have a smaller width and thickness to meet different usage requirements.

[0414] In some examples, a fifth through hole is further formed in the insulating layer to expose a portion of the surface of the second conductive pattern 172 , and the fourth bridge portion 144 is electrically connected to the exposed surface areas of at least two second conductive patterns 172 .

[0415] In some embodiments, in the same first voltage line group 150 , at least two first voltage lines 151 are connected to each other at a side away from the binding area BB along the second direction Y.

[0416] It can be understood that setting at least two first voltage lines 151 to be connected to each other along the second direction Y away from the side of the binding area BB can reduce the voltage drop of the first voltage line 151, which is beneficial to reducing the width of the first voltage line 151 along the first direction X, which is beneficial to achieving a narrow frame of the substrate 100, and is also beneficial to reducing the thickness of the first voltage line 151 and reducing the cost of the substrate 100.

[0417] In some embodiments, in the same second voltage line group 160 , at least two second voltage lines 161 are connected to each other at a side away from the bonding area BB along the second direction Y.

[0418] It can be understood that at least two second voltage lines 161 are connected to each other along the second direction Y away from the side of the binding area BB, so as to reduce the voltage drop of the second voltage line 161, which is beneficial to reducing the width of the second voltage line 161 along the first direction X, which is beneficial to achieving a narrow frame of the substrate 100, and is also beneficial to reducing the thickness of the second voltage line 161 and reducing the cost of the substrate 100.

[0419] Figure 6A is a structural diagram of a substrate according to some further embodiments. Figure 6B is a structural diagram of a substrate according to some further embodiments. Figure 6C is a structural diagram of a substrate according to some further embodiments.

[0420] As can be seen from the above, in some examples, at least two signal lines 131 in a signal line group 130 may be electrically connected via the bridge portion 140 and / or the conductive pattern 170 .

[0421] In other examples, as shown in FIG. 6A and FIG. 6B , at least two signal lines 131 in at least one signal line group 130 are electrically connected via a bridge portion 140 .

[0422] For example, as shown in Figures 6A and 6B, at least two signal lines 131 in at least one signal line group 130 may not be connected through the conductive pattern 170, but may be electrically connected only through the bridge portion 140. It can be understood that after the at least two signal lines 131 in a signal line group 130 are electrically connected through the bridge portion 140, the voltage drop of the signal line 131 can be reduced, thereby facilitating a reduction in the width of the signal line 131 along the first direction X, facilitating a narrow frame of the substrate 100, and further facilitating a reduction in the thickness of the second voltage line 161, thereby reducing the cost of the substrate 100.

[0423] Furthermore, in some examples, as shown in Figures 6A and 6B, at least one bridge portion 140 is located in the central area AA1, and at least two signal lines 131 in a signal line group 130 can be electrically connected within the central area AA1 via the bridge portion 140. This allows the electrically connected multiple signal lines 131 to share a common electrical connection with the binding pins within the binding area BB. This eliminates the need for the signal lines 131 to extend along the first direction X within the lower edge area AA22, reducing the space occupied by the signal lines 131 within the lower edge area AA22 and facilitating a reduction in the width of the lower edge area AA22, thereby facilitating a narrow frame for the substrate 100. Furthermore, this improves the ease with which the multiple signal lines 131 can be electrically connected to the binding pins, thereby improving the wiring convenience of the substrate 100.

[0424] As can be seen from the above, in some examples, the first-type first conductive pattern 171a is electrically connected to the first voltage line group 150, and the first-type second conductive pattern 172a is electrically connected to the second voltage line group 160. In some examples, as shown in Figures 6A and 6B, after the multiple first voltage lines 151 in the first voltage line group 150 are electrically connected via the bridge portion 140, they are electrically connected to the binding pins via the first-type first conductive pattern 171a. After the multiple second voltage lines 161 in the second voltage line group 160 are electrically connected via the bridge portion 140, they are electrically connected to the binding pins via the first-type second conductive pattern 172a.

[0425] It can be understood that after the multiple first voltage lines 151 are electrically connected, they are electrically connected to the binding pins through the first type first conductive pattern 171a, which can reduce the number of binding pins electrically connected to the multiple first voltage lines 151, thereby reducing the width of the flexible circuit board 105 along the first direction X and reducing costs.

[0426] Similarly, after the multiple second voltage lines 161 are electrically connected, they are electrically connected to the binding pins through the first type second conductive pattern 172a, which can reduce the number of binding pins electrically connected to the multiple second voltage lines 161, thereby reducing the width of the flexible circuit board 105 along the first direction X and reducing costs.

[0427] In some examples, as shown in FIG6A , a bridge portion 140 electrically connecting at least two signal lines 131 is located between two adjacent device groups 110 along the second direction Y. This arrangement allows the bridge portion 140 to be located outside the region where the device groups 110 are located, thereby reducing the impact of the bridge portion 140 on the light emission of the electronic components 120 in the device groups 110 and improving the reliability of the substrate 100.

[0428] In other examples, as shown in FIG. 6B , the bridge portion 140 electrically connecting at least two signal lines 131 may also overlap with the area where the device group 110 is located, thereby improving the wiring flexibility of the substrate 100 .

[0429] In some embodiments, as shown in FIG6B , at least one first voltage line 151 in the first voltage line group 150 includes at least two first sub-portions 152 , and the at least two first sub-portions 152 are spaced apart along the second direction Y. The plurality of bridge portions 140 include a plurality of fifth bridge portions 145 , each of which electrically connects two adjacent first sub-portions 152 in the same first voltage line 151 .

[0430] As shown in Figure 6B, two adjacent first sub-sections 152 in the same first voltage line 151 are connected by a fifth bridge portion 145. It is understood that by adjusting the thickness and width of the fifth bridge portion 145, the current carrying capacity of the fifth bridge portion 145 can be adjusted. In some examples, the fifth bridge portion 145 can be configured to have a larger width and thickness to increase its current carrying capacity. In other examples, the fifth bridge portion 145 can be configured to have a smaller width and thickness to meet different usage requirements.

[0431] It can be understood that the greater the current-carrying capacity of the fifth bridging portion 145 is set, the smaller the current-carrying capacity of the first sub-portion 152 can be set, thereby helping to reduce the width of the first sub-portion 152 along the first direction X, helping to achieve a narrow frame of the substrate 100, and also helping to reduce the thickness of the first sub-portion 152, thereby reducing the cost of the substrate 100.

[0432] 6B , each first voltage line 151 in the first voltage line group 150 includes at least two first sub-portions 152. For example, at least one first sub-portion 152 of a first voltage line 151 can be electrically connected to a first sub-portion 152 of another first voltage line 151 via a bridge portion 140.

[0433] In this way, the first sub-sections 152 between different first voltage lines 151 can be electrically connected, thereby reducing the voltage drop on the first sub-section 152, which is beneficial to reducing the width of the first sub-section 152 along the first direction X, and also beneficial to reducing the thickness of the first sub-section 152, thereby reducing the cost of the substrate 100.

[0434] In some examples, as shown in FIG6B , each first voltage line 151 includes two first sub-portions 152. For example, the two first sub-portions 152 include a first first sub-portion 152a and a second first sub-portion 152b. The first first sub-portion 152a and the second first sub-portion 152b are located on either side of a center line Q of the central area AA1 along the second direction Y. It will be appreciated that the center line Q extends along the first direction X and is located at the center of the central area AA1 along the second direction Y.

[0435] It should be noted that the first first sub-portion 152 a and the second first sub-portion 152 b are only used to distinguish two different first sub-portions 152 , and do not further limit the first sub-portion 152 .

[0436] In some examples, as shown in FIG. 6B , the first first sub-portion 152 a is farther away from the bonding area BB than the second first sub-portion 152 b .

[0437] 6B , the first first sub-portions 152 a of the plurality of first voltage lines 151 are electrically connected via the bridge portion 140, and the second first sub-portions 152 of the plurality of first voltage lines 151 are also electrically connected via the bridge portion 140. The first first sub-portion 152 a of one of the first voltage lines 151 is electrically connected to the second first sub-portion 152 a of the first voltage line 151 via the fifth bridge portion 145.

[0438] For example, after the first first sub-portion 152a of the plurality of first voltage lines 151 is electrically connected, it can be electrically connected to the conductive pattern 170 (e.g., the first type first conductive pattern 171a) through the bridge portion 140. After the second first sub-portion 152b of the plurality of first voltage lines 151 is electrically connected, it can also be electrically connected to the conductive pattern 170 (e.g., the first type first conductive pattern 171a) through the bridge portion 140.

[0439] It can be understood that the first first sub-section 152a and the second first sub-section 152b are arranged along the second direction Y, on both sides of the center line Q of the central area AA1, and the first first sub-sections 152a of the multiple first voltage lines 151 are electrically connected, and the second first sub-sections 152b of the multiple first voltage lines 151 are electrically connected, which can reduce the current on each first sub-section 152 (including the first first sub-section 152a and the second first sub-section 152b).

[0440] For example, a first voltage line 151 including two first sub-sections 152 can carry half the current of a single first voltage line 151. Because the current carrying capacity of each first sub-section 152 is smaller, the design requirements for the first sub-sections 152 (e.g., line width, line thickness, or material used) can be reduced. In some examples, this configuration can significantly reduce the thickness of the first sub-sections 152 included in the first voltage line 151, thereby reducing material usage and lowering the cost of the substrate 100.

[0441] In some embodiments, as shown in FIG6B , at least one second voltage line 161 in the second voltage line group 160 includes at least two second sub-portions 162 , and the at least two second sub-portions 162 are spaced apart along the second direction Y. The plurality of bridge portions 140 include a plurality of sixth bridge portions 146 , and the sixth bridge portion 146 electrically connects two adjacent second sub-portions 162 in the same second voltage line 161 .

[0442] As shown in Figure 6B, two adjacent second sub-sections 162 in the same second voltage line 161 are connected by the sixth bridge portion 146. It is understood that by adjusting the thickness and width of the sixth bridge portion 146, the current carrying capacity of the sixth bridge portion 146 can be adjusted. In some examples, the sixth bridge portion 146 can be configured to have a larger width and thickness to increase its current carrying capacity. In other examples, the sixth bridge portion 146 can be configured to have a smaller width and thickness to meet different usage requirements.

[0443] It can be understood that the greater the current-carrying capacity of the sixth bridging portion 146 is set, the smaller the current-carrying capacity of the first sub-portion 152 can be set, thereby helping to reduce the width of the first sub-portion 152 along the first direction X, helping to achieve a narrow frame of the substrate 100, and also helping to reduce the thickness of the first sub-portion 152, thereby reducing the cost of the substrate 100.

[0444] 6B , each second voltage line 161 in the second voltage line group 160 includes at least two second sub-portions 162. For example, at least one second sub-portion 162 of one second voltage line 161 can be electrically connected to a second sub-portion 162 of another second voltage line 161 via a bridge portion 140.

[0445] In this way, the second sub-sections 162 between different second voltage lines 161 can be electrically connected, thereby reducing the voltage drop on the second sub-section 162, which is beneficial to reducing the width of the first sub-section 152 along the first direction X, and also beneficial to reducing the thickness of the first sub-section 152, thereby reducing the cost of the substrate 100.

[0446] In some examples, as shown in FIG6B , any second voltage line 161 includes two second sub-portions 162 . For example, the two second sub-portions 162 include a first second sub-portion 162 a and a second second sub-portion 162 b . The first second sub-portion 162 a and the second second sub-portion 162 b are located along the second direction Y on either side of the center line Q of the central area AA1 .

[0447] It should be noted that the first second sub-portion 162 a and the second second sub-portion 162 b are only used to distinguish two different second sub-portions 162 , and do not further limit the second sub-portion 162 .

[0448] In some examples, as shown in FIG. 6B , the first second sub-portion 162 a is farther away from the bonding area BB than the second second sub-portion 162 b .

[0449] 6B , the first second sub-portions 162 a of the plurality of second voltage lines 161 are electrically connected via the bridge portion 140, and the second second sub-portions 162 of the plurality of second voltage lines 161 are also electrically connected via the bridge portion 140. The first second sub-portion 162 a of one of the second voltage lines 161 is electrically connected to the second second sub-portion 162 a of the second voltage line 161 via the sixth bridge portion 146.

[0450] For example, after the first second sub-portion 162a of the plurality of second voltage lines 161 is electrically connected, it can be electrically connected to the conductive pattern 170 (e.g., the first type second conductive pattern 172a) through the bridge portion 140. After the second second sub-portion 162b of the plurality of second voltage lines 161 is electrically connected, it can also be electrically connected to the conductive pattern 170 (e.g., the first type second conductive pattern 172a) through the bridge portion 140.

[0451] It can be understood that the first second sub-section 162a and the second second sub-section 162b are arranged along the second direction Y, on both sides of the center line Q of the central area AA1, and the first second sub-section 162a of the multiple second voltage lines 161 are electrically connected, and the second second sub-section 162b of the multiple second voltage lines 161 are electrically connected, which can reduce the current on each second sub-section 162 (including the first second sub-section 162a and the second first sub-section 152b).

[0452] For example, a second voltage line 161 including two second sub-sections 162 can carry half the current required by a single second voltage line 161. Because the current carrying capacity of each second sub-section 162 is smaller, the design requirements for the second sub-sections 162 (e.g., line width, line thickness, or material used) can be reduced. In some examples, the above configuration can significantly reduce the thickness of the second sub-sections 162 of the second voltage line 161, thereby reducing material usage and lowering the cost of the substrate 100.

[0453] 6C , at least two second conductive patterns 172 arranged along the second direction Y form a second conductive pattern column 183. A second conductive pattern column 183 adjacent to an edge P of the substrate 101 along the first direction X overlaps with a region where device groups 110 arranged in a column along the second direction Y are located.

[0454] 6C , the second conductive pattern column 183 includes a plurality of second conductive patterns 172. In some examples, as shown in FIG6C , any second conductive pattern 172 in the second conductive pattern column 183 is adjacent to the edge P of the substrate 101 along the first direction X.

[0455] The second conductive pattern row 183 overlaps with the region where a column of device groups 110 arranged along the second direction Y is located. That is, the plurality of second conductive patterns 172 in the second conductive pattern row 183 are located within the region where a column of device groups 110 arranged along the second direction Y is located. It will be understood that the region where a column of device groups 110 is located includes the region where each device group 110 in the column of device groups 110 is located, as well as the region between two adjacent device groups 110 in the column of device groups 110 along the second direction Y.

[0456] It can be understood that the second conductive pattern column 183 overlaps with the area where a column of device groups 110 arranged along the second direction Y is located, which can improve the area utilization of the substrate 101 and allow more device groups 110 to be arranged on the substrate 101.

[0457] In some examples, the second conductive pattern column 183 is located within a region where a column of device groups 110 is located, adjacent to an edge P of the substrate 101 along the first direction X. This arrangement can reduce the distance between the plurality of second conductive patterns 172 within the second conductive pattern column 183 and a side edge P of the substrate 101 along the first direction X, thereby reducing the distance between the second conductive pattern column 183 and the side edge area AA21, and improving the convenience of electrical connection between the signal line 131 (e.g., the second voltage line 161) within the side edge area AA21 and the second conductive pattern column 183.

[0458] In some examples, as shown in FIG6C , the signal lines 131 (e.g., the second voltage lines 161) within the side edge area AA21 can be electrically connected to the bonding pins within the bonding area BB via the second conductive pattern arrays 183. In other words, by providing the second conductive pattern arrays 183, the signal lines 131 within the side edge area AA21 do not need to extend into the lower edge area AA22, thereby reducing the width of the lower edge area AA22 and facilitating a narrower bezel (lower bezel) of the substrate 100.

[0459] In some examples, as shown in FIG6C , the first driver chip 103 is located in the central area AA1, and the second voltage line 161 extends into the central area AA1 and is electrically connected to the first driver chip 103. This arrangement eliminates the need for the first driver chip 103 to occupy space in the side edge area AA21, thereby reducing the width of the side edge area AA21 along the first direction X, thereby facilitating a narrow frame for the substrate 100.

[0460] In some examples, when a column of device groups 110 is electrically connected to multiple first driver chips 103 , as shown in FIG. 6C , the second voltage line 161 includes multiple sub-segments 1621 , which are spaced apart along the second direction Y, and one sub-segment 1621 is electrically connected to one first driver chip 103 .

[0461] It is understandable that the bridge portion 140 may have a certain angle with the first direction X or the second direction Y. As shown in FIG. 6C , the bridge portion 140X is neither parallel to the first direction X nor parallel to the second direction Y.

[0462] Figure 7A is a structural diagram of a substrate according to some further embodiments. Figure 7B is a partial enlarged diagram of area 1 in Figure 7A.

[0463] As can be seen from the above, in some examples, by providing a conductive pattern 170 and a bridging portion 140, etc., multiple signal lines 131 in a signal line group 130 can be electrically connected, and through compensation by the conductive pattern 170, the voltage drop of the signal line 131 can be reduced.

[0464] In some examples, the device area AA is divided into P regions along a first direction X. The P regions are adjacently arranged along the first direction X, and each region is provided with at least two columns of device groups 110. It is understood that the number of columns of device groups 110 in different regions can be the same or different. In some examples, the absolute value of the difference in the number of columns of device groups 110 between any two regions is less than or equal to 2.

[0465] It can be understood that one region corresponds to one bonding area BB. In some examples, as shown in FIG7A and FIG7B , the substrate 100 has four bonding areas BB, that is, the device assembly AA can be divided into four regions along the first direction X (P=4).

[0466] It is understandable that at least two columns of device groups 110 in the same region are connected to the same bonding area BB. For example, in the same region, the plurality of signal line groups 130 connected to one bonding area BB include a first voltage line group 150 and a second voltage line group 160 .

[0467] For example, taking any region in device area AA as an example, at least two first voltage lines 151 in the first voltage line group 150 are electrically connected via the second-type first conductive pattern 171b located in device area AA, and then electrically connected to a bonding pin in a bonding area BB via two first-type first conductive patterns 171a. At least two second voltage lines 161 in the second voltage line group 160 are electrically connected via the second-type second conductive pattern 172b located in device area AA, and then electrically connected to a bonding pin in a bonding area BB via two first-type second conductive patterns 172a.

[0468] It is understandable that since there are four binding areas BB, four flexible circuit boards 105 are required to be electrically connected to the binding areas BB. That is, a large number of binding areas BB will increase the number of flexible circuit boards 105 and thus increase the cost.

[0469] Figure 8A is a structural diagram of a substrate according to further embodiments. Figure 8B is a partial enlarged view of region 2 in Figure 8A. Figure 8C is a partial enlarged view of region 3 in Figure 8A. Figure 8D is a partial enlarged view of region 4 in Figure 8A.

[0470] 8A and 8B , the substrate 100 has only one binding region BB. In some examples, the center line of the binding region BB along the second direction Y coincides with the center line of the device assembly AA along the second direction Y.

[0471] It is understandable that since the substrate 100 is provided with only one binding area BB, the signal lines 131 in the plurality of signal line groups 130 (including the first voltage line group 150 and the second voltage line group 160 ) need to be electrically connected to the binding pins in the same binding area BB.

[0472] It can be understood that setting the number of the binding area BB to one can reduce the number of flexible circuit boards 105, thereby reducing costs.

[0473] The following describes an example of how the first voltage line group 150 and the second voltage line group 160 are electrically connected to the bonding area BB.

[0474] As can be seen from the above, at least two first conductive patterns 171 arranged along the first direction X constitute a first conductive pattern row 181. It is understood that in some examples, the number of first conductive pattern rows 181 can be at least two. In other examples, the number of first conductive pattern rows 181 can also be one. The embodiments of the present disclosure use one first conductive pattern row 181 as an example to illustrate the electrical connection relationship between the first voltage line group 150 and the bonding area BB.

[0475] In some examples, as shown in Figures 8B and 8C, at least two first conductive patterns 171 arranged along the second direction Y constitute a first conductive pattern column 184. As shown in Figure 8C, the first conductive pattern row 181 is electrically connected to the first conductive pattern column 184, and as shown in Figure 8B, the first-type first conductive pattern 171a is electrically connected to the first conductive pattern column 184. It will be understood that the first conductive pattern row 181 and the first conductive pattern column 184 can be located in the central area AA1 of the device area AA to avoid the first conductive pattern row 181 and the first conductive pattern column 184 occupying space in the edge area AA2 (including the side edge area AA21 and the lower edge area AA22), thereby facilitating a narrow frame of the substrate 100.

[0476] In some examples, as shown in FIG8C , multiple first voltage lines 151 in the first voltage line group 150 can be electrically connected via a first conductive pattern row 181. One first conductive pattern 171 in a first conductive pattern column 184 is electrically connected to the first conductive pattern row 181 via a bridge 140. As shown in FIG8B , another first conductive pattern 171 in the first conductive pattern column 184 is electrically connected to a first-type first conductive pattern 171a via a bridge 140, thereby enabling the electrically connected multiple first voltage lines 151 in the first voltage line group 150 to be electrically connected to a binding pin.

[0477] As can be understood, because the multiple first conductive patterns 171 in the multiple first conductive pattern columns 184 are arranged in a row along the second direction Y, the electrically connected multiple first voltage lines 151 can be electrically connected to the binding pins within a single binding area BB via the first-type first conductive patterns 171a. In other words, by providing the first conductive pattern rows 181 and the first conductive pattern columns 184, the multiple first voltage lines 151 can be electrically connected to the binding pins within a single binding area BB.

[0478] In this way, the number of flexible circuit boards 105 connected to the binding pins can be reduced, thereby reducing the cost of the substrate 100 .

[0479] In some examples, the first conductive pattern column 184 is electrically connected to the binding pin through a first-type first conductive pattern 171a, reducing the number of first-type first conductive patterns 171a, and can reduce the number of binding pins electrically connected to the first voltage line 151, thereby reducing the width of the flexible circuit board 105 along the first direction X and reducing the cost of the substrate 100.

[0480] That is, by providing the first conductive pattern rows 181 and the first conductive pattern columns 184 , the substrate 100 can reduce the number of binding areas BB and the number of binding pins electrically connected to the first voltage line group 150 while achieving a narrow frame, thereby reducing costs.

[0481] In addition, by providing electrical connections through multiple first voltage lines 151 through the first conductive pattern column 184 and electrically connecting to the binding pins in a binding area BB, the number of bridge portions 140 can be reduced, thereby simplifying the preparation process of the substrate 100, improving the production efficiency of the substrate 100, and reducing costs.

[0482] In some embodiments, the first conductive pattern row 181 is located at the center of the device area AA along the second direction Y.

[0483] It can be understood that arranging the first conductive pattern row 181 at the center of the device area AA along the second direction Y enables the plurality of first voltage lines 151 to be electrically connected at the center position along the second direction Y. In this way, the current value that the first voltage line 151 needs to carry is half of the current value that the first voltage line 151 needs to carry when the first conductive pattern row 181 is not provided.

[0484] That is, arranging the first conductive pattern row 181 in the center of the device area AA along the second direction Y can reduce the current value that the first voltage line 151 needs to carry, reduce the risk of overloading the first voltage line 151, and improve the reliability of the substrate 100. In addition, it can also facilitate the thinning of the first voltage line 151, reducing the cost of the substrate 100.

[0485] In some examples, the first conductive pattern row 181 is located in the center of the device area AA along the second direction Y, so that the thickness of the first voltage line 151 can be reduced to half of the thickness when the first conductive pattern row 181 is not provided.

[0486] As can be seen from the above, in some embodiments, as shown in FIG8D , multiple second voltage lines 161 in a second voltage line group 160 are interconnected on a side away from the bonding area BB along the second direction Y. Furthermore, at least two second conductive patterns 172 arranged along the second direction Y form a second conductive pattern column 183 .

[0487] In some embodiments, as shown in Figures 8B and 8D , the second conductive pattern column 183 is electrically connected to a side of the plurality of second voltage lines 161 in a second voltage line group 160 that is away from the bonding area BB, and the first-type second conductive pattern 172a is electrically connected to the second conductive pattern column 183. It will be appreciated that the plurality of second voltage lines 161 in a second voltage line group 160 are interconnected on a side away from the bonding area BB along the second direction Y, enabling electrical connection of the plurality of second voltage lines 161 in a second voltage line group 160.

[0488] As shown in Figures 8B and 8D , one second conductive pattern 172 in the second conductive pattern row 183 is electrically connected to one end of the plurality of second voltage lines 161 away from the bonding area BB. As shown in Figure 8B , another second conductive pattern 172 in the second conductive pattern row 183 is electrically connected to the first-type second conductive pattern 172a, allowing the plurality of second voltage lines 161 to be electrically connected to the bonding pins through the second conductive pattern row 183.

[0489] As can be understood, because the multiple second conductive patterns 172 in the multiple second conductive pattern columns 183 are arranged in a row along the second direction Y, the electrically connected multiple second voltage lines 161 can be electrically connected to the binding pins within a single binding area BB via the first-type second conductive patterns 172a. In other words, by providing the second conductive pattern columns 183, the multiple second voltage lines 161 can be electrically connected to the binding pins within a single binding area BB.

[0490] In this way, the number of flexible circuit boards 105 connected to the binding pins can be reduced, thereby reducing the cost of the substrate 100 .

[0491] In some examples, the second conductive pattern column 183 is electrically connected to the binding pin through a first-type second conductive pattern 172a, reducing the number of first-type second conductive patterns 172a, and can reduce the number of binding pins electrically connected to the second voltage line 161, thereby reducing the width of the flexible circuit board 105 along the first direction X and reducing the cost of the substrate 100.

[0492] That is, by providing the second conductive pattern column 183 , the substrate 100 can reduce the number of bonding areas BB and the number of bonding pins electrically connected to the second voltage line group 160 while achieving a narrow frame, thereby reducing costs.

[0493] In addition, by providing electrical connections through multiple second voltage lines 161 through the second conductive pattern column 183 and electrically connecting to the binding pins in a binding area BB, the number of bridge portions 140 can be reduced, thereby simplifying the preparation process of the substrate 100, improving the production efficiency of the substrate 100, and reducing costs.

[0494] It can be understood that the multiple second voltage lines 161 in a second voltage line group 160 extend along the second direction Y, and one second voltage line 161 is located on the second side of a column of device groups 110 electrically connected to the second voltage line 161. The multiple second voltage lines 161 do not extend to the lower edge area AA22, but are connected to each other on the side away from the bonding area BB along the second direction Y. As a result, the second conductive pattern column 183 can be electrically connected to the multiple second voltage lines 161 on the side away from the bonding area BB along the second direction Y.

[0495] That is, the embodiment of the present disclosure can connect the plurality of second voltage lines 161 in the second voltage line group 160 to each other at a side away from the binding area BB along the second direction Y, and electrically connect them to the binding pins through a second conductive pattern column 183 .

[0496] It can be understood that the multiple second voltage lines 161 in a second voltage line group 160 are interconnected on the side away from the binding area BB along the second direction Y, thereby increasing the area of ​​the conductive structure (the multiple signal line groups 130 and the multiple conductive patterns 170) on the conductive layer as projected onto the substrate 101. For example, when the conductive layer is made of Cu, the multiple second voltage lines 161 in a second voltage line group 160 are interconnected on the side away from the binding area BB along the second direction Y. This can increase the ratio of the Cu area in the conductive layer to the area of ​​the substrate 101, thereby improving the ESD (Electro Static Discharge) capability of the substrate 100 and enhancing the reliability of the substrate 100.

[0497] In some examples, as shown in FIG8B to FIG8D , the substrate 100 further includes a packaging portion 122 . The packaging portion 122 is located on a side of the electronic component 120 away from the substrate 101 and covers the electronic component 120 .

[0498] It can be understood that the packaging part 122 can protect the electronic component 120. On the one hand, it can prevent the electronic component 120 from being corroded by external water or oxygen; on the other hand, it can reduce the risk of the electronic component 120 being scratched and dropped under the action of external force, thereby extending the service life of the electronic component 120 and improving the reliability of the substrate 100.

[0499] In some examples, when the electronic component 120 is a light-emitting diode, the packaging portion 122 that covers the light-emitting diode is made of a transparent material (e.g., transparent silicone) to reduce light blocking by the packaging portion 122. When the electronic component 120 is not a light-emitting element or a light-sensing element, the packaging portion 122 can be made of a non-transparent material.

[0500] In some examples, the packaging portion 122 may be mushroom-shaped or approximately mushroom-shaped. It is understandable that the shapes of the packaging portions 122 covering different electronic components 120 may be the same or different.

[0501] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A substrate having multiple edges; the substrate comprising a device region and at least one bonding region, the bonding region being closer to any edge of the substrate relative to the device region; the substrate comprising: substrate; A plurality of device groups are located on one side of the substrate, and the plurality of device groups are located in the device area; The plurality of device groups are arranged along a first direction and a second direction respectively; the first direction and the second direction intersect, and the first direction and the second direction are parallel to the substrate; a device group includes at least one electronic component; A plurality of signal line groups are located on the same side of the substrate as the plurality of device groups; one signal line group includes a plurality of signal lines; the plurality of signal lines all extend along the second direction, and the plurality of signal lines are arranged at intervals along the first direction; any one of the signal lines extends from the binding area to the device area, and any one of the signal lines is electrically connected to a column of the device groups arranged along the second direction; as well as, A plurality of conductive patterns, located on the same side of the substrate as the plurality of device groups; at least one conductive pattern among the plurality of conductive patterns is located in a region where one of the device groups is located; and / or, at least one conductive pattern among the plurality of conductive patterns is located in a region between two adjacent device groups; At least one of the signal lines in at least one of the signal line groups is electrically connected to one of the conductive patterns.

2. The substrate according to claim 1, wherein The plurality of conductive patterns are arranged in the same layer as the plurality of signal line groups.

3. The substrate according to claim 1 or 2, wherein The plurality of signal line groups include: a first voltage line group, wherein the first voltage line group includes a plurality of first voltage lines; The plurality of conductive patterns include a plurality of first conductive patterns electrically connected to at least one first voltage line in the first voltage line group.

4. The substrate according to claim 3, further comprising: A plurality of first bridge portions are provided, and at least one first conductive pattern is electrically connected to one of the first voltage lines via the first bridge portion.

5. The substrate according to claim 4, wherein At least one of the plurality of first bridge portions is a jumper resistor.

6. The substrate according to any one of claims 3 to 5, wherein At least one of the first conductive patterns and one of the first voltage lines form an integrated structure.

7. The substrate according to any one of claims 3 to 6, wherein: At least two of the first conductive patterns are arranged along the first direction.

8. The substrate according to claim 7, wherein At least two of the first conductive patterns arranged along the first direction constitute a first conductive pattern row, and the plurality of first conductive patterns constitute at least two of the first conductive pattern rows.

9. The substrate according to claim 8, wherein The number of the first conductive pattern rows is two, and the number of the first conductive patterns included in the two first conductive pattern rows is different; the length of any one of the device groups along the second direction is L; along the second direction, one first conductive pattern row is close to the binding area relative to the other first conductive pattern row, and the interval between the two first conductive pattern rows along the second direction is in the range of 3L to 5L.

10. The substrate according to claim 8 or 9, wherein The plurality of device groups include a first row of device groups, the first row of device groups being adjacent to the bonding region along the second direction; At least one first conductive pattern row is located in a region where the first row device group is located.

11. The substrate according to any one of claims 3 to 10, wherein The plurality of first conductive patterns include first-type first conductive patterns; One end of the first-type first conductive pattern is directly connected to an end of the binding area close to the device area, and the other end of the first-type first conductive pattern is electrically connected to the first voltage line group; The number of the first-type first conductive patterns is a, where a is smaller than the number of the first voltage lines in the first voltage line group, and a is a positive integer.

12. The substrate according to claim 11, wherein a is not greater than half the number of the first voltage lines in the first voltage line group.

13. The substrate according to any one of claims 3 to 12, wherein The plurality of signal line groups further include: a second voltage line group, wherein the second voltage line group includes a plurality of second voltage lines; The plurality of conductive patterns further include a plurality of second conductive patterns electrically connected to at least one second voltage line in the second voltage line group.

14. The substrate according to claim 13, further comprising: A plurality of second bridge portions are provided, and at least one second conductive pattern is electrically connected to one of the second voltage lines via the second bridge portion.

15. The substrate according to claim 14, wherein At least one of the plurality of second bridge portions is a jumper resistor.

16. The substrate according to any one of claims 13 to 15, wherein At least one of the second conductive patterns and one of the second voltage lines form an integrated structure.

17. The substrate according to any one of claims 13 to 16, wherein At least two of the second conductive patterns are arranged along the first direction.

18. The substrate according to claim 17, wherein At least two second conductive patterns arranged along the first direction constitute a second conductive pattern row, and the plurality of second conductive patterns constitute at least two second conductive pattern rows.

19. The substrate according to claim 18, wherein The number of the second conductive pattern rows is two, and the number of second conductive patterns included in the two second conductive pattern rows is different; the length of any one of the device groups along the second direction is L; along the second direction, one second conductive pattern row is close to the binding area relative to the other second conductive pattern row, and the interval between the two second conductive pattern rows along the second direction is in the range of 3L to 5L.

20. The substrate according to claim 18 or 19, wherein The plurality of device groups include a first row of device groups, the first row of device groups being adjacent to the bonding region along the second direction; At least one second conductive pattern row is located in the region where the first row device group is located.

21. The substrate according to any one of claims 13 to 20, wherein The plurality of second conductive patterns include a first type of second conductive patterns; One end of the first-type second conductive pattern is directly connected to one end of the binding area close to the device area, and the other end of the first-type second conductive pattern is electrically connected to the second voltage line group; The number of the first-type second conductive patterns is b, where b is smaller than the number of the second voltage lines in the second voltage line group, and b is a positive integer.

22. The substrate according to claim 21, wherein Y is not greater than half the number of the second voltage lines in the second voltage line group.

23. The substrate according to any one of claims 13 to 22, further comprising: a plurality of third bridge portions, at least two of the first conductive patterns being electrically connected via the third bridge portions; and / or, A plurality of fourth bridge portions, at least two of the second conductive patterns are electrically connected via the fourth bridge portions.

24. The substrate according to any one of claims 13 to 23, wherein In the same first voltage line group, at least two first voltage lines are connected to each other on a side away from the binding area along the second direction; and / or, In the same second voltage line group, at least two second voltage lines are connected to each other at a side away from the binding area along the second direction.

25. The substrate according to any one of claims 13 to 24, wherein The width of the first voltage line along the first direction ranges from 0.5 mm to 1 mm; and / or the width of the second voltage line along the first direction ranges from 0.5 mm to 1 mm.

26. The substrate according to any one of claims 13 to 25, wherein Any one of the first voltage lines is located along the first direction on the first side of a column of the device groups electrically connected to the first voltage line; any one of the second voltage lines is located along the first direction on the second side of a column of the device groups electrically connected to the second voltage line.

27. The substrate according to any one of claims 1 to 26, wherein There are multiple binding areas, and multiple signal lines in one signal line group are electrically connected to one of the multiple binding areas.

28. The substrate according to any one of claims 1 to 27, further comprising: an electrostatic loop, disposed around the plurality of device groups and electrically connected to the binding area; A circuit board is electrically connected to the binding area.

29. An electronic device comprising the substrate according to any one of claims 1 to 28.

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