Interface connection disconnection protocol

Abstract

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for managing an interface between a pair of processing cores of a device configured to exchange data. The apparatus is configured to enable or disable one or more processing cores of a pair of processing cores. One of the methods includes: configuring a connected / disconnected interface implemented as logical circuitry between a pair of processing cores to assume a connected state in which the pair of processing cores can exchange data; and configuring a connection / disconnection interface between the pair of processing cores to assume a disconnected state in which one or more of the processing cores are unable to receive data.

Description

Background Art

[0001] Mobile computing devices—e.g., smart phones, personal digital assistants, electronic tablets, laptop computers, etc.—typically use power provided by one or more rechargeable batteries. Rechargeable batteries only provide a limited amount of power to the device before they must be recharged, such as by applying an electrical current to the battery. Recharging the battery of a mobile computing device typically requires connecting the mobile computing device to an electrical power grid, which reduces or eliminates the mobility of the mobile computing device.

[0002] Mobile computing devices often include a system on a chip (SOC) that provides many of the functions required in the device. Because mobile computing devices often operate from a limited power source (e.g., a battery), energy conservation is a key design consideration for the device. Therefore, it is desirable to frequently power down at least some components of the SOC to eliminate leakage current losses, which are a significant factor in energy consumption in modern integrated circuit technology.

[0003] However, a more reliable communication protocol is needed to determine the status of data interfaces between different components of the SOC, because traffic (i.e., data transfer) between active components of the SOC and standby components that cannot receive data may often result in unrecoverable data loss, which hinders device performance and user experience. Summary of the invention

[0004] This specification describes techniques for implementing and managing a connect / disconnect interface between a pair of processing cores of a system on a chip (SOC) of a computing device. The connect / disconnect interface enables a more reliable communication protocol for a computing device that has to cope with frequent power failures of various components of the SOC.

[0005] In general, an innovative aspect of the subject matter described in this specification can be embodied as a device comprising a pair of processing cores configured to exchange data, and wherein the device is configured to enable or disable one or more processing cores in the pair of processing cores, and wherein the device comprises a logic circuit system that implements a connect / disconnect interface between the pair of processing cores, wherein the connect / disconnect interface between the pair of processing cores is configured to adopt: a connect state, in which the pair of processing cores can exchange data; and a disconnect state, in which one or more of the processing cores cannot receive data.

[0006] Other embodiments of this aspect include corresponding methods, which include operations performed by devices, computer systems, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method.

[0007] The foregoing and other embodiments may each optionally include one or more of the following features, alone or in combination. In particular, one embodiment includes all of the following features in combination.

[0008] A pair of processing cores that share a connect / disconnect interface may be controlled by a corresponding power controller.

[0009] While in the disconnected state, the interface may adopt a disconnect-with-wakeup mode during which new traffic causes the interface to adopt a connected state.

[0010] When in the disconnected state, the interface may adopt a disconnect-with-terminate mode during which any traffic is terminated by one of the processing cores in the pair of processing cores.

[0011] Each processing core may be configured to transmit output signals to another processing device including: i) sending a request to connect, ii) sending a request to disconnect, and iii) sending a rejection of a disconnect request.

[0012] Each processing core may be configured to receive input signals from another processing device, including: i) receiving a request to connect, ii) receiving a request to disconnect, and iii) receiving a rejection of a disconnect request.

[0013] Output and input signals may be implemented using six separate wires between the processing cores.

[0014] Specific embodiments of the subject matter described in this specification may be implemented to achieve one or more of the following advantages. A system on chip (SOC) may more reliably exchange data between multiple processing cores of the SOC by utilizing a connect / disconnect interface implemented in addition to a data interface for data transfer between processing cores. The connect / disconnect interface allows a processing core to initiate business only to other processing cores that are capable of receiving business, without initiating business to any processing core that is in standby mode or other low-power mode and may not have the clock or power required to capture ongoing business. This approach avoids unrecoverable data loss that may otherwise occur when a processing core initiates business to another processing core that may already be in standby mode or may be transitioning to / from standby mode, and further eliminates the need to restart the system due to such data loss. This approach improves the user experience of a device implementing the SOC while also reducing the power consumption of the device.

[0015] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a diagram of an example system.

[0017] Figure 2 is an example illustration of a data interface and a connect / disconnect interface.

[0018] Figure 3 is a flow diagram of an example process for managing an interface between a pair of processing cores.

[0019] Figure 4 is an illustration of an example state diagram that handles different states of an interface between a pair of cores.

[0020] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0021] Figure 1 1 is a diagram of an example system 100. The system includes multiple independent processing cores, for example, processing cores 110a and 110b. Multiple processing cores are generally capable of providing data processing capabilities, although they can be implemented in different ways and for different purposes. For example, implementations of such cores may include: 1) a general-purpose programmable processing core that includes registers, control circuitry, and an arithmetic logic unit (ALU) intended for general-purpose computing; and 2) a special-purpose processing core that has special-purpose hardware intended primarily for graphics computing, signal processing computing, cryptographic computing, etc.

[0022] The system also includes a corresponding power controller for each of the multiple processing cores, e.g., power controllers 130a and 130b. Each power controller may generally include the logic and components required to regulate the power state of the multiple processing cores. In some implementations, the power controllers independently shut down or adjust the voltage to each processing core by operating independently of each other, while in other implementations, both of them may be managed by a common power manager that controls which components of the system 100 receive power and how much power each component receives.

[0023] Multiple independent processing cores and their corresponding power controllers may be integrated onto a single system on a chip (SOC) 102. SOC 102 may be an integrated circuit that includes the foregoing components of the system and possibly other components on a single silicon substrate or on multiple interconnected dies—for example, using a silicon interposer, stacked dies, or interconnect bridges.

[0024] SOC 102 is an example of a device that may be installed on or integrated into any suitable computing device, which may be referred to as a host device. Because the techniques described in this specification are particularly well suited to reducing power consumption and improving performance of host devices, SOC 102 may be particularly beneficial when installed on a mobile host device that relies on battery power, such as a smartphone, smart watch or other wearable computing device, tablet computer, or laptop computer, to name a few examples.

[0025] Note that the number of components of SOC 102 may vary depending on the implementation. For example, there may be more than Figure 1 Greater numbers of processing cores are shown, which may be included in the same processor or in separate processors.

[0026] SOC 102 includes logic circuitry that implements a corresponding interface block for each of the plurality of processing cores that functions as a communication interface between the plurality of processing cores 110a-b and other components in SOC 102, including power controllers 130a-b. A power controller for each of the plurality of processing cores, e.g., power controller 130a, may be connected to a corresponding processing core, e.g., processing core 110a, and to an interface block for the corresponding processing core, e.g., interface block 120a. Figure 1 As shown, the control interface between the power controller and the processing core and the interface block, for example, the control interface 132a-134a and the control interface 132b-134b, can convey control signals, such as voltage control signals, to the processing core and the interface block. The control interface protocol exchanged between the power controller, the processing core and the interface block is used to support the handshake protocol between the interface blocks by providing the function of continuously monitoring the interface status provided by the interface block 120a-b.

[0027] The interface block of each processing core, e.g., interface block 120a of processing core 110a, can be coupled to another interface block of another processing core, e.g., interface block 120b of processing core 110b, through a programmable interconnect of SOC 102. The programmable interconnect is coupled to multiple interface blocks to form connections so that one or more links or channels can be formed to transmit data packets or other signals between the processing core pair. The programmable interconnect can be, for example, an asynchronous interconnect or a combinatorial interconnect.

[0028] like Figure 1As shown, a pair of interface blocks 120a-b provide an interface including: 1) a point-to-point data interface 122 for communication between corresponding processing core pairs, wherein the transmission and reception of data packets occur on a unidirectional link pair, or wherein the transmission and reception of data packets occur on a simultaneous bidirectional link; and 2) a connect / disconnect interface 124, which allows the corresponding processing core pair to access the state of the interface between them, i.e., the connected state or the disconnected state. By allowing the processing core pair to view and change whether the interface between them is in a connected state or a disconnected state without any race conditions, the connect / disconnect interface 124 allows one processing core to initiate a service through the point-to-point data interface 122 only to another processing core that can receive the service. For example, when the interface is in a connected state, a data packet initiated by processing core 110a can enter through interface block 120a, pass through the programmable interconnect, and reach processing core 110b through interface block 120b.

[0029] Figure 2 is an example diagram of an interface 200, which includes Figure 1 The data interface 122 and the connection / disconnection interface 124 between the processing cores 110a-b of the processing cores 110a-b. The data interface 122 may include a point-to-point link pair as shown in the figure, wherein the processing core 110a can be connected to a first link 123a for receiving data sent by the processing core 110b and a second link 123b for transmitting data to the processing core 110b. In other words, it can be said that the link 123a and the link 123b form a data interface between the processing core 110a and the processing core 110b. Therefore, the processing cores 110a-110b can each include a transceiver capable of transmitting and receiving data packets on the corresponding links 123a-b.

[0030] exist Figure 2 In the example of FIG. 1 , the connect / disconnect interface 124 is implemented as a six-wire handshake protocol, where two mode bits work in conjunction with the control interface protocol. The six separate lines include a request line (u0req), an acknowledgement line (u0ack), and a negative acknowledgement line (u0nak) flowing in one direction, and a request line (u1req), an acknowledgement line (u1ack), and a negative acknowledgement line (u1nak) flowing in the other direction.

[0031] For a total of six signals for the handshake protocol, each processing core transmits three signals (idoreq, idoack, idonak), and receives three signals (idireq, idiack, idinak). The handshake protocol provides each processing core with the ability to: 1) send a request to connect; 2) send a request to disconnect; and 3) send a rejection of a request to disconnect. Likewise, the handshake protocol also provides each processing core with the ability to: 1) receive a request to connect; 2) receive a request to disconnect; and 3) receive a rejection of a request to disconnect.

[0032] In terms of handshake protocols, the connect / disconnect interface 124 includes two three-signal sub-handshake protocols that coordinate with each other to achieve connection and disconnection of the interface 200. Specifically, three signals idoreq, idiack, and idinak are used to manage—i.e., connect or disconnect—the outgoing link of the processing core, and the remaining three signals idireq, idoack, and idonak are used to manage the incoming link of the processing core.

[0033] Each processing core also transmits a 1-bit idomode signal (received as idimode at the other processing core) indicating which disconnect mode is being requested. For example, a low idomode signal indicates disconnect mode with termination, while a high idomode signal indicates disconnect mode with wakeup.

[0034] These mode signals may not be considered part of the handshake protocol, but are used to determine the operating mode of the handshake. Combining the incoming and outgoing mode signals allows the two processing cores to reach the same disconnect state. The requirements for the mode signals are: 1) when either or both processing cores intend to disconnect with termination, the interface 200 must reach a disconnect mode with termination; and 2) when both processing cores intend to disconnect with wakeup, the interface 200 must reach a disconnect mode with wakeup. The mode signals must be stable before performing a connect or disconnect handshake. This eliminates any possible race conditions between the two processing cores that perceive the interface 200 to be in different states.

[0035] In this specification, the term wake-up (or enable) will be used to mean the amount of power supplied to a particular processing core or other electronic circuit system that is increased. SOC 102 may or may not have supplied power to the processing component or other circuit system being awakened. In other words, the processing core being awakened may or may not have been completely powered off before. Waking up the processing core may cause the processing core to perform a startup process and cause instructions and data for the processing core to be loaded into a random access memory. Alternatively or additionally, waking up the processing core may include recovering from a previous suspended state. In this specification, the term terminate (or disable) will be used to mean the amount of power supplied to a particular processing core or other electronic circuit system that is reduced, and the particular processing core or other electronic circuit system may not have been in an activated state before. Terminating the processing core may cause the processing core to perform a shutdown process and cause instructions and data for the processing core to be erased from the random access memory.

[0036] Figure 3 3 is a flow chart of an example process 300 for managing an interface between a pair of processing cores. The example process 300 may be performed by a pair of processing cores, which may be any two processing cores of a SOC having corresponding interface blocks that provide an interface between the processing cores, including a data interface and a connect / disconnect interface. The example process 300 will be described as being performed by a pair of processing cores on a device's SOC having corresponding interface blocks appropriately programmed according to the present specification.

[0037] The processing core pair is generally capable of providing data processing capabilities and exchanging data among themselves. One or more processing cores in the processing core pair may be enabled or disabled by the device using a power controller that regulates the power state of the processing cores.

[0038] The connection / disconnection interface between the processing core pair adopts the connection state of the interface, in which the processing core pair can exchange data (310). Therefore, step 310 can be referred to as a connection handshake protocol. The connection state refers to the state of the interface during which the processing core pair can initiate and / or receive services through the data interface. The interface in the connection state can transmit services at any time.

[0039] In order to transition to the connected state, one processing core generates a connection request to the other processing core by sending a high idoreq signal (which is received as a high idireq signal at the other processing core) through the connect / disconnect interface, and the other processing core can send a reply confirmation (i.e., a high idoack signal) back to the one processing core, which is received as a high idiack signal at the one processing core.

[0040] The connect / disconnect interface between the processing core pair adopts a disconnected state of the interface in which one or more of the processing cores cannot receive data (320). Therefore, step 320 can be referred to as a disconnect handshake protocol. The disconnected state refers to a state of the interface during which the processing core may not initiate traffic over the data interface because the other processing core may not be in an enabled state to receive such traffic. An interface in a disconnected state may not transmit traffic over the data interface.

[0041] In order to transition to the disconnected state, one processing core generates a disconnection request to the other processing core by sending a low idoreq signal (which is received as a low idireq signal at the other processing core) through the connect / disconnect interface, and the other processing core can send a reply confirmation (i.e., a low idoack signal) back to the one processing core, which is received as a low idiack signal at the one processing core.

[0042] Unlike a connect request from one processing core to another processing core, which cannot be rejected because the interface connection is a planned event, a disconnect request can be rejected by another processing core. That is, after receiving a low idireq signal, another processing core can send back a negative reply confirmation (i.e., a high idonak signal) that is received as a high idinak signal at the processing core. In this case, the interface returns to the connected state.

[0043] In the disconnect state, there are two modes: 1) a disconnect with wakeup (DSCWK) mode, during which a new service causes the interface to adopt a connected state; and 2) a disconnect with termination (DSCGT) mode, during which any service is terminated by one of the processing cores in the processing core pair, for example, by the initiating processing core. That is, the disconnect with wakeup (DSCWK) mode allows a connection request to be generated based on new services for the interface, while the disconnect with termination (DSCGT) mode does not allow any service to cause the interface to exit the disconnect state and enter the connected state. In order to indicate which disconnect mode is being requested, one processing core may additionally send an idomode signal (which is received as idimode at the other processing core) through the connect / disconnect interface.

[0044] Figure 4 is an illustration of an example state diagram 400 that processes different states of an interface between a pair of cores. State diagram 400 describes states associated with an interface and possible state transitions between states.

[0045] The interface may be in disconnect with termination (DSCGT) mode 410. A mode transition from DSCGT mode 410 to disconnect with wakeup (DSCWK) mode 420 may occur when both processing cores have power, clock, and are not in reset. This indicates that each processing core is ready to participate in a connection handshake.

[0046] While in DSCWK mode 420, if either processing core detects that it has new traffic for the data interface between the pair of processing cores, it then generates a connection request to the other processing core using the connection handshake protocol as described above, which when accepted by the other processing core causes the interface to transition to the connected state 430. Thereafter, the pair of processing cores can begin exchanging data.

[0047] Later, when the power controller of any processing core detects that the interface has been inactive—e.g., has zero traffic—for a predetermined amount of time, the power controller can generate an opportunistic disconnect request using the disconnect handshake protocol as described above. If the other processing core accepts the disconnect request, the interface transitions from the connected state 430 to the DSCWK state 420.

[0048] Alternatively, if the other processing core sends a rejection (negative acknowledgement) of the disconnect request, the interface remains in the connected state 430 .

[0049] Further alternatively, when either power controller detects that the interface has been inactive for a predetermined amount of time, or when the power controller receives a command for a planned low power state, the power controller can generate a planned disconnect request using the disconnect handshake protocol as described above. If the other processing core accepts the disconnect request, the interface transitions from the connected state 430 to the DSCGT state 410.

[0050] Embodiments of the subject matter and functional operations described in this specification may be implemented in digital electronic circuit systems, in tangibly embodied computer software or firmware, in computer hardware including the structures disclosed in this specification and their structural equivalents, or in a combination of one or more of them. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory storage medium, for execution by a data processing device or for controlling the operation of a data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. Alternatively or in addition, program instructions may be encoded on an artificially generated propagation signal (e.g., a machine-generated electrical, optical, or electromagnetic signal), which is generated to encode information for transmission to a suitable receiver device for execution by a data processing device.

[0051] The term "data processing equipment" refers to data processing hardware, and includes all kinds of equipment, devices and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. The equipment may also be or further include a dedicated logic circuit system, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, the equipment may also optionally include code for creating an execution environment for a computer program, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0052] A computer program, which may also be referred to or described as a program, software, software application, app, module, software module, script or code, may be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages); and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, subroutines or code portions). A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a data communications network.

[0053] For a system of one or more computers to be configured to perform specific operations or actions, it is meant that the system has installed thereon software, firmware, hardware, or a combination thereof that, in operation, causes the system to perform those operations or actions. For one or more computer programs to be configured to perform specific operations or actions, it is meant that the one or more programs include instructions that, when executed by a data processing device, cause the device to perform the operations or actions.

[0054] As used in this specification, "engine" or "software engine" refers to a hardware-implemented or software-implemented input / output system that provides an output different from the input. The engine can be implemented in a dedicated digital circuit system, or implemented as a computer-readable instruction to be executed by a computing device. Each engine can be implemented in any suitable type of computing device including one or more processing modules and a computer-readable medium, such as a server, a mobile phone, a tablet computer, a notebook computer, a music player, an e-book reader, a laptop or desktop computer, a PDA, a smart phone, or other fixed or portable device. In addition, two or more engines in an engine can be implemented on the same computing device or on different computing devices.

[0055] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by a dedicated logic circuit system such as an FPGA or ASIC, or by a combination of a dedicated logic circuit system and one or more programmed computers.

[0056] A computer suitable for executing a computer program may be based on a general or special purpose microprocessor or both, or any other kind of central processing unit. Typically, the central processing unit will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer are a central processing unit for fulfilling or executing instructions and one or more memory devices for storing instructions and data. The central processing unit and the memory may be supplemented by or incorporated into a dedicated logic circuit system. Typically, the computer will also include one or more mass storage devices for storing data, such as a magnetic disk, a magneto-optical disk, or an optical disk, or will be operatively coupled to receive data from or transfer data to the one or more mass storage devices, or both. However, the computer does not have to have such a device. In addition, the computer may be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.

[0057] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0058] To provide interaction with a user, embodiments of the subject matter described in this specification may be implemented on a host device having a display device for displaying information to the user, such as a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, and a keyboard and pointing device, such as a mouse, trackball, or presence sensitive display or other surface, through which the user can provide input to the computer. Other kinds of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user may be received in any form, including sound, voice, or tactile input. In addition, the computer may interact with the user by sending documents to and receiving documents from the device used by the user; for example, by sending a web page to a web browser on the user's device in response to a request received from the web browser. In addition, the computer may interact with the user by sending text messages or other forms of messages to a personal device, such as a smart phone running a messaging application, and receiving a responsive message from the user in response.

[0059] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but should be interpreted as descriptions of features that may be peculiar to a particular embodiment of a particular invention. Certain features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may involve a variant of a sub-combination or a sub-combination.

[0060] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed to achieve the desired results. In certain contexts, multitasking and parallel processing can be advantageous. In addition, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0061] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the actions set forth in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain cases, multitasking and parallel processing can be advantageous.

Claims

1. An apparatus comprising a pair of processing cores configured to exchange data, and wherein the apparatus is configured to enable or disable one or more processing cores in the pair of processing cores, and wherein the apparatus comprises logic circuitry implementing a connect / disconnect interface between the pair of processing cores, The connect / disconnect interface between the processing core pair is configured to adopt: a connect state, in which the processing core pair can exchange data; and a disconnect state, in which one or more of the processing cores cannot receive data.

2. The apparatus of claim 1, wherein the pair of processing cores sharing the connect / disconnect interface are controlled by corresponding power controllers.

3. The apparatus according to any one of claims 1 to 2, wherein when in the disconnected state, the interface is capable of adopting a disconnected mode with wake-up, during which new traffic causes the interface to adopt a connected state.

4. The apparatus of claim 3, wherein when in the disconnected state, the interface is capable of adopting a disconnected mode with termination, during which any traffic is terminated by one of the processing cores in the pair of processing cores.

5. The apparatus according to any one of claims 1 to 4, wherein each processing core is configured to transmit an output signal to another processing device, comprising: i) sending a request to connect, ii) sending a request to disconnect, and iii) sending a rejection of the disconnect request.

6. The apparatus of claim 5, wherein each processing core is configured to receive an input signal from the another processing device, comprising: i) receiving a request to connect, ii) receiving a request to disconnect, and iii) receiving a rejection of the disconnect request.

7. The apparatus of any one of claims 5 to 6, wherein the output signal and the input signal are implemented using six separate lines between the processing cores.

8. A method performed by an apparatus, the apparatus comprising a pair of processing cores configured to exchange data, and wherein the apparatus is configured to enable or disable one or more processing cores in the pair of processing cores, and wherein the apparatus comprises logic circuitry implementing a connect / disconnect interface between the pair of processing cores, wherein the method comprises: configuring the connect / disconnect interface between the pair of processing cores to adopt a connected state in which the pair of processing cores can exchange data, and The connect / disconnect interface between the pair of processing cores is configured to adopt a disconnect state in which one or more of the processing cores are unable to receive data.

9. The method of claim 8, wherein the pair of processing cores sharing the connect / disconnect interface are peer processing cores both controlled by a power manager.

10. The method according to any one of claims 8 to 9, wherein when in the disconnected state, the interface is capable of adopting a disconnected mode with wake-up, during which new traffic causes the interface to adopt a connected state.

11. The method of claim 10, wherein when in the disconnected state, the interface is capable of adopting a disconnected mode with termination, during which any traffic is terminated by one of the processing cores in the pair of processing cores.

12. The method according to any one of claims 8 to 11, wherein each processing core is configured to transmit an output signal to another processing device, comprising: i) sending a request to connect, ii) sending a request to disconnect, and iii) sending a rejection of the disconnect request.

13. The method of claim 12, wherein each processing core is configured to receive an input signal from the another processing device, comprising: i) receiving a request to connect, ii) receiving a request to disconnect, and iii) receiving a rejection of the disconnect request.

14. The method of any one of claims 12 to 13, wherein the output signal and the input signal are implemented using six separate wires between the processing cores.

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