Stepped clocked frequency mode for integrated circuit assembly

Abstract

Aspects relate to a stepped clocked frequency mode for an integrated circuit assembly. In one embodiment, an apparatus includes a processor core configured to perform an operation at a received clocked frequency; and a clock controller. The clock controller is configured to: clock the processor core at a default frequency in response to the processor core operating in a default mode of operation; and entering a stepped clocked frequency mode in response to a parameter value associated with the processor core exceeding a first threshold, the step-by-step clocked frequency pattern includes alternating between clocking the processor core at a first frequency for a first time interval and clocking the processor core at a second frequency different from the first frequency for a second time interval.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 17 / 901,468, filed on September 1, 2022, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Background Art

[0003] Aspects of the present disclosure relate generally to clocking frequencies for integrated circuit components, and particularly to stepped clocking frequency patterns suitable for use with integrated circuits.

[0004] The performance of an integrated circuit (IC) is increased by increasing the clock frequency applied to the circuit. The increased clock frequency requires a correspondingly increased operating voltage to ensure that the circuit operates correctly. For some IC components, different clock frequencies are mapped to different voltage inflection points so that the voltage changes with the clock frequency. The increased speed and voltage increase the heat generated by the circuit and the temperature of the circuit. Much of this increased temperature appears in the form of leakage current through the semiconductor structure of the IC. The leakage current reduces the efficiency of the IC and the maximum speed of the IC. The IC has a maximum temperature at which it can operate reliably.

[0005] ICs typically operate well below the maximum steady-state clock frequency and voltage in order to reduce power consumption and improve the life of the IC. Safety margins are also included in the default clock frequency to account for variations in the production of each IC. Some ICs are equipped with thermal mitigation systems to reduce the clock frequency when the IC gets too hot. Thermal mitigation allows the IC to run faster in a cold environment and forces the IC to run slower in a hot environment. Some IC systems use dynamic frequency adjustment, which allows the IC to operate at a higher frequency and voltage for a short period of time to meet short-term processing requirements. For short pulse trains, the IC can safely operate at a higher clock frequency than its steady-state clock speed. However, after the IC is heated, it must operate at a slower clock frequency in order to cool back to a safe temperature.

[0006] Dynamic voltage frequency scaling (DVFS) is a technique for reducing power consumption by dynamically scaling changes in applied voltage to changes in applied clock frequency. Voltage, current, load, utilization, or a combination is used as a parameter for decision making to determine the most appropriate voltage and clock frequency under operating conditions. DVFS is typically used in the core of a processor, such as a central processing unit (CPU), a graphics processing unit (GPU), or a digital signal processor (DSP). The cores can be controlled individually or as a single unit. Dynamic clock voltage scaling (DCVS) is another technique for adjusting the frequency and voltage applied to an IC to deliver the desired performance at an ideal power level. Summary of the invention

[0007] The following content presents a summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a preface to the more detailed description that is subsequently presented.

[0008] In one example, an apparatus having a stepped clocking frequency mode for an integrated circuit component is disclosed. The apparatus includes a processor core configured to perform operations at a received clocking frequency and a clock controller. The clock controller is configured to: clock the processor core at a default frequency in response to the processor core operating in a default operating mode; and enter a stepped clocking frequency mode in response to a parameter value associated with the processor core exceeding a first threshold, the stepped clocking frequency mode comprising alternating between clocking the processor core at a first frequency for a first time interval and clocking the processor core at a second frequency different from the first frequency for a second time interval.

[0009] Another example provides a method that includes clocking a processor core at a default frequency in response to the processor core operating in a default operating mode, and entering a stepped clocking frequency mode in response to a parameter value associated with the processor core exceeding a first threshold, the stepped clocking frequency mode including alternating between clocking the processor core at a first frequency for a first time interval and clocking the processor core at a second frequency different from the first frequency for a second time interval.

[0010] Another example provides an apparatus comprising: means for clocking a processor core at a default frequency in response to the processor core operating in a default operating mode; and means for entering a stepped clocking frequency mode in response to a parameter value associated with the processor core exceeding a first threshold, the stepped clocking frequency mode comprising alternating between clocking the processor core at a first frequency for a first time interval and clocking the processor core at a second frequency different from the first frequency for a second time interval.

[0011] To achieve the foregoing and related purposes, one or more specific implementations include the features fully described below and specifically pointed out in the claims. The following description and the attached figures set forth in detail certain illustrative aspects of one or more specific implementations. However, these aspects are merely indicative of several of the various ways in which the principles of various specific implementations may be employed, and the described implementations are intended to cover all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A block diagram illustrating a system on a chip in accordance with certain aspects of the present disclosure is shown.

[0013] Figure 2 A hardware block diagram of a processor with a DCVS for controlling clocking of components is illustrated.

[0014] Figure 3 A graph illustrating a DCVS clocking frequency pattern.

[0015] Figure 4 A hardware block diagram of a clock controller for clocking components according to certain aspects of the present disclosure is illustrated.

[0016] Figure 5 A functional block diagram of a clock controller for clocking components according to certain aspects of the present disclosure is illustrated.

[0017] Figure 6 Graph illustrating a stepped clocking frequency mode pattern according to certain aspects of the present disclosure.

[0018] Figure 7 Graph illustrating a second stepped clocking frequency mode pattern according to certain aspects of the present invention.

[0019] Fig. 9 A flow chart illustrating a method of using a stepped clocking frequency pattern according to entry and exit thresholds in accordance with certain aspects of the present disclosure.

[0020] Fig.10 A flow chart illustrating a method of setting parameters for a stepped clocking frequency mode according to certain aspects of the present disclosure.

[0021] Fig.11 A block diagram illustrating an example hardware implementation for a device having a clocked processor core, a clock controller, and memory, among other components, in accordance with certain aspects of the present disclosure.

[0022] Fig.12 A flow chart illustrating a method of implementing a stepped clocked frequency mode according to certain aspects of the present disclosure. DETAILED DESCRIPTION

[0023] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations with which the concepts described herein can be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, in order to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0024] Aspects disclosed herein provide a stepped clock frequency (SCF) mode to improve the performance of an IC. For example, the SCF mode described herein can delay thermal mitigation events and reduce power consumption. The SCF mode can be used as an extension of another power scaling technique, such as DFVS or DCVS. The SCF mode can also be used independently of other power scaling and clock throttling techniques. The SCF mode can be used for a single IC, a packaged processor, or for a clocked component of a system on a chip (SoC), including a CPU and a specific core of the CPU. As described herein, in the SCF mode, the clocked frequency can be configured to oscillate rapidly between two or more frequency inflection points. The frequency inflection points can be mapped to corresponding different voltage inflection points. The SCF mode can allow the operating stack to operate faster at lower overall temperature and power consumption.

[0025] SCF mode can be used at a slower clock frequency to slow down the rate of thermal throttling in thermal mitigation. By reducing the thermal load on the IC, SCF mode prevents thermal mitigation events from occurring. The frequency inflection point and voltage inflection point can be selected for different operating modes, such as high-efficiency mode, high-efficiency mode, power saving mode, etc. SCF mode can be applied to any clocked processor, including processor cores for CPU, GPU or DSP, wireless controllers for Wi-Fi, cellular or Bluetooth, dedicated processor cores such as for artificial intelligence (AI), video or camera processor cores, cache controllers, cache memories such as dynamic random access memory (DRAM), and storage controllers.

[0026] In some examples, SCF mode is applied to extended high-performance operations, such as heavy workloads that push the boundaries of the thermal cooling system. During conventional heavy workload thermal management scenarios, the processor pushes the frequency inflection point higher by incrementally increasing the clock frequency until the processor reaches a thermal threshold. The frequency is then pushed down by the thermal mitigation system. The processor frequency is driven at a speed lower than normal until the excess heat can be dissipated. In SCF mode, the temperature thresholds are carefully balanced. If the processor operates more slowly, the workload may take longer to execute and the processor may consume energy and generate heat for a longer period of time. On the other hand, if the processor is driven as fast as possible, it may become overheated, and therefore it may operate at a lower speed for a longer period of time in order to dissipate the excess heat.

[0027] Using SCF, the average frequency of a component over many steps can be configured to be higher than the normal default clocked frequency that is thermally mitigated. This provides higher performance for steady-state operation of the component. Frequency steps can be configured above and below the default frequency, with the average speed being higher than the default frequency. Lower frequency steps allow the processor to cool, while higher frequency steps provide higher performance that ends before excess heat accumulates in the component. This can result in overall power savings.

[0028] Although various aspects and examples are described in this application by illustrating some examples, it will be understood by those skilled in the art that additional specific implementations and use cases can be generated in many different arrangements and scenarios. The innovation described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, various aspects or uses can be generated via integrated circuit chip examples and other devices based on non-module components (e.g., end-user devices, vehicles, communication equipment, computing equipment, industrial equipment, retail / shopping equipment, medical equipment, AI-enabled devices, etc.). Although some examples may or may not specifically point to use cases or applications, the applicability of a wide range of described innovations may occur. The scope of specific implementation may be from chip-level or modular components to non-modular non-chip-level specific implementations, and further to aggregated, distributed or OEM (original equipment manufacturer) devices or systems incorporating one or more aspects of the described innovation. In some practical environments, the equipment in combination with the various aspects and features described may also necessarily include additional components and features for implementing and practicing the various aspects claimed and described. For example, temperature and power sensors may use multiple components for analog and digital purposes (e.g., hardware components including power supplies, transducers, detectors, accumulators, digital-to-analog converters, etc.) It is intended that the innovations described herein may be practiced in a wide variety of devices, chip-level components, systems, distributed arrangements, end-user devices, etc., of various sizes, shapes, and configurations.

[0029] Figure 1 1 is a block diagram of a system on a chip (SoC) suitable for use with a portable device or computer. SoC 102 has a multi-core processor such as a CPU 104, a multi-core graphics processor such as a GPU 106, a multi-core digital signal processor such as a DSP 108, and a security module 110 that provides secret keys, device security, encryption, and decryption. SoC 102 may also include a user interface 112 coupled to external components such as a touch screen, a keyboard, buttons, etc. Figure 1 The illustrated SoC also includes mass storage 114, inertial reference unit 116, camera, display driver, and position sensor 122 such as a satellite positioning system. Additionally, the SoC may include a wireless interface 124 coupled to analog RF components and antenna (not shown) to support wireless data and control interfaces.

[0030] Each of the components is coupled by a bus (not shown) or by CPU 104, and more or fewer components may be used to suit a particular application. As an alternative to SoC 102, any one or more components may be fabricated on separate chips and packaged together or separately, as shown.

[0031] The system including the SoC 102 is coupled to a power source 130 such as a battery, or a mains converter coupled to the SoC 102 through a power manager 132, which may be on-chip or a discrete component. The power manager 132 regulates power to the components of the SoC 102 and controls the operating clock frequency and voltage applied to the components of the SoC 102. The power manager 132 further controls the voltage applied to the SoC and can also measure the battery charge level of the power source.

[0032] The core of the CPU 104, GPU 106, and other components such as the mass storage device 114 and the wireless interface 124 may include or be equipped with thermal sensors and power sensors in the form of voltage sensors, current sensors, or both. The sensors provide information to the power manager 132 for adjusting the frequency and voltage provided to the components. The power manager 132 may include clocking circuits and voltage regulators and other components, as described in more detail below. In some examples, the CPU 104, GPU 106, and other clocked components may also include power manager circuits or software for determining appropriate clocking frequencies and voltages. The determined clocking frequencies and voltages may be transmitted to the power manager 132 for application, or the clocked components may adjust the clocking frequencies and voltages independently of the power manager 132. The SCF mode may be implemented by the power manager or implemented independently in the processor or processor core.

[0033] Figure 2A hardware block diagram of a processor 202 having a dynamic clock voltage scaling (DCVS) circuit 208 for controlling the clocking of a clocked component 216, such as a clocked processor core, is illustrated. The processor 202 may include more components that are not shown here to simplify the description. The DCVS circuit 208 attempts to optimize the power consumption of the clocked component 216 while maintaining an acceptable performance level. A voting aggregator 204 is coupled to various clients (not shown) to receive and aggregate votes. The votes may include operating system scheduler status, application performance logs including application startup and shutdown, expected application processing requirements, and bandwidth votes from clients. The aggregated votes indicate the utilization of the clocked component and may also indicate the expected utilization of the clocked component. This may be based on, for example, application status and bandwidth votes. Additional parameters in addition to the votes may also be used to determine the utilization or load of the clocked component. Additional parameters may be used instead of or in addition to the votes. All of these parameters may be aggregated in the voting aggregator 204.

[0034] The sensor reader 206 reads measurements from any connected sensor, which may include a frequency sensor, a temperature sensor, and a battery charge level sensor. The voting aggregator 204 and the sensor reader 206 are coupled to the DCVS circuit 208 of the processor 202, which predicts the optimal clock frequency and voltage settings based on current or expected performance requirements. The DCVS circuit 208 receives these inputs and includes a table of frequency nodes 210 (also referred to herein as frequency points or frequencies) of the clock controller 212 and selects a higher or lower clocked frequency node. The selected frequency node is provided to the connected clock controller 214 to change the clocked frequency of the clocked component 216, such as a processor core. The table of frequency nodes 210 may also include corresponding voltages so that the clock controller directly or indirectly controls the voltage change. Each frequency node may have a corresponding voltage different from another frequency node or the same corresponding voltage.

[0035] The DCVS technique may be performed by an application specific integrated circuit (ASIC) or in software executed in a programmable processor. A single DCVS ASIC or program may be shared between more than one clocked component 216.

[0036] The clocking frequency can also be controlled by thermal mitigation techniques. Thermal mitigation can be performed by the DCVS circuit or as a separate system. Although DCVS attempts to optimize the power consumption of the clocked components, thermal mitigation throttles the clocking frequency to prevent the clocked components from getting too hot. In an example, thermal mitigation is coupled to a temperature sensor that measures a temperature value associated with the clocked component. When the temperature exceeds a threshold, the thermal mitigation technique reduces the clocking frequency by a certain value or a certain percentage to reduce the heat generated by the clocked component. More complex techniques can be used, and the clocking frequency reduction can be linked to work with the DCVS technique.

[0037] Figure 3 A graph of a DCVS clock frequency pattern 300 is illustrated. For reference, the graph shows a high clock frequency value 304, a medium clock frequency value 306, and a low clock frequency value 308. The clock frequency of the processor is depicted on the vertical axis, and time is depicted on the horizontal axis. The pattern begins with the clocked component being at a high clock frequency value for a certain duration 310. This is typical for a startup sequence, however, the clocked component can start at any clock frequency value. The DCVS circuit then reduces the clock frequency. The DCVS may determine that less processing performance is needed based on the results of the voting aggregator, or determine that the processor core is too hot based on the results of the sensor reader, and then reduce the clock frequency received at the processor core and the received voltage to prevent the processor core from overheating. This may be performed by the processor's thermal mitigation system without regard to the voting aggregator in order to protect the processor core from thermal overload. The DCVS circuit reduces the clock frequency with a first falling time ramp 322 to a second lower clock frequency duration 312. This is followed by a second falling time ramp 324 to a third lower clocking frequency duration 314 at the medium clocking frequency value 306, a third falling time ramp 326 to a fourth lower clocking frequency duration 316 at the low clocking frequency value 308, and a fourth falling time ramp 328 to a fifth lower clocking frequency duration 318. The particular pattern of clocking frequency changes is determined by DCVS or thermal mitigation or both based on inputs such as Figure 2 shown and may change over time. Figure 3 The patterns are provided only as examples of possible clocking frequency changes.

[0038] When DCVS is combined with thermal mitigation, the DCVS circuit will reduce the clocking frequency and voltage to protect the processor core from thermal overload. If the processor core is not too hot and there is high utilization or high expected utilization, the DCVS circuit increases the clocking frequency and voltage of the processor core. For higher performance aggregate voting, there may be a rise time ramp 330 to a much higher clocking frequency duration, followed by more rise time ramps. Depending on the votes and sensor values, there may be many minimum points 332 and maximum points 334 in rapid succession in the pattern 300. The clocking frequency values ​​and the duration at each clocking frequency value do not depend on any particular value, and the pattern is not regular or predictable. In this default operating mode, the performance of the core matches the vote and is limited to the thermal capabilities of the clocked components. For clocked components with DCVS, Figure 3 The pattern of is the default frequency. For clocked components with thermal mitigation separate from DCVS, any one or more of the peaks may be reduced to mitigate thermal overload of the clocked components.

[0039] DCVS attempts to optimize the power consumption of clocked components. However, when high-performance operation is required, such as for heavy workloads or low latency, DCVS will allow the clocked components to operate at high clocked frequencies. When the clocked components heat up, thermal relief can be triggered, thereby reducing the established high-performance operation. High-performance operation also increases power consumption. Similarly, for low-power operations, high latency can be caused by low clocked frequencies. Various aspects provide an SCF technology that enables the clocked frequency to vibrate between at least two frequency nodes (e.g., frequency points or frequencies). By vibrating between two frequency points with a period of milliseconds, the user will not feel any latency. Stepped clocked frequencies provide low latency with only slightly reduced performance. High frequency levels allow workloads to be processed quickly, while lower frequency levels allow the clocked components to cool. The duty cycle of the clocked components can be significantly reduced to provide lower power consumption and reduce the heat generated.

[0040] SCF mode is suitable for boundary conditions and extended operating situations, for example, extended power requirements that can withstand thermal mitigation. One such example is a heavy workload that crosses the boundary to demonstrate key performance indicators. A sufficiently heavy workload that pushes the operating frequency inflection point up one level at a time and pushes the power or thermal cooling limits of the system will begin to reach the maximum performance threshold. The thermal mitigation system will reduce the clock frequency and voltage to protect the processor core from overload. By entering SCF mode at a lower temperature, thermal limits can be protected to avoid the operation of the thermal mitigation system with only a small performance loss compared to the DCVS system.

[0041] Figure 4 is a hardware block diagram of a processor 402 including a clock control component such as a processor core 404 or controller. Such a processor may be Figure 1 The processing units 106, 108, 104, Fig.11 The processor 402 includes a DCVS circuit 420 (as described above with respect to Figure 2 and Figure 3 ) and the stepped clock frequency circuit 450. Figure 4 In the example shown, the clocked component is a processor core 404. The core may be part of a CPU, a GPU, a DSP, or any other clocked component. Although only one processor core is shown, multiple processor cores may exist. The processor core 404 is configured to perform operations at a received clocked frequency. The clocked frequency is received from a clock controller 422 of the processor 402.

[0042] The processor 402 receives a temperature value corresponding to the measured temperature from the thermal sensor 406 and a power value corresponding to the measured power from the power sensor 410, and further adjusts the voltage and clock frequency of the processor core 404 based at least in part on these temperature values ​​and power values. In addition to temperature and power, other parameters can be measured, and these parameter values ​​can be provided to corresponding parameter registers for comparison with appropriate parameter thresholds. In some examples, the thermal sensor 406 measures the temperature of the processor core 404. The thermal sensor can also measure the temperature of other components, such as the main core of the processing core, the interface, or the cooler. The thermal sensor 406 is coupled to the thermal sensor register 408 of the processor 402. The thermal sensor register 408 is a parameter register configured to store the temperature value measured by the thermal sensor. In some examples, the thermal sensor 406 can transmit the temperature value to the thermal sensor register 408 for storage therein. In some examples, the thermal sensor register 408 can read or interrogate the thermal sensor 406 to obtain the temperature value. There can be multiple temperature values ​​with associated timestamps in the thermal sensor register 408. Additionally, there may be multiple thermal sensors to determine the temperature at multiple locations.

[0043] The power sensor 410 measures the power of the processor core, and the measured power value is stored in the power sensor register 412 of the processor 402. The power sensor register 412 is a parameter register for multiple representations of the power being used by the processor core 404 or provided to the processor core. The power can be represented by a voltage, a current, a wattage, or another form of power measurement. The power sensor 410 is coupled to the power sensor register 412 to store the measured power value in the power sensor register 412. In some examples, the power sensor 410 can transmit the power value to the power sensor register 412. In some examples, the power sensor register 412 can read or interrogate the power sensor 410 to obtain the power value. There can be multiple power values ​​with associated timestamps in the power sensor register 412. In addition, there can be multiple power sensors 410 to determine the power values ​​at multiple locations and have multiple measurements of power, such as volts, amperes, watts, reactance, etc.

[0044] In some examples, power source 428 is or includes a battery. Charge sensor 430 measures the battery charge level and stores the value of the battery charge level in battery charge sensor register 432. When the battery charge level is less than a battery charge level threshold as determined by SCF charge comparator 458, processor 402 may enter SCF mode in response, as described below. This operates to conserve battery power until the battery is charged and the battery charge level is greater than the battery charge level threshold.

[0045] Within the DCVS circuit 420, the thermal sensor register 408 is coupled to a DCVS thermal comparator 414. The DCVS thermal comparator 414 is coupled to the DCVS circuit 420. The DCVS thermal comparator 414 compares the stored temperature in the thermal sensor register 408 with a programmed threshold value and generates a comparator result to the DCVS circuit 420. The power sensor register 412 is coupled to a DCVS power comparator 416, which is also coupled to the SCF circuit 420. The DCVS power comparator 416 compares the power value in the power sensor register 412 with a programmed threshold value to generate a power comparator result. The power comparator result is provided to the DCVS circuit 420. The DCVS charge comparator 418 is also coupled to the DCVS circuit 420 to provide a battery charge level result. In some examples, a voting aggregator 440 is coupled to the DCVS circuit 420 for use by the DCVS circuit 420 to optimize the power consumption of the current or expected utilization of the processor core. There are different implementations of DCVS that use different inputs to optimize power consumption. The described implementations are provided for context only. The SCF circuit may be adapted to suit any such implementation and may also be integrated with DVFS (rather than DCVS) or operate independently of DVFS or DCVS or without any such clock scaling system (e.g., processor 400 may not include DCVS or DVFS circuitry).

[0046] Within the SCF circuit 450, the thermal sensor register 408 is coupled to an SCF thermal comparator 454. The SCF thermal comparator 454 is coupled to the SCF circuit 450. The SCF thermal comparator 454 compares the stored temperature in the thermal sensor register 408 to a programmed threshold value and generates a comparator result to the SCF circuit 450. The power sensor register 412 is coupled to an SCF power comparator 456, which is also coupled to the SCF circuit 450. The SCF power comparator 456 compares the power value in the power sensor register 412 to a programmed threshold value to generate a power comparator result. The power comparator result is provided to the SCF circuit 450. An SCF charge comparator 458 is also coupled to the SCF circuit 450 to provide a battery charge level result.

[0047] The DCVS circuit 420 and the SCF circuit 450 are coupled to a clock controller 422 to control the clocking frequency, and to a voltage regulator 426 to control the voltage provided to the processor core 404. In some examples, the clock controller 422 may receive a reference clock from an internal or external reference clock source 424, and then select or modify the reference clock to drive the processor core 404 at the received clocking frequency as determined by the DCVS circuit 420 and the SCF circuit 450. Similarly, the voltage regulator 426 may receive power from a power supply 428 and select or modify the received power to provide a voltage to drive the processor core 404 at the received voltage as determined by the DCVS circuit 420 and the SCF circuit 450.

[0048] Thus, the clock frequency and voltage of the processor core are adjusted by the DCVS circuit 420 of the processor 402 based on measurements from the thermal sensor 406 and the power sensor 410, and in some cases using results from the voting aggregator 440. The processor 402 includes the DCVS circuit 420, as described above with respect to Figure 2 and Figure 3 4 and 5. The DCVS circuit 420 and SCF circuit 450 are components that control the operation of the clock controller 422 (as described herein), provide thermal protection, and are capable of optimizing the performance of the processor core for a particular operating situation. More or fewer components may be used to accommodate different applications. In some examples, only thermal sensors or only power sensors are used. In some aspects, other sensors are used instead of or in addition to thermal sensors and power sensors. As compared to the SCF circuit 450, the DCVS circuit 420 may use the same or different sensors.

[0049] exist Figure 4In the embodiment of the present invention, the DCVS circuit 420 transmits clock and voltage commands to the clock controller 422 and the voltage regulator 426 through the SCF circuit 450. This allows the SCF circuit 450 to interrupt the commands from the DCVS circuit 420 and cause the processor core to enter the SCF mode. Alternatively, the SCF circuit 450 can transmit commands through the DCVS circuit 420, or the two can operate independently. The SCF circuit 450 can operate as an extension of the DCVS circuit 420. In some examples, the SCF circuit 450 operates independently of the DCVS circuit 420. In some examples, the DCVS circuit 420 selects a frequency point for the processor core 404. When the frequency point drives the clocked component to a temperature or power within the entry and exit thresholds of the SCF circuit 450, the SCF circuit enters the corresponding SCF mode. Even in the SCF mode, when the clocked component reaches a temperature or power above or below the entry and exit thresholds of the SCF circuit 450, the SCF circuit 450 exits the SCF mode. Although the description is presented with DCVS, the examples herein may be adapted to use DVFS instead of DCVS, simple thermal mitigation, or other clocking frequency methods. Alternatively, SCF may be used without any of these other methods.

[0050] In some aspects, the DCVS circuit 420 operates using the time rate of change of temperature and power as determined from the thermal comparator and the power comparator. As an example, in some aspects, a parameter associated with the processor core is the rate of increase of the temperature of the processor core. This can be used in combination with the current temperature or independently of the temperature. In some aspects, the parameter is a combination of the temperature of the processor core or the rate of increase of the temperature and the power applied to the processor core.

[0051] Figure 55 is a functional block diagram of a processor 502 including a clock controller 514 coupled to a DCVS module 508 and an SCF manager 516. The functional blocks may be implemented as software on a general purpose processor, or firmware on a dedicated IC, or in other ways. The processor 502 includes one or more clock control components 530, for example, a first clock control core 532 and a second clock control core 534. The processor 502 includes a voting aggregator 504 coupled to the DCVS module 508 of the processor 502. A sensor reader 506 is also coupled to the DCVS module 508. The voting aggregator 504 collects votes from various clients about the current and expected operating conditions of the processor core, including votes about utilization, buffer queues, workload, and other expected demands on the processor core. The voting aggregator 504 aggregates this information and then provides it to the DCVS module 508. The sensor reader 506 collects information about temperature, power, battery charge level, and other environmental conditions of the processor core and provides this information to the DCVS module 508. The sensor reader 506 may also use comparators, aggregators, combiners, or other functional blocks to analyze the sensor readings.

[0052] The DCVS module 508 operates in the default operating mode to adjust the clocking frequency and voltage applied to each processor core. The DCVS module 508 uses the comparator 512 of the DCVS module 508 to compare the values ​​from the voting aggregator 504 and the sensor reader 506 with various thresholds. Based on these comparisons, the DCVS module 508 determines the optimal clocking. If the DCVS module 508 includes thermal mitigation, the clocking frequency will be reduced at high temperatures to prevent the processor core from overheating. If the processor core is not too hot and there is a high utilization or expected high utilization, the DCVS module 508 increases the clocking frequency and voltage of the processor core in the default operating mode. The DCVS module includes a table of frequency nodes 510 (e.g., frequency points or frequencies), and selects a higher or lower clocking frequency node in response to a higher or lower utilization or expected utilization. The selected frequency node is provided to the connected clock controller 514 to provide a change in the clocking frequency of the processor core. The table of frequency nodes 510 may also include a corresponding voltage so that the clock controller 514 also commands the corresponding voltage to change.

[0053] The processor 502 also allows for a stepped clock frequency (SCF) configuration 528 of an SCF manager 516 coupled to the clock controller 514. The SCF configuration 528 may be within the SCF manager 516 or in a separate memory storage area. In some examples, the SCF manager 516 is coupled to the DCVS module 508 of the processor 502 to enable the first clocked core 532 or the second clocked core 534 of the clocked component 530 to enter and exit the SCF mode. In some examples, the SCF manager 516 operates independently of the DCVS module 508. In the illustrated example, the SCF manager 516 is coupled to the DCVS module 508 and operates through the DCVS module 508.

[0054] The SCF configuration 528 may have a first entry and exit threshold for the first core and a second entry and exit threshold for the second core. As an example, the first temperature threshold may be higher than the second temperature threshold. The second processor core may be a low power core such that when the temperature of the second processor core exceeds the second temperature threshold, the second processor core enters a second SCF mode at a lower temperature. In other examples, the SCF manager 516 may operate without or independently of the DCVS module 508. The SCF manager 516 receives sensor information from the sensor reader 506, such as an indication of temperature and power, and applies the information to the SCF comparator 518 including entry and exit thresholds. The SCF manager 516 uses the comparison to determine whether to enter or exit the SCF mode. The SCF configuration 528 includes thresholds for determining whether to enter or exit the SCF mode. The SCF configuration 528 also determines parameters for each SCF mode, such as frequency or frequency points and time intervals. By controlling each core individually, if the system is running a single-threaded task and requires maximum performance from only one core, only one core is operated at a high voltage, while the other cores remain in a low power state until needed. This reduces power consumption and allows the thermal cooler to more easily remove the reduced amount of heat generated by the processor as a whole.

[0055] Figure 6 is a graph of the SCF mode pattern. On the vertical axis are depicted the clocked components, e.g. Figure 5The clocking frequency of the first clocked core 532 or the second clocked core 534 is plotted on the horizontal axis, while time is plotted on the horizontal axis. The pattern 600 has a high clocking frequency value 604, a medium clocking frequency value 606, and a low clocking frequency value 608. The pattern has a high frequency duration 612, during which the pattern is at the high clocking frequency value 603, and a low frequency duration 614, during which the pattern is at the low clocking frequency value 608. There is also a falling time ramp 616 from the high clocking frequency value 608 to the low clocking frequency value 604 and a rising time ramp 618 from the low clocking frequency value 604 to the high clocking frequency value 608. The cycle repeats with being at the high clocking frequency value 604 for a second high frequency duration 622, another falling time ramp, and so on. The slopes of these ramps can be configured to accommodate the reaction time of the clocked component without affecting the reliability and accuracy of the operation of the component.

[0056] Although the high frequency duration 612 and the low frequency duration 614 are shown as being about the same duration, these durations may be different. Using a low frequency duration 614 that is shorter than the high frequency duration 612 allows the clocked component to operate at a cooler temperature than the average clocking frequency between the high clocking frequency value 604 and the low clocking frequency value 608. For typical ramp slopes, even with equal durations, the clocked component operates at the high clocking frequency value less than half the time, e.g., about 40% of the time, resulting in a significant reduction in heat generation and corresponding losses.

[0057] Pattern 600 repeats from left to right in time, and the complete cycle has a high frequency duration 612 and a low frequency duration 614 in each cycle. The pattern can be defined by two frequency points and two durations. The definition can also include the slope of the ramp between each frequency point, or a default slope can be used. The voltage at each frequency point can be fixed or defaulted for the pattern so that the voltage applied to the clocked component by the voltage regulator is determined based on the clocking frequency. As compared with the fixed clocking frequency, whether at the medium clocking frequency value 606 or at the low clocking frequency value 608, this simple dual-frequency pattern provides improved performance. The high clocking frequency value 604 may be too high for the clocked component to be maintained within its thermal envelope. The low clocking frequency duration allows the clocked component to be executed at a higher level in the form of a pulse train. When the pattern is used in low battery mode, a dual-frequency pattern with a lower clocking frequency value can be used to provide higher performance than the typical low battery mode while still reducing power consumption. SCF configuration 528 may include multiple SCF patterns to accommodate different situations, such as high performance, standard use, and low battery.

[0058] Figure 7700 has a high clocking frequency value 704, a medium clocking frequency value 706, and a low clocking frequency value 708. The pattern has: a first intermediate frequency duration 710 during which the pattern is at the medium clocking frequency value 706; a low frequency duration 712 during which the pattern is at the low clocking frequency value 708; a second intermediate frequency duration 714 during which the pattern is at the medium clocking frequency value 706 for a second time; and a high frequency duration 716 during which the pattern is at the high clocking frequency value 704. The pattern repeats with a third intermediate frequency duration 718 during the next cycle of the pattern. The pattern shows three frequency points corresponding to the three clocking frequency values ​​704, 706, 708.

[0059] There is also an upper falling time ramp 722 from the high clocking frequency value 704 to the medium clocking frequency value 706 and a lower falling time ramp 724 from the medium clocking frequency value 706 to the low clocking frequency value 708. On the upward side of the cycle, there is a lower upward time ramp 726 from the low clocking frequency value 708 to the medium clocking frequency value 706 and an upper upward time ramp 728 from the medium clocking frequency value 706 to the high clocking frequency value 704. The slopes of these ramps can be configured to accommodate the reaction time of the clocked component without affecting the reliability and accuracy of the operation of the component.

[0060] exist Figure 7 In the pattern 700 shown, all clock frequencies are of equal duration and have equal slopes. This regular three-frequency pattern can be used instead of Figure 6 The SCF configuration may include a dual frequency pattern with two, three or more frequencies to accommodate different situations as determined by the SCF manager. Any of the durations may be shorter or longer than another duration to suit a particular implementation. In addition, the first duration may be different from the second duration. For example, the first intermediate frequency duration 710 may be longer or shorter than the second intermediate frequency duration 714. The slope of the ramp may be modified as well as the number of different frequency values ​​and the order in which each frequency value is used. The illustrated patterns are provided as examples and these patterns may be modified or other patterns may be used.

[0061] Figure 8800 has a high clocking frequency value 804, a medium clocking frequency value 806, and a low clocking frequency value 808. The pattern has a first medium frequency duration 812 during which the pattern is above the medium clocking frequency value 806, a second medium frequency duration 816 during which the pattern is at the medium clocking frequency value 806, and a low frequency duration 820 during which the pattern is at the low clocking frequency value 808. The pattern then rises to a second high frequency duration 824 during which the pattern is at the high clocking frequency value 804 for a second time and a third medium frequency duration 828 during which the pattern is between the high clocking frequency value 802 and the medium clocking frequency value 806. The third SCF pattern 800 has five different clocking frequency values, and the time at each value is different from the time at each other value. The complete cycle of the pattern is not shown, but the cycle may include several more transitions before the next repetition.

[0062] There is also a first upper falling time ramp 810 and a second upper falling time ramp 814 from the high clocking frequency value 804 to the medium clocking frequency value 806 and a lower falling time ramp 818 from the medium clocking frequency value 806 to the low clocking frequency value 808. On the upward side of the cycle, there is an upward time ramp 822 from the low clocking frequency value 808 to the high clocking frequency value 804. An additional falling time ramp 826 connects the second high frequency duration 824 to the third medium frequency duration 828. The slopes of these ramps can be different from each other and are configured to accommodate the reaction time of the clocked components and other factors. The third SCF pattern is provided as an example of a possible variation of the simpler dual-frequency and triple-frequency patterns described above. Other modifications and variations can be made to the illustrated patterns to accommodate different clocked components and operating conditions.

[0063] Fig. 9 906 , a wait timer is set. After the timer expires, the process continues back to testing the new, more recent sensed value against the entry threshold at box 904.

[0064] Conversely, if the entry threshold is exceeded, then at block 908, the SCF mode is entered. The SCF mode is maintained until the SCF mode is exited at block 914. At block 910, the currently measured parameter value, e.g., the currently measured temperature and / or the currently measured power, is tested against the exit threshold. If the exit threshold is not exceeded, then at block 912, a wait timer is set. Upon expiration of the timer, the new sensed value is again tested against the exit threshold at block 910. If the exit threshold is exceeded, then at block 914, the SCF mode is exited. Although only one SCF mode and one entry and exit threshold are shown, multiple SCF modes with different entry and exit thresholds may exist to accommodate different situations.

[0065] Fig.10 1006. The process flow chart is for configuring the SCF mode. The process has a selection portion at box 1004 and an application portion at box 1006. The selection portion at box 1004 includes selecting parameters to be balanced based on the threshold value triggered at box 1010. The threshold may include, for example, power, performance, and thermal thresholds. The performance threshold may be related to the expected demand from the application or bandwidth vote. The thermal threshold may be related to the current temperature of the clocked core as sensed directly or indirectly or as inferred by the current entering the clocked core. The thermal mitigation system may have a peak temperature of, for example, 95°C or 100°C. By selecting an SCF mode temperature threshold, such as 85°C, which is less than the thermal mitigation system temperature threshold, the SCF mode may be entered before the clocked core reaches the thermal mitigation system temperature threshold, and thermal mitigation may be avoided. In some examples, thermal mitigation takes precedence over all other clocks. If the temperature exceeds the thermal mitigation threshold, this may reduce the clocked frequency in the SCF mode.

[0066] The selection portion at block 1004 also includes selecting the minimum of two or more frequency points to vibrate between or among at block 1012. The frequency points correspond to those nodes that are closest to the voting nodes. The voted nodes correspond to the use of a clock control component that receives votes on operating system scheduler status, application performance logs including application startup and shutdown, expected application processing requirements and bandwidth, etc. These nodes are voted by various clients using the clock control component. The two or more frequency points correspond to the nodes that are closest to the voting nodes. Figure 5 , Figure 6 and Figure 7 The clock frequency values ​​used in the pattern are two, three or more frequency values ​​used. The clock frequency oscillates between the selected frequency points because the clock frequency changes over time, such as Figure 5 , Figure 6 and Figure 7. At box 1012, two or more frequency points may be selected for voting to be higher from a high-performance application startup. A lower frequency point may be selected for voting from a low battery mode. The selection is based on the selected parameters of the balance box 1010. As an example, the first frequency point may be at least 10% higher than the second frequency point. For a specific clocked component, the high frequency may be 2 GHz and the low frequency point may be 1 GHz. The periodicity between the two frequency points results in an average value of less than 1.5 GHz. For another example, the first frequency point may be at least 3% higher than the second frequency point. For a specific clocked component, the high frequency may be 3 GHz and the low frequency may be 2.91 GHz.

[0067] The selection at block 1004 includes, in part, selecting, at block 1014, a duration between or among the selected frequency bins selected at block 1012. The duration may be the same for each frequency bin, or may be different for different frequencies or for different portions of the cycle. Figure 6 and Figure 7 The durations are all equal. Figure 8 The selection of different durations at different frequency points and different times in the cycle is illustrated. The selection of duration can be tuned based on the basic system architecture, expectations from the end product and design requirements. The duration can be selected to achieve a balance of all selected parameters such as power, performance and thermal parameters. A good choice of duration meets or exceeds the negative error correlation between expectations and requirements. As an example, the duration at two frequency points can be 0.5ms or 1.0ms. The duration can be much longer than the period of the cycle of the clocked frequency. As an example, the duration can exceed one million cycles of the clocked frequency.

[0068] At block 1006, the selected configuration is applied to the Stepped Clocked Frequency (SCF) configuration. The selected configuration is a combination of the threshold, frequency point, and duration from the selection phase. Figure 4 In the example of , the selected configuration is the SCF mode used by the SCF circuit 438 in the clock controller 420. The thresholds are installed at the comparators 414, 416 and 434. The SCF pattern is installed in the SCF circuit 438. Figure 5 In the example of FIG. 5 , the selected configuration is stored in SCF configuration 528, and SCF manager 516 operates through DCVS module 508 to adjust the frequency through clock controller 514. The configuration can be applied to the DCVS module or a separate system. DCVS provides a structure by which the power manager can drive the processor core for thermal mitigation regardless of whether the processor core is operating in SCF mode.

[0069] In some applications, such as the Linux kernel, a clocked frequency control circuit or technique is referred to as a regulator or CPU frequency regulator. Examples herein such as DCVS, DVFS, thermal mitigation, and SCF modes and other frequency scaling schemes may be referred to as schemes of regulators. The regulator controls the behavior of the clocked frequencies of different processors, interconnects, memory controllers, etc. Therefore, the final operation of box 1106 may be referred to as applying the selected scheme to the associated frequency regulator via DCVS or DVFS. Other terms are used for other applications. Regardless of the terminology, the stepped clocked frequency mode provides significant benefits in performance and reliability in part by better balancing speed and thermal budget than a fixed clocked frequency scheme.

[0070] Fig.11 A block diagram of an example of a hardware implementation for a device 1100 is illustrated, the device such as a user equipment, a portable device, a notebook computer, a tablet computer, a computer, a server, a router, a memory array, or any other suitable device having one or more integrated circuits with a clocked component. In this example, the clocked component is a processor 1120 having one or more processor cores as described above. According to various aspects of the present disclosure, the processing system 1102 may be used to implement an element or any part of an element or any combination of elements. The processing system 1102 may include one or more processors 1120. Examples of processors 1120 include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to be controlled by clocked frequencies and voltages as described throughout the present disclosure. In various examples, the device 1100 may be configured to perform any one or more of the functions described herein.

[0071] In this example, the processing system 1102 may be implemented using a bus architecture (generally represented by bus 1122). The bus 1122 may include any number of interconnecting buses and bridges, depending on the specific application of the processing system 1102 and the overall design constraints. The bus 1122 communicatively couples various circuits including one or more processors (generally represented by processor 1120), clock controller 1104, memory 1108, and computer readable media (generally represented by computer readable media 1106) having instructions stored thereon. The bus 1122 may also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further. The bus interface 1110 provides an interface between the bus 1122 and a host radio, shown as a first transmitter / receiver 1112 or transceiver and a first at least one antenna 1114, and between the bus 1122 and an interface 1130. The first transmitter / receiver 1112 provides a communication interface or component for communicating with various other devices over a wireless transmission medium through a first at least one antenna 1114. The bus interface 1110 also provides an interface between the bus 1122 and a secondary radio shown as a second transmitter / receiver 1116 and a second at least one antenna 1118. In some examples, the wireless device may include two or more transceivers, each of which is configured to communicate with a corresponding network type (e.g., terrestrial or non-terrestrial) through the same or different antennas. The interface 1130 provides a communication interface or component for communicating with various other devices and equipment (e.g., other devices contained in the same device or other external devices) through an internal bus or an external transmission medium such as an Ethernet cable. Depending on the nature of the device, the interface 1130 may include a user interface (e.g., a keypad, a display, a speaker, a microphone, a joystick). Of course, such a user interface is optional and may be omitted in some examples (such as IoT devices).

[0072] The processor 1120 is responsible for managing the bus 1122 and general processing, including executing software stored on the computer-readable medium 1106. The software, when executed by the processor 1120, causes the processing system 1102 to perform the various functions described below for any particular device. The computer-readable medium 1106 and memory 1108 may also be used to store data that is manipulated by the processor 1120 when executing the software.

[0073] The clock controller 1104 may be part of one or more processor cores of the processor 1120 and perform operations with the aid of the processor cores executing software stored in the computer-readable medium 1106, or the clock controller 1104 may be independent of the processor 1120 within the processing system 1102 to execute software stored on the computer-readable medium 1106 using its own processing resources. Software should be construed broadly to mean instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside on the computer-readable medium 1106. The clock controller 1104 executes software stored by Figure 4 The clock controller 1104 performs the operations performed by the comparators 414, 416, 434 and the clock controller 420. Figure 5 The operations performed by the SCF manager 516, the DCVS module 508, the table of selected frequency nodes 510 and the clock controller 514.

[0074] The computer-readable medium 1106 may be a non-transitory computer-readable medium. As an example, a non-transitory computer-readable medium includes a magnetic storage device (e.g., a hard disk, a floppy disk, a magnetic tape), an optical disk (e.g., a compact disk (CD) or a digital versatile disk (DVD)), a smart card, a flash memory device (e.g., a card, a stick, or a key-type drive), a random access memory (RAM), a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing software or instructions that can be accessed and read by a computer. The computer-readable medium 1106 may reside in the processing system 1102, be located outside the processing system 1102, or be distributed across multiple entities including the processing system 1102. The computer-readable medium 1106 may be embodied in a computer program product. For example, a computer program product may include a computer-readable medium in a packaging material. Those skilled in the art will recognize how to best implement the described functionality presented throughout this disclosure, depending on the specific application and the overall design constraints imposed on the overall system.

[0075] The device 1100 may be configured to perform any one or more of the operations described herein.In some aspects of the disclosure, a clock controller 1104 as utilized in the device 1100 may include circuits configured for various functions.

[0076] The clock controller 1104 is coupled to the memory 1108 via the bus 1122. The memory 1108 includes parameter registers 1148, which may include parameters, thresholds, frequencies, durations, etc. for various different clocking frequency modes, which may be used to define the clocking frequency modes and to determine entry and exit from different clocking frequency modes, and may also include tables, maps, or other data structures indicating current and average temperature, power, or other operating parameters of the clocked components of the processing system 1102. The configuration registers 1148 may perform operations similar to Figure 5 The operation of the SCF configuration 528.

[0077] The clock controller 1104 may include a default frequency clocking circuit 1140 to clock the processor 1120 at a default clocking frequency. The default frequency clocking circuit 1140 may include one or more hardware components that provide a physical structure for performing various processes related to generating a default clocking frequency and driving the processor 1120 at the default clocking frequency. The default frequency clocking circuit 1140 may include functionality of components for clocking the processor core at a default frequency in response to the processor core operating in a default operating mode. The default frequency clocking circuit 1140 may also be configured to execute the default clocking frequency software 1160 included on the computer readable medium 1106 to implement the default clocking frequency described herein.

[0078] The clock controller 1104 may include a stepped frequency clocking circuit 1142 configured to generate an SCF pattern and drive the processor 1120 in an SCF mode as discussed herein. The stepped frequency clocking circuit may include functionality of components for entering an SCF mode in response to a parameter associated with a processor core exceeding a first threshold, the SCF mode including alternating between clocking the processor core at a first frequency for a first time interval and clocking the processor core at a second frequency different from the first frequency for a second time interval.

[0079] The stepped frequency clocking circuit 1142 may also be configured to execute SCF software 1152 included on the computer readable medium 1106 to implement one or more functions described herein.

[0080] The processing system 1102 clock controller 1104 may include an entry and exit circuit 1144 configured to perform operations for entering and exiting different frequency clocking modes as discussed herein. The entry and exit circuit 1144 may include functionality for: reading parameters of the processor 1120 from parameter registers 1148 of the memory 1108 during operation of the processor 1120; comparing these parameters to thresholds stored in the parameter registers 1148 of the memory 1108; and determining which clocking frequency mode to enter and exit, including the default frequency clocking circuit 1140 and the stepped frequency clocking circuit 1142.

[0081] The entry and exit circuitry may include functionality for detecting a parameter associated with the processor core below a second threshold and for exiting the SCF mode in response to the parameter associated with the processor core being below the second threshold. The entry and exit circuitry 1144 may also be configured to execute entry and exit determination software 1164 included on the computer readable medium 1106 to implement one or more functions described herein. The entry and exit circuitry performs similar Figure 4 The comparators 414, 416, 434 and Figure 5 Operation of the DCVS module 508.

[0082] The circuit architecture described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described herein may also be manufactured using various process technologies, such as complementary metal oxide semiconductor (CMOS), NMOS, PMOS, bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistor (HBT), high electron mobility transistor (HEMT), silicon on insulator (SOI), etc.

[0083] The apparatus implementing the circuits described herein may be a stand-alone device or may be part of a larger device. The device may be (i) a stand-alone IC, (ii) a collection of one or more ICs that may include a memory IC for storing data and / or instructions, (iii) a radio frequency integrated circuit (RFIC) such as an RF receiver (RFR) or RF transmitter / receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded in other devices, (vi) a receiver, a cellular phone, a wireless device, a handset or a mobile unit, (vii) and the like.

[0084] Fig.12 is an example for use with devices such as Figure 1 Equipment 102, Figure 4processor 402, Figure 5 The processor 502 or Fig.11 The method may also be performed by other circuits or components or processing resources other than those shown and described herein. Fig.11 The clock controller 1104 or other circuits as well as Fig.11 The method 1200 begins at block 1202 where a processor core is clocked at a default frequency in response to the processor core operating in a default operating mode.

[0085] In block 1204, in response to a parameter associated with a processor core exceeding a first threshold, the clock controller may enter an SCF mode. In the SCF mode, the clock controller alternates between clocking the processor core at a first frequency for a first time interval and clocking the processor core at a second frequency different from the first frequency for a second time interval. In some examples, the parameter includes at least one of a temperature of the processor core, a rate of heat increase of the processor core, and a power applied to the processor core. The core may refer to, for example, Figure 1 , Figure 5 and Fig.11 Any clocked components shown.

[0086] In some aspects, the first frequency is at least 3% higher than the second frequency. In some aspects, the first time interval and the second time interval are substantially the same. In some aspects, the first time interval and the second time interval are the same. In some aspects, the first time interval or the second time interval is longer than one million cycles of the first frequency.

[0087] In block 1206, detecting that a parameter associated with the processor core is below a second threshold is performed. In block 1208, exiting SCF mode is performed in response to the parameter associated with the processor core being below the second threshold.

[0088] Can be executed simultaneously for one or more clocked components Fig.12 For multi-core processors, each processor core may be clocked with a different frequency and frequency mode. There may be multiple SCF modes to accommodate different operating situations with different entry and exit thresholds.

[0089] As used herein, "or" is intended to be interpreted as inclusive unless otherwise expressly indicated. For example, "a or b" may include only a, only b, or a combination of a and b. As used herein, a phrase referring to "at least one of" or "one or more of" a list of items refers to any combination of those items, including individual members. For example, "at least one of a, b, or c" is intended to cover the following examples: only a, only b, only c, a combination of a and b, a combination of a and c, a combination of b and c, and a combination of a and b and c.

[0090] The various illustrative components, logical components, logical blocks, modules, circuits, operations, and algorithmic processes described in conjunction with the specific implementations disclosed herein may be implemented as electronic hardware, firmware, software, or a combination of hardware, firmware, or software, including the structures disclosed in this specification and their structural equivalents. This interchangeability of hardware, firmware, and software has been generally described in terms of their functionality and exemplified in the various illustrative components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware, firmware, or software depends on the specific application and the design constraints imposed on the overall system.

[0091] The various illustrative logical blocks, modules, and circuits described in conjunction with the exemplary aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration.

[0092] In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on a computer-readable medium or sent via a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices, disk storage devices, or other magnetic storage devices, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer. Moreover, any connection is appropriately referred to as a computer-readable medium. For example, if the software is sent from a website, a server, or other remote source using a coaxial cable, a fiber optic cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0093] Various modifications to the specific implementations described in this disclosure will be apparent to those of ordinary skill in the art, and the general principles defined herein may be applied to other specific implementations without departing from the spirit or scope of the disclosure. Therefore, the claims are not intended to be limited to the specific implementations shown herein, but are to be consistent with the broadest scope consistent with the disclosure, the principles and novel features disclosed herein.

[0094] Additionally, various features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable subcombination. Thus, although features may be described above as functioning in a particular combination, and even initially claimed as such, one or more features from a claimed combination may in some cases be deleted from the combination, and a claimed combination may be directed to a subcombination or a variation of a subcombination.

[0095] Similarly, although operations are depicted in a specific order in the figure, this should not be understood as requiring such operations to be performed in the specific order shown or in a sequential order, or to perform all illustrated operations to achieve the desired result. In addition, the accompanying drawings may schematically depict one or more example processes in the form of a flow chart or a flow diagram. However, other operations not depicted can be incorporated into the example processes schematically illustrated. For example, one or more additional operations may be performed before, after, simultaneously or between any operations in the illustrated operations. In some environments, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the specific implementation described above should not be understood as requiring such separation in all specific implementations, but it should be understood as described program components and systems can usually be integrated together in a single software product, or be packaged in multiple software products.

[0096] The following provides an overview of various embodiments of the disclosure.

[0097] Embodiment 1: A device comprises: a processor core, the processor core being configured to perform operations at a received clock control frequency; and a clock controller, the clock controller being configured to clock the processor core at a default frequency in response to the processor core operating in a default operating mode, and to enter a stepped clock control frequency mode in response to a parameter value associated with the processor core exceeding a first threshold, the stepped clock control frequency mode comprising alternating between clocking the processor core at a first frequency for a first time interval and clocking the processor core at a second frequency different from the first frequency for a second time interval.

[0098] Embodiment 2: The apparatus of embodiment 1, wherein the parameter value associated with the processor core comprises a temperature or a rate of increase in temperature of the processor core.

[0099] Embodiment 3: The apparatus of embodiment 1, wherein the parameter value associated with the processor core comprises power applied to the processor core by a power manager.

[0100] Embodiment 4: The apparatus of Embodiment 1, wherein the parameter value associated with the processor core comprises a combination of a temperature or a rate of increase in temperature of the processor core and a power applied to the processor core.

[0101] Embodiment 5: The device according to any one or more of the above embodiments further includes: a battery charge sensor register, and wherein the clock controller further enters the stepped clock frequency mode in response to the battery charge level value in the battery charge sensor register being less than a battery charge level threshold.

[0102] Embodiment 6: An apparatus according to any one or more of the above embodiments, wherein the clock controller is further configured to: determine that the parameter value associated with the processor core is lower than a second threshold; and exit the stepped clock frequency mode in response to the parameter value being lower than the second threshold.

[0103] Embodiment 7: The device of any one or more of the above embodiments, wherein the stepped clocked frequency pattern further comprises alternating to a third frequency for a third time interval between the first time interval and the second time interval.

[0104] Embodiment 8: An apparatus according to any one or more of the above embodiments, wherein the processor core is composed of a multi-core processor having a second processor core, and the apparatus further comprises: a second processor core; and a second clock controller, wherein the second clock controller is configured to enter the stepped clock frequency mode in response to a parameter value of the second processor core exceeding a second core threshold.

[0105] Embodiment 9: The device according to any one or more of the above embodiments further includes: a parameter register, which is used to store the value of the parameter; and a comparator, which is coupled to the parameter register and the clock controller to compare the value stored in the parameter register with the first threshold and send a signal to the clock controller.

[0106] Embodiment 10: The apparatus according to embodiment 9 further comprises: a thermal sensor configured to measure a temperature value of the processor core and transmit the temperature value to the parameter register.

[0107] Embodiment 11: The apparatus of any one or more of the above embodiments, wherein the first frequency and the second frequency are selected based on at least one of power, performance, and temperature.

[0108] Embodiment 12: The apparatus of any one or more of the above embodiments, wherein the first time interval and the second time interval are selected based on the first frequency and the second frequency.

[0109] Embodiment 13: A method, comprising: clocking a processor core at a default frequency in response to the processor core operating in a default operating mode; and entering a stepped clocking frequency mode in response to a parameter value associated with the processor core exceeding a first threshold, the stepped clocking frequency mode comprising alternating between clocking the processor core at a first frequency for a first time interval and clocking the processor core at a second frequency different from the first frequency for a second time interval.

[0110] Embodiment 14: The method according to embodiment 13 further includes: detecting that a parameter value associated with the processor core is lower than a second threshold; and in response to the parameter value associated with the processor core being lower than the second threshold, exiting the stepped clock frequency mode.

[0111] Embodiment 15: The method of Embodiment 13 or 13, wherein the first frequency is at least 3% higher than the second frequency.

[0112] Embodiment 16: The method of any one or more of Embodiments 13 to 15, wherein the first time interval is longer than one million cycles of the first frequency.

[0113] Embodiment 17: The method according to any one or more of Embodiments 13 to 16, wherein the first time interval and the second time interval are substantially the same.

[0114] Embodiment 18: The method according to any one or more of Embodiments 13 to 17 further includes: transmitting the parameter value to a parameter register; and comparing the parameter value stored in the parameter register with the first threshold value.

[0115] Embodiment 19: The method of Embodiment 18, wherein the parameter value comprises at least one of a temperature of the processor core, a rate of heat increase of the processor core, and a power applied to the processor core.

[0116] Embodiment 20: The method of any one or more of Embodiments 13 to 19, wherein the stepped clocked frequency pattern further comprises alternating to a third frequency for a third time interval between the first time interval and the second time interval.

[0117] Embodiment 21: The method according to any one or more of embodiments 13 to 20, wherein the processor core is composed of a multi-core processor having a second processor core, the method further comprising:

[0118] measuring a temperature of the second processor core; and in response to the temperature of the second processor core exceeding a second temperature threshold, entering the stepped clock frequency mode of the second processor core.

[0119] Embodiment 22: The method according to any one or more of Embodiments 13 to 21 further includes: selecting the first frequency and the second frequency based on one or more additional parameters.

[0120] Embodiment 23: The method of Embodiment 22, wherein the one or more additional parameters include at least one of power, performance, or temperature.

[0121] Embodiment 24: The method according to any one or more of Embodiments 13 to 23 further includes: selecting the first time interval and the second time interval based on the first frequency and the second frequency.

[0122] Embodiment 25: A device comprising: a component for clocking a processor core at a default frequency in response to the processor core operating in a default operating mode; and a component for entering a stepped clocking frequency mode in response to a parameter value associated with the processor core exceeding a first threshold, the stepped clocking frequency mode comprising alternating between clocking the processor core at a first frequency for a first time interval and clocking the processor core at a second frequency different from the first frequency for a second time interval.

[0123] Embodiment 26: The apparatus according to embodiment 25 further comprises: a component for detecting that a parameter value associated with the processor core is lower than a second threshold; and a component for exiting the stepped clock frequency mode in response to the parameter value associated with the processor core being lower than the second threshold.

[0124] Embodiment 27: The apparatus of Embodiment 25 or 26, further comprising means for setting a voltage supply to the processor core to a first voltage during the first time interval and to a different second voltage during the second time interval.

Claims

1. A device comprising: a processor core configured to perform operations at the received clock frequency; as well as a clock controller configured to clock the processor core at a default frequency in response to the processor core operating in a default operating mode, and to enter a stepped clocking frequency mode in response to a parameter value associated with the processor core exceeding a first threshold, the stepped clocking frequency mode comprising alternating between clocking the processor core at a first frequency for a first time interval and clocking the processor core at a second frequency different from the first frequency for a second time interval. 2 . The apparatus of claim 1 , wherein the parameter value associated with the processor core comprises a temperature or a rate of temperature increase of the processor core. 3 . The apparatus of claim 1 , wherein the parameter value associated with the processor core comprises power applied to the processor core by a power manager. 4 . The apparatus of claim 1 , wherein the parameter value associated with the processor core comprises a combination of a temperature or a rate of temperature increase of the processor core and a power applied to the processor core.

5. The apparatus according to claim 1, further comprising: A battery charge sensor register is provided, and wherein the clock controller enters the stepped clocking frequency mode further in response to a battery charge level value in the battery charge sensor register being less than a battery charge level threshold.

6. The apparatus of claim 1, wherein the clock controller is further configured to: determine that the parameter value associated with the processor core is below a second threshold; and exit the stepped clocking frequency mode in response to the parameter value being below the second threshold.

7. The apparatus of claim 1, wherein the stepped clocked frequency pattern further comprises alternating to a third frequency for a third time interval between the first time interval and the second time interval.

8. The apparatus of claim 1, wherein the processor core is comprised of a multi-core processor having a second processor core, the apparatus further comprising: Second processor core; and A second clock controller is configured to enter the stepped clocking frequency mode in response to a parameter value of the second processor core exceeding a second core threshold.

9. The apparatus according to claim 1, further comprising: A parameter register, the parameter register being used to store the parameter value; and A comparator is coupled to the parameter register and the clock controller to compare the parameter value stored in the parameter register with the first threshold value and to signal the clock controller.

10. The apparatus according to claim 9, further comprising: A thermal sensor is configured to measure a temperature value of the processor core and transmit the temperature value to the parameter register.

11. The apparatus of claim 1, wherein the first frequency and the second frequency are selected based on at least one of power, performance, and temperature.

12. The apparatus of claim 1, wherein the first time interval and the second time interval are selected based on the first frequency and the second frequency.

13. A method comprising: clocking the processor core at a default frequency in response to the processor core operating in a default operating mode; as well as In response to a parameter value associated with the processor core exceeding a first threshold, a stepped clocked frequency mode is entered, the stepped clocked frequency mode comprising alternating between clocking the processor core at a first frequency for a first time interval and clocking the processor core at a second frequency different from the first frequency for a second time interval.

14. The method according to claim 13, further comprising: detecting that the parameter value associated with the processor core is below a second threshold; as well as In response to the parameter value associated with the processor core being below the second threshold, the stepped clocked frequency mode is exited.

15. The method of claim 13, wherein the first frequency is at least 3% higher than the second frequency.

16. The method of claim 13, wherein the first time interval is longer than one million cycles of the first frequency. The method of claim 13 , wherein the first time interval and the second time interval are substantially the same.

18. The method according to claim 13, further comprising: transferring the parameter value to a parameter register; as well as The parameter value stored in the parameter register is compared to the first threshold value.

19. The method of claim 18, wherein the parameter value comprises at least one of a temperature of the processor core, a rate of heat increase of the processor core, and a power applied to the processor core.

20. The method of claim 13, wherein the stepped clocked frequency pattern further comprises alternating to a third frequency for a third time interval between the first time interval and the second time interval.

21. The method of claim 13, wherein the processor core is comprised of a multi-core processor having a second processor core, the method further comprising: measuring a temperature of the second processor core; as well as In response to the temperature of the second processor core exceeding a second temperature threshold, the stepped clock frequency mode of the second processor core is entered.

22. The method of claim 13, further comprising: The first frequency and the second frequency are selected based on one or more additional parameters.

23. The method of claim 22, wherein the one or more additional parameters include at least one of power, performance, or temperature.

24. The method of claim 13, further comprising: The first time interval and the second time interval are selected based on the first frequency and the second frequency.

25. An apparatus comprising: means for clocking the processor core at a default frequency in response to the processor core operating in a default operating mode; as well as Means for entering a stepped clocking frequency mode in response to a parameter value associated with the processor core exceeding a first threshold, the stepped clocking frequency mode comprising alternating between clocking the processor core at a first frequency for a first time interval and clocking the processor core at a second frequency different from the first frequency for a second time interval.

26. The apparatus according to claim 25, further comprising: means for detecting that the parameter value associated with the processor core is below a second threshold; as well as Means for exiting the stepped clocked frequency mode in response to a parameter value associated with the processor core falling below the second threshold.

27. The apparatus of claim 25, further comprising: Means for setting a voltage supply to the processor core to a first voltage during the first time interval and to a different second voltage during the second time interval.

28. The apparatus of claim 25, wherein the first frequency is at least 3% higher than the second frequency.

29. The apparatus of claim 25, wherein the first time interval is longer than one million cycles of the first frequency.

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