Ring oscillator with stages implemented to assess PFET-NFET process performance

Abstract

An integrated circuit (IC) includes: a first ring oscillator (RO) including a first set of cascade stages, where each of the first set of cascade stages includes a first logic inverter (400) including: a first set of field effect transistors (FETs) (M13, M14, M15), a first set of field effect transistors (FET) coupled in parallel between a first voltage rail (Vdd) and a first intermediate node (OUT), wherein the first set of FETs includes a set of gates coupled to an input (IN) of the first logic inverter; and a second set of FETs (M16, M17, M18) coupled in series between the first intermediate node (OUT) and a second voltage rail (GND), where the second set of FETs comprises at least a first FET (M16, M1-) And at least a first FET (M18) comprising a gate coupled to the input (IN) of the first logic inverter, the at least second FET being diode-connected according to a first mode of operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 17 / 898,332, filed on August 29, 2022, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure are generally directed to evaluating process performance (e.g., skew) of p-channel field effect transistors (PFETs) and n-channel field effect transistors (NFETs) in an integrated circuit (IC) using a ring oscillator (RO) that is implemented for such process evaluation. Background Art

[0004] An integrated circuit (IC), such as a system on a chip (SOC), may include many transistors. These transistors may be implemented as complementary metal oxide semiconductor (CMOS) field effect transistors (FETs), including n-channel FETs (NFETs) and p-channel FETs (PFETs). Since ICs (such as SoCs) are often mass-produced, there may be process variations that affect the switching performance of NFETs and PFETs. The process variations that affect NFETs and PFETs may be evaluated or measured based on their respective switching speeds. Process monitoring, modeling, and circuit compensation may follow such evaluation or measurement of process variations of NFETs and PFETs. Summary of the invention

[0005] The following content presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is subsequently presented.

[0006] One aspect of the present disclosure relates to an integrated circuit (IC). The IC includes a first ring oscillator (RO), the first ring oscillator (RO) including a first set of cascaded stages, wherein each of the first set of cascaded stages includes a first logic inverter, the first logic inverter including: a first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and a first intermediate node, wherein the first set of FETs includes a set of gates coupled to an input of the first logic inverter; and a second set of FETs coupled in series between the first intermediate node and a second voltage rail, wherein the second set of FETs includes at least a first FET and at least a second FET, the first FET including a gate coupled to the input of the first logic inverter, the second FET being diode-connected according to a first operating mode.

[0007] Another aspect of the present disclosure relates to a logic inverter. The logic inverter includes: a first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and an output, wherein the first set of FETs includes a set of gates respectively coupled to inputs; and a second set of FETs coupled in series between the output and the second voltage rail, wherein the second set of FETs includes at least a first FET and at least a second FET, the first FET including a gate coupled to the input, the second FET being diode-connected according to a first operating mode.

[0008] Another aspect of the present disclosure relates to a wireless communication device. The wireless communication device includes: at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver; and a ring oscillator (RO) coupled to the one or more signal processing cores, wherein the RO includes a set of cascaded stages, wherein each of the set of cascaded stages includes a first logic inverter, the first logic inverter including: a first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and a first intermediate node, wherein the first set of FETs includes a set of gates coupled to an input of the first logic inverter; and a second set of FETs coupled in series between the first intermediate node and the second voltage rail, wherein the second set of FETs includes at least a first FET and at least a second FET, the first FET including a gate coupled to the input of the first logic inverter, the second FET being diode-connected according to a first operating mode.

[0009] To achieve the foregoing and related purposes, one or more specific implementations include the features fully described below and specifically pointed out in the claims. The following description and the accompanying illustrations set forth in detail certain illustrative aspects of the one or more specific implementations. However, these aspects are merely indicative of several of the various ways in which the principles of each specific implementation can be employed, and the specification specific implementations are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A A block diagram of an example process measurement device for measuring process performance (eg, skew) associated with n-channel field effect transistors (NFETs) and p-channel field effect transistors (PFETs) in an integrated circuit (IC) is illustrated according to an aspect of the present disclosure.

[0011] Figure 1B 1 illustrates a signal S generated by a ring oscillator (RO) for measuring NFET process performance according to another aspect of the present disclosure. N The frequency f N Relative to the signal S generated by the second RO used to measure the performance of the PfET process P The frequency f P Graph of the curve.

[0012] Figure 2A A schematic diagram illustrating an example ring oscillator (RO) implemented to evaluate n-channel field effect transistor (NFET) process performance according to another aspect of the present disclosure is illustrated.

[0013] Figure 2B Another aspect of the present disclosure is illustrated. Figure 2A Schematic diagram of an example logic inverter of a ring oscillator (RO).

[0014] Figure 3A A schematic diagram illustrating an example ring oscillator (RO) implemented to evaluate p-channel field effect transistor (PFET) process performance according to another aspect of the present disclosure is illustrated.

[0015] Figure 3B Another aspect of the present disclosure is illustrated. Figure 3A Schematic diagram of an example logic inverter stage of a ring oscillator (RO).

[0016] Figure 4 A schematic diagram illustrating an example logic inverter of a ring oscillator (RO) implemented to evaluate n-channel field effect transistor (NFET) process performance according to another aspect of the present disclosure is illustrated.

[0017] Figure 5A schematic diagram illustrating an example logic inverter of a ring oscillator (RO) implemented to evaluate p-channel field effect transistor (PFET) process performance according to another aspect of the present disclosure is illustrated.

[0018] Figure 6 A schematic diagram illustrating an example stage of a ring oscillator (RO) implemented to evaluate n-channel field effect transistor (NFET) process performance according to another aspect of the present disclosure is illustrated.

[0019] Figure 7 A schematic diagram illustrating an example stage of a ring oscillator (RO) implemented to evaluate p-channel field effect transistor (PFET) process performance according to another aspect of the present disclosure is illustrated.

[0020] Figure 8 A schematic diagram illustrating another example ring oscillator (RO) implemented to evaluate n-channel field effect transistor (NFET) process performance according to another aspect of the present disclosure is illustrated.

[0021] Fig. 9 A schematic diagram illustrating another example ring oscillator (RO) implemented to evaluate p-channel field effect transistor (PFET) process performance according to another aspect of the present disclosure is illustrated.

[0022] Fig.10 A bar graph comparing different logic inverters for evaluating n-channel field effect transistor (NFET) process performance is illustrated in accordance with another aspect of the present disclosure.

[0023] Fig.11 A bar graph comparing different logic inverters for evaluating p-channel field effect transistor (PFET) process performance is illustrated in accordance with another aspect of the present disclosure.

[0024] Fig.12 A schematic diagram illustrating an example logic inverter of a ring oscillator (RO) implemented to evaluate n-channel field effect transistor (NFET) process aging performance according to another aspect of the present disclosure is illustrated.

[0025] Fig.13 A schematic diagram illustrating an example logic inverter of a ring oscillator (RO) implemented to evaluate p-channel field effect transistor (PFET) process aging performance according to another aspect of the present disclosure is illustrated.

[0026] Fig.14 A schematic diagram illustrating another example ring oscillator (RO) implemented to evaluate n-channel field effect transistor (NFET) process aging performance according to another aspect of the present disclosure is illustrated.

[0027] Fig.15A schematic diagram illustrating another example ring oscillator (RO) implemented to evaluate p-channel field effect transistor (PFET) process aging performance according to another aspect of the present disclosure is illustrated.

[0028] Fig.16 Illustrated is a bar graph comparing a PFET process contribution to a NFET process contribution to a frequency of a signal generated by a ring oscillator (RO) implemented to evaluate n-channel field effect transistor (NFET) process aging performance according to another aspect of the present disclosure.

[0029] Fig.17 Illustrated is a bar graph comparing NFET process contribution to PFET process contribution to the frequency of a signal generated by a ring oscillator (RO) implemented to evaluate p-channel field effect transistor (PFET) process aging performance according to another aspect of the present disclosure.

[0030] Fig.18 A block diagram of an example wireless communication device according to another aspect of the disclosure is illustrated. DETAILED DESCRIPTION

[0031] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, in order to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0032] An integrated circuit (IC), such as a system on a chip (SOC), may include many transistors, such as in the billion range. Many of these transistors are complementary metal oxide semiconductor (CMOS) field effect transistors (FETs), including n-channel FETs (NFETs) (or sometimes referred to as n-channel metal oxide semiconductor (NMOS) FETs) and p-channel FETs (PFETs) (or sometimes referred to as p-channel metal oxide semiconductor (NMOS) FETs). Since ICs, such as SOCs, are often mass-produced, there may be process variations that affect NFETs and PFETs across different ICs and even across different locations on the same IC die. The process variations that affect NFETs and PFETs may be evaluated or measured based on their respective switching speeds.

[0033] For example, if both the NFET and PFET of the IC have a switching speed lower than the average switching speed compared to the average switching speed of the NFETs and PFETs of a significant sample size, the corresponding NFET and PFET of the IC may be characterized as having a slow-slow (SS) process inflection point. If both the NFET and PFET of the IC have a switching speed higher than the average switching speed, the corresponding NFET and PFET of the IC may be characterized as having a fast-fast (FF) process inflection point. If the NFET of the IC has a switching speed higher than the average switching speed and the PFET of the IC has a switching speed lower than the average switching speed, the corresponding NFET and PFET of the IC may be characterized as having a fast-slow (FS) process inflection point. And, if the NFET of the IC has a switching speed lower than the average switching speed and the PFET of the IC has a switching speed higher than the average switching speed, the corresponding NFET and PFET of the IC may be characterized as having a slow-fast (SF) process inflection point.

[0034] There may be many reasons to measure the process inflection point of an IC. For example, it may be desirable to evaluate process variations across many ICs manufactured by an IC manufacturing plant to evaluate quality control, as well as to develop a process model for the ICs. Second, it may be desirable to characterize the process inflection point of an IC to tune and compensate the IC for process variations (e.g., increase the clock frequency if an SS process inflection point is determined, decrease the clock frequency if an FF process inflection point is determined, and perform duty cycle distortion (DCD) compensation if an FS or SF process inflection point is determined). Third, it may be desirable to characterize the process inflection point of an IC over its operating lifetime to tune and compensate for process aging (e.g., process aging due to positive bias temperature instability (PBTI) affecting NFETs and negative bias temperature instability (NBTI) affecting PFETs (e.g., threshold voltage V T Increase)).

[0035] Figure 1A A block diagram of an example process measurement device 100 for measuring process performance (e.g., skew) of associated NFETs and PFETs in an integrated circuit (IC) according to an aspect of the present disclosure is illustrated. The process measurement device 100 includes a first ring oscillator (RO) 110, a second ring oscillator (RO) 120, and a process evaluation circuit 130.

[0036] As discussed in greater detail further herein, the first RO 110 may be implemented or configured to generate a periodic or oscillating signal S N , compared with PFET, its frequency f N In other words, the signal S is more based on the process performance of the NFET than the NBTI or switching speed of the PFET of the first RO 110. N The frequency f NIt may be more related to or dependent on the PBTI or switching speed of the NFET of the first RO 110 .

[0037] Similarly, the second RO 120 may be implemented or configured to generate a periodic or oscillating signal S P , compared with NFET, its frequency f P In other words, the signal S is more based on the process performance of the PFET than the PBTI or switching speed of the NFET of the second RO 120. P The frequency f P It may be more related to or dependent on the NBTI or switching speed of the PFET of the second RO 120 .

[0038] The process evaluation circuit 130 is configured to receive a signal S N and S P , determine its corresponding frequency f N and f P , and based on the frequency f N and f P For example, the process evaluation circuit 130 may output the frequency measurement for analysis by an IC manufacturing plant to evaluate the consistency and quality of its IC process, improve its IC process, and model the process performance of its IC's NFET and PFET. Alternatively or in addition, the process evaluation circuit 130 may be based on the frequency f N and f P To tune or compensate various circuits in the IC to address different process inflection points.

[0039] For example, if the frequency f N and f P If the frequency f indicates an SS or FF process inflection point, the process evaluation circuit 130 may tune the associated clock generation circuit to increase or decrease the frequency of its clock signal. N and f P If the FS or SF process inflection point is indicated, the process evaluation circuit 130 may perform operations to reduce the duty cycle distortion (DCD) of the clock signal generated by the clock generation circuit. The process evaluation circuit 130 may monitor the frequency f at specific time intervals over the operating life of the IC. N and f P To compensate for the aging effects on the NFET and PFET.

[0040] Figure 1B exemplifies a signal S generated by the first RO 110 according to another aspect of the present disclosure. N The frequency f N The signal S generated by the second RO 120 P The frequency f PThe y-axis or vertical axis represents the signal S ranging from 480 megahertz (MHz) to 1140 MHz. N The frequency f N The x-axis or horizontal axis represents the signal S ranging from 650MHz to 1250MHz. P The frequency f P The horizontal dashed line represents the signal S for a significant sample size of the IC tested. N The first average frequency (eg, 810 MHz). The vertical dashed line represents the signal S for a significant sample size of the IC tested. P The average frequency (e.g., 910 MHz).

[0041] In this example, if the process evaluation circuit 130 determines that the frequency f N and f P All lower than the corresponding average frequency (e.g., 810MHz) and (e.g., 910 MHz), the process evaluation circuit 130 may classify the process inflection point of such IC or region thereof as an SS process inflection point and may take appropriate action accordingly. On the other hand, if the process evaluation circuit 130 determines that the frequency f N and f P Higher than the corresponding average frequency (e.g., 810MHz) and (e.g., 910 MHz), the process evaluation circuit 130 may classify the process inflection point of such IC or region thereof as a FF process inflection point and may take appropriate action accordingly.

[0042] If the process evaluation circuit 130 determines that the frequency f N Above average frequency (e.g., 810 MHz) and the frequency f P Below average frequency (e.g., 910 MHz), the process evaluation circuit 130 may classify the process inflection point of such IC or region thereof as a FS process inflection point and may take appropriate action accordingly. N Below average frequency (e.g., 810 MHz) and the frequency f P Above average frequency (e.g., 910 MHz), the process evaluation circuit 130 may classify the process inflection point of such IC or region thereof as a SF process inflection point and may take appropriate action accordingly.

[0043] Figure 2AA schematic diagram of an example ring oscillator (RO) 200 according to another aspect of the present disclosure is illustrated. RO 200 may be an example detailed implementation of the previously discussed ring oscillator (RO) 110. RO 200 includes a group of cascaded logic inverters 210-1 to 210-K (where K is an odd integer) arranged in a ring. That is, the group of cascaded logic inverters 210-1 to 210-K includes a group of outputs coupled to a group of inputs of cascaded logic inverters 210-2 to 210-K and 210-1, respectively.

[0044] Each of the set of cascaded logic inverters 210-1 to 210-K may be implemented as a three-input NAND gate with its three inputs coupled together. As further discussed herein, in this configuration, RO 200 is configured to generate an oscillating or periodic signal S N , compared with the PFETs of the cascaded logic inverters 210 - 1 to 210 -K, whose frequency f N The process evaluation circuit 130 may be configured to receive and analyze the signal S N To produce a characterization of the process performance of the NFETs associated with the set of cascaded logic inverters 210 - 1 to 210 -K.

[0045] Figure 2B Schematic diagram of an example logic inverter 250 according to another aspect of the present disclosure is illustrated. The logic inverter 250 may be an example detailed implementation of one of the set of cascaded logic inverters 210-1 to 210-K of the RO 200.

[0046] Specifically, the logic inverter 250 includes three (3) p-channel metal oxide semiconductor field effect transistors (PMOS FETs) M1, M2, and M3 coupled in parallel between the upper voltage rail Vdd and the output of the logic inverter 250. More specifically, the PMOSFETs M1, M2, and M3 include respective sources coupled to the upper voltage rail Vdd, respective gates coupled together and coupled to the input of the logic inverter 250, and respective drains coupled together and coupled to the output of the logic inverter 250.

[0047] The logic inverter 250 also includes three (3) n-channel metal oxide semiconductor field effect transistors (NMOS FETs) M4, M5, and M6 coupled in series between the output of the logic inverter 250 and a lower voltage rail Vss (e.g., ground). More specifically, the NMOS FET M4 includes a drain coupled to the output of the logic inverter 250 and a gate coupled to the input of the logic inverter 250. The NMOS FET M5 includes a drain coupled to the source of the NMOS FET M4 and a gate coupled to the input of the logic inverter 250. The NMOS FET M6 includes a drain coupled to the source of the NMOS FET M5, a gate coupled to the input of the logic inverter 250, and a source coupled to the lower voltage rail Vss.

[0048] In operation, if the input signal is at a logic zero (0) (e.g., at substantially Vss potential), the PMOS FETs M1, M2, and M3 are turned on, and the NMOS FETs M4, M5, and M6 are turned off. The turned-on PMOS FETs M1, M2, and M3 couple the upper voltage rail Vdd to the output of the logic inverter 250, causing the output to produce an output signal at a logic one (1) (e.g., at substantially Vdd potential). The turned-off NMOS FETs M4, M5, and M6 electrically isolate the output of the logic inverter 250 from the lower voltage rail Vss.

[0049] Similarly, if the input signal is at a logic one (1) (e.g., at substantially Vdd potential), the PMOS FETs M1, M2, and M3 are turned off, and the NMOS FETs M4, M5, and M6 are turned on. The turned-on NMOS FETs M4, M5, and M6 couple the output of the logic inverter 250 to the lower voltage rail Vss, causing the output to produce an output signal at a logic zero (0) (e.g., at substantially Vss potential). The turned-off PMOS FETs M1, M2, and M3 electrically isolate the output of the logic inverter 250 from the upper voltage rail Vdd.

[0050] The process performance or switching speed of the logic inverter 250 is based on the first delay (Delay) associated with the PMOS FETs M1, M2, and M3 turning on in response to the input signal transitioning to a logic zero (0) and causing the output to transition to a logic one (1). P ); and a second delay (Delay ) associated with NMOS FETs M4, M5, and M6 turning on in response to the input signal transitioning to a logic one (1) and causing the output to transition to a logic zero (0). N1 ). The signal S generated by RO 200 N The frequency f N Can be compared with 1 / (K*(Delay P +DelayN1 ), where K is the number of RO 200 levels.

[0051] Delay P is inversely related to the sum of the currents flowing through the parallel PMOS FETs M1, M2, and M3. N1 is inversely related to the current flowing through the series NMOS FETs M4, M5 and M6. Since the effective on-resistance between the upper voltage rail Vdd and the output is the parallel resistance of the three (3) turned-on PMOS FETs M1, M2 and M3, and the effective on-resistance between the output and the lower voltage rail Vss is the series resistance of the three (3) turned-on NMOS FETs M4, M5 and M6, the sum of the currents flowing through the parallel PMOS FETs M1, M2 and M3 is significantly greater than the current flowing through the series NMOS FETs M4, M5 and M6. Therefore, Delay N1 Significantly greater than Delay P Then, with Delay P In comparison, signal S N The frequency f N More dominated or based on Delay N1 .

[0052] In theory, since RO 200 is configured to generate its frequency f N The measured signal S is a process performance (eg, skew) signal of the NMOS FETs M4, M5, and M6. N , so the expected frequency f N Delay only N1 However, as discussed above, the frequency f N It is Delay N1 and Delay P By making Delay N1 Delay P Much larger (Delay N1 >>Delay P ), frequency f N Close to only Delay N1 Its ideal frequency is a function of .

[0053] Figure 3AA schematic diagram of an example ring oscillator (RO) 300 according to another aspect of the present disclosure is illustrated. The RO 300 may be an example detailed implementation of the previously discussed ring oscillator (RO) 120. The RO 300 includes a group of cascaded logic inverters 310-1 to 310-K (where K is an odd integer) arranged in a ring. That is, the group of cascaded logic inverters 310-1 to 310-K includes a group of outputs coupled to a group of inputs of the cascaded logic inverters 310-2 to 310-K and 310-1, respectively.

[0054] Each of the set of cascaded logic inverters 310-1 to 310-K may be implemented as a three-input NOR gate with its three inputs coupled together. As further discussed herein, in this configuration, RO 300 is configured to generate an oscillating or periodic signal S p , compared with the NFETs of the cascaded logic inverters 310-1 to 310-K, whose frequency f P The process evaluation circuit 130 may be configured to receive and analyze the signal S , based more on the process performance (eg, switching speed or skew) of the PFETs of the cascaded logic inverters 310 - 1 to 310 -K. P To produce a characterization of the process performance of the PFETs associated with the set of cascaded logic inverters 310 - 1 through 310 -K.

[0055] Figure 3B Schematic diagram of an example logic inverter 350 according to another aspect of the present disclosure is illustrated. The logic inverter 350 may be an example detailed implementation of one of the set of cascaded logic inverters 310-1 to 310-K of the RO 300.

[0056] Specifically, the logic inverter 350 includes three (3) PMOS FETs M7, M8, and M9 coupled in series between an upper voltage rail Vdd and the output of the logic inverter 350. More specifically, the PMOS FET M7 includes a source coupled to the upper voltage rail Vdd and a gate coupled to the input of the logic inverter 350. The PMOS FET M8 includes a source coupled to the drain of the PMOS FET M7 and a gate coupled to the input of the logic inverter 350. The PMOS FET M9 includes a source coupled to the drain of the PMOS FET M8, a gate coupled to the input of the logic inverter 350, and a drain coupled to the output of the logic inverter 350.

[0057] The logic inverter 350 also includes three (3) NMOS FETs M10, M11, and M12 coupled in parallel between the output of the logic inverter 350 and a lower voltage rail Vss (e.g., ground). More specifically, the NMOS FETs M10, M11, and M12 include respective drains coupled to the output of the logic inverter 350, respective gates coupled together and coupled to the input of the logic inverter 350, and respective sources coupled to the lower voltage rail Vss.

[0058] In operation, if the input signal is at a logic zero (0) (e.g., at substantially Vss potential), the PMOS FETs M7, M8, and M9 are turned on, and the NMOS FETs M10, M11, and M12 are turned off. The turned-on PMOS FETs M7, M8, and M9 couple the upper voltage rail Vdd to the output of the logic inverter 350, causing the output to produce an output signal at a logic one (1) (e.g., at substantially Vdd potential). The turned-off NMOS FETs M10, M11, and M12 electrically isolate the output of the logic inverter 350 from the lower voltage rail Vss.

[0059] Similarly, if the input signal is at a logic one (1) (e.g., at substantially Vdd potential), the PMOS FETs M7, M8, and M9 are turned off, and the NMOS FETs M10, M11, and M12 are turned on. The turned-on NMOS FETs M10, M11, and M12 couple the output of the logic inverter 350 to the lower voltage rail Vss, causing the output to produce an output signal at a logic zero (0) (e.g., at substantially Vss potential). The turned-off PMOS FETs M7, M8, and M9 electrically isolate the output of the logic inverter 350 from the upper voltage rail Vdd.

[0060] The process performance or switching speed of the logic inverter 350 is based on the first delay (Delay) associated with the PMOS FETs M7, M8, and M9 turning on in response to the input signal transitioning to a logic zero (0) and causing the output to transition to a logic one (1). P1 ); and a second delay (Delay ) associated with NMOS FETs M10, M11, and M12 turning on in response to the input signal transitioning to a logic one (1) and causing the output to transition to a logic zero (0). N ). The signal S generated by RO 300 P The frequency f P Can be compared with 1 / (K*(Delay P1 +Delay N ), where K is the number of RO 300 levels.

[0061] Delay P1is inversely related to the current flowing through the series PMOS FETs M7, M8, and M9. However, Delay N The Delay Current is inversely related to the sum of the currents flowing through the parallel NMOS FETs M10, M11, and M12. Since the effective on-resistance between the upper voltage rail Vdd and the output is the series resistance of the three (3) turned-on PMOS FETs M7, M8, and M9, and the effective on-resistance between the output and the lower voltage rail Vss is the parallel resistance of the three (3) turned-on NMOS FETs M10, M11, and M12, the sum of the currents flowing through the parallel NMOS FETs M10, M11, and M12 is significantly greater than the current flowing through the series PMOS FETs M7, M8, and M9. Therefore, the ... P1 Significantly greater than Delay N Then, with Delay N In comparison, signal S P The frequency f P More dominated or based on Delay P1 .

[0062] Similarly, as discussed, in theory, since RO 300 is configured to generate its frequency f P The measured signal S is a process performance (eg, skew) signal of the PMOS FETs M7, M8, and M9. P , so the expected frequency f P Delay only P1 However, as discussed above, the frequency f P It is Delay P1 and Delay N By making Delay P1 Delay N Much larger (Delay P1 >>Delay N ), frequency f P Close to only Delay P1 Its ideal frequency is a function of .

[0063] Figure 4 4 is a schematic diagram illustrating an example logic inverter 400 according to another aspect of the present disclosure. As further discussed herein, the logic inverter 400 may be used in generating a signal S N A ring oscillator (RO) is implemented in a ring oscillator (RO) to measure or evaluate process performance (e.g., skew) of an NMOS FET in an integrated circuit (IC) incorporating the RO or an NMOS FET in the IC or at a location near the RO.

[0064] Specifically, the logic inverter 400 includes a group of PMOS FETs M13, M14, and M15 (e.g., three (3), but may be two (2) or four (4) or more) coupled in parallel between the upper voltage rail Vdd and the output of the logic inverter 400. More specifically, the PMOS FETs M13, M14, and M15 include respective sources coupled to the upper voltage rail Vdd, respective gates coupled to the input of the logic inverter 400, and respective drains coupled to the output of the logic inverter 400.

[0065] The logic inverter 400 also includes a set of NMOS FETs M16, M17, and M18 (e.g., three (3), but may be two (2) or four (4) or more) coupled in series between the output of the logic inverter 400 and a lower voltage rail Vss (e.g., ground). More specifically, the NMOS FET M16 includes a drain coupled to the output of the logic inverter 400 and a gate coupled to the input of the logic inverter 400. The NMOS FET M17 includes a drain coupled to the source of the NMOS FET M16 and a gate coupled to the input of the logic inverter 400. In this specific implementation, the NMOS FET M18 is diode-connected, including a drain and a gate coupled to the source of the NMOS FET M17, and a source coupled to the lower voltage rail Vss. It should be understood that the series path between the output of the logic inverter 400 and the lower voltage rail Vss may include more than one diode-connected NMOS FET.

[0066] In operation, if the input signal is at a logic zero (0) (e.g., at substantially Vss potential), the PMOS FETs M13, M14, and M15 are turned on, and the NMOS FETs M16 and M17 are turned off, including the diode-connected NMOS FET M18, because there is no drain current through the device M18. The turned-on PMOS FETs M13, M14, and M15 couple the upper voltage rail Vdd to the output of the logic inverter 400, causing the output to produce an output signal at a logic one (1) (e.g., at substantially Vdd potential). The turned-off NMOS FETs M16, M17, and M18 electrically isolate the output of the logic inverter 400 from the lower voltage rail Vss.

[0067] Similarly, if the input signal is at a logic one (1) (e.g., at substantially Vdd potential), the PMOS FETs M13, M14, and M15 are turned off, and the NMOS FETs M16 and M17 are turned on, including the diode-connected NMOS FET M18, because there is a drain current through the device M18. The turned-on NMOS FETs M16, M17, and M18 couple the output of the logic inverter 400 to the lower voltage rail Vss, causing the output to produce an output signal at a logic zero (0). However, due to the diode-connected NMOS FET M18, there is a threshold voltage V across the device M18. T Therefore, the output of logic inverter 400 is at substantially V T The turned-off PMOS FETs M13, M14 and M15 electrically isolate the output of the logic inverter 400 from the upper voltage rail Vdd.

[0068] The process performance or switching speed of the logic inverter 400 is based on the first delay associated with the PMOS FETs M13, M14, and M15 turning on in response to the input signal transitioning to a logic zero (0) and causing the output to transition to a logic one (1). P ); and a second delay (Delay ) associated with NMOS FET M18 connected to NMOS FET M16 and M17 and a diode turning on in response to the input signal transitioning to a logic one (1) and causing the output to transition to a logic zero (0). N2 ). The signal S generated by the ring oscillator (RO) incorporated into the logic inverter 400 N The frequency f N Can be compared with 1 / (K*(Delay P +Delay N2 ) where K is the number of levels in RO.

[0069] Compared to the previously discussed logic inverter 250, due to the diode-connected NMOS FET M18, the on-resistance of the series path (M16→M17→M18) increases compared to the on-resistance of the series path (M4→M5→M6) of the logic inverter 250. Therefore, the current through the series path decreases; thereby increasing the delay to Delay N2 Therefore, assuming the same technology node and device size, the Delay associated with logic inverter 400 is N2 Significantly greater than the Delay associated with logic inverter 250 N1 .

[0070] Delay Pis inversely related to the sum of the currents flowing through the parallel PMOS FETs M13, M14, and M15. However, Delay N2 Inversely related to the current flowing through the series NMOS FETs M16 and M17 and the diode-connected NMOS FET M18. Since the effective on-resistance between the upper voltage rail Vdd and the output is the parallel resistance of the three (3) turned-on PMOS FETs M13, M14 and M15, and the effective on-resistance between the output and the lower voltage rail Vss is the series resistance of the three (3) turned-on NMOS FETs M16 and M17 and the diode-connected M18, the sum of the currents flowing through the parallel PMOS FETs M13, M14 and M15 is significantly greater than the current flowing through the series NMOS FETs M16, M17 and M18.

[0071] Therefore, due to the diode-connected NMOS FET M18, the Delay of the logic inverter 250 N1 With Delay P Compared with the difference between N2 With Delay P The difference between has increased significantly. Therefore, with Delay P In comparison, signal S N The frequency f N More dominated or based on Delay N2 In theory, since the RO incorporated into the logic inverter 400 is configured to generate its frequency f N The measured signal S is a process performance (eg, skew) of the NMOS FETs M16, M17, and M18. N , so the expected frequency f N Delay only N2 function. N2 Delay greater than 250 of logic inverter N1 , so the signal S generated by RO incorporated into the logic inverter 400 N The frequency f N A better measurement or assessment of the process performance of the NMOS FETs M16 , M17 , and M18 is provided than the RO 200 with the logic inverter 250 .

[0072] Figure 5 1 is a schematic diagram illustrating an example logic inverter 500 according to another aspect of the present disclosure. As further discussed herein, the logic inverter 500 may be used in generating a signal S PA ring oscillator (RO) is implemented in a ring oscillator (RO) to measure or evaluate a PMOS FET in an integrated circuit (IC) incorporating the RO or a process performance (e.g., skew) of a PMOS FET in the IC or at a location near the RO.

[0073] Specifically, the logic inverter 500 includes a set of PMOS FETs M19, M20, and M21 (e.g., three (3), but may be two (2) or four (4) or more) coupled in series between an upper voltage rail Vdd and the output of the logic inverter 500. In this specific implementation, the PMOS FET M19 is diode-connected, including a source coupled to the upper voltage rail Vdd and a gate coupled to its drain. It should be understood that the series path between the upper voltage rail Vdd and the output of the logic inverter 500 may include more than one diode-connected PMOS FET. The PMOS FET M20 includes a source coupled to the gate / drain of the diode-connected PMOS FET M19 and a gate coupled to the input of the logic inverter 500. The PMOS FET M21 includes a source coupled to the drain of the PMOSFET M20, a gate coupled to the input of the logic inverter 500, and a drain coupled to the output of the logic inverter 500.

[0074] The logic inverter 500 also includes a group of NMOS FETs M22, M23, and M24 (e.g., three (3), but may be two (2) or four (4) or more) coupled in parallel between the output of the logic inverter 500 and a lower voltage rail Vss (e.g., ground). More specifically, the NMOS FETs M22, M23, and M24 include respective drains coupled to the output of the logic inverter 500, respective gates coupled to the input of the logic inverter 500, and respective sources coupled to the lower voltage rail Vss.

[0075] In operation, if the input signal is at a logic zero (0) (e.g., at substantially Vss potential), the diode-connected PMOS FET M19 and other PMOS FETs M20 and M21 are turned on, and the NMOS FETs M22, M23, and M24 are turned off. The turned-on PMOS FETs M19, M20, and M21 couple the upper voltage rail Vdd to the output of the logic inverter 500, causing the output to produce an output signal at a logic one (1). However, due to the diode-connected PMOS FET M19, there is a threshold voltage V across the device M19. T Therefore, the output of logic inverter 500 is at substantially Vdd-V T The turned-off NMOS FETs M22, M23, and M24 electrically isolate the output of the logic inverter 500 from the lower voltage rail Vss.

[0076] Similarly, if the input signal is at a logic one (1) (e.g., at substantially Vdd potential), the diode-connected PMOS FET M19 and other PMOS FETs M20 and M21 are turned off, and the NMOS FETs M22, M23, and M24 are turned on. The turned-on NMOS FETs M22, M23, and M24 couple the output of the logic inverter 500 to the lower voltage rail Vss, causing the output to produce an output signal at a logic zero (0) (e.g., at substantially Vss potential). The turned-off PMOS FETs M19, M20, and M21 electrically isolate the output of the logic inverter 500 from the upper voltage rail Vdd.

[0077] The process performance or switching speed of the logic inverter 500 is based on the first delay (Delay) associated with the PMOS FETs M19, M20, and M21 turning on in response to the input signal transitioning to a logic zero (0) and causing the output to transition to a logic one (1). P2 ); and a second delay (Delay ) associated with NMOS FETs M22, M23, and M24 turning on in response to the input signal transitioning to a logic one (1) and causing the output to transition to a logic zero (0). N ). The signal S generated by RO incorporated into the logic inverter 500 P The frequency f P Can be compared with 1 / (K*(Delay P2 +Delay N ), where K is the order of RO.

[0078] Compared to the previously discussed logic inverter 350, due to the diode-connected PMOS FET M19, the on-resistance of the series path (M19→M20→M21) increases compared to the on-resistance of the series path (M7→M8→M9) of the logic inverter 350. Therefore, the current through the series path decreases; thereby increasing the delay to Delay P2 Therefore, assuming the same technology node and device size, the Delay associated with logic inverter 500 is P2 Significantly greater than the Delay associated with logic inverter 350 P1 .

[0079] Delay P1 The current flowing through the series diode-connected PMOS FET M19 and the PMOS FETs M20 and M21 is inversely related. NThe sum of the currents flowing through the parallel NMOS FETs M22, M23 and M24 is inversely related to the sum of the currents flowing through the parallel NMOS FETs M22, M23 and M24. Since the effective on-resistance between the upper voltage rail Vdd and the output is the series resistance of the three (3) turned-on PMOS FETs M19, M20 and M21, and the effective on-resistance between the output and the lower voltage rail Vss is the parallel resistance of the three (3) turned-on NMOS FETs M22, M23 and M24, the sum of the currents flowing through the parallel NMOS FETs M22, M23 and M24 is significantly greater than the current flowing through the series PMOSFETs M19, M20 and M21.

[0080] Therefore, due to the diode-connected PMOS FET M19, the Delay of the logic inverter 350 P1 With Delay N Compared with the difference between P2 With Delay N The difference between has increased significantly. Therefore, with Delay N In comparison, signal S P The frequency f P Even more dominated or based on Delay P2 In theory, since the RO incorporated into the logic inverter 500 is configured to generate its frequency f P The measured signal S is a process performance (eg, skew) of the PMOS FETs M19, M20, and M21. P , so the expected frequency f P Delay only P2 function. P2 Delay greater than 350 of logic inverter P1 , so the signal S generated by RO incorporated into the logic inverter 500 P The frequency f P Provides a better measurement or assessment of the process performance of the PMOS FETs M19 , M20 , and M21 than the RO 300 with the logic inverter 350 .

[0081] Figure 6 A schematic diagram of an example two logic inverter stage 600 of a ring oscillator (RO) according to another aspect of the present disclosure is illustrated. As further discussed herein, the two logic inverter stage 600 can be used in the RO for measuring or evaluating process performance of an NFET. Specifically, the two logic inverter stage 600 includes a first logic inverter 610 followed by a second logic inverter 620.

[0082] The first logic inverter 610 may be implemented as the logic inverter 400 discussed in detail previously. That is, the first logic inverter 610 includes a group of PMOS FETs M25, M26, and M27 (e.g., three (3), but may be two (2) or four (4) or more) coupled in parallel between the upper voltage rail Vdd and the intermediate node (int). The intermediate node may be the output of the first logic inverter 610. The group of parallel PMOS FETs M25, M26, and M27 include respective sources coupled to the upper voltage rail Vdd, respective gates coupled to the inputs of the two logic inverter stages 600, and drains coupled to the intermediate node.

[0083] The first logic inverter 610 includes a set of NMOS FETs M28, M29, and M30 (e.g., three (3), but may be two (2) or four (4) or more) coupled in series between an intermediate node and a lower voltage rail Vss (e.g., ground). The NMOSFET M30 may be diode-connected. It should be understood that the series path between the intermediate node and the lower voltage rail Vss may include more than one diode-connected NMOS FET. More specifically, the NMOS FET M28 includes a drain coupled to the intermediate node and a gate coupled to the input of the two logic inverter stages 600. The NMOS FET M29 includes a drain coupled to the source of the NMOS FET M28 and a gate coupled to the input of the two logic inverter stages 600. The diode-connected NMOS FET M30 includes a drain and a gate coupled together and coupled to the source of the NMOS FET M29, and a source coupled to the lower voltage rail Vss.

[0084] The second logic inverter 620 can be implemented as the logic inverter 250 discussed in detail previously. Specifically, the second logic inverter 620 includes a group of PMOSFETs M31, M32, and M33 (e.g., three (3), but may be two (2) or four (4) or more) coupled in parallel between the upper voltage rail Vdd and the output of the two logic inverter stages 600. The group of PMOS FETs M31, M32, and M33 includes respective sources coupled to the upper voltage rail Vdd, respective gates coupled to the intermediate nodes, and drains coupled to the outputs.

[0085] The second logic inverter 620 also includes a set of NMOS FETs M34, M35, and M36 (e.g., three (3), but may be two (2) or four (4) or more) coupled in series between the output and the lower voltage rail Vss. More specifically, the NMOS FET M34 includes a drain coupled to the output and a gate coupled to the intermediate node. The NMOS FET M35 includes a drain coupled to the source of the NMOS FET M34 and a gate coupled to the intermediate node. The NMOS FET M36 includes a drain coupled to the source of the NMOS FET M35, a gate coupled to the intermediate node, and a source coupled to the lower voltage rail Vss.

[0086] As previously discussed with respect to logic inverter 400, the voltage swing at the intermediate node of first logic inverter 610 is not a full rail-to-rail swing (e.g., between Vdd and Vss potentials). Instead, the voltage swing at the intermediate node is substantially between Vdd and V T +Vss potential, where V T is the threshold voltage of the diode-connected NMOS FET M30. If the first logic inverter 610 were to be cascaded with other similarly configured logic inverters in a ring oscillator (RO), the non-rail-to-rail swing of the logic inverters might not be sufficient to oscillate the RO. Therefore, the second logic inverter 620 (without the diode-connected NMOS FET) is able to generate a rail-to-rail voltage swing at the output; and therefore, the two logic inverter stages 600 can be cascaded to form a RO that is able to generate and sustain an oscillating or periodic signal.

[0087] Figure 7 A schematic diagram of another example two logic inverter stage 700 of a ring oscillator (RO) according to another aspect of the present disclosure is illustrated. As further discussed herein, the two logic inverter stage 700 can be used in the RO for measuring or evaluating process performance (e.g., skew) of a PFET. Specifically, the two logic inverter stage 700 includes a first logic inverter 710 followed by a second logic inverter 720.

[0088] The first logic inverter 710 may be implemented as the logic inverter 500 discussed in detail previously. That is, the first logic inverter 710 includes a set of PMOS FETs M37, M38, and M39 (e.g., three (3), but may be two (2) or four (4) or more) coupled in series between the upper voltage rail Vdd and the intermediate node (int). The intermediate node may be the output of the first logic inverter 710. The PMOS FET M37 may be diode-connected. It should be understood that the series path between the upper voltage rail Vdd and the intermediate node may include more than one diode-connected PMOS FET. More specifically, the diode-connected PMOS FET M37 includes a source coupled to the upper voltage rail VDD and a gate and drain coupled together. The PMOS FET M38 includes a source coupled to the gate / drain of the diode-connected PMOS FET M37 and a gate coupled to the input of the two logic inverter stages 700. PMOS FET M39 includes a source coupled to the drain of PMOS FET M38, a gate coupled to the input of the two logic inverter stage 700, and a drain coupled to the intermediate node.

[0089] The first logic inverter 710 also includes a group of NMOS FETs M40, M41, and M42 (e.g., three (3), but may be two (2) or four (4) or more) coupled in parallel between the intermediate node and the lower voltage rail Vss (e.g., ground). The group of NMOS FETs M40, M41, and M42 include respective drains coupled to the intermediate node, respective gates coupled to the inputs of the two logic inverter stages 700, and sources coupled to the lower voltage rail Vss.

[0090] The second logic inverter 720 may be implemented as the logic inverter 350 discussed in detail previously. Specifically, the second logic inverter 720 includes a set of PMOSFETs M43, M44, and M45 (e.g., three (3), but may be two (2) or four (4) or more) coupled in series between the upper voltage rail Vdd and the output of the two logic inverter stages 700. More specifically, the PMOSFET M43 includes a source coupled to the upper voltage rail Vdd and a gate coupled to an intermediate node. The PMOS FET M44 includes a source coupled to the drain of the PMOS FET M43 and a gate coupled to the intermediate node. The PMOS FET M45 includes a source coupled to the drain of the PMOS FET M44, a gate coupled to the intermediate node, and a drain coupled to the output of the two logic inverter stages 700.

[0091] The second logic inverter 720 also includes a group of NMOS FETs M46, M47, and M48 (e.g., three (3), but may be two (2) or four (4) or more) coupled in parallel between the output of the two logic inverter stages 700 and the lower voltage rail Vss. The group of NMOS FETs M46, M47, and M48 includes respective drains coupled to the output, respective gates coupled to the intermediate node, and sources coupled to the lower voltage rail Vss.

[0092] As previously discussed with respect to logic inverter 500, the voltage swing at the intermediate node of first logic inverter 710 is not a full rail-to-rail swing (e.g., between Vdd and Vss potentials). Instead, the voltage swing at the intermediate node is substantially between Vdd-V T and Vss potential, where V T is the threshold voltage of the diode-connected PMOS FET M37. If the first logic inverter 710 were to be cascaded with other similarly configured logic inverters in a ring oscillator (RO), the non-rail-to-rail swing of the logic inverters might not be sufficient to oscillate the RO. Therefore, the second logic inverter 720 (without the diode-connected PMOS FET) is able to generate a rail-to-rail voltage swing at the output; and therefore, the two logic inverter stages 700 can be cascaded to form a RO that is able to generate and sustain an oscillating or periodic signal.

[0093] Figure 8 FIG. 8 is a schematic diagram illustrating another example ring oscillator (RO) 800 according to another aspect of the present disclosure. The RO 800 may be configured to generate a signal S N , whose frequency f N Related to the process performance (eg, skew) of the NMOS FETs used in the RO 800 (and other NMOS FETs in an integrated circuit (IC) incorporating the RO 800).

[0094] Specifically, the RO 800 includes a set of cascade stages 810-1 to 810-P, where P is a positive integer. Each of the cascade stages 810-1 to 810-P can be implemented as the two logic inverter stages 600 discussed previously. For example, the first cascade stage 810-1 includes a first logic inverter 812-1A, followed by a second logic inverter 812-1B; the second cascade stage 810-2 includes a first logic inverter 812-2A, followed by a second logic inverter 812-2B; and so on to the Pth cascade stage 810-P, which includes a first logic inverter 812-PA, followed by a second logic inverter 812-PB. Each of the first logic inverters 812-1A, 812-2A to 812-PA can be implemented as the first logic inverter 610 discussed previously. Similarly, each of the second logic inverters 812-1B, 812-2B to 812-PB may be implemented as the second logic inverter 620 discussed previously.

[0095] In the above arrangement, the output of the first logic inverter 812-1A is coupled to the input of the second logic inverter 812-1B of the first cascade stage 810-1; the output of the first cascade stage 810-1 is coupled to the input of the first logic inverter 812-2A of the second cascade stage 810-2; the output of the first logic inverter 812-2A is coupled to the input of the second logic inverter 812-2B of the second cascade stage 810-2; the output of the second cascade stage 810-2 is coupled to the input of the first logic inverter of the third cascade stage (not shown); the input of the first logic inverter 812-PA is coupled to the output of the P-1th cascade stage (not shown); and the output of the first logic inverter 812-PA is coupled to the input of the second logic inverter 812-PB of the Pth cascade stage 810-P.

[0096] The output of the second logic inverter 812-PB of the P-th cascade stage 810-P is coupled to a first input of a selectively enabled inverter 820. The selectively enabled inverter 820 includes an output coupled to an input of the first logic inverter 812-1A of the first cascade stage 810-1. The selectively enabled inverter 820 includes a second input configured to receive an enable signal (en). The selectively enabled inverter 820 may be implemented as a NAND gate, which includes a first input coupled to the output of the second logic inverter 812-PB of the P-th cascade stage 810-P, a second input configured to receive an enable signal (en), and an output coupled to an input of the first logic inverter 812-1A of the first cascade stage 810-1. Alternatively, the selectively enabled inverter 820 may be implemented as a NOR gate comprising a first input coupled to the output of the second logic inverter 812-PB of the Pth cascade stage 810-P, a second input configured to receive an enable signal (en), and an output coupled to the input of the first logic inverter 812-1A of the first cascade stage 810-1.

[0097] When the enable signal (en) is asserted (e.g., a logic one (1) in the case of a NAND-type selectively enabled inverter 820 and a logic zero (0) in the case of a NOR-type selectively enabled inverter 820), the selectively enabled inverter 820 implements an odd number of inversion stages (e.g., 2*P+1) to generate a periodic or oscillating signal S N When the enable signal (en) is de-asserted (e.g., logic zero (0) in the case of a NAND-type selectively enabled inverter 820, and logic one (1) in the case of a NOR-type selectively enabled inverter 820), the selectively enabled inverter 820 outputs a constant logic level (e.g., logic one (1) in the case of a NAND-type inverter 820; and logic zero (0) in the case of a NOR-type inverter 820); thereby disabling the RO 800 from generating the periodic or oscillating signal S N .

[0098] Fig. 9 FIG. 2 is a schematic diagram illustrating another example ring oscillator (RO) 900 according to another aspect of the present disclosure. The RO 900 may be configured to generate a signal S P , whose frequency f P Related to process performance (eg, skew) of the PMOS FET of the RO 900 (and other PMOS FETs in an integrated circuit (IC) incorporating the RO 900).

[0099] Specifically, the RO 900 includes a set of cascade stages 910-1 to 910-P, where P is a positive integer. Each of the cascade stages 910-1 to 910-P can be implemented as the two logic inverter stages 700 discussed previously. For example, the first cascade stage 910-1 includes a first logic inverter 912-1A, followed by a second logic inverter 912-1B; the second cascade stage 910-2 includes a first logic inverter 912-2A, followed by a second logic inverter 912-2B; and so on to the Pth cascade stage 910-P, which includes a first logic inverter 912-PA, followed by a second logic inverter 912-PB. Each of the first logic inverters 912-1A, 912-2A to 912-PA can be implemented as the first logic inverter 710 discussed previously. Similarly, each of the second logic inverters 912-1B, 912-2B to 912-PB may be implemented as the second logic inverter 720 discussed previously.

[0100] In the above arrangement, the output of the first logic inverter 912-1A is coupled to the input of the second logic inverter 912-1B of the first cascade stage 910-1; the output of the first cascade stage 910-1 is coupled to the input of the first logic inverter 912-2A of the second cascade stage 910-2; the output of the first logic inverter 912-2A is coupled to the input of the second logic inverter 912-2B of the second cascade stage 910-2; the output of the second cascade stage 910-2 is coupled to the input of the first logic inverter of the third cascade stage (not shown); the input of the first logic inverter 912-PA is coupled to the output of the P-1th cascade stage (not shown); and the output of the first logic inverter 912-PA is coupled to the input of the second logic inverter 912-PB of the Pth cascade stage 910-P.

[0101] The output of the second logic inverter 912-PB of the P-th cascade stage 910-P is coupled to a first input of a selectively enabled inverter 920. The selectively enabled inverter 920 includes an output coupled to an input of the first logic inverter 912-1A of the first cascade stage 910-1. The selectively enabled inverter 920 includes a second input configured to receive an enable signal (en). The selectively enabled inverter 920 may be implemented as a NAND gate, which includes a first input coupled to the output of the second logic inverter 912-PB of the P-th cascade stage 910-P, a second input configured to receive an enable signal (en), and an output coupled to an input of the first logic inverter 912-1A of the first cascade stage 910-1. Alternatively, the selectively enabled inverter 920 may be implemented as a NOR gate comprising a first input coupled to the output of the second logic inverter 912-PB of the Pth cascade stage 910-P, a second input configured to receive an enable signal (en), and an output coupled to the input of the first logic inverter 912-1A of the first cascade stage 910-1.

[0102] When the enable signal (en) is asserted (e.g., a logic one (1) in the case of a NAND-type selectively enabled inverter 920 and a logic zero (0) in the case of a NOR-type selectively enabled inverter 920), the selectively enabled inverter 920 implements an odd number of inversion stages (e.g., 2*P+1) to generate a periodic or oscillating signal S P When the enable signal (en) is de-asserted (e.g., logic zero (0) in the case of a NAND-type selectively enabled inverter 920, and logic one (1) in the case of a NOR-type selectively enabled inverter 920), the selectively enabled inverter 920 outputs a constant logic level (e.g., logic one (1) in the case of a NAND-type inverter 920; and logic zero (0) in the case of a NOR-type inverter 920); thereby disabling the RO 900 from generating the periodic or oscillating signal S P .

[0103] Fig.10 A bar graph comparing different logic inverters for evaluating n-channel field effect transistor (NFET) process performance according to another aspect of the present disclosure is illustrated. The x-axis or horizontal axis of the bar graph represents different process inflection points SS, FF, SF, and FS, including a reference (e.g., average) process inflection point TT. The y-axis or vertical axis of the bar graph represents a signal S generated by a ring oscillator (RO) for characterizing the process performance of the NFET. N The frequency f N (as a percentage of normalized frequency). The y-axis or vertical axis has a range from zero (0) percent (%) to above 250%. The non-shaded bar represents the signal S generated by the RO 200.N The frequency f N , and the shaded bar represents the signal S generated by RO 800 N The frequency f N .

[0104] With respect to the reference process inflection point TT, RO 200 and 800 each generate a normalized frequency f N For 100% signal S N At the inflection point of the SS process, RO 200 generates a frequency f N The signal S is 79% of the normalized frequency N , while RO 800 generates frequency f N The signal S is 39% of the normalized frequency N At the inflection point of the FF process, RO 200 generates a frequency f N The signal S is 116% of the normalized frequency N , while RO 800 generates frequency f N The signal S is 181% of the normalized frequency N At the inflection point of the SF process, RO 200 generates a frequency f N The signal S is 93% of the normalized frequency N , while RO 800 generates frequency f N The signal S is 64% of the normalized frequency N And, at the inflection point of the FS process, RO 200 generates a frequency f N The signal S is 101% of the normalized frequency N , while RO 800 generates frequency f N The signal S is 132% of the normalized frequency N .

[0105] As previously discussed, RO 200 includes a set of cascaded logic inverters 210-1 to 210-K (e.g., NAND-type logic inverters 250 without diode-connected NMOS FETs). However, RO 800 includes a set of cascaded stages 810-1 to 810-P, which respectively include first logic inverters 812-1A to 812-PA with diode-connected NMOS FETs. Therefore, the bar graph shows that since the difference in the frequency of the process corner points SS, FF, SF, and FS compared to the normalized frequency of the normalized corner point TT is significantly larger for RO 800 (compared to RO 200), the sensitivity to NFET process performance is significantly improved by RO 800 and thus outperforms RO 200.

[0106] Fig.11A bar graph comparing different logic inverters for evaluating a p-channel field effect transistor (PFET) process performance according to another aspect of the present disclosure is illustrated. The x-axis or horizontal axis of the bar graph represents different process inflection points SS, FF, SF, and FS, including a reference (e.g., average) process inflection point TT. The y-axis or vertical axis of the bar graph represents a signal S generated by a ring oscillator (RO) for characterizing the process performance of the PFET. P The frequency f P (as a percentage of normalized frequency). The y-axis or vertical axis has a range from zero (0) percent (%) to 400%. The non-shaded bar represents the signal S generated by the RO 300. P The frequency f P , and the shaded bar represents the signal S generated by RO 900 P The frequency f P .

[0107] With respect to the reference process inflection point TT, RO 300 and 900 each generate a normalized frequency f P For 100% signal S P At the inflection point of the SS process, RO 300 generates a frequency f P The signal S is 75% of the normalized frequency P , while RO 900 generates frequency f P The signal S is 16% of the normalized frequency. P At the inflection point of the FF process, RO 300 generates a frequency f P The signal S is 121% of the normalized frequency P , while RO 900 generates frequency f P The signal S is 337% of the normalized frequency P At the inflection point of the SF process, RO 300 generates a frequency f P The signal S is 107% of the normalized frequency P , while RO 900 generates frequency f P The signal S is 254% of the normalized frequency P And, at the inflection point of the FS process, the RO 300 generates a frequency f P The signal S is the 90% of the normalized frequency P , while RO 900 generates frequency f P The signal S is 32% of the normalized frequency P .

[0108] Similarly, as previously discussed, RO 300 includes a set of cascaded logic inverters 310-1 to 310-K (e.g., NOR-type logic inverters 350 without diode-connected NMOS FETs). However, RO 900 includes a set of cascaded stages 910-1 to 910-P, which respectively include first logic inverters 912-1A to 912-PA with diode-connected PMOS FETs. Therefore, the bar graph shows that since the difference in the frequency of the process corner points SS, FF, SF, and FS compared to the normalized frequency of the reference process corner point TT is significantly larger for RO 900 (compared to RO 300), the sensitivity to PFET process performance is significantly improved by RO 900 over RO 300.

[0109] Fig.12 A schematic diagram of an example reconfigurable logic inverter 1200 according to another aspect of the present disclosure is illustrated. As further discussed herein, the reconfigurable logic inverter 1200 can be used in a ring oscillator (RO) for characterizing process performance of an NFET. For example, the reconfigurable logic inverter 1200 can be used as the first logic inverter 812-1A, 812-2A to 812-PA of the set of cascaded stages 810-1 to 810-P of the RO 800, respectively. In addition, as further discussed herein, the reconfigurable logic inverter 1200 can be reconfigured for applying aging stress conditions or for process performance measurement / monitoring based on a pattern signal.

[0110] Specifically, the reconfigurable logic inverter 1200 is similar to the logic inverter 400. For example, the reconfigurable logic inverter 1200 includes a set of PMOSFETs M49, M50, and M51 (e.g., three (3), but may be two (2) or four (4) or more) coupled in parallel between the upper voltage rail Vdd and the output of the reconfigurable logic inverter 1200. More specifically, the PMOSFETs M49, M50, and M51 include respective sources coupled to the upper voltage rail Vdd, respective gates coupled to the input of the reconfigurable logic inverter 1200, and respective drains coupled to the output of the reconfigurable logic inverter 1200.

[0111] The reconfigurable logic inverter 1200 also includes a set of NMOS FETs M52, M53, and M54 (e.g., three (3), but may be two (2) or four (4) or more) coupled in series between the output of the reconfigurable logic inverter 1200 and a lower voltage rail Vss (e.g., ground). More specifically, the NMOS FET M52 includes a drain coupled to the output of the reconfigurable logic inverter 1200 and a gate coupled to the input of the reconfigurable logic inverter 1200. The NMOS FET M53 includes a drain coupled to the source of the NMOS FET M52 and a gate coupled to the input of the reconfigurable logic inverter 1200.

[0112] As discussed in more detail further herein, in a reconfigurable implementation, if the mode signal indicates an aging stress operating mode, the NMOS FET M54 may not be diode-connected. In such a case, the NMOS FET M54 includes a drain coupled to the source of the NMOS FET M53, a gate coupled to the input of the reconfigurable logic inverter 1200, and a source coupled to the lower voltage rail Vss. If the mode signal indicates a process performance measurement / monitoring operating mode, the NMOS FET M54 may be diode-connected. In such a case, the NMOS FET M54 includes a drain and a gate coupled together and coupled to the source of the NMOS FET M53, and a source coupled to the lower voltage rail Vss.

[0113] In order to realize the non-diode connection and the diode connection of the NMOS FET M54, the reconfigurable logic inverter 1200 further includes a first switch device M55 and a second switch device M56. In this example, the first switch device M55 and the second switch device M56 can be implemented as a transmission gate, but it should be understood that the first switch device M55 and the second switch device M56 can be implemented as other types of switch devices.

[0114] The first switch device M55 includes a first terminal coupled to the input of the reconfigurable logic inverter 1200 and a second terminal coupled to the gate of the NMOS FET M54. The first switch device M55 also includes a gate configured to receive a non-complementary mode signal (mode) and a complementary mode signal (mode), respectively. The second switch device M56 includes a first terminal coupled to the drain of the NMOS FET M54 and a second terminal coupled to the gate of the NMOS FET M54. The second switch device M56 also includes a non-complementary and complementary control input. The second switch device M56 includes a first terminal coupled to the drain of the NMOS FET M54 and a second terminal coupled to the gate of the NMOS FET M54. The second switch device M56 also includes a and non-complementary and complementary control inputs for non-complementary mode signals (MODE).

[0115] For aging stress purposes, it is desirable that the output of the reconfigurable logic inverter 1200 achieve a full rail-to-rail voltage swing so that the aging of the NMOS FETs M52, M53, and M54 is consistent with the aging of other NMOS FETs in or near the IC. For improved NFET process measurement / monitoring sensitivity of the NMOS FETs M52, M53, and M54, it is desirable that the reconfigurable logic inverter 1200 include a diode-connected NMOS FET M54 as previously discussed.

[0116] Thus, if the mode signal indicates an aging stress operating mode (eg, mode=1,

[0117] ), the first switch device M55 is turned on and the second switch device M56 is turned off. The turned-on first switch device M55 couples the input of the reconfigurable logic inverter 1200 to the gate of the NMOS FET M54, so that a full rail-to-rail voltage swing is achieved at the output of the reconfigurable logic inverter 1200. If the mode signal indicates a process measurement / monitoring operation mode (e.g., mode=0,

[0118] ), the first switching device M55 is turned off and the second switching device M56 is turned on. The turned-on second switching device M56 couples the drain and gate of the NMOS FET M54 together to configure the device M54 as a diode-connected NMOSFET for improved NFET process measurement sensitivity.

[0119] Fig.13 A schematic diagram of an example reconfigurable logic inverter 1300 according to another aspect of the present disclosure is illustrated. As further discussed herein, the reconfigurable logic inverter 1300 can be used in a ring oscillator (RO) for characterizing process performance of a PFET. For example, the reconfigurable logic inverter 1300 can be used as the first logic inverters 912-1A, 912-2A to 912-PA of the set of cascaded stages 910-1 to 910-P of the RO 900, respectively. In addition, as further discussed herein, the reconfigurable logic inverter 1300 can be reconfigured for applying aging stress conditions or for process performance measurement / monitoring based on a pattern signal.

[0120] Specifically, the reconfigurable logic inverter 1300 is similar to the logic inverter 500. For example, the reconfigurable logic inverter 1300 includes a set of PMOSFETs M57, M58, and M59 (e.g., three (3), but may be two (2) or four (4) or more) coupled in series between the upper voltage rail Vdd and the output of the reconfigurable logic inverter 1300. In a reconfigurable implementation, if the mode signal indicates an aging stress operating mode, the PMOS FET M57 may not be diode-connected. In such a case, the PMOS FET M57 includes a source coupled to the upper voltage rail Vdd and a gate coupled to the input of the reconfigurable logic inverter 1300. If the mode signal indicates a process performance measurement / monitoring operating mode, the PMOS FET M57 may be diode-connected. In such a case, the PMOS FET M57 includes a source coupled to the upper voltage rail VDD and a gate and a drain coupled together.

[0121] PMOS FET M58 includes a source coupled to the drain (aging stress operation mode) or gate / drain (process measurement / monitoring operation mode) of PMOS FET M57, and a gate coupled to the input of reconfigurable logic inverter 1300. PMOS FET M59 includes a source coupled to the drain of PMOS FET M58, a gate coupled to the input of reconfigurable logic inverter 1300, and a drain coupled to the output of reconfigurable logic inverter 1300.

[0122] The reconfigurable logic inverter 1300 also includes a group of NMOS FETs M60, M61, and M62 (e.g., three (3), but may be two (2) or four (4) or more) coupled in parallel between the output of the reconfigurable logic inverter 1300 and a lower voltage rail Vss (e.g., ground). More specifically, the NMOS FETs M60, M61, and M62 include respective drains coupled to the output of the reconfigurable logic inverter 1300, respective gates coupled to the input of the reconfigurable logic inverter 1300, and respective sources coupled to the lower voltage rail Vss.

[0123] In order to realize the non-diode connection and the diode connection of the PMOS FET M57, the reconfigurable logic inverter 1300 further includes a first switch device M63 and a second switch device M64. In this example, the first switch device M63 and the second switch device M64 can be implemented as a transmission gate, but it should be understood that the first switch device M63 and the second switch device M64 can be implemented as other types of switch devices.

[0124] The first switch device M63 includes a first terminal coupled to the input of the reconfigurable logic inverter 1300 and a second terminal coupled to the gate of the PMOS FET M57. The first switch device M63 also includes a gate configured to receive a non-complementary mode signal (mode) and a complementary mode signal (mode), respectively. The second switch device M64 includes a first terminal coupled to the drain of the PMOS FET M57 and a second terminal coupled to the gate of the PMOS FET M57. The second switch device M64 also includes a non-complementary and complementary control input. The second switch device M64 includes a first terminal coupled to the drain of the PMOS FET M57 and a second terminal coupled to the gate of the PMOS FET M57. and non-complementary and complementary control inputs for non-complementary mode signals (MODE).

[0125] As previously discussed, for aging stress purposes, it is desirable that the output of the reconfigurable logic inverter 1200 achieve a full rail-to-rail voltage swing so that the aging of the PMOS FETs M57, M58, and M59 is consistent with the aging of other PMOS FETs in or near the IC. For improved PFET process measurement / monitoring sensitivity of the PMOS FETs M57, M58, and M59, it is desirable that the reconfigurable logic inverter 1300 include a diode-connected PMOS FET M57 as previously discussed.

[0126] Thus, if the mode signal indicates an aging stress operating mode (eg, mode=1,

[0127] ), the first switch device M63 is turned on and the second switch device M64 is turned off. The turned-on first switch device M63 couples the input of the reconfigurable logic inverter 1300 to the gate of the PMOS FET M57, so that a full rail-to-rail voltage swing is achieved at the output of the reconfigurable logic inverter 1300. If the mode signal indicates a process measurement / monitoring operation mode (e.g., mode=0,

[0128] ), the first switching device M63 is turned off and the second switching device M64 is turned on. The turned-on second switching device M64 couples the gate and drain of the PMOS FET M57 together to configure the device M57 as a diode-connected PMOSFET for improved PFET process measurement / monitoring sensitivity.

[0129] Fig.14 FIG. 2 is a schematic diagram illustrating another example ring oscillator (RO) 1400 according to another aspect of the present disclosure. The RO 1400 may be configured to generate a signal S N , whose frequency f NRelated to process performance (eg, skew) of the NMOS FETs used in the RO 1400 (and other NMOS FETs in an integrated circuit (IC) incorporating the RO 1400).

[0130] Specifically, RO 1400 includes a set of cascade stages 1410-1 to 1410-P, where P is a positive integer. Each of the cascade stages 1410-1 to 1410-P may include a first logic inverter followed by a second logic inverter. For example, the first cascade stage 1410-1 includes a first logic inverter 1412-1A followed by a second logic inverter 1412-1B; the second cascade stage 1410-2 includes a first logic inverter 1412-2A followed by a second logic inverter 1412-2B; and so on to the Pth cascade stage 1410-P, which includes a first logic inverter 1412-PA followed by a second logic inverter 1412-PB. Each of the first logic inverters 1412-1A, 1412-2A to 1412-PA may be implemented as the reconfigurable logic inverter 1200 discussed previously. Therefore, each of the first logic inverters 1412-1A, 1412-2A to 1412-PA is configured to receive a mode signal. As previously discussed, the mode signal may indicate an aging stress mode or a process measurement / monitoring mode. Similarly, each of the second logic inverters 1412-1B, 1412-2B to 1412-PB may be implemented as the previously discussed logic inverter 250.

[0131] In the above arrangement, the output of the first logic inverter 1412-1A is coupled to the input of the second logic inverter 1412-1B of the first cascade stage 1410-1; the output of the first cascade stage 1410-1 is coupled to the input of the first logic inverter 1412-2A of the second cascade stage 1410-2; the output of the first logic inverter 1412-2A is coupled to the input of the second logic inverter 1412-2B of the second cascade stage 1410-2; the output of the second cascade stage 1410-2 is coupled to the input of the first logic inverter of the third cascade stage (not shown); the input of the first logic inverter 1412-PA is coupled to the output of the P-1th cascade stage (not shown); and the output of the first logic inverter 1412-PA is coupled to the input of the second logic inverter 1412-PB of the Pth cascade stage 1410-P.

[0132] The output of the second logic inverter 1412-PB of the P-th cascade stage 1410-P is coupled to a first input of a selectively enabled inverter 1420. The selectively enabled inverter 1420 includes an output coupled to an input of the first logic inverter 1412-1A of the first cascade stage 1410-1. The selectively enabled inverter 1420 includes a second input configured to receive an enable signal (en). The selectively enabled inverter 1420 may be implemented as a NAND gate, which includes a first input coupled to the output of the second logic inverter 1412-PB of the P-th cascade stage 1410-P, a second input configured to receive an enable signal (en), and an output coupled to an input of the first logic inverter 1412-1A of the first cascade stage 1410-1. Alternatively, the selectively enabled inverter 1420 may be implemented as a NOR gate comprising a first input coupled to the output of the second logic inverter 1412-PB of the Pth cascade stage 1410-P, a second input configured to receive an enable signal (en), and an output coupled to the input of the first logic inverter 1412-1A of the first cascade stage 1410-1.

[0133] When the enable signal (en) is asserted (e.g., a logic one (1) in the case of a NAND-type selectively enabled inverter 1420 and a logic zero (0) in the case of a NOR-type selectively enabled inverter 1420), the selectively enabled inverter 1420 implements an odd number of inversion stages (e.g., 2*P+1) to generate a periodic or oscillating signal S N When the enable signal (en) is de-asserted (e.g., logic zero (0) in the case of a NAND-type selectively enabled inverter 1420, and logic one (1) in the case of a NOR-type selectively enabled inverter 1420), the selectively enabled inverter 1420 outputs a constant logic level (e.g., logic one (1) in the case of a NAND-type inverter 1420; and logic zero (0) in the case of a NOR-type inverter 1420); thereby disabling the RO 1400 from generating the periodic or oscillating signal S N .

[0134] Fig.15 FIG. 2 is a schematic diagram illustrating another example ring oscillator (RO) 1500 according to another aspect of the present disclosure. The RO 1500 may be configured to generate a signal S P , whose frequency f P Related to the process performance (eg, skew) of the PMOS FETs used in the RO 1500 (and other PMOS FETs in an integrated circuit (IC) incorporating the RO 1500).

[0135] Specifically, RO 1500 includes a set of cascade stages 1510-1 to 1510-P, where P is a positive integer. Each of the cascade stages 1510-1 to 1510-P may include a first logic inverter followed by a second logic inverter. For example, the first cascade stage 1510-1 includes a first logic inverter 1512-1A followed by a second logic inverter 1512-1B; the second cascade stage 1510-2 includes a first logic inverter 1512-2A followed by a second logic inverter 1512-2B; and so on to the Pth cascade stage 1510-P, which includes a first logic inverter 1512-PA followed by a second logic inverter 1512-PB. Each of the first logic inverters 1512-1A, 1512-2A to 1512-PA may be implemented as the reconfigurable logic inverter 1300 discussed previously. Therefore, each of the first logic inverters 1512-1A, 1512-2A to 1512-PA is configured to receive a mode signal. As previously discussed, the mode signal may indicate an aging stress mode or a process measurement / monitoring mode. Similarly, each of the second logic inverters 1512-1B, 1512-2B to 1512-PB may be implemented as the previously discussed logic inverter 350.

[0136] In the above arrangement, the output of the first logic inverter 1512-1A is coupled to the input of the second logic inverter 1512-1B of the first cascade stage 1510-1; the output of the first cascade stage 1510-1 is coupled to the input of the first logic inverter 1512-2A of the second cascade stage 1510-2; the output of the first logic inverter 1512-2A is coupled to the input of the second logic inverter 1512-2B of the second cascade stage 1510-2; the output of the second cascade stage 1510-2 is coupled to the input of the first logic inverter of the third cascade stage (not shown); the input of the first logic inverter 1512-PA is coupled to the output of the P-1th cascade stage (not shown); and the output of the first logic inverter 1512-PA is coupled to the input of the second logic inverter 1512-PB of the Pth cascade stage 1510-P.

[0137] The output of the second logic inverter 1512-PB of the P-th cascade stage 1510-P is coupled to a first input of a selectively enabled inverter 1520. The selectively enabled inverter 1520 includes an output coupled to an input of the first logic inverter 1512-1A of the first cascade stage 1510-1. The selectively enabled inverter 1520 includes a second input configured to receive an enable signal (en). The selectively enabled inverter 1520 may be implemented as a NAND gate, which includes a first input coupled to the output of the second logic inverter 1512-PB of the P-th cascade stage 1510-P, a second input configured to receive an enable signal (en), and an output coupled to an input of the first logic inverter 1512-1A of the first cascade stage 1510-1. Alternatively, the selectively enabled inverter 1520 may be implemented as a NOR gate comprising a first input coupled to the output of the second logic inverter 1512-PB of the Pth cascade stage 1510-P, a second input configured to receive an enable signal (en), and an output coupled to the input of the first logic inverter 1512-1A of the first cascade stage 1510-1.

[0138] When the enable signal (en) is asserted (e.g., a logic one (1) in the case of a NAND-type selectively enabled inverter 1520 and a logic zero (0) in the case of a NOR-type selectively enabled inverter 1520), the selectively enabled inverter 1520 implements an odd number of inversion stages (e.g., 2*P+1) to generate a periodic or oscillating signal S P When the enable signal (en) is de-asserted (e.g., logic zero (0) in the case of a NAND-type selectively enabled inverter 1520, and logic one (1) in the case of a NOR-type selectively enabled inverter 1520), the selectively enabled inverter 1520 outputs a constant logic level (e.g., logic one (1) in the case of a NAND-type inverter 1520; and logic zero (0) in the case of a NOR-type inverter 1520); thereby disabling the RO 1500 from generating the periodic or oscillating signal S P .

[0139] Fig.16 The signal S generated by a ring oscillator (RO) implemented to evaluate the process aging performance of an n-channel field effect transistor (NFET) is illustrated. N The frequency f N Bar chart comparing the PFET process contribution to the NFET process contribution.

[0140] The left half of the x-axis or horizontal axis of the bar graph represents different process corners SS, FF, SF, and FS, including a reference (e.g., average) process corner TT for RO 200. The right half of the x-axis or horizontal axis of the bar graph represents different process corners SS, FF, SF, and FS, including a reference (e.g., average) process corner TT for RO 1400. The y-axis or vertical axis of the bar graph represents the threshold voltages V for the PMOS FET and NMOS FET in response to the RO being turned on. T The signal S N The frequency f N To achieve normalization (V T In other words, the bar graph shows how many mV of Vmin is degraded by one (1) mV of V in the NMOS / PMOS chain. T The y-axis or vertical axis is measured in millivolts (mV) and ranges from 0 mV to above 2.5 mV.

[0141] Considering RO 200, for the reference process inflection point TT, Vmin is approximately 0.3 mV for PMOS FET and approximately 0.85 mV for NMOSFET; for the process inflection point SS, Vmin is approximately 0.3 mV for PMOS FET and approximately 0.85 mV for NMOS FET; for the process inflection point FF, Vmin is approximately 0.5 mV for PMOS FET and 1.1 mV for NMOS FET; for the process inflection point SF, Vmin is approximately 0.4 mV for PMOS FET and 1.05 mV for NMOS FET; and for the process inflection point FS, Vmin is approximately 0.4 mV for PMOS FET and 1.05 mV for NMOS FET.

[0142] Considering RO 1400, for the reference process inflection point TT, Vmin is approximately 0.2 mV for PMOS FET and approximately 2.2 mV for NMOS FET; for the process inflection point SS, Vmin is approximately 2.25 mV for PMOS FET and approximately 2.1 mV for NMOS FET; for the process inflection point FF, Vmin is approximately 0.25 mV for PMOS FET and 2.4 mV for NMOS FET; for the process inflection point SF, Vmin is approximately 0.1 mV for PMOS FET and 2.35 mV for NMOS FET; and for the process inflection point FS, Vmin is approximately 0.3 mV for PMOS FET and 2.3 mV for NMOS FET.

[0143] Thus, the bar graph shows that by including a diode-connected NMOS in the stage of RO 1400, the sensitivity to the NMOS process performance is significantly improved over the sensitivity to the NMOS process of RO 200. Furthermore, the NBTI / PBTI separation is much higher with the diode-connected FET RO 1400 compared to the all-input-connected gate FET RO 200. For example, from a two-to-one NBTI / PBTI separation with the all-input-connected gate FET RO 200 to a 10-to-one NBTI / PBTI separation for the diode-connected RO 1400.

[0144] Fig.17 1 illustrates a signal S generated by a ring oscillator (RO) implemented to evaluate the process aging performance of a p-channel field effect transistor (PFET) according to another aspect of the present disclosure. P The frequency f P Bar chart comparing the NFET process contribution to the PFET process contribution.

[0145] Similarly, the left half of the x-axis or horizontal axis of the bar graph represents different process corner points SS, FF, SF, and FS, including a reference (e.g., average) process corner point TT for RO 300. The right half of the x-axis or horizontal axis of the bar graph represents different process corner points SS, FF, SF, and FS, including a reference (e.g., average) process corner point TT for RO 1500. The y-axis or vertical axis of the bar graph represents the threshold voltages V for the NMOS FET and the PMOS FET in response to the RO. T The signal S P The frequency f P To achieve normalization (V T In other words, the bar graph shows how many mV of Vmin is degraded by one (1) mV of V in the NMOS / PMOS chain. T The y-axis or vertical axis is measured in millivolts (mV) and ranges from 0 mV to above 2.5 mV.

[0146] Considering RO 300, for the reference process inflection point TT, Vmin is approximately 0.25 mV for NMOS FET and approximately 1.15 mV for PMOS FET; for the process inflection point SS, Vmin is approximately 0.3 mV for NMOS FET and approximately 1.25 mV for PMOS FET; for the process inflection point FF, Vmin is approximately 0.6 mV for NMOS FET and 1.8 mV for PMOS FET; for the process inflection point SF, Vmin is approximately 0.4 mV for NMOS FET and 1.4 mV for PMOS FET; and for the process inflection point FS, Vmin is approximately 0.5 mV for NMOS FET and 1.45 mV for PMOS FET.

[0147] Considering RO 1500, for the reference process inflection point TT, Vmin is approximately 0.1 mV for NMOS FET and approximately 2.25 mV for PMOS FET; for the process inflection point SS, Vmin is approximately 0.1 mV for NMOS FET and approximately 2.13 mV for PMOS FET; for the process inflection point FF, Vmin is approximately 0.15 mV for PMOS FET and 2.4 mV for NMOS FET; for the process inflection point SF, Vmin is approximately 0.1 mV for NMOS FET and 2.4 mV for PMOS FET; and for the process inflection point FS, Vmin is approximately 0.1 mV for NMOS FET and 2.3 mV for PMOS FET.

[0148] Similarly, the bar graph shows that by including a diode-connected PMOS in the stage of RO 1500, the sensitivity to the PMOS process performance is significantly improved over that of RO 300. Furthermore, the NBTI / PBTI separation is much higher with the diode-connected FET RO 1500 as compared to the all-input-connected gate FET RO 300. For example, from a two-to-one NBTI / PBTI separation with the all-input-connected gate FET RO 300 to a 10-to-one NBTI / PBTI separation for the diode-connected RO 1500.

[0149] Fig.18 A block diagram of an example wireless communication device 1800 according to another aspect of the present disclosure is illustrated. The wireless communication device 1800 may be a smartphone, a desktop computer, a laptop computer, a tablet device, the Internet of Things (IoT), a wearable wireless device (e.g., a wireless watch), and other types of wireless devices.

[0150] Specifically, the wireless communication device 1800 includes an integrated circuit (IC) that can be implemented as a system on chip (SOC) 1810. The SOC 1810 includes one or more signal processing cores 1820, a first ring oscillator (RO) 1825, a second RO 1830, and a process evaluation circuit 1835. The first RO 1825 is configured to generate a signal S N , whose frequency f N The first RO 1825 may be implemented in accordance with any of the previously discussed ROs 800 and 1400. Similarly, the second RO 1830 is configured to generate a signal S P , whose frequency f P Related to the process performance (eg, skew) of the PFET implemented in the second RO 1830 and other PFETs in the SOC 1810. The second RO 1830 may be implemented in accordance with either of the ROs 900 and 1500 discussed previously.

[0151] The process evaluation circuit 1835 is configured to receive signals S from the first RO 1825 and the second RO 1830, respectively. N and S P . The process evaluation circuit 1835 may determine a process inflection point (e.g., SS, FF, FS, or SF) of the SOC 1810 and generate a control signal (CS) based on the aforementioned determination. The one or more signal processing cores 1820 may be configured to generate a transmit baseband (BB) signal and process the received baseband (BB) signal based on one or more clock signals (e.g., a periodic signal that drives a sequential circuit). The one or more signal processing cores 1820 receive the control signal (CS) from the process evaluation circuit 1835 and may control various operations based on the control signal (CS), such as adjusting the frequency of one or more clock signals, performing duty cycle distortion (DCD) compensation on one or more clock signals, and / or other operations.

[0152] The wireless communication device 1800 may also include a transceiver 1850 and at least one antenna 1860 (e.g., an antenna array). The transceiver 1850 is coupled to one or more signal processing cores 1820 to receive a transmit BB signal therefrom and provide a receive BB signal thereto. The transceiver 1850 is configured to convert the transmit BB signal into a transmit radio frequency (RF) signal and convert the receive RF signal into a receive BB signal. The transceiver 1850 is coupled to at least one antenna 1860 to provide it with a transmit RF signal for electromagnetic radiation into a wireless medium for wireless transmission, and to receive a receive RF signal electromagnetically picked up from the wireless medium by at least one antenna 1860.

[0153] The following provides an overview of various aspects of the disclosure:

[0154] Aspect 1: An integrated circuit (IC), comprising: a first ring oscillator (RO), the first ring oscillator (RO) comprising a first set of cascade stages, wherein each of the first set of cascade stages comprises a first logic inverter, the first logic inverter comprising: a first set of field effect transistors (FETs), the first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and a first intermediate node, wherein the first set of FETs comprises a set of gates coupled to an input of the first logic inverter; and a second set of FETs, the second set of FETs coupled in series between the first intermediate node and a second voltage rail, wherein the second set of FETs comprises at least a first FET and at least a second FET, the first FET comprising a gate coupled to the input of the first logic inverter, the second FET being diode-connected according to a first operating mode.

[0155] Aspect 2: The IC of aspect 1, wherein the first set of FETs comprises a set of p-channel metal oxide semiconductor field effect transistors (PMOS FETs), and wherein the second set of FETs comprises a set of n-channel metal oxide semiconductor field effect transistors (NMOS FETs).

[0156] Aspect 3: The IC of aspect 2, wherein the set of PMOS FETs comprises: respective sources coupled to the first voltage rail, respective gates coupled to the input of the first logic inverter, and respective drains coupled to the first intermediate node.

[0157] Aspect 4: An IC according to Aspect 2 or 3, wherein: the at least first FET includes a first NMOS FET, the first NMOS FET includes a first drain coupled to the first intermediate node, a first gate coupled to the input of the first logic inverter, and a first source; the at least first FET also includes a second NMOS FET, the second NMOSFET includes a second drain coupled to the first source, a second gate coupled to the input of the first logic inverter; and a second source; and the at least second FET includes a third NMOS FET coupled between the second NMOS FET and the second voltage rail.

[0158] Aspect 5: The IC of aspect 1, wherein the first set of FETs comprises a set of n-channel metal oxide semiconductor field effect transistors (NMOS FETs), and wherein the second set of FETs comprises a set of p-channel metal oxide semiconductor field effect transistors (PMOS FETs).

[0159] Aspect 6: The IC of aspect 5, wherein the set of NMOS FETs comprises: respective sources coupled to the first voltage rail, respective gates coupled to the input of the first logic inverter, and respective drains coupled to the first intermediate node.

[0160] Aspect 7: An IC according to Aspect 5 or 6, wherein: the at least first FET includes a first PMOS FET, the first NMOS FET includes a first drain coupled to the first intermediate node, a first gate coupled to the input of the first logic inverter, and a first source; the at least first FET also includes a second PMOS FET, the second NMOSFET includes a second drain coupled to the first source, a second gate coupled to the input of the first logic inverter; and a second source; and the at least second FET includes a third PMOS FET coupled between the second PMOS FET and the second voltage rail.

[0161] Aspect 8: The IC of any one of aspects 1 to 7, wherein according to the second operating mode, the at least second FET is not diode-connected.

[0162] Aspect 9: According to claim 8, the IC further includes: a first switching device, the first switching device being coupled between the input of the first logic inverter and the gate of the at least second FET, wherein the first switching device responds to a mode signal indicating the first or second operating mode; and a second switching device, the second switching device being coupled between the drain of the at least second FET and the gate of the at least second FET, wherein the second switching device responds to the mode signal; wherein the first switching device is turned off and the second switching device is turned on in response to the mode signal indicating the first operating mode, and wherein the first switching device is turned on and the second switching device is turned off in response to the mode signal indicating the second operating mode.

[0163] Aspect 10: The IC of aspect 9, wherein the first switch device and the second switch device each comprise a transmission gate.

[0164] Aspect 11: The IC of any of Aspects 1 to 10, wherein each of the first set of cascade stages comprises a second logic inverter.

[0165] Aspect 12: An IC according to Aspect 11, wherein the second logic inverter includes: a third group of field effect transistors (FETs), the third group of field effect transistors (FETs) being coupled in parallel between the first voltage rail and the output of the second logic inverter, wherein the third group of FETs includes a group of gates coupled to the first intermediate node; and a fourth group of FETs, the fourth group of FETs being coupled in series between the output and the second voltage rail, wherein the fourth group of FETs includes a group of gates coupled to the first intermediate node.

[0166] Aspect 13: An IC according to Aspect 12, wherein the first group of FETs and the third group of FETs include a group of p-channel metal oxide semiconductor field effect transistors (PMOS FETs), and wherein the second group of FETs and the fourth group of FETs include a group of n-channel metal oxide semiconductor field effect transistors (NMOS FETs).

[0167] Aspect 14: An IC according to Aspect 12, wherein the first group of FETs and the third group of FETs include a group of n-channel metal oxide semiconductor field effect transistors (NMOS FETs), and wherein the second group of FETs and the fourth group of FETs include a group of p-channel metal oxide semiconductor field effect transistors (PMOS FETs).

[0168] Aspect 15: The IC of any of Aspects 1 to 14, wherein the first RO further comprises a selectively enabled inverter coupled between two of the first set of cascade stages.

[0169] Aspect 16: An IC according to Aspect 15, wherein the selectively enabled inverter includes a NAND gate, the NAND gate including a first input coupled to the output of one of the two cascade stages, a second input configured to receive an enable signal, and an output coupled to the input of the other of the two cascade stages.

[0170] Aspect 17: An IC according to Aspect 15, wherein the selectively enabled inverter includes a NOR gate, the NOR gate including a first input coupled to the output of one of the two cascade stages, a second input configured to receive an enable signal, and an output coupled to the input of the other of the two cascade stages.

[0171] Aspect 18: An IC according to any one of Aspects 1 to 17, wherein the IC also includes a second ring oscillator (RO), the second ring oscillator (RO) including a second group of cascade stages, wherein each of the second group of cascade stages includes a second logic inverter, the second logic inverter including: a third group of field effect transistors (FETs), the third group of field effect transistors (FETs) coupled in parallel between the first voltage rail and the second intermediate node, wherein the third group of FETs includes a group of gates coupled to the input of the second logic inverter; and a fourth group of FETs, the fourth group of FETs coupled in series between the second intermediate node and the second voltage rail, wherein the fourth group of FETs includes at least a third FET and at least a fourth FET, the third FET including a gate coupled to the input of the second logic inverter, and the fourth FET being diode-connected according to the first operating mode.

[0172] Aspect 19: An IC according to Aspect 18, wherein the first group of FETs and the fourth group of FETs include a group of p-channel metal oxide semiconductor field effect transistors (PMOS FETs), and wherein the second group of FETs and the third group of FETs include a group of n-channel metal oxide semiconductor field effect transistors (NMOS FETs).

[0173] Aspect 20: The IC of aspect 19, further comprising a process evaluation circuit coupled to the first RO and the second RO.

[0174] Aspect 21: An IC according to Aspect 20, wherein: the first RO is configured to generate a first oscillating signal having a first frequency; the second RO is configured to generate a second oscillating signal cycling at a second frequency; and the process evaluation circuit is configured to determine process inflection points associated with the first group of FETs, the second group of FETs, the third group of FETs, and the fourth group of FETs based on the first frequency and the second frequency.

[0175] Aspect 22: An IC according to Aspect 20 or 21, wherein: the first RO is configured to generate a first oscillating signal having a first frequency; the second RO is configured to generate a second oscillating signal cycling at a second frequency; and the process evaluation circuit is configured to perform one or more operations based on the first frequency and the second frequency.

[0176] Aspect 23: A logic inverter, comprising: a first group of field effect transistors (FETs), the first group of field effect transistors (FETs) being coupled in parallel between a first voltage rail and an output, wherein the first group of FETs comprises a group of gates respectively coupled to inputs; and a second group of FETs, the second group of FETs being coupled in series between the output and a second voltage rail, wherein the second group of FETs comprises at least a first FET and at least a second FET, the first FET comprising a gate coupled to the input, and the second FET being diode-connected according to a first operating mode.

[0177] Aspect 24: The logic inverter of aspect 23, wherein the first set of FETs comprises a set of p-channel metal oxide semiconductor field effect transistors (PMOS FETs), and wherein the second set of FETs comprises a set of n-channel metal oxide semiconductor field effect transistors (NMOS FETs).

[0178] Aspect 25: The logic inverter of aspect 23, wherein the first set of FETs comprises a set of n-channel metal oxide semiconductor field effect transistors (NMOS FETs), and wherein the second set of FETs comprises a set of p-channel metal oxide semiconductor field effect transistors (PMOS FETs).

[0179] Aspect 26: The logic inverter of any one of aspects 23 to 25, wherein according to the second operating mode, the at least second FET is not diode-connected.

[0180] Aspect 27: According to the logic inverter of Aspect 26, the logic inverter also includes: a first switching device, the first switching device is coupled between the input of the first logic inverter and the gate of the at least second FET, wherein the first switching device responds to a mode signal indicating the first or second operating mode; and a second switching device, the second switching device is coupled between the drain of the at least second FET and the gate of the at least second FET, wherein the second switching device responds to the mode signal; wherein the first switching device is turned off and the second switching device is turned on in response to the mode signal indicating the first operating mode, and wherein the first switching device is turned on and the second switching device is turned off in response to the mode signal indicating the second operating mode.

[0181] Aspect 28: A wireless communication device, the wireless communication device comprising: at least one antenna; a transceiver, the transceiver coupled to the at least one antenna; one or more signal processing cores, the one or more signal processing cores coupled to the transceiver; and a ring oscillator (RO), the ring oscillator (RO) coupled to the one or more signal processing cores, wherein the RO comprises a set of cascade stages, wherein each of the set of cascade stages comprises a first logic inverter, the first logic inverter comprising: a first set of field effect transistors (FETs), the first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and a first intermediate node, wherein the first set of FETs comprises a set of gates coupled to an input of the first logic inverter; and a second set of FETs, the second set of FETs coupled in series between the first intermediate node and a second voltage rail, wherein the second set of FETs comprises at least a first FET and at least a second FET, the first FET comprising a gate coupled to the input of the first logic inverter, the second FET being diode-connected according to a first operating mode.

[0182] Aspect 29: The wireless communication device of aspect 28, wherein the first set of FETs comprises a set of p-channel metal oxide semiconductor field effect transistors (PMOS FETs), and wherein the second set of FETs comprises a set of n-channel metal oxide semiconductor field effect transistors (NMOS FETs).

[0183] Aspect 30: The wireless communication device of aspect 28, wherein the first set of FETs comprises a set of n-channel metal oxide semiconductor field effect transistors (NMOS FETs), and wherein the second set of FETs comprises a set of p-channel metal oxide semiconductor field effect transistors (PMOS FETs).

[0184] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit (IC), comprising: a first ring oscillator (RO), the first ring oscillator (RO) comprising a first set of cascaded stages, wherein each of the first set of cascaded stages comprises a first logic inverter, the first logic inverter comprising: a first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and a first intermediate node, wherein the first set of FETs includes a set of gates coupled to an input of the first logic inverter; and A second set of FETs, the second set of FETs are coupled in series between the first intermediate node and a second voltage rail, wherein the second set of FETs includes at least a first FET and at least a second FET, the at least first FET including a gate coupled to the input of the first logic inverter, and the at least second FET is diode-connected according to a first operating mode.

2. The IC of claim 1 , wherein the first set of FETs comprises a set of p-channel metal oxide semiconductor field effect transistors (PMOS FETs), and wherein the second set of FETs comprises a set of n-channel metal oxide semiconductor field effect transistors (NMOSFETs).

3. The IC of claim 2, wherein the set of PMOS FETs comprises: A respective source coupled to the first voltage rail, a respective gate coupled to the input of the first logic inverter, and a respective drain coupled to the first intermediate node.

4. The IC of claim 2, wherein: The at least first FET comprises a first NMOS FET comprising a first drain coupled to the first intermediate node, a first gate coupled to the input of the first logic inverter, and a first source; The at least first FET also includes a second NMOS FET including a second drain coupled to the first source, a second gate coupled to the input of the first logic inverter, and a second source; and The at least second FET includes a third NMOSFET coupled between the second NMOS FET and the second voltage rail.

5. The IC of claim 1 , wherein the first set of FETs comprises a set of n-channel metal oxide semiconductor field effect transistors (NMOS FETs), and wherein the second set of FETs comprises a set of p-channel metal oxide semiconductor field effect transistors (PMOSFETs).

6. The IC of claim 5, wherein the set of NMOS FETs comprises: A respective source coupled to the first voltage rail, a respective gate coupled to the input of the first logic inverter, and a respective drain coupled to the first intermediate node.

7. The IC of claim 5, wherein: The at least first FET comprises a first PMOS FET, the first NMOS FET comprising a first drain coupled to the first intermediate node, a first gate coupled to the input of the first logic inverter, and a first source; The at least first FET further includes a second PMOS FET, the second NMOSFET including a second drain coupled to the first source, a second gate coupled to the input of the first logic inverter, and a second source; and The at least second FET includes a third PMOSFET coupled between the second PMOS FET and the second voltage rail.

8. The IC of claim 1, wherein according to a second operating mode, the at least second FET is not diode-connected.

9. The IC of claim 8, further comprising: a first switching device coupled between the input of the first logic inverter and the gate of the at least second FET, wherein the first switching device is responsive to a mode signal indicating the first or second operating mode; and a second switching device coupled between a drain of the at least a second FET and the gate of the at least a second FET, wherein the second switching device is responsive to the mode signal; wherein the first switching device is turned off and the second switching device is turned on in response to the mode signal indicating the first operating mode, and wherein the first switching device is turned on and the second switching device is turned off in response to the mode signal indicating the second operating mode.

10. The IC of claim 9, wherein the first switching device and the second switching device each comprise a transmission gate.

11. The IC of claim 1 , wherein each of the first set of cascade stages comprises a second logic inverter.

12. The IC of claim 11 , wherein the second logic inverter comprises: a third set of field effect transistors (FETs) coupled in parallel between the first voltage rail and the output of the second logic inverter, wherein the third set of FETs includes a set of gates coupled to the first intermediate node; and A fourth set of FETs is coupled in series between the output and the second voltage rail, wherein the fourth set of FETs includes a set of gates coupled to the first intermediate node.

13. The IC of claim 12, wherein the first group of FETs and the third group of FETs comprise a group of p-channel metal oxide semiconductor field effect transistors (PMOS FETs), and wherein the second group of FETs and the fourth group of FETs comprise a group of n-channel metal oxide semiconductor field effect transistors (NMOS FETs).

14. The IC of claim 12, wherein the first group of FETs and the third group of FETs comprise a group of n-channel metal oxide semiconductor field effect transistors (NMOSFETs), and wherein the second group of FETs and the fourth group of FETs comprise a group of p-channel metal oxide semiconductor field effect transistors (PMOS FETs).

15. The IC of claim 1, wherein the first RO further comprises a selectively enabled inverter coupled between two of the first set of cascade stages.

16. The IC of claim 15, wherein the selectively enabled inverter comprises a NAND gate comprising a first input coupled to an output of one of the two cascade stages, a second input configured to receive an enable signal, and an output coupled to an input of the other of the two cascade stages.

17. The IC of claim 15, wherein the selectively enabled inverter comprises a NOR gate comprising a first input coupled to an output of one of the two cascade stages, a second input configured to receive an enable signal, and an output coupled to an input of the other of the two cascade stages.

18. The IC of claim 1 , further comprising a second ring oscillator (RO), the second ring oscillator (RO) comprising a second set of cascaded stages, wherein each of the second set of cascaded stages comprises a second logic inverter, the second logic inverter comprising: a third set of field effect transistors (FETs) coupled in parallel between the first voltage rail and a second intermediate node, wherein the third set of FETs includes a set of gates coupled to an input of the second logic inverter; and a fourth group of FETs coupled in series between the second intermediate node and the second voltage rail, wherein the fourth group of FETs includes at least a third FET and at least a fourth FET, the at least third FET including a gate coupled to the input of the second logic inverter, the at least fourth FET being diode-connected according to the first operating mode.

19. The IC of claim 18, wherein the first group of FETs and the fourth group of FETs comprise a group of p-channel metal oxide semiconductor field effect transistors (PMOS FETs), and wherein the second group of FETs and the third group of FETs comprise a group of n-channel metal oxide semiconductor field effect transistors (NMOS FETs).

20. The IC of claim 19, further comprising a process evaluation circuit coupled to the first RO and the second RO.

21. The IC of claim 20, wherein: The first RO is configured to generate a first oscillating signal having a first frequency; The second RO is configured to generate a second oscillating signal that cycles at a second frequency; and The process evaluation circuit is configured to determine process inflection points associated with the first group of FETs, the second group of FETs, the third group of FETs, and the fourth group of FETs based on the first frequency and the second frequency.

22. The IC of claim 20, wherein: The first RO is configured to generate a first oscillating signal having a first frequency; The second RO is configured to generate a second oscillating signal that cycles at a second frequency; and The process evaluation circuit is configured to perform one or more operations based on the first frequency and the second frequency.

23. A logic inverter, comprising: a first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and an output, wherein the first set of FETs includes a set of gates respectively coupled to the inputs; and A second set of FETs are coupled in series between the output and a second voltage rail, wherein the second set of FETs includes at least a first FET and at least a second FET, the at least first FET including a gate coupled to the input, the at least second FET being diode-connected according to a first operating mode.

24. The logic inverter of claim 23, wherein the first set of FETs comprises a set of p-channel metal oxide semiconductor field effect transistors (PMOS FETs), and wherein the second set of FETs comprises a set of n-channel metal oxide semiconductor field effect transistors (NMOS FETs).

25. The logic inverter of claim 23, wherein the first set of FETs comprises a set of n-channel metal oxide semiconductor field effect transistors (NMOS FETs), and wherein the second set of FETs comprises a set of p-channel metal oxide semiconductor field effect transistors (PMOS FETs).

26. The logic inverter of claim 23, wherein according to a second mode of operation, the at least second FET is not diode-connected.

27. The logic inverter according to claim 26, further comprising: a first switching device coupled between the input of the first logic inverter and the gate of the at least second FET, wherein the first switching device is responsive to a mode signal indicating the first or second operating mode; and a second switching device coupled between a drain of the at least a second FET and the gate of the at least a second FET, wherein the second switching device is responsive to the mode signal; wherein the first switching device is turned off and the second switching device is turned on in response to the mode signal indicating the first operating mode, and wherein the first switching device is turned on and the second switching device is turned off in response to the mode signal indicating the second operating mode.

28. A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver; and a ring oscillator (RO) coupled to the one or more signal processing cores, wherein the RO comprises a set of cascaded stages, wherein each of the set of cascaded stages comprises a first logic inverter, the first logic inverter comprising: a first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and a first intermediate node, wherein the first set of FETs includes a set of gates coupled to an input of the first logic inverter; and A second set of FETs, the second set of FETs are coupled in series between the first intermediate node and a second voltage rail, wherein the second set of FETs includes at least a first FET and at least a second FET, the at least first FET including a gate coupled to the input of the first logic inverter, and the at least second FET is diode-connected according to a first operating mode.

29. The wireless communication device of claim 28, wherein the first set of FETs comprises a set of p-channel metal oxide semiconductor field effect transistors (PMOS FETs), and wherein the second set of FETs comprises a set of n-channel metal oxide semiconductor field effect transistors (NMOS FETs).

30. The wireless communication device of claim 28, wherein the first set of FETs comprises a set of n-channel metal oxide semiconductor field effect transistors (NMOS FETs), and wherein the second set of FETs comprises a set of p-channel metal oxide semiconductor field effect transistors (PMOS FETs).

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