Receiver for high density and low latency chip-to-chip links

Abstract

A system includes a receiver. The receiver includes: an input stage having an input and an output; and a first resistor coupled between the output of the input stage and the input of the input stage. The receiver also includes an output stage having an input and an output, where the input of the output stage is coupled to the output of the input stage; and a feedback path coupled between the output of the output stage and the input of the input stage, the feedback path including a second resistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional patent application serial number 17 / 951,790 filed in the United States Patent and Trademark Office on September 23, 2022. Technical Field

[0003] Aspects of the present disclosure relate generally to receivers, and more particularly to receivers for chip-to-chip links. Background Art

[0004] Multiple chips (i.e., dies) can be packaged together in a multi-chip package or multi-chip module. For example, a first chip and a second chip can be packaged together with a link between the chips to facilitate chip-to-chip communication between the chips. In this example, each of the chips can include one or more drivers for transmitting signals to another chip via one or more links, and each of the chips can include one or more receivers for receiving signals from another chip via one or more links. Summary of the Invention

[0005] The following is a simplified overview of one or more implementations to provide a basic understanding of these implementations. This summary is not an extensive overview of all contemplated implementations and is neither intended to identify key or important elements of all implementations nor to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0006] A first aspect relates to a system. The system includes a receiver, wherein the receiver comprises an input stage having an input and an output; and a first resistor coupled between the output of the input stage and an input of the input stage. The receiver also comprises an output stage having an input and an output, wherein the input of the output stage is coupled to the output of the input stage; and a feedback path coupled between the output of the output stage and the input of the input stage, the feedback path comprising a second resistor.

[0007] A second aspect relates to a system. The system includes a first chip, wherein the first chip includes: a driver having an input and an output; and a first pad coupled to the output of the driver. The system also includes a second chip, wherein the second chip includes a second pad and a receiver, the receiver having an input and an output, wherein the input of the receiver is coupled to the second pad. The receiver includes: an input stage having an input and an output; a first resistor coupled between the output of the input stage and the input of the input stage; an output stage having an input and an output, wherein the input of the output stage is coupled to the output of the input stage; and a feedback path coupled between the output of the output stage and the input of the input stage, the feedback path including a second resistor. The system also includes a link coupled between the first pad and the second pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Shown are examples of multiple chips according to certain aspects of the present disclosure.

[0009] Figure 2 Examples of drivers, receivers, and links between the drivers and receivers are shown, in accordance with certain aspects of the present disclosure.

[0010] Figure 3 An example of a receiver according to certain aspects of the present disclosure is shown.

[0011] Figure 4 An example of a receiver including a feedback path in accordance with certain aspects of the present disclosure is shown.

[0012] Figure 5 is a voltage-time graph illustrating an example of voltage at the input of an input stage of a receiver varying over time, in accordance with certain aspects of the present disclosure.

[0013] Figure 6 An example of a feedback resistor with programmable resistance according to certain aspects of the present disclosure is shown.

[0014] Figure 7 An example of a termination circuit according to certain aspects of the present disclosure is shown.

[0015] Figure 8 An example of a power supply noise filter according to certain aspects of the present disclosure is shown.

[0016] Figure 9 An example of a receiver including an intermediate stage in accordance with certain aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0017] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, to avoid obscuring these concepts, well-known structures and components are shown in block diagram form.

[0018] Multiple chips (i.e., dies) can be packaged together in a multi-chip package or multi-chip module. Figure 1 An example of a first chip 110 and a second chip 120 packaged together is shown. The first chip 110 and the second chip 120 may be mounted on a common substrate 125 (eg, a printed circuit board, a ceramic substrate, etc.). Figure 1 Also shown are a plurality of links 130 coupled between first chip 110 and second chip 120 to facilitate chip-to-chip (i.e., die-to-die) communication between chip 110 and chip 120. Links 130 may include metal traces on substrate 125 and / or metal traces embedded in substrate 125. In this example, each of chip 110 and chip 120 may include one or more drivers for transmitting signals to the other of chip 110 and chip 120 via one or more links 130, and each of chip 110 and chip 120 may include one or more receivers for receiving signals from the other of chip 110 and chip 120 via one or more links 130.

[0019] Figure 2 Shown by Figure 1 1 . An example of chip-to-chip communication for one link 230 of multiple links 130 is shown in FIG. In this example, first chip 110 includes a driver 210 (i.e., a transmitter); a first processing circuit 218 coupled to an input 212 of driver 210; and a first pad 216 coupled to an output 214 of driver 210. Second chip 120 includes a receiver 220; a second processing circuit 228 coupled to an output 224 of receiver 220; and a second pad 226 coupled to an input 222 of receiver 220. One end of link 230 is coupled to first pad 216, and the other end of link 230 is coupled to second pad 226.

[0020] In operation, the first processing circuit 218 receives data (e.g., bits), generates a data signal carrying the data, and outputs the data signal to the input 212 of the driver 210. The driver 210 receives the data signal and transmits the data signal to the receiver 220 on the second chip 120 via the link 230. The receiver 220 receives the data signal at the input 222 of the receiver 220, amplifies the received data signal, and outputs the amplified signal to the second processing circuit 228.

[0021] In some implementations, the first processing circuit 218 and the second processing circuit 228 may support a serializer / deserializer (SerDes). In this example, the first processing circuit 218 is configured to receive data in parallel data streams and serialize the data streams into data signals, and the second processing circuit 228 is configured to receive the data signals from the receiver 220 and deserialize the data signals into parallel data streams. However, it should be understood that the present disclosure is not limited to SerDes. It should be understood that the first processing circuit 218 and the second processing circuit 228 may perform encoding / decoding and / or one or more other functions.

[0022] It should be understood that driver 210 , link 230 , and receiver 220 are not limited to data signals and may be used to transmit clock signals or other types of signals between chip 110 and chip 120 .

[0023] Figure 3 1 shows an exemplary implementation of receiver 220. In this example, receiver 220 includes an input stage 310, an output stage 340 (also referred to as an output buffer), an alternating current (AC) coupling capacitor 335, and a feedback resistor 330. AC coupling capacitor 335 is coupled between input 222 of receiver 220 and input 312 of input stage 310. AC coupling capacitor 335 is configured to AC-couple a data signal from link 230 to input 312 of input stage 310. AC coupling capacitor 335 may also be referred to simply as a coupling capacitor.

[0024] The input 342 of the output stage 340 is coupled to the output 314 of the input stage 310, and the output 344 of the output stage 340 is coupled to the output 224 of the receiver 220. It should be understood that the receiver 220 may also include one or more intermediate stages ( Figure 3 (not shown in the figure), the one or more intermediate stages are coupled between the output 314 of the input stage 310 and the input 342 of the output stage 340. Furthermore, in this example, the output stage 340 is inverting and can be implemented using one or more inverting circuits. However, it should be understood that the present disclosure is not limited to this example.

[0025] exist Figure 3In the example shown in , the input stage 310 is implemented by a complementary inverting circuit including a first transistor 320 and a second transistor 325. The source of the first transistor 320 is coupled to the power supply rail 350, the drain of the first transistor 320 is coupled to the output 314 of the input stage 310, and the gate of the first transistor 320 is coupled to the input 312 of the input stage 310. The source of the second transistor 325 is coupled to the lower rail 355, the drain of the second transistor 325 is coupled to the output 314 of the input stage 310, and the gate of the second transistor 325 is coupled to the input 312 of the input stage 310. The power supply rail 350 provides a power supply voltage Vdd, and the lower rail 355 is at a potential Vss that is lower than the power supply voltage Vdd (for example, the lower rail 355 can be coupled to ground). The power supply rail 350 can also be referred to as a first rail, and the lower rail can also be referred to as a second rail. In Figure 3 In the example shown in FIG, the first transistor 320 is implemented with a p-type field effect transistor (PFET), and the second transistor 325 is implemented with an n-type field effect transistor (NFET). However, it should be understood that the present disclosure is not limited to this example.

[0026] Feedback resistor 330 is coupled between input 312 and output 314 of input stage 310. In this example, input stage 310 is self-biased via feedback resistor 330. For example, input 312 of input stage 310 can be biased to a bias voltage approximately equal to half the supply voltage Vdd of supply rail 350 via feedback resistor 330. Note that AC coupling capacitor 335 blocks the bias voltage at input 312 from input 222 of receiver 220.

[0027] In operation, the input 222 of the receiver 220 is connected to the link 230 (eg Figure 3 2 (shown in FIG), receives the data signal, amplifies the data signal, and outputs the amplified data signal at output 224 of receiver 220. To reduce power on link 230, driver 210 can transmit the data signal with a low voltage swing (e.g., a 0.2V voltage swing). In this example, AC coupling capacitor 335 couples the data signal to input 312 of input stage 310. In one example, receiver 220 can amplify the data signal to a rail-to-rail output signal (e.g., an output signal having a voltage swing approximately equal to supply voltage Vdd) at output 224 of receiver 220.

[0028] The AC coupling capacitor 335 AC couples the data signal to the input 312 of the input stage 310 (e.g., an inverting circuit), where the data signal shifts the voltage at the input 312 of the input stage 310 according to the bit value represented by the data signal. For example, for an example where the data signal has a low voltage swing of 0.2V, the data signal can shift the voltage at the input 312 of the input stage 310 to Vmid+0.1V for a bit value of 1, and to Vmid−0.1V for a bit value of 0, where Vmid is a bias voltage approximately equal to half the supply voltage Vdd. As discussed above, the feedback resistor 330 can self-bias the input 312 of the input stage 310 to Vmid. In this example, because the input stage 310 is implemented with an inverting circuit in this example, the voltage Vmid+0.1V drives the output 314 of the input stage 310 low, and the voltage Vmid−0.1V drives the output 314 of the input stage 310 high.

[0029] Figure 3 The challenge with the receiver 220 shown in FIG is that after a bit of the data signal shifts the voltage at the input 312 of the input stage 310 to Vmid+0.1V or Vmid−0.1V, depending on the value of the bit, the input 312 of the input stage 310 may settle back to Vmid before the next bit transition. Settling back to Vmid can allow noise to trigger the output 314 of the input stage 310, causing the output 314 of the input stage 310 to enter an unknown state. The unknown state at the output 314 of the input stage 310 causes the output 224 of the receiver 220 to also enter an unknown state, because the output state of the receiver 220 depends on the output 314 of the input stage 310.

[0030] The settling time at the input 312 of the input stage 310 depends on the resistance-capacitance (RC) time constant of the AC coupling capacitor 335 and the feedback resistor 330 (i.e., the RC time constant of the circuit formed by the AC coupling capacitor 335 and the feedback resistor 330). To prevent the output 224 of the receiver 220 from entering an unknown state before the next bit transition, the settling time can be increased by making the RC time constant relatively large (e.g., several unit intervals, where a unit interval is the interval of one bit of the data signal). A long settling time prevents the input 312 of the input stage 310 from settling to Vmid before the next bit transition. For example, by making the capacitance of the AC coupling capacitor 335 larger, the RC time constant can be made larger, which increases the area of ​​the AC coupling capacitor 335.

[0031] Although a large RC time constant prevents the output 224 of the receiver 220 from entering an unknown state, the large RC time constant allows a relatively long stream of consecutive 1s or consecutive 0s in the data signal to cause the characteristics of the input stage 310 to change, resulting in an inter-symbol interference (ISI) problem, in which the previous bit affects the current bit at the output 314. To mitigate ISI caused by a long stream of consecutive 1s or consecutive 0s, the first processing circuit 218 may include an encoder that encodes the data signal to balance the density of 1s and 0s, which limits the duration of consecutive 1s and 0s in the data signal. However, encoding consumes additional power and increases delay. A large RC time constant can also make the input stage 310 more sensitive to power supply noise.

[0032] To solve Figure 3 To address the challenges of receiver implementation shown in FIG, aspects of the present disclosure provide a receiver with a small RC time constant and a built-in latch or hysteresis to hold the receiver's output state until the next bit transition at the receiver's input. As discussed further below, the small RC time constant can mitigate ISI and power supply noise, while the built-in latch or hysteresis can prevent the small RC time constant from causing the receiver's output to enter an unknown state.

[0033] Figure 4 An example of a receiver 220 according to aspects of the present disclosure is shown. In this example, the RC time constant of the AC coupling capacitor 335 and the feedback resistor 330 (i.e., the RC time constant of the circuit formed by the AC coupling capacitor 335 and the feedback resistor 330) is relatively small to mitigate ISI. In some aspects, the RC time constant can be as small as or less than one unit interval (UI), where the UI is the interval of one bit of the data signal. The small RC time constant reduces the settling time of the voltage at the input 312 of the input stage 310 (i.e., causes the voltage to settle faster). Because the voltage at the input in this example is stable within one UI, the output 224 of the receiver 220 is not affected by the previous bit pattern of the data signal, which significantly reduces ISI without the need for DC balancing or encoding the data signal to balance the density of 1s and 0s. In contrast, in Figure 3 In the implementation shown, the RC time constant is made large (eg, several UI) to increase the settling time of the voltage at the input 312 of the input stage 310 .

[0034] and Figure 3 The small RC time constant also allows the area of ​​the AC coupling capacitor 335 to be significantly reduced compared to the area of ​​the AC coupling capacitor 335 in FIG. 2. In addition, the small RC time constant helps suppress lower frequency device and power supply noise.

[0035] However, as discussed above, a small RC time constant may cause the output 224 of the receiver 220 to enter an unknown state between bit transitions due to the fast settling time of the voltage at the input 312 of the input stage 310. To prevent the small RC time constant from causing the output 224 of the receiver 220 to enter an unknown state, the receiver 220 in this example includes a feedback path 410 between the output 344 of the output stage 340 and the input 312 of the input stage 310. The feedback path 410 provides a built-in latch or hysteresis that holds the output state of the receiver 220 until the next bit transition at the input 222 of the receiver 220. Figure 4 In the example of FIG, the feedback path 410 includes the second feedback resistor 420. However, the feedback path 410 is not limited to this example. In the following discussion, the feedback resistor 330 is referred to as the first feedback resistor 330.

[0036] The built-in latch or hysteresis provided by the feedback path 410 can be used Figure 5 The example in this section explains this. Figure 5 is a voltage-time graph illustrating an example of the voltage at input 312 of input stage 310 varying over time. In this example, a zero bit in the data signal causes the voltage at input 312 to shift downward by 510, which drives output 314 of input stage 310 high. This produces a zero (e.g., a voltage corresponding to ground potential) at output 224 of receiver 220 because output stage 340 is inverting in this example. After the downward shift, the voltage at input 312 quickly settles due to the small RC time constant in this example. However, due to feedback path 410, the voltage at input 312 of input stage 310 does not settle to Vmid, but rather to a voltage 515 below Vmid (indicated by the dashed line). Voltage 515 causes output 224 of receiver 220 to remain at zero until the next bit transition in the data signal. For example, voltage 515 can be lower than Vmid by an amount sufficient to prevent noise at input 312 from triggering output 224 of receiver 220. Without the feedback path 410 , the voltage at the input 312 of the input stage 310 would quickly settle to Vmid, which could cause the output 224 of the receiver 220 to enter an unknown state before the next bit transition.

[0037] exist Figure 5In the example shown in FIG, a bit of the data signal causes the voltage at the input 312 of the input stage 310 to shift upward 520, which drives the output 314 of the input stage 310 low. This produces a unity (e.g., Vdd) at the output 224 of the receiver 220 because the output stage 340 is inverting in this example. After the upward shift, due to the feedback path 410, the voltage quickly settles to a voltage 525 that is higher than Vmid (indicated by the dashed line). The voltage 525 causes the output 224 of the receiver 220 to remain at unity until the next bit transition of the data signal. For example, the voltage 525 can be a sufficiently large amount higher than Vmid to prevent noise at the input 312 from triggering the output 224 of the receiver 220. Without the feedback path 410, the voltage at the input 312 of the input stage 310 would quickly settle to Vmid, which could cause the output of the receiver 220 to enter an unknown state before the next bit transition.

[0038] Thus, in this example, for a zero bit of the data signal, the feedback path 410 causes the voltage at the input 312 of the input stage 310 to settle to a voltage 515 below Vmid to maintain the output 224 of the receiver 220 at zero until the next bit transition of the data signal (i.e., a transition from zero to one). For a one bit of the data signal, the feedback path 410 causes the voltage at the input 312 of the input stage 310 to settle to a voltage 525 above Vmid to maintain the output 224 of the receiver 220 at one until the next bit transition of the data signal (i.e., a transition from one to zero).

[0039] Voltage 515 and voltage 525 depend on the ratio of the resistance of first feedback resistor 330 to the resistance of second feedback resistor 420. More specifically, the amount by which voltage 515 is below Vmid increases by making the ratio larger, and decreases by making the ratio smaller. Similarly, the amount by which voltage 525 is above Vmid increases by making the ratio larger, and decreases by making the ratio smaller. Therefore, by appropriately setting the ratio of the resistance of first feedback resistor 330 to the resistance of second feedback resistor 420, voltage 515 and voltage 525 can be set to desired voltages.

[0040] For example, voltage 515 can be set to a voltage lower than Vmid by an amount that is large enough to maintain zero at output 224 of receiver 220 until the next bit transition of the data signal, while not being so large that voltage 515 prevents the next bit transition of the data signal from changing the logic state at output 314 of input stage 310. In one example, this can be achieved by having the ratio of the resistance of first feedback resistor 330 to the resistance of second feedback resistor 420 be between 0.1 and 0.3. However, it should be understood that the present disclosure is not limited to this example.

[0041] Furthermore, voltage 525 can be set to a voltage higher than Vmid by an amount that is large enough to maintain unity at output 224 of receiver 220 until the next bit transition of the data signal, while not being so large that voltage 515 prevents the next bit transition of the data signal from changing the logic state at output 314 of input stage 310. In one example, this can be achieved by having a ratio of the resistance of first feedback resistor 330 to the resistance of second feedback resistor 420 between 0.1 and 0.3. However, it should be understood that the present disclosure is not limited to this example.

[0042] As discussed above, the RC time constant of the first feedback resistor 330 and the coupling capacitor 335 (i.e., the RC time constant of the circuit formed by the first feedback resistor 330 and the coupling capacitor 335) can be less than or equal to one unit interval (UI), where the UI is the interval of one bit of the data signal. In some aspects, the RC time constant can be equal to or less than one UI of the data signal. The UI can also be expressed as 1 / f, where f is the frequency of the data signal, or as 1 / r, where r is the data rate of the data signal. In some aspects, the first processing circuit 218 on the first chip 110 is configured to generate data signals at the above-mentioned frequencies or data rates. In some aspects, the first processing circuit 218 supports multiple frequencies or data rates. In these aspects, the UI discussed above can refer to the UI of the highest one of the multiple frequencies or data rates.

[0043] In certain aspects, one or both of the feedback resistors 330 and 420 are programmable. In this aspect, Figure 6 An example is shown in which the first feedback resistor 330 has a programmable resistance and the second feedback resistor 420 has a programmable resistance. However, it should be understood that the present disclosure is not limited to this example, and in another example, only one of the feedback resistors 330 and 420 may be programmable. In this example, each of the feedback resistors 330 and 420 may be implemented with a network of resistors and switches (e.g., digitally controlled switches) or another type of programmable resistor.

[0044] exist Figure 6 In the example of FIG, second chip 120 includes control circuit 610 configured to program the resistance of first feedback resistor 330 and / or the resistance of second feedback resistor 420. As discussed above, voltage 515 and voltage 525 depend on the ratio of the resistance of first feedback resistor 330 to the resistance of second feedback resistor 420. Therefore, control circuit 610 can adjust voltage 515 and voltage 525 by adjusting the resistance of first feedback resistor 330 and / or the resistance of second feedback resistor 420 accordingly.

[0045] Figure 7An example is shown in which, according to certain aspects, the second chip 120 further includes a termination circuit 710. The termination circuit 710 is coupled between the input 222 of the receiver 220 and the lower rail 355 (e.g., ground). In certain aspects, the termination circuit 710 is configured to provide impedance matching between the input 222 of the receiver 220 and the link 230.

[0046] The termination circuit 710 includes a termination resistor 720 and an AC coupling capacitor 730. The termination resistor 720 and the AC coupling capacitor 730 are coupled in series between the input 222 of the receiver 220 and the lower rail 355 (e.g., ground). The AC coupling capacitor 730 AC-couples the termination resistor 720 to the lower rail 355 to provide impedance matching for the data signal. In some aspects, the resistance of the termination resistor 720 can be selected to match the characteristic impedance of the link 230 (e.g., 50 ohms). The AC coupling capacitor 730 helps prevent the termination circuit 710 from consuming direct current (DC) power by acting as an open circuit to DC, thereby reducing power consumption.

[0047] Figure 8 An example is shown in which the second chip 120 further includes a first current-limiting resistor 820 coupled between the power rail 350 and the input stage 310 (e.g., the source of the first transistor 320). In this example, the first current-limiting resistor 820 can be used to adjust the current to the input stage 310 (e.g., across process, voltage, and temperature (PVT) corners). In this example, the resistance of the first current-limiting resistor 820 can be increased to reduce the current and can be reduced to increase the current. The second chip 120 can also include a second current-limiting resistor 850 coupled between the input stage 310 (e.g., the source of the second transistor 325) and the lower rail 355. The second current-limiting resistor 850 can also be used for current regulation (e.g., across PVT corners). In some aspects, each of the current-limiting resistor 820 and the current-limiting resistor 850 can be implemented with a resistor having a programmable resistance (e.g., to adjust the current regulation).

[0048] exist Figure 8In the example shown in FIG, second chip 120 also includes a first capacitor 830 having a first terminal coupled between the first current-limiting resistor 820 and the input stage 310 (e.g., the source of the first transistor 320); and a second terminal coupled to the lower rail 355 (e.g., ground). In this example, the first capacitor 830 and the first current-limiting resistor 820 form an RC filter 810, which helps filter noise from the power supply rail 350, thereby providing power supply noise suppression. In other words, the RC filter 810 helps clean the power supply voltage. The second chip 120 may also include a second capacitor 860 coupled in parallel with the second current-limiting resistor 850, wherein the second capacitor 860 and the second current-limiting resistor 850 form a second RC filter 840. The second RC filter 840 can be used to suppress noise on the lower rail 355.

[0049] As discussed above, the receiver 220 may also include one or more intermediate stages coupled between the output 314 of the input stage 310 and the input 342 of the output stage 340. In this regard, Figure 9 An example is shown in which receiver 220 includes an intermediate stage 910 having an input 912 coupled to output 314 of input stage 310 and an output 914 coupled to input 342 of output stage 340. Thus, in this example, input 342 of output stage 340 is coupled to output 314 of input stage 310 via intermediate stage 910.

[0050] exist Figure 9 In the example of , the intermediate stage 910 is implemented with an inverting circuit. However, it should be understood that the present disclosure is not limited to this example. Figure 9 , feedback path 410 includes an inverter circuit 920 having an input 922 coupled to output 344 of output stage 340 and an output 924 coupled to second feedback resistor 420. In this example, inverter circuit 920 is included in feedback path 410 so that feedback to input 312 of input stage 310 has the same polarity as the data signal.

[0051] It is understood that the second chip 120 may include an additional buffer between the output 224 of the receiver 220 and the second processing circuit 228. For example, the second chip 120 may include an inverting buffer (not shown) between the output 244 of the receiver 220 and the second processing circuit 228.

[0052] It should be understood that the receiver 220 may include Figure 4 、 Figure 6 、 Figure 7 、 Figure 8 and Figure 9For example, in some implementations, input stage 310 can include one or more resistors between the drains of transistor 320 and transistor 325. Furthermore, it should be understood that each of transistor 320 and transistor 325 can be implemented using multiple transistors coupled in parallel.

[0053] It should be understood that the present disclosure is not limited to the exemplary terms used above to describe various aspects of the present disclosure. For example, a pad may also be referred to as a pin, input / output (I / O) pad, I / O pin, or other terms. In addition, a processing circuit may also be referred to as a processor, a signal processor, a transmission / reception circuit, an interface, a modem, or another term. A link may also be referred to as a channel, a transmission line, an interconnect, a bus, or other terms.

[0054] Each of the first processing circuit 218, the second processing circuit 228, and the control circuit 610 can be implemented using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof designed to perform the functions described herein. The processor can perform the functions described herein by executing software including code for performing the functions. The software can be stored on a computer-readable storage medium (such as RAM, ROM, EEPROM, optical disk, and / or magnetic disk).

[0055] Example implementations are described in the following numbered clauses:

[0056] 1. A system comprising:

[0057] A receiver, wherein the receiver comprises:

[0058] an input stage, having input and output;

[0059] a first resistor coupled between the output of the input stage and the input of the input stage;

[0060] an output stage having an input and an output, wherein the input of the output stage is coupled to the output of the input stage; and

[0061] A feedback path is coupled between the output of the output stage and the input of the input stage, the feedback path including a second resistor.

[0062] 2. The system of clause 1, wherein the first resistor has a first resistance, the second resistor has a second resistance, and the second resistance is greater than the first resistance.

[0063] 3. The system of clause 2, wherein a ratio of the first resistor to the second resistor is between 0.1 and 0.3.

[0064] 4. The system of any of clauses 1 to 3, wherein at least one of the first resistor and the second resistor has a programmable resistance.

[0065] 5. The system of any of clauses 1 to 4, wherein the receiver further comprises a coupling capacitor coupled between an input of the receiver and an input of the input stage.

[0066] 6. The system of clause 5, wherein the receiver is configured to receive a data signal, and a resistance-capacitance (RC) time constant of the first resistor and the coupling capacitor is equal to or less than a unit interval (UI) of the data signal.

[0067] 7. The system of clause 6, further comprising a termination circuit coupled between the input of the receiver and the track, the termination circuit comprising:

[0068] Termination resistors; and

[0069] another coupling capacitor, wherein the terminating resistor and the another coupling capacitor are coupled in series between the input of the receiver and the rail.

[0070] 8. A system according to any one of clauses 1 to 4, wherein:

[0071] The receiver includes a first coupling capacitor coupled between an input of the receiver and an input of the input stage; and

[0072] The system also includes a termination circuit coupled between the input of the receiver and the track, the termination circuit comprising:

[0073] Termination resistors; and

[0074] a second coupling capacitor, wherein the terminating resistor and the second coupling capacitor are coupled in series between the input of the receiver and the rail.

[0075] 9. The system of clause 8, wherein the track is coupled to ground.

[0076] 10. The system of clause 8 or 9, wherein the receiver is configured to receive a data signal, and a resistance-capacitance (RC) time constant of the first resistor and the first coupling capacitor is equal to or less than a unit interval (UI) of the data signal.

[0077] 11. The system of clause 10, further comprising a pad coupled to an input of the receiver.

[0078] 12. The system of any of clauses 1 to 11, further comprising a current-limiting resistor coupled between the input stage and the first rail.

[0079] 13. The system of clause 12, further comprising a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled between the current-limiting resistor and the input stage, and the second terminal is coupled to a second rail, the second rail having a lower potential than the first rail.

[0080] 14. The system of any one of clauses 1 to 13, further comprising:

[0081] a first resistor-capacitor (RC) filter coupled between the first rail and the input stage; and

[0082] A second RC filter is coupled between the input stage and a second rail, the second rail having a lower potential than the first rail.

[0083] 15. The system of any of clauses 1 to 14, wherein the input stage comprises an inverter circuit.

[0084] 16. The system of clause 15, wherein the inverter circuit comprises:

[0085] a first transistor, wherein a source of the first transistor is coupled to the first rail, a gate of the first transistor is coupled to the input of the input stage, and a drain of the first transistor is coupled to the output of the input stage; and

[0086] a second transistor, wherein a source of the second transistor is coupled to the second rail, a gate of the second transistor is coupled to the input of the input stage, and a drain of the second transistor is coupled to the output of the input stage.

[0087] 17. The system of any one of clauses 1 to 16, wherein the feedback path further comprises an inverter circuit.

[0088] 18. The system of any of clauses 1 to 17, further comprising an intermediate stage having an input and an output, wherein the input of the intermediate stage is coupled to the output of the input stage, and the output of the intermediate stage is coupled to the input of the output stage.

[0089] 19. The system of clause 18, wherein the input stage comprises a first inverter circuit and the intermediate stage comprises a second inverter circuit.

[0090] 20. A system comprising:

[0091] A first chip, wherein the first chip comprises:

[0092] a driver having an input and an output; and

[0093] a first pad coupled to an output of the driver;

[0094] A second chip, wherein the second chip comprises:

[0095] a second pad; and

[0096] A receiver according to any of clauses 1 to 19, the receiver having an input and an output, wherein the input of the receiver is coupled to the second pad; and

[0097] A link is coupled between the first pad and the second pad.

[0098] 21. A system comprising:

[0099] A first chip, wherein the first chip comprises:

[0100] a driver having an input and an output; and

[0101] a first pad coupled to an output of the driver;

[0102] A second chip, wherein the second chip comprises:

[0103] a second pad; and

[0104] a receiver having an input and an output, wherein the input of the receiver is coupled to the second pad, and the receiver comprises:

[0105] an input stage, having input and output;

[0106] a first resistor coupled between the output of the input stage and the input of the input stage;

[0107] an output stage having an input and an output, wherein the input of the output stage is coupled to the output of the input stage; and

[0108] a feedback path coupled between an output of the output stage and an input of the input stage, the feedback path comprising a second resistor; and

[0109] A link is coupled between the first pad and the second pad.

[0110] 22. The system of clause 21, wherein the first resistor has a first resistance, the second resistor has a second resistance, and the second resistance is greater than the first resistance.

[0111] 23. The system of clause 22, wherein a ratio of the first resistance to the second resistance is between 0.1 and 0.3.

[0112] 24. The system of any of clauses 21 to 23, wherein at least one of the first resistor and the second resistor has a programmable resistance.

[0113] 25. The system of any of clauses 21 to 24, wherein the receiver further comprises a coupling capacitor coupled between an input of the receiver and an input of the input stage.

[0114] 26. The system of clause 25, wherein the receiver is configured to receive a data signal, and a resistance-capacitance (RC) time constant of the first resistor and the coupling capacitor is equal to or less than a unit interval (UI) of the data signal.

[0115] 27. The system of clause 26, wherein the second chip further comprises a termination circuit coupled between the input of the receiver and the track, the termination circuit comprising:

[0116] Termination resistors; and

[0117] another coupling capacitor, wherein the terminating resistor and the another coupling capacitor are coupled in series between the input of the receiver and the rail.

[0118] 28. A system according to any of clauses 21 to 24, wherein:

[0119] The receiver includes a first coupling capacitor coupled between an input of the receiver and an input of the input stage; and

[0120] The second chip also includes a termination circuit coupled between the input of the receiver and the rail, the termination circuit including:

[0121] Termination resistors; and

[0122] a second coupling capacitor, wherein the terminating resistor and the second coupling capacitor are coupled in series between the input of the receiver and the rail.

[0123] 29. The system of clause 28, wherein the track is coupled to ground.

[0124] 30. The system of clause 28 or 29, wherein the receiver is configured to receive a data signal, and a resistance-capacitance (RC) time constant of the first resistor and the first coupling capacitor is equal to or less than a unit interval (UI) of the data signal.

[0125] 31. The system of any of clauses 21 to 30, wherein the second chip further comprises a current-limiting resistor coupled between the input stage and the first rail.

[0126] 32. The system of clause 31, wherein the second chip further comprises a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled between the current-limiting resistor and the input stage, and the second terminal is coupled to a second rail having a lower potential than the first rail.

[0127] 33. The system according to any one of clauses 21 to 32, wherein the second chip further comprises:

[0128] a first resistor-capacitor (RC) filter coupled between the first rail and the input stage; and

[0129] A second RC filter is coupled between the input stage and a second rail, the second rail having a lower potential than the first rail.

[0130] 34. A system according to any of clauses 21 to 33, wherein the input stage comprises an inverter circuit.

[0131] 35. The system of clause 34, wherein the inverter circuit comprises:

[0132] a first transistor, wherein a source of the first transistor is coupled to the first rail, a gate of the first transistor is coupled to the input of the input stage, and a drain of the first transistor is coupled to the output of the input stage; and

[0133] a second transistor, wherein a source of the second transistor is coupled to the second rail, a gate of the second transistor is coupled to the input of the input stage, and a drain of the second transistor is coupled to the output of the input stage.

[0134] 36. The system of any of clauses 21 to 35, wherein the feedback path further comprises an inverter circuit.

[0135] 37. The system of any of clauses 21 to 36, wherein the receiver further comprises an intermediate stage having an input and an output, wherein the input of the intermediate stage is coupled to the output of the input stage, and the output of the intermediate stage is coupled to the input of the output stage.

[0136] 38. The system of clause 37, wherein the input stage comprises a first inverter circuit and the intermediate stage comprises a second inverter circuit.

[0137] In this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" as used herein refers to a direct or indirect electrical coupling between two structures. It should also be understood that the term "ground" can refer to either a DC ground or an AC ground, and thus the term "ground" encompasses both possibilities.

[0138] The foregoing description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples described herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: A receiver, wherein the receiver comprises: an input stage, having input and output; a first resistor coupled between the output of the input stage and the input of the input stage; an output stage having an input and an output, wherein the input of the output stage is coupled to the output of the input stage; and A feedback path is coupled between the output of the output stage and the input of the input stage, the feedback path comprising a second resistor. 2 . The system of claim 1 , wherein the first resistor has a first resistance, the second resistor has a second resistance, and the second resistance is greater than the first resistance. 3 . The system of claim 2 , wherein a ratio of the first resistor to the second resistor is between 0.1 and 0.

3. 4 . The system of claim 1 , wherein at least one of the first resistor and the second resistor has a programmable resistance.

5. The system of claim 1, wherein the receiver further comprises a coupling capacitor coupled between an input of the receiver and the input of the input stage.

6. The system of claim 5, wherein the receiver is configured to receive a data signal, and a resistance-capacitance (RC) time constant of the first resistor and the coupling capacitor is equal to or less than a unit interval (UI) of the data signal.

7. The system of claim 1, wherein: The receiver includes a first coupling capacitor coupled between an input of the receiver and the input of the input stage; as well as The system also includes a termination circuit coupled between the input of the receiver and a track, the termination circuit comprising: Terminal resistor; as well as a second coupling capacitor, wherein the terminating resistor and the second coupling capacitor are coupled in series between the input of the receiver and the rail. The system of claim 7 , wherein the rail is coupled to ground.

9. The system of claim 7, wherein the receiver is configured to receive a data signal, and a resistance-capacitance (RC) time constant of the first resistor and the first coupling capacitor is equal to or less than a unit interval (UI) of the data signal.

10. The system of claim 9, further comprising a pad coupled to the input of the receiver.

11. The system of claim 1 , further comprising a current-limiting resistor coupled between the input stage and a first rail.

12. The system of claim 11 further comprising a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled between the current-limiting resistor and the input stage, and the second terminal is coupled to a second rail, the second rail having a lower potential than the first rail.

13. The system of claim 1, further comprising: a first resistor-capacitor (RC) filter coupled between the first rail and the input stage; as well as A second RC filter is coupled between the input stage and a second rail having a lower potential than the first rail.

14. The system of claim 1, wherein the input stage comprises an inverter circuit.

15. The system of claim 14, wherein the inverter circuit comprises: a first transistor, wherein a source of the first transistor is coupled to a first rail, a gate of the first transistor is coupled to the input of the input stage, and a drain of the first transistor is coupled to the output of the input stage; as well as a second transistor, wherein a source of the second transistor is coupled to a second rail, a gate of the second transistor is coupled to the input of the input stage, and a drain of the second transistor is coupled to the output of the input stage.

16. The system of claim 1, wherein the feedback path further comprises an inverter circuit.

17. The system of claim 1, further comprising an intermediate stage having an input and an output, wherein the input of the intermediate stage is coupled to the output of the input stage, and the output of the intermediate stage is coupled to the input of the output stage.

18. The system of claim 17, wherein the input stage comprises a first inverter circuit and the intermediate stage comprises a second inverter circuit.

19. A system comprising: A first chip, wherein the first chip comprises: a driver having an input and an output; and a first pad coupled to the output of the driver; A second chip, wherein the second chip comprises: a second pad; and a receiver having an input and an output, wherein the input of the receiver is coupled to the second pad, and the receiver comprises: an input stage, having input and output; a first resistor coupled between the output of the input stage and the input of the input stage; an output stage having an input and an output, wherein the input of the output stage is coupled to the output of the input stage; and a feedback path coupled between the output of the output stage and the input of the input stage, the feedback path comprising a second resistor; and A link is coupled between the first pad and the second pad.

20. The system of claim 19, wherein the first resistor has a first resistance, the second resistor has a second resistance, and the second resistance is greater than the first resistance.

21. The system of claim 20, wherein a ratio of the first resistor to the second resistor is between 0.1 and 0.

3.

22. The system of claim 19, wherein at least one of the first resistor and the second resistor has a programmable resistance.

23. The system of claim 19, wherein the receiver further comprises a coupling capacitor coupled between the input of the receiver and the input of the input stage.

24. The system of claim 23, wherein the receiver is configured to receive a data signal, and a resistance-capacitance (RC) time constant of the first resistor and the coupling capacitor is equal to or less than a unit interval (UI) of the data signal.

25. The system of claim 19, wherein: The receiver includes a first coupling capacitor coupled between the input of the receiver and the input of the input stage; as well as The second chip also includes a termination circuit coupled between the input of the receiver and the track, the termination circuit including: Terminal resistor; as well as a second coupling capacitor, wherein the terminating resistor and the second coupling capacitor are coupled in series between the input of the receiver and the rail.

26. The system of claim 25, wherein the rail is coupled to ground.

27. The system of claim 25, wherein the receiver is configured to receive a data signal, and a resistance-capacitance (RC) time constant of the first resistor and the first coupling capacitor is equal to or less than a unit interval (UI) of the data signal.

28. The system of claim 19, wherein the second chip further comprises a current-limiting resistor coupled between the input stage and the first rail.

29. The system of claim 28, wherein the second chip further comprises a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled between the current-limiting resistor and the input stage, and the second terminal is coupled to a second rail having a lower potential than the first rail.

30. The system of claim 19, wherein the second chip further comprises: a first resistor-capacitor (RC) filter coupled between the first rail and the input stage; as well as A second RC filter is coupled between the input stage and a second rail having a lower potential than the first rail.

31. The system of claim 19, wherein the input stage comprises an inverter circuit.

32. The system of claim 31 , wherein the inverter circuit comprises: a first transistor, wherein a source of the first transistor is coupled to a first rail, a gate of the first transistor is coupled to the input of the input stage, and a drain of the first transistor is coupled to the output of the input stage; as well as a second transistor, wherein a source of the second transistor is coupled to a second rail, a gate of the second transistor is coupled to the input of the input stage, and a drain of the second transistor is coupled to the output of the input stage.

33. The system of claim 19, wherein the feedback path further comprises an inverter circuit.

34. The system of claim 19, wherein the receiver further comprises an intermediate stage having an input and an output, wherein the input of the intermediate stage is coupled to the output of the input stage and the output of the intermediate stage is coupled to the input of the output stage.

35. The system of claim 34, wherein the input stage comprises a first inverter circuit and the intermediate stage comprises a second inverter circuit.

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