Clock signal skew calibration apparatus and control method

Abstract

An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, where a first clock skew calibration unit includes: a frequency multiplier configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signal and generate a down-converted signal based on the clock signal; and a delay line control circuit configured to compare a duty cycle of the down-converted signal to a predetermined duty cycle and generate a first control signal to adjust the skew of the first multi-phase clock signal by adjusting a first delay applied to the first multi-phase clock signal, until a calibrated signal of the first multiphase clock signal is achieved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to, and is specifically a continuation-of-, U.S. application No. 18 / 227,255, filed on July 27, 2023, and entitled “Clock Signal Skew Calibration Apparatus and Control Method,” which is incorporated herein by reference as if its entire contents were reproduced. Technical Field

[0003] Embodiments of the present invention relate to a clock signal skew calibration apparatus, and in a specific embodiment, to a clock signal skew calibration apparatus for reducing clock skew of a 4-phase clock signal. Background Art

[0004] Data communication systems are constantly being adapted to serve the growing demand for high-speed data communications. Data communication systems, such as serial communication systems, include a transmitter and a receiver. The transmitter modulates a lower speed parallel data bus into a higher speed serial data stream. The higher speed serial data stream is transmitted through a suitable communication channel. The serial data stream travels on the communication channel and is then acquired by the receiver. The serial data stream is then processed by the receiver to recover the original data.

[0005] To achieve higher speeds, the transmitter transmits the data signal without the accompanying clock signal. The receiver is equipped with a clock data recovery (CDR) circuit. The CDR circuit is used to sample the incoming data signal, extract the clock from the incoming data signal, and retime the sampled data. The clock generated by the CDR circuit is synchronized with the data signal. There may be various CDR circuits, such as a phase-locked loop (PLL)-based CDR circuit, a delay-locked loop (DLL)-based CDR circuit, and a phase interpolator (PI)-based CDR circuit.

[0006] In a PI-based CDR circuit, a multi-phase clock signal (e.g., a 4-phase clock signal) is used to perform phase interpolation on a data signal. Multi-phase clock signals are also widely used in other data communication applications. For example, in a time-interleaved analog-to-digital conversion (ADC) system at a receiver, a multi-phase clock signal is used to sample input data.

[0007] Many techniques have been used to generate multi-phase clock signals. One possible technique is to make a ring oscillator and tap its nodes. A voltage-controlled or current-controlled differential ring oscillator with multi-stage delayed differential inverter amplifiers connected in a ring form is used to generate a multi-phase clock signal.

[0008] In higher frequency data communication applications, the temporal and spatial shift or deviation between two clock signals is called skew. Skew of clock signals can produce errors in the analog-to-digital conversion process and degrade system performance. As the clock rates of data communication systems increase, timing becomes more critical. It would be desirable to have a simple and reliable calibration method to reduce the skew of multi-phase clock signals. Summary of the invention

[0009] These and other problems are generally solved or avoided, and technical advantages are generally achieved, by preferred embodiments of the present disclosure that provide a clock signal skew calibration apparatus for reducing clock skew of a 4-phase clock signal.

[0010] According to an embodiment, a device includes a clock skew calibration circuit, which is configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit of the clock skew calibration circuit includes: a frequency multiplier, which is configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider, which is configured to receive the clock signal and generate a down-converted signal based on the clock signal, the down-converted signal having a duty cycle indicating a skew of a first multi-phase clock signal; and a delay line control circuit, which is configured to compare the duty cycle of the down-converted signal with a predetermined duty cycle and generate a first control signal to adjust the skew of the first multi-phase clock signal by adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

[0011] According to another embodiment, a method includes: generating a clock signal based on multiple multi-phase clock signals through a frequency multiplier; generating a down-clocked signal based on the clock signal through a frequency divider, the down-clocked signal having a duty cycle indicating a skew of a first multi-phase clock signal; comparing the duty cycle of the down-clocked signal with a predetermined duty cycle; and generating a first control signal through a delay line control circuit to adjust the skew of the first multi-phase clock signal by adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

[0012] According to another embodiment, a system includes: a multi-phase clock generator, which is configured to generate multiple multi-phase clock signals; multiple delay lines, which are configured to receive corresponding multi-phase clock signals; and a clock skew calibration circuit, which is configured to be coupled to the multi-phase clock generator through the multiple delay lines, wherein the clock skew calibration circuit includes a first clock skew calibration unit, a second clock skew calibration unit and a third clock skew calibration unit, and wherein the first clock skew calibration unit includes: a multiplier, which is configured to receive the multiple multi-phase clock signals and generate a clock signal based on the multiple multi-phase clock signals; a divider, which is configured to receive the clock signal and generate a down-converted signal based on the clock signal, the down-converted signal having a duty cycle indicating the skew of the first multi-phase clock signal; and a delay line control circuit, which is configured to compare the duty cycle of the down-converted signal with a predetermined duty cycle, and generate a first control signal to adjust a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

[0013] The foregoing has been a fairly broad overview of the features and technical advantages of the present disclosure so that the following detailed description of the present disclosure may be better understood. Additional features and advantages of the present disclosure will be described below, which constitute the subject matter of the claims of the present disclosure. It will be appreciated by those skilled in the art that the disclosed concepts and specific embodiments may be readily used as a basis for modifying or designing other structures or processes for the same purpose of carrying out the present disclosure. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 A block diagram illustrating a clock signal skew calibration circuit according to various embodiments of the present disclosure;

[0016] Figure 2 Description of various embodiments according to the present disclosure Figure 1 Schematic diagram of a multi-phase clock generator shown in;

[0017] Figure 3 Description of various embodiments according to the present disclosure Figure 1 Schematic diagram of the delay line shown in;

[0018] Figure 4 Description of various embodiments according to the present disclosure Figure 1 A block diagram of a first clock skew calibration unit as shown in FIG.

[0019] Figure 5Description of various embodiments according to the present disclosure Figure 4 Schematic diagram of the frequency doubler shown in ;

[0020] Figure 6 Description of various embodiments according to the present disclosure Figure 4 Schematic diagram of the crossover shown in ;

[0021] Figure 7 Description of various embodiments according to the present disclosure Figure 4 Schematic diagram of the filter shown in;

[0022] Figure 8 Description of various embodiments according to the present disclosure Figure 4 A schematic diagram of the delay line control circuit shown in FIG.

[0023] Fig. 9 illustrating various waveforms associated with a first clock skew calibration unit according to various embodiments of the present disclosure;

[0024] Fig.10 Description of various embodiments according to the present disclosure Figure 1 A schematic diagram of a second clock skew calibration unit shown in FIG.

[0025] Fig.11 illustrating various waveforms associated with a second clock skew calibration unit according to various embodiments of the present disclosure;

[0026] Fig.12 Description of various embodiments according to the present disclosure Figure 1 A schematic diagram of a third clock skew calibration unit shown in FIG.

[0027] Fig.13 illustrating various waveforms associated with a third clock skew calibration unit according to various embodiments of the present disclosure; and

[0028] Fig.14 Description of the control method according to various embodiments of the present disclosure Figure 1 Flowchart of the clock signal skew calibration circuit shown in .

[0029] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0030] The making and use of the currently preferred embodiments are discussed in detail below. However, it should be understood that the present disclosure provides many applicable creative concepts that can be embodied in various specific contexts. The specific embodiments discussed only illustrate specific ways to make and use the present disclosure and do not limit the scope of the present disclosure.

[0031] The present disclosure will be described with respect to a preferred embodiment in a specific context, namely a clock signal skew calibration device for reducing the clock skew of a 4-phase clock signal. However, the present disclosure may also be applied to a clock signal skew calibration device for reducing the clock skew of a multi-phase clock signal. In the following, various embodiments will be explained in detail with reference to the accompanying drawings.

[0032] Figure 1 A block diagram illustrating a clock signal skew calibration circuit according to various embodiments of the present disclosure is shown. Figure 1 As shown in , the clock skew calibration circuit 120 is configured to be coupled to the multi-phase clock generator 110 through a plurality of delay lines 111 , 112 , 113 , and 114 .

[0033] The multi-phase clock generator 110 is configured to generate a plurality of multi-phase clock signals. In some embodiments, the multi-phase clock generator 110 is configured to generate a 4-phase clock signal. Figure 1 0 degree clock signal PH0, 90 degree clock signal PH90, 180 degree clock signal PH180 and 270 degree clock signal PH270 are shown in FIG. PH0, PH90, PH180 and PH270 generated by multi-phase clock generator 110 are 4-phase clock signals having their phases separated by 90 degrees from each other, respectively.

[0034] In some embodiments, PH0, PH90, PH180, and PH270 are 4-phase clock signals with a frequency of 5 GHz. The 4-phase clock signals PH0, PH90, PH180, and PH270 are used for 20 Gbps (billions of bits per second) data transmission applications. Figure 2 A detailed implementation of the multi-phase clock generator 110 is described.

[0035] like Figure 1 As shown in FIG. 1 , the first delay line 111 is configured to receive a 0-degree clock signal PH0 and a predetermined reference signal Vref1. Based on the predetermined reference signal Vref1, the first delay line 111 adds a predetermined delay to the 0-degree clock signal. Figure 1 As shown in FIG. , PH0D is generated by the first delay line 111.

[0036] In some embodiments, the 0 degree clock signal PH0D is a reference clock signal for the 4-phase clock signals. Thus, during the skew calibration process, the delay added to PH0 is not adjusted. The skew of other clock signals (e.g., 180 degree clock signals) is determined with respect to the reference clock signal PH0D. By adjusting the delay added to the corresponding clock signal, the skew of the other clock signals can be reduced.

[0037] like Figure 1As shown in FIG. 1 , the second delay line 112 is configured to receive the 180-degree clock signal PH180 and the first control signal VC1. VC1 is generated by the clock skew calibration circuit 120. VC1 is used to determine the delay added to the 180-degree clock signal PH180. By adjusting the delay added to the 180-degree clock signal, the skew of the 180-degree clock signal is reduced accordingly. Figure 1 As shown in FIG. 1 , the second delay line 112 receives PH180 and generates PH180D by adding an initial delay. Both PH180 and PH180D are 180 degree clock signals with a delay therebetween. During the calibration process of the 180 degree clock signal, the initial delay is adjusted to become a first delay determined by the first control signal VC1. Once the initial delay has been changed to the first delay, PH180C is generated at the output of the second delay line 112. PH180C is a calibrated 180 degree clock signal. In other words, the phase difference between the reference clock signals PH0D and PH180C is 180 degrees.

[0038] like Figure 1 As shown in FIG. 1 , the third delay line 113 is configured to receive the 90-degree clock signal PH90 and the second control signal VC2. VC2 is generated by the clock skew calibration circuit 120. VC2 is used to determine the delay added to the 90-degree clock signal PH90. By adjusting the delay added to the 90-degree clock signal, the skew of the 90-degree clock signal is reduced accordingly. Figure 1 As shown in FIG. 1 , the third delay line 113 receives PH90 and generates PH90D by adding an initial delay. Both PH90 and PH90D are 90 degree clock signals with a delay therebetween. During the calibration process of the 90 degree clock signal, the initial delay is adjusted to become a second delay determined by the second control signal VC2. Once the initial delay has been changed to the second delay, PH90C is generated at the output of the third delay line 113. PH90C is a calibrated 90 degree clock signal. In other words, the phase difference between the reference clock signals PH0D and PH90C is 90 degrees.

[0039] like Figure 1 As shown in FIG. 1 , the fourth delay line 114 is configured to receive the 270 degree clock signal PH270 and the third control signal VC3. VC3 is generated by the clock skew calibration circuit 120. VC3 is used to determine the delay added to the 270 degree clock signal PH270. By adjusting the delay added to the 270 degree clock signal, the skew of the 270 degree clock signal is reduced accordingly. Figure 1, the fourth delay line 114 receives PH270 and generates PH270D by adding an initial delay. Both PH270 and PH270D are 270 degree clock signals with a delay therebetween. During the calibration process of the 270 degree clock signal, the initial delay is adjusted to become a third delay determined by the third control signal VC3. Once the initial delay has been changed to the third delay, PH270C is generated at the output of the fourth delay line 114. PH270C is a calibrated 270 degree clock signal. In other words, the phase difference between the reference clock signals PH0D and PH270C is 270 degrees.

[0040] The clock skew calibration circuit 120 includes a PH180 calibration unit 121, a PH90 calibration unit 122, and a PH270 calibration unit 123. Throughout the description, the PH180 calibration unit 121 is alternatively referred to as a first clock skew calibration unit 121. The PH90 calibration unit 122 is alternatively referred to as a second clock skew calibration unit 122. The PH270 calibration unit 123 is alternatively referred to as a third clock skew calibration unit 123.

[0041] In some embodiments, the first clock skew calibration unit 121 includes a frequency multiplier, a frequency divider, and a delay line control circuit. Figure 4 The detailed structure of the first clock skew calibration unit 121 is described.

[0042] In operation, the first clock skew calibration unit 121 and the second delay line 112 form a closed-loop control system. This closed-loop control system determines the first control signal VC1 based on the skew of the 180-degree clock signal, and adjusts the delay added to the 180-degree clock signal to reduce or eliminate the skew of the 180-degree clock signal. Thus, the skew of the 180-degree clock signal is calibrated.

[0043] In operation, the first clock skew calibration unit 121 is configured to receive a plurality of multi-phase clock signals including: Figure 1PH0D, PH90D, PH180D and PH270D shown in . Based on a plurality of multi-phase clock signals PH0D, PH90D, PH180D and PH270D, the frequency multiplier generates a clock signal. The frequency divider is configured to receive the clock signal and generate a down-converted signal based on the clock signal. The down-converted signal has a duty cycle indicating a skew of a first multi-phase clock signal (e.g., a 180 degree clock signal). The delay line control circuit is configured to compare the duty cycle of the down-converted signal with a predetermined duty cycle and generate a first control signal VC1. The first control signal VC1 is used to adjust a first delay applied to the first multi-phase clock signal (e.g., a 180 degree clock signal) until a calibrated signal of the first multi-phase clock signal is achieved. Once the skew calibration process is completed, the PH180C generated by the second delay line 112 is a calibrated signal of the 180 degree clock signal.

[0044] In some embodiments, the second clock skew calibration unit 122 includes a first logic gate, a second logic gate, and a first comparator. Fig.10 The detailed structure of the second clock skew calibration unit 122 is described.

[0045] In operation, the second clock skew calibration unit 122 and the third delay line 113 form a closed-loop control system. This closed-loop control system determines the second control signal VC2 based on the skew of the 90-degree clock signal and adjusts the delay added to the 90-degree clock signal to reduce or eliminate the skew of the 90-degree clock signal. Thus, the skew of the 90-degree clock signal is calibrated.

[0046] In operation, the second clock skew calibration unit 122 is configured to receive PH0D, PH90D, and PH180C. In some embodiments, PH0D is a reference multi-phase clock signal. PH180C is a calibrated signal of the first multi-phase clock signal. PH90D is a second multi-phase clock signal.

[0047] The first logic gate is configured to perform a first AND operation on a calibrated signal of the first multi-phase clock signal (PH180C) and a second multi-phase clock signal (PH90D). The second logic gate is configured to perform a second AND operation on a reference multi-phase clock signal (PH0D) and a second multi-phase clock signal (PH90D). The first comparator is configured to compare the output of the first logic gate with the output of the second logic gate and generate a second control signal VC2. The second control signal VC2 is used to adjust the second delay applied to the second multi-phase clock signal (90 degree clock signal) until a calibrated signal of the second multi-phase clock signal is achieved. Once the skew calibration process is completed, the PH90C generated by the third delay line 113 is a calibrated signal of the 90 degree clock signal.

[0048] In some embodiments, the third clock skew calibration unit 123 includes a third logic gate, a fourth logic gate, and a second comparator. Fig.12 The detailed structure of the second clock skew calibration unit 123 is described.

[0049] In operation, the third clock skew calibration unit 123 and the fourth delay line 114 form a closed-loop control system. This closed-loop control system determines the third control signal VC3 based on the skew of the 270-degree clock signal, and adjusts the delay added to the 270-degree clock signal to reduce or eliminate the skew of the 270-degree clock signal. Thus, the skew of the 270-degree clock signal is calibrated.

[0050] In operation, the third clock skew calibration unit 123 is configured to receive PH0D, PH180C, and PH270D. In some embodiments, PH0D is a reference multi-phase clock signal. PH180C is a calibrated signal of the first multi-phase clock signal. PH270D is a third multi-phase clock signal.

[0051] The third logic gate is configured to perform a third AND operation on the calibrated signal of the first multi-phase clock signal (PH180C) and the third multi-phase clock signal (PH270D). The fourth logic gate is configured to perform a fourth AND operation on the reference multi-phase clock signal (PH0D) and the third multi-phase clock signal (PH270D). The second comparator is configured to compare the output of the first logic gate with the output of the second logic gate and generate a third control signal VC3. The third control signal VC3 is used to adjust the third delay applied to the third multi-phase clock signal (270 degree clock signal) until the calibrated signal of the third multi-phase clock signal is achieved. Once the skew calibration process is completed, the PH270C generated by the fourth delay line 114 is the calibrated signal of the 270 degree clock signal.

[0052] Figure 2 Description of various embodiments according to the present disclosure Figure 1 In some embodiments, the multi-phase clock generator 110 is implemented as follows: Figure 2 The 4-phase clock generator shown in FIG. The multi-phase clock generator 110 includes a first oscillator 211, a second oscillator 212, a third oscillator 213, and a fourth oscillator 214 connected in cascade.

[0053] like Figure 2As shown in , the inverting output of the first oscillator 211 is connected to the non-inverting input of the second oscillator 212. The inverting output of the first oscillator 211 is configured to generate a 270 degree clock signal PH270. The non-inverting output of the first oscillator 211 is connected to the inverting input of the second oscillator 212. The inverting output of the second oscillator 212 is connected to the non-inverting input of the third oscillator 213. The inverting output of the second oscillator 212 is configured to generate a 180 degree clock signal PH180. The non-inverting output of the second oscillator 212 is connected to the inverting input of the third oscillator 213.

[0054] The inverting output of the third oscillator 213 is connected to the non-inverting input of the fourth oscillator 214. The inverting output of the third oscillator 213 is configured to generate a 90-degree clock signal PH90. The non-inverting output of the third oscillator 213 is connected to the inverting input of the fourth oscillator 214. The inverting output of the fourth oscillator 214 is connected to the non-inverting input of the first oscillator 211. The inverting output of the fourth oscillator 214 is configured to generate a 0-degree clock signal PH0. The non-inverting output of the fourth oscillator 214 is connected to the inverting input of the first oscillator 211.

[0055] Figure 2 The operating principle of the 4-phase clock generator shown in is well known in the art and is therefore not discussed herein to avoid repetition.

[0056] Figure 3 Description of various embodiments according to the present disclosure Figure 1 Schematic diagram of the delay line shown in . Figure 1 The four delay lines shown in FIG. 1 may have the same structure. The second delay line 112 is used as an example to illustrate Figure 1 The structure and operation principle of the delay line are shown in FIG.

[0057] The second delay line 112 includes a bias circuit and a plurality of inverting branches. The bias circuit includes an upper transistor M41 and a lower transistor M42 connected in series between a power supply voltage VDD and ground. The plurality of inverting branches are connected in parallel between the power supply voltage VDD and ground. Each inverting branch includes a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series. Figure 2As shown in , the first inverting branch in the plurality of inverting branches includes transistors M11, M12, M13, M14 connected in series between VDD and ground. The second inverting branch in the plurality of inverting branches includes transistors M21, M22, M23, M24 connected in series between VDD and ground. The last inverting branch in the plurality of inverting branches includes transistors M31, M32, M33, M34 connected in series between VDD and ground. In some embodiments, M11, M12, M21, M22, M31, M32 and M41 are p-type transistors. M13, M14, M23, M24, M33, M34 and M42 are n-type transistors.

[0058] like Figure 3 As shown in , the gates of transistors M11, M21 and M31 are connected to the gate of the upper transistor M41. In the first inverting branch, the gate of M12 is connected to the gate of M13 and serves as the input of the first inverting branch. The midpoint VM1 of the first inverting branch serves as the output of the first inverting branch. In the second inverting branch, the gate of M22 is connected to the gate of M23 and serves as the input of the second inverting branch. The midpoint VM2 of the second inverting branch serves as the output of the second inverting branch. In the last inverting branch, the gate of M32 is connected to the gate of M33 and serves as the input of the last inverting branch. The midpoint VM3 of the last inverting branch serves as the output of the last inverting branch. The gates of transistors M14, M24 and M34 are connected to the gate of the lower transistor M42.

[0059] like Figure 3 As shown in FIG. 1 , the input of the first inverting branch is configured to receive the first multi-phase clock signal PH180. The output of the first inverting branch is connected to the input of the second inverting branch. The output of the second inverting branch is connected to the input of the adjacent inverting branch (not shown). The input of the last inverting branch is connected to the output of the adjacent inverting branch (not shown). The output of the last inverting branch is configured to generate Figure 3 Once the calibration process of the first multi-phase clock signal PH180 is completed, the output of the last inverting branch is configured to generate a calibrated signal of the first multi-phase clock signal (PH180C).

[0060] In operation, each inverting branch acts as a current-starved inverter. The second delay line 112 is configured to receive a first control signal VC1 at the gate of M42. The current-starved inverter is capable of converting the first control signal VC1 into a voltage-controlled delay. In each inverting branch, the topmost transistor (e.g., M11) and the bottommost transistor (e.g., M14) act as current sources. Two middle transistors (e.g., M12 and M13) act as inverters. In response to the first control signal VC1, the current source (e.g., M11 and M14) is capable of controlling the current supplied to the inverter (e.g., M12 and M13). In particular, the current supplied to the inverter is determined by a bias circuit formed by M41 and M42. The current through M42 is proportional to the gate-to-source voltage (VC1) of M42. Therefore, the largest current results in the shortest delay. Thus, when VC1 increases, the delay decreases. On the other hand, the smaller the current, the greater the delay. Thus, when VC1 decreases, the delay increases. The second delay line 112 is capable of adding an adjustable delay to PH180 in response to VC1. Once the appropriate delay has been added to PH180, the second delay line 112 generates PH180C. PH180C is the calibrated signal of PH180.

[0061] Figure 4 Description of various embodiments according to the present disclosure Figure 1 The first clock skew calibration unit 121 includes a frequency multiplier 402 , a frequency divider 404 , a latch circuit 406 , a buffer 408 , a delay line control circuit 410 , and a filter 412 .

[0062] like Figure 4 As shown in FIG. 4 , the frequency multiplier 402 is configured to receive a plurality of multi-phase clock signals PH0D, PH90D, PH180D, and PH270D. Based on the plurality of multi-phase clock signals, the frequency multiplier 402 generates a clock signal CLKOUT. The frequency divider 404 is configured to receive the clock signal CLKOUT and generate a down-converted signal CLKDIV2 based on the clock signal CLKOUT. The frequency of CLKDIV2 is half the frequency of CLKOUT. The down-converted signal CLKDIV2 has a duty cycle indicating the skew of the first multi-phase clock signal PH180D.

[0063] The down-clocked signal CLKDIV2 is fed into the data input of the latch circuit 406. The 90 degree clock signal PH90 is fed into the clock input of the latch circuit 406 through the buffer 408. The latch circuit 406 is configured to generate a direction control signal SEL.

[0064] The filter 412 is configured to receive the down-converting signal CLKDIV2 and generate a dc signal VDUTY. The voltage of VDUTY is proportional to the duty cycle of the down-converting signal CLKDIV2.

[0065] The delay line control circuit 410 is configured to receive VDUTY, SEL and a predetermined reference voltage Vref. The delay line control circuit 410 is configured to compare the duty cycle of the frequency reduction signal CLKDIV2 with the predetermined duty cycle. In some embodiments, VDUTY represents the duty cycle of the frequency reduction signal CLKDIV2. Vref represents the predetermined duty cycle. In some embodiments, the predetermined duty cycle is equal to 50%.

[0066] In operation, based on VDUTY, Vref, and SEL, the delay line control circuit 410 generates a first control signal VC1 to adjust the skew of the first multiphase clock signal PH180 by adjusting a first delay applied to the first multiphase clock signal PH180 until a calibrated signal of the first multiphase clock signal is achieved.

[0067] Figure 5 Description of various embodiments according to the present disclosure Figure 4 Schematic diagram of the frequency multiplier shown in FIG. The frequency multiplier 402 includes a first transmission gate 501 and a second transmission gate 502. The frequency multiplier 402 is configured to receive PH0D, PH90D, PH180D, and PH270D, and generate a clock signal CLKOUT.

[0068] The input of the first transmission gate 501 is configured to receive the 0 degree clock signal PH0D. The output of the first transmission gate 501 is connected to the output of the frequency multiplier 402. The first control terminal of the first transmission gate 501 is configured to receive the 90 degree clock signal PH90D. The second control terminal of the first transmission gate 501 is configured to receive the 270 degree clock signal PH270D.

[0069] The input of the second transmission gate 502 is configured to receive the 180 degree clock signal PH180D. The output of the second transmission gate 502 is connected to the output of the frequency multiplier 402. The first control terminal of the second transmission gate 502 is configured to receive the 270 degree clock signal PH270D. The second control terminal of the second transmission gate 502 is configured to receive the 90 degree clock signal PH90D.

[0070] Figure 5 The operating principle of the frequency multiplier shown in is well known in the art and therefore is not discussed herein to avoid repetition.

[0071] Figure 6 Description of various embodiments according to the present disclosure Figure 4Schematic diagram of the frequency divider shown in FIG. The frequency divider 404 is implemented as a latch circuit 602. The clock signal CLKOUT is fed into the clock input of the latch circuit 602. The data input and Q-bar output of the latch circuit 602 are connected together. The Q output of the latch circuit 602 is configured to generate a down-clocked signal CLKDIV2.

[0072] Figure 6 The operating principle of the frequency divider shown in is well known in the art and is therefore not discussed herein to avoid repetition.

[0073] Figure 7 Description of various embodiments according to the present disclosure Figure 4 . Filter 412 includes a resistor R1 and a capacitor C1. One terminal of R1 is the input of filter 412. The common node of R1 and C1 is the output of filter 412. Filter 412 is a low pass filter configured to convert the down-converted signal CLKDIV2 into a dc signal VDUTY. The voltage of the dc signal VDUTY is proportional to the duty cycle of the down-converted signal CLKDIV2.

[0074] Figure 8 Description of various embodiments according to the present disclosure Figure 4 The delay line control circuit 410 includes an inverter 804 , a first switch S1 , a second switch S2 , a third switch S3 , a fourth switch S4 and a comparator 802 .

[0075] like Figure 8 As shown in FIG. 8 , the inverter 804 is configured to receive the direction control signal SEL and generate an inverted signal SELB of the direction control signal SEL. The first drain / source terminal of the first switch S1 is configured to receive the dc signal VDUTY. The second drain / source terminal of the first switch S1 is connected to the non-inverting input of the comparator 802. The gate of the first switch S1 is controlled by the direction control signal SEL.

[0076] A first drain / source terminal of the second switch S2 is configured to receive a reference voltage Vref. A second drain / source terminal of the second switch S2 is connected to a non-inverting input of the comparator 802. A gate of the second switch S2 is controlled by an inverted signal SELB of the direction control signal SEL.

[0077] A first drain / source terminal of the third switch S3 is configured to receive the dc signal VDUTY. A second drain / source terminal of the third switch S3 is connected to the inverting input of the comparator 802. A gate of the third switch S3 is controlled by an inverted signal SELB of the direction control signal SEL.

[0078] A first drain / source terminal of the fourth switch S4 is configured to receive a reference voltage Vref. A second drain / source terminal of the fourth switch S4 is connected to an inverting input of the comparator 802. A gate of the fourth switch S4 is controlled by a direction control signal SEL.

[0079] In operation, SEL and SELB control the turning on and off of switches S1, S2, S3, and S4. When SEL is a logic high state, VDUTY is fed into the non-inverting input of the comparator 802, and Vref is fed into the inverting input of the comparator 802. On the other hand, when SEL is a logic low state, VDUTY is fed into the inverting input of the comparator 802, and Vref is fed into the non-inverting input of the comparator 802. The output of the comparator 802 is configured to generate a first control signal VC1.

[0080] Fig. 9 Various waveforms associated with a first clock skew calibration unit according to various embodiments of the present disclosure are illustrated. Fig. 9 The horizontal axis represents the time interval. Fig. 9 There may be eight rows in . The first row represents PH0D. The second row represents PH90D. The third row represents PH180D. The fourth row represents PH270D. The fifth row represents the clock signal CLKOUT. The sixth row represents the first frequency reduction signal CLKDIV2A. The seventh row represents the second frequency reduction signal CLKDIV2B. The eighth row represents the direction control signal SEL.

[0081] Return to reference Figure 1 , the multi-phase clock generator 110 is configured to generate PH0, PH90, PH180 and PH270. After PH0, PH90, PH180 and PH270 pass through the corresponding delay lines, PH0D, PH90D, PH180D and PH270D are generated and fed into the clock signal skew calibration circuit. In some embodiments, there is a skew at PH180D. This skew is indicated by the dotted line between t2 and t3.

[0082] The clock signal CLKOUT is generated based on PH0D, PH90D, PH180D and PH270D. Fig. 9 As shown in FIG. 1 , at t1, CLKOUT changes from a logic high state to a logic low state in response to the leading edge of PH90D and the falling edge of PH270D. At t3, CLKOUT changes from a logic low state to a logic high state (dashed line) in response to the leading edge of PH180D. At t4, CLKOUT changes from a logic high state to a logic low state in response to the leading edge of PH270 and the falling edge of PH90D. At t5, CLKOUT changes from a logic low state to a logic high state in response to the leading edge of PH0D.

[0083] There are two frequency reduction signals CLKDIV2A and CLKDIV2B. Fig. 9 As shown in , the rising edge of CLKDIV2A is aligned with the rising edge of PH0. The rising edge of CLKDIV2B is aligned with the rising edge of PH180D. When PH180D lags, the duty cycle of CLKDIV2A is greater than 50%, and the duty cycle of CLKDIV2B is less than 50%. Thus, the skew calibration process has two opposite directions.

[0084] Return to reference Figure 8 , when the rising edge of the frequency reduction signal is aligned with the rising edge of PH0, SEL has a logic high state. When the rising edge of the frequency reduction signal is aligned with the rising edge of PH180, SEL has a logic low state. When SEL has a logic high state and PH180D lags, the duty cycle of the frequency reduction signal is greater than 50%. When SEL has a logic low state and PH180D lags, the duty cycle of the frequency reduction signal is less than 50%.

[0085] Return to reference Figure 8 , when SEL has a logic high state, VDUTY is connected to the non-inverting input of comparator 802, and Vref is connected to the inverting input of comparator 802. Since the duty cycle of the down-converting signal is greater than 50%, VDUTY is greater than Vref. VC1 increases. Return to reference Figure 3 , the increased VC1 reduces the delay added to PH180. Therefore, the skew of PH180 is reduced. When SEL has a logic low state, VDUTY is connected to the inverting input of comparator 802, and Vref is connected to the non-inverting input of comparator 802. Since the duty cycle of the down-converting signal is less than 50%, VDUTY is less than Vref. VC1 increases. Return to reference Figure 3 , the added VC1 reduces the delay added to PH180. Therefore, the skew of PH180 is reduced.

[0086] In operation, the skew calibration process has two opposite directions. The direction of the skew calibration process can be determined by sampling the down-clocked signal using PH90D. For example, PH90D is used to sample CLKDIV2A, and the result is a logic high state. This logic high state indicates that the rising edge of CLKDIV2A is aligned with PH0D. The duty cycle of CLKDIV2A is greater than 50%. After knowing this direction of the skew calibration process, the delay line control circuit can reduce the delay added to PH180D so that the duty cycle of CLKDIV2A is equal to 50%. Once the duty cycle of CLKDIV2A is equal to 50%, the corresponding delay is the appropriate delay added to PH180. Under this appropriate delay, the output PH180C is the calibrated signal of PH180.

[0087] Fig. 9 One advantageous feature of the skew calibration control scheme presented in is that the duty cycle of the down-clocked signal (e.g., CLKDIV2A) is set to 50% by adjusting the delay added to PH180. Once the duty cycle of the down-clocked signal (e.g., CLKDIV2A) is set to 50%, the phase difference between PH0D and PH180C is equal to 180 degrees.

[0088] Fig.10 Description of various embodiments according to the present disclosure Figure 1 Schematic diagram of the second clock skew calibration unit shown in FIG. The second clock skew calibration unit 122 includes a first logic gate 1011, a second logic gate 1021, a first filter 1012, a second filter 1022, and a first comparator 1002. The first logic gate 1011 and the second logic gate 1021 are implemented as AND gates.

[0089] The first logic gate 1011 is configured to perform a first AND operation on the calibrated signal of the first multi-phase clock signal and the second multi-phase clock signal. Fig.10 , the calibrated signal of the first multi-phase clock signal is PH180C. The second multi-phase clock signal is PH90D.

[0090] The second logic gate 1021 is configured to perform a second AND operation on the reference multi-phase clock signal and the second multi-phase clock signal. Fig.10 As shown in , the reference multi-phase clock signal is PH0D.

[0091] The output of the first logic gate 1011 is fed into the non-inverting input of the first comparator 1002 through the first filter 1012. The output of the second logic gate 1021 is fed into the inverting input of the first comparator 1002 through the second filter 1022. Both filters 1012 and 1022 are RC filters, similar to the above description of Figure 7 Filter 412 is described.

[0092] The first comparator 1002 is configured to compare the output of the first logic gate 1011 with the output of the second logic gate 1021, and generate a second control signal VC2 to adjust the skew of the second multi-phase clock signal PH90D by adjusting the second delay applied to the second multi-phase clock signal until a calibrated signal PH90C of the second multi-phase clock signal is achieved.

[0093] Fig.11 Various waveforms associated with the second clock skew calibration unit according to various embodiments of the present disclosure are illustrated. Fig.11 The horizontal axis represents the time interval. Fig.11There may be five rows in . The first row represents PH0D. The second row represents PH90D. The third row represents PH180C. The fourth row represents the result after performing an AND operation on PH0D and PH90D. The fifth row represents the result after performing an AND operation on PH90D and PH180C.

[0094] PH90D is the clock signal to be calibrated. There is a skew at PH90D. This skew is indicated by the dotted line between t1 and t2. The output of the second logic gate 1021 (PH0D & PH90D) has a logic high state from t2 to t3. The output of the first logic gate 1011 (PH90D & PH180C) has a logic high state from t3 to t4. When PH90D lags, the duty cycle of the output of the first logic gate 1011 is greater than the duty cycle of the output of the second logic gate 1021. This duty cycle difference can be used to generate Fig.10 1021. For example, in response to VC2, the delay added to PH90D is reduced so that the duty cycle of the output of the first logic gate 1011 is equal to the duty cycle of the output of the second logic gate 1021. Once the two duty cycles are equal, the corresponding delay is the appropriate delay added to PH90. At this appropriate delay, the output PH90C is the calibrated signal of PH90.

[0095] Fig.12 Description of various embodiments according to the present disclosure Figure 1 The third clock skew calibration unit 123 includes a third logic gate 1211, a fourth logic gate 1221, a third filter 1212, a fourth filter 1222, and a second comparator 1202. The third logic gate 1211 and the fourth logic gate 1221 are implemented as AND gates.

[0096] The third logic gate 1211 is configured to perform a third AND operation on the reference multi-phase clock signal and the third multi-phase clock signal. Fig.12 As shown in , the reference multi-phase clock signal is PH0D. The third multi-phase clock signal is PH270D.

[0097] The fourth logic gate 1221 is configured to perform a fourth AND operation on the calibrated signal of the first multi-phase clock signal and the third multi-phase clock signal. Fig.12 As shown in , the calibrated signal of the first multi-phase clock signal is PH180C.

[0098] The output of the third logic gate 1211 is fed into the non-inverting input of the second comparator 1202 through the third filter 1212. The output of the fourth logic gate 1221 is fed into the inverting input of the second comparator 1202 through the fourth filter 1222. Both filters 1212 and 1222 are RC filters, similar to the above description of Figure 7 Filter 412 is described.

[0099] The second comparator 1202 is configured to compare the output of the third logic gate 1211 with the output of the fourth logic gate 1221, and generate a third control signal VC3 to adjust the skew of the third multi-phase clock signal PH270 by adjusting the third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved.

[0100] Fig.13 Various waveforms associated with the third clock skew calibration unit according to various embodiments of the present disclosure are illustrated. Fig.13 The horizontal axis represents the time interval. Fig.13 There may be five rows in . The first row represents PH0D. The second row represents PH180C. The third row represents PH270D. The fourth row represents the result after performing an AND operation on PH0D and PH270D. The fifth row represents the result after performing an AND operation on PH180C and PH270D.

[0101] PH270D is the clock signal to be calibrated. There is a skew at PH270D. This skew is indicated by the dotted line between t1 and t2. The output of the third logic gate 1211 (PH0D & PH270D) has a logic high state from t3 to t4. The output of the fourth logic gate 1221 (PH180C & PH270D) has a logic high state from t2 to t3. When PH270D lags, the duty cycle of the output of the third logic gate 1211 is greater than the duty cycle of the output of the fourth logic gate 1221. This duty cycle difference can be used to generate Fig.12 . For example, in response to VC3, the delay added to PH270 is reduced so that the duty cycle of the output of the fourth logic gate 1221 is equal to the duty cycle of the output of the third logic gate 1211. Once the two duty cycles are equal, the corresponding delay is the appropriate delay added to PH270. At this appropriate delay, the output PH270C is the calibrated signal of PH270.

[0102] Fig.14 Description of the control method according to various embodiments of the present disclosure Figure 1 Flowchart of the clock signal skew calibration circuit shown in . Fig.14The flowchart shown in the is merely an example, which should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Fig.14 The steps described in .

[0103] Return to reference Figure 1 The clock signal skew calibration circuit includes a first clock skew calibration unit 121, a second clock skew calibration unit 122 and a third clock skew calibration unit 123. Return to reference Figure 4 The first clock skew calibration unit 121 includes a frequency multiplier 402 , a frequency divider 404 , a latch circuit 406 , a buffer 408 , a delay line control circuit 410 , and a filter 412 .

[0104] At step 1402, a clock signal is generated based on a plurality of multi-phase clock signals by a frequency multiplier.

[0105] At step 1404, a frequency divider is used to generate a down-converted signal based on the clock signal. The down-converted signal has a duty cycle that indicates a skew of the first multi-phase clock signal.

[0106] At step 1406 , the duty cycle of the down-converted signal is compared with a predetermined duty cycle.

[0107] At step 1408, a first control signal is generated by the delay line control circuit. The first control signal is used to adjust the skew of the first multi-phase clock signal by adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

[0108] The method further includes performing a first AND operation on the calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal, performing a second AND operation on a reference multi-phase clock signal and the second multi-phase clock signal, and comparing a result of the first AND operation with a result of the second AND operation, and based on a comparison result from the step of comparing the result of the first AND operation with the result of the second AND operation, generating a second control signal to adjust a skew of the second multi-phase clock signal by adjusting a second delay applied to the second multi-phase clock signal until a calibrated signal of the second multi-phase clock signal is achieved.

[0109] The method further includes performing a third AND operation on the calibrated signal of the first multi-phase clock signal and a third multi-phase clock signal, performing a fourth AND operation on the reference multi-phase clock signal and the third multi-phase clock signal, and comparing a result of the third AND operation with a result of the fourth AND operation, and based on a comparison result from the step of comparing the result of the third AND operation with the result of the fourth AND operation, generating a third control signal to adjust a skew of the third multi-phase clock signal by adjusting a third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved.

[0110] The method further includes generating a 4-phase clock signal by a multi-phase clock generator, which includes a 0 degree clock signal, a 90 degree clock signal, a 180 degree clock signal and a 270 degree clock signal, wherein the reference multi-phase clock signal is the 0 degree clock signal, the first multi-phase clock signal is the 180 degree clock signal, the second multi-phase clock signal is the 90 degree clock signal, and the third multi-phase clock signal is the 270 degree clock signal.

[0111] In some embodiments, the multi-phase clock generator includes a first oscillator, a second oscillator, a third oscillator and a fourth oscillator connected in cascade, and wherein the inverting output of the first oscillator is connected to the non-inverting input of the second oscillator, wherein the inverting output of the first oscillator is configured to generate the 270 degree clock signal, the non-inverting output of the first oscillator is connected to the inverting input of the second oscillator, the inverting output of the second oscillator is connected to the non-inverting input of the third oscillator, wherein the inverting output of the second oscillator is configured to generate the 180 degree clock signal, the non-inverting output of the second oscillator is connected to the inverting input of the third oscillator, the inverting output of the third oscillator is connected to the non-inverting input of the fourth oscillator, wherein the inverting output of the third oscillator is configured to generate the 90 degree clock signal, the non-inverting output of the third oscillator is connected to the inverting input of the fourth oscillator, the inverting output of the fourth oscillator is connected to the non-inverting input of the first oscillator, wherein the inverting output of the fourth oscillator is configured to generate the 0 degree clock signal, and the non-inverting output of the fourth oscillator is connected to the inverting input of the first oscillator.

[0112] In some embodiments, the frequency divider is a latch circuit, and the frequency multiplier includes a first transmission gate and a second transmission gate, and wherein the input of the first transmission gate is configured to receive the 0 degree clock signal, the output of the first transmission gate is connected to the output of the frequency multiplier, the first control terminal of the first transmission gate is configured to receive the 90 degree clock signal, the second control terminal of the first transmission gate is configured to receive the 270 degree clock signal, the input of the second transmission gate is configured to receive the 180 degree clock signal, the output of the second transmission gate is connected to the output of the frequency multiplier, the first control terminal of the second transmission gate is configured to receive the 270 degree clock signal, and the second control terminal of the second transmission gate is configured to receive the 90 degree clock signal.

[0113] The method further includes converting the down-converted signal into a DC signal, wherein a voltage of the DC signal is proportional to the duty cycle of the down-converted signal, and comparing the voltage of the DC signal with a reference voltage proportional to the predetermined duty cycle to obtain the first control signal.

[0114] In some embodiments, the delay line control circuit includes an inverter, a first switch, a second switch, a third switch, a fourth switch and a third comparator, wherein the inverter is configured to receive a direction control signal and generate an inverted signal of the direction control signal, a first drain / source terminal of the first switch is configured to receive the dc signal, a second drain / source terminal of the first switch is connected to a non-inverting input of the third comparator, a gate of the first switch is controlled by the direction control signal, a first drain / source terminal of the second switch is configured to receive the reference voltage proportional to the predetermined duty cycle, and a second drain / source terminal of the second switch is connected to the non-inverting input of the third comparator. input, the gate of the second switch is controlled by the inverted signal of the direction control signal, the first drain / source terminal of the third switch is configured to receive the dc signal, the second drain / source terminal of the third switch is connected to the inverting input of the third comparator, the gate of the third switch is controlled by the inverted signal of the direction control signal, the first drain / source terminal of the fourth switch is configured to receive the reference voltage proportional to the predetermined duty cycle, the second drain / source terminal of the fourth switch is connected to the inverting input of the third comparator, the gate of the fourth switch is controlled by the direction control signal, and the output of the third comparator is configured to generate the first control signal.

[0115] Although the embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0116] In addition, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, material compositions, components, methods, and steps described in the specification. As will be readily understood by a person of ordinary skill in the art from the disclosure of the present disclosure, according to the present disclosure, processes, machines, manufactures, material compositions, components, methods, or steps that currently exist or are later developed to perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein may be utilized. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, components, methods, or steps within their scope.

Claims

1. A device comprising: A clock skew calibration circuit is configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit of the clock skew calibration circuit comprises: a frequency multiplier configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signal and generate a down-clocked signal based on the clock signal, the down-clocked signal having a duty cycle indicative of a skew of the first multi-phase clock signal; and a delay line control circuit configured to compare the duty cycle of the downclocked signal with a predetermined duty cycle and generate a first control signal to adjust the skew of the first multi-phase clock signal by adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

2. The device according to claim 1, wherein the second clock skew calibration unit of the clock skew calibration circuit comprises: a first logic gate configured to perform a first AND operation on the calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal; a second logic gate configured to perform a second AND operation on the reference multi-phase clock signal and the second multi-phase clock signal; and a first comparator configured to compare the output of the first logic gate with the output of the second logic gate and to generate a second control signal to adjust the skew of the second multi-phase clock signal by adjusting a second delay applied to the second multi-phase clock signal until a calibrated signal of the second multi-phase clock signal is achieved.

3. The device according to claim 1 or 2, wherein the third clock skew calibration unit of the clock skew calibration circuit comprises: a third logic gate configured to perform a third AND operation on the calibrated signal of the first multi-phase clock signal and a third multi-phase clock signal; a fourth logic gate configured to perform a fourth AND operation on the reference multi-phase clock signal and the third multi-phase clock signal; and a second comparator configured to compare the output of the third logic gate with the output of the fourth logic gate and to generate a third control signal to adjust the skew of the third multi-phase clock signal by adjusting a third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved.

4. The apparatus according to any one of claims 1 to 3, wherein: The multi-phase clock generator is configured to generate a 4-phase clock signal including a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal, and a 270-degree clock signal, and wherein: The reference multi-phase clock signal is the 0 degree clock signal; The first multi-phase clock signal is the 180-degree clock signal; The second multi-phase clock signal is the 90 degree clock signal; and The third multi-phase clock signal is the 270 degree clock signal.

5. The apparatus of any one of claims 1 to 4, wherein the frequency multiplier comprises a first transmission gate and a second transmission gate, and wherein: An input of the first transmission gate is configured to receive the 0 degree clock signal; The output of the first transmission gate is connected to the output of the frequency multiplier; The first control terminal of the first transmission gate is configured to receive the 90 degree clock signal; The second control terminal of the first transmission gate is configured to receive the 270 degree clock signal; An input of the second transmission gate is configured to receive the 180 degree clock signal; The output of the second transmission gate is connected to the output of the frequency multiplier; The first control terminal of the second transmission gate is configured to receive the 270 degree clock signal; A second control terminal of the second transmission gate is configured to receive the 90 degree clock signal.

6. The apparatus according to any one of claims 1 to 5, wherein the first clock skew calibration unit further comprises: a latch circuit configured to generate a direction control signal; and A filter is configured to receive the down-converted signal and generate a DC signal, wherein a voltage of the DC signal is proportional to the duty cycle of the down-converted signal.

7. The apparatus of any one of claims 1 to 6, wherein the delay line control circuit comprises an inverter, a first switch, a second switch, a third switch, a fourth switch, and a third comparator, and wherein: The inverter is configured to receive the direction control signal and generate an inverted signal of the direction control signal; a first drain / source terminal of the first switch configured to receive the dc signal; a second drain / source terminal of the first switch connected to a non-inverting input of the third comparator; The gate of the first switch is controlled by the direction control signal; a first drain / source terminal of the second switch configured to receive a reference voltage proportional to the predetermined duty cycle; a second drain / source terminal of the second switch connected to the non-inverting input of the third comparator; The gate of the second switch is controlled by the inverted signal of the direction control signal; a first drain / source terminal of the third switch configured to receive the dc signal; a second drain / source terminal of the third switch connected to an inverting input of the third comparator; The gate of the third switch is controlled by the inverted signal of the direction control signal; a first drain / source terminal of the fourth switch configured to receive the reference voltage proportional to the predetermined duty cycle; a second drain / source terminal of the fourth switch connected to the inverting input of the third comparator; The gate of the fourth switch is controlled by the direction control signal; and An output of the third comparator is configured to generate the first control signal.

8. The apparatus of any one of claims 1 to 7, wherein the first delay is generated by a first delay line, and wherein the first delay line comprises: a bias circuit including an upper transistor and a lower transistor connected in series between a power supply voltage and ground; and A plurality of inverting branches are connected in parallel between the power supply voltage and ground, and each of the inverting branches comprises a first transistor, a second transistor, a third transistor and a fourth transistor connected in series, and wherein: The gate of the first transistor is connected to the gate of the upper transistor; The gate of the second transistor is connected to the gate of the third transistor and serves as the input of the inverting branch, and the midpoint of the inverting branch serves as the output of the inverting branch, and The gate of the fourth transistor is connected to the gate of the lower transistor, and wherein: An input of a first inverting branch of the plurality of inverting branches is configured to receive the first multi-phase clock signal; The output of the first inverting branch of the plurality of inverting branches is connected to the input of the second inverting branch of the plurality of inverting branches; and An output of a last inversion branch of the plurality of inversion branches is configured to generate the calibrated signal of the first multi-phase clock signal.

9. A method comprising: generating a clock signal based on a plurality of multi-phase clock signals by a frequency multiplier; generating a down-converted signal based on the clock signal by a frequency divider, the down-converted signal having a duty cycle indicating a skew of the first multi-phase clock signal; comparing the duty cycle of the frequency-reduced signal with a predetermined duty cycle; and A first control signal is generated by a delay line control circuit to adjust the skew of the first multi-phase clock signal by adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

10. The method according to claim 9, further comprising: performing a first AND operation on the calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal; performing a second AND operation on the reference multi-phase clock signal and the second multi-phase clock signal; and comparing a result of the first AND operation with a result of the second AND operation; and Based on a comparison result from the step of comparing the result of the first AND operation with the result of the second AND operation, a second control signal is generated to adjust the skew of the second multi-phase clock signal by adjusting a second delay applied to the second multi-phase clock signal until a calibrated signal of the second multi-phase clock signal is achieved.

11. The method according to claim 9 or 10, further comprising: performing a third AND operation on the calibrated signal of the first multi-phase clock signal and a third multi-phase clock signal; performing a fourth AND operation on the reference multi-phase clock signal and the third multi-phase clock signal; and comparing a result of the third AND operation with a result of the fourth AND operation; and Based on a comparison result from the step of comparing the result of the third AND operation with the result of the fourth AND operation, a third control signal is generated to adjust a skew of the third multi-phase clock signal by adjusting a third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved.

12. The method according to any one of claims 9 to 11, further comprising: A 4-phase clock signal is generated by a multi-phase clock generator, which includes a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal, and a 270-degree clock signal, wherein: The reference multi-phase clock signal is the 0 degree clock signal; The first multi-phase clock signal is the 180-degree clock signal; The second multi-phase clock signal is the 90 degree clock signal; and The third multi-phase clock signal is the 270 degree clock signal.

13. The method according to any one of claims 9 to 12, wherein the multi-phase clock generator comprises a first oscillator, a second oscillator, a third oscillator and a fourth oscillator connected in cascade, and wherein: an inverting output of the first oscillator connected to a non-inverting input of the second oscillator, wherein the inverting output of the first oscillator is configured to generate the 270 degree clock signal; The non-inverting output of the first oscillator is connected to the inverting input of the second oscillator; an inverting output of the second oscillator connected to a non-inverting input of the third oscillator, wherein the inverting output of the second oscillator is configured to generate the 180 degree clock signal; The non-inverting output of the second oscillator is connected to the inverting input of the third oscillator; an inverting output of the third oscillator connected to a non-inverting input of the fourth oscillator, wherein the inverting output of the third oscillator is configured to generate the 90 degree clock signal; The non-inverting output of the third oscillator is connected to the inverting input of the fourth oscillator; an inverting output of the fourth oscillator is connected to a non-inverting input of the first oscillator, wherein the inverting output of the fourth oscillator is configured to generate the 0 degree clock signal; and The non-inverting output of the fourth oscillator is connected to the inverting input of the first oscillator.

14. The method according to any one of claims 9 to 13, wherein: The frequency divider is a latch circuit; and The frequency multiplier comprises a first transmission gate and a second transmission gate, and wherein: An input of the first transmission gate is configured to receive the 0 degree clock signal; The output of the first transmission gate is connected to the output of the frequency multiplier; The first control terminal of the first transmission gate is configured to receive the 90 degree clock signal; The second control terminal of the first transmission gate is configured to receive the 270 degree clock signal; An input of the second transmission gate is configured to receive the 180 degree clock signal; The output of the second transmission gate is connected to the output of the frequency multiplier; The first control terminal of the second transmission gate is configured to receive the 270 degree clock signal; and A second control terminal of the second transmission gate is configured to receive the 90 degree clock signal.

15. The method according to any one of claims 9 to 14, further comprising: Converting the down-converted signal into a DC signal, wherein the voltage of the DC signal is proportional to the duty cycle of the down-converted signal; and The voltage of the dc signal is compared with a reference voltage proportional to the predetermined duty cycle to obtain the first control signal.

16. The method of any one of claims 9 to 15, wherein the delay line control circuit comprises an inverter, a first switch, a second switch, a third switch, a fourth switch, and a third comparator, and wherein: The inverter is configured to receive a direction control signal and generate an inverted signal of the direction control signal; a first drain / source terminal of the first switch configured to receive the dc signal; a second drain / source terminal of the first switch connected to a non-inverting input of the third comparator; The gate of the first switch is controlled by the direction control signal; a first drain / source terminal of the second switch configured to receive the reference voltage proportional to the predetermined duty cycle; a second drain / source terminal of the second switch connected to the non-inverting input of the third comparator; The gate of the second switch is controlled by the inverted signal of the direction control signal; a first drain / source terminal of the third switch configured to receive the dc signal; a second drain / source terminal of the third switch connected to an inverting input of the third comparator; The gate of the third switch is controlled by the inverted signal of the direction control signal; a first drain / source terminal of the fourth switch configured to receive the reference voltage proportional to the predetermined duty cycle; a second drain / source terminal of the fourth switch connected to the inverting input of the third comparator; The gate of the fourth switch is controlled by the direction control signal; and An output of the third comparator is configured to generate the first control signal.

17. A system comprising: a multi-phase clock generator configured to generate a plurality of multi-phase clock signals; a plurality of delay lines configured to receive corresponding multi-phase clock signals; and a clock skew calibration circuit configured to be coupled to the multi-phase clock generator through the plurality of delay lines, wherein the clock skew calibration circuit comprises a first clock skew calibration unit, a second clock skew calibration unit, and a third clock skew calibration unit, and wherein the first clock skew calibration unit comprises: a frequency multiplier configured to receive the plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signal and generate a down-clocked signal based on the clock signal, the down-clocked signal having a duty cycle indicative of a skew of the first multi-phase clock signal; and A delay line control circuit is configured to compare the duty cycle of the downclocked signal with a predetermined duty cycle and generate a first control signal to adjust a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

18. The system of claim 17, wherein: The second clock skew calibration unit of the clock skew calibration circuit comprises: a first logic gate configured to perform a first AND operation on the calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal; a second logic gate configured to perform a second AND operation on the reference multi-phase clock signal and the second multi-phase clock signal; and a first comparator configured to compare the output of the first logic gate with the output of the second logic gate and generate a second control signal to adjust a second delay applied to the second multi-phase clock signal until a calibrated signal of the second multi-phase clock signal is achieved; and The third clock skew calibration unit of the clock skew calibration circuit comprises: a third logic gate configured to perform a third AND operation on the calibrated signal of the first multi-phase clock signal and a third multi-phase clock signal; a fourth logic gate configured to perform a fourth AND operation on the reference multi-phase clock signal and the third multi-phase clock signal; and A second comparator is configured to compare the output of the third logic gate with the output of the fourth logic gate and generate a third control signal to adjust a third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved.

19. A system according to claim 17 or 18, wherein: The multi-phase clock generator is configured to generate a 4-phase clock signal including a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal, and a 270-degree clock signal, and wherein: The reference multi-phase clock signal is the 0 degree clock signal; The first multi-phase clock signal is the 180-degree clock signal; The second multi-phase clock signal is the 90 degree clock signal; and The third multi-phase clock signal to be calibrated is the 270 degree clock signal.

20. The system of any one of claims 17 to 19, wherein: A first delay line of the plurality of delay lines is configured to receive the 0 degree clock signal and a predetermined reference signal and to add a predetermined delay to the 0 degree clock signal based on the predetermined reference signal; a second delay line of the plurality of delay lines configured to receive the 180 degree clock signal and the first control signal and to add the first delay to the 180 degree clock signal based on the first control signal; a third delay line of the plurality of delay lines configured to receive the 90 degree clock signal and the second control signal and to add the second delay to the 90 degree clock signal based on the second control signal; and A fourth delay line of the plurality of delay lines is configured to receive the 270 degree clock signal and the third control signal, and to add the third delay to the 270 degree clock signal based on the third control signal.

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