P-GAN high electron mobility transistor field plate

Abstract

A high electron mobility transistor (HEMT) includes a source disposed on a surface, a drain disposed on the surface, a gate disposed on the surface between the source and the drain, and a first field plate disposed on the surface between the gate and the drain. In certain embodiments, the first field plate includes a p-type doped gallium nitride (P-GAN). In some embodiments, the first field plate includes a doping concentration, doping material, geometry, and / or location configured to minimize an increase in HEMT on resistance. In some embodiments, the first field plate is continuous between and extends parallel to the source and drain regions such that any path from the source to the drain passes under, through, or over the first field plate. In some embodiments, the first field plate extends continuously between the source and drain beyond the entire width of the surface.

Description

Technical Field

[0001] The present disclosure relates to transistor devices, and more particularly to field plates of high electron mobility transistor (HEMT) devices. Background Art

[0002] HEMT is a field effect transistor (FET) that uses the junction between two materials with different band gaps as the channel. This junction may be called a heterojunction, and HEMT may also be called a heterostructure FET (HFET). HEMT may also be called a modulation doped FET (MODFET). This is in contrast to the doped region that is usually used as the channel in a metal oxide semiconductor FET (MOSFET). HEMTs typically have relatively low on-resistance, high breakdown voltage, and low switching losses.

[0003] Typical HEMTs are used in power amplifiers, wireless communication systems, voltage converters, and other applications.

[0004] During operation, HEMTs generate electromagnetic fields. In some cases, the electromagnetic fields may interfere with the operation of the gate. Some HEMTs include a metal structure called a field plate to mitigate the effects of the electromagnetic fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention can be more fully understood through the following examples with reference to the accompanying drawings:

[0006] Figure 1 is a cross-sectional view of an example HEMT;

[0007] Figure 2 yes Figure 1 A cross-sectional view of an example HEMT in FIG. 1 , showing the electric field distribution;

[0008] Figure 3A is a cross-sectional view of another example HEMT;

[0009] Figure 3B yes Figure 3A A magnified view of a portion of Figure 3A Details of the example HEMT in FIG.

[0010] Figure 4 yes Figure 3A and Figure 3B A cross-sectional view of an example HEMT in FIG. 1 , showing the electric field distribution;

[0011] Figure 5 Yes Display Figure 1 and Figure 2 The AlGaN region of the HEMT shown in the figure is Figure 2 A graph of the field strength corresponding to the electric field shown;

[0012] Figure 6 Yes Display Figure 3A , Figure 3B and Figure 4 The AlGaN region of the HEMT shown in the figure is Figure 4 A graph of the field strength corresponding to the electric field shown;

[0013] Figure 7 Yes Display Figure 1 and Figure 2 The two-dimensional electron gas (2DEG) region of the HEMT shown in Figure 1 is Figure 2 A graph of the field strength corresponding to the electric field shown;

[0014] Figure 8 Yes Display Figure 3A , Figure 3B and Figure 4 The 2DEG region of the HEMT shown in Figure 4 A graph of the field strength corresponding to the electric field shown;

[0015] Fig. 9 yes Figure 3A , Figure 3B and Figure 4 a plan view of the HEMT shown; and

[0016] Fig.10 is a flow chart showing example steps for fabricating an example HEMT.

[0017] Brief Description

[0018] A high electron mobility transistor (HEMT) comprising a source disposed on a surface, a drain disposed on the surface, a gate disposed on the surface between the source and the drain, and a first field plate disposed on the surface between the gate and the drain. In certain embodiments, the first field plate comprises p-type doped GaN (P-GaN). In some embodiments, the first field plate comprises a doping concentration, doping material, geometry, and / or position configured to minimize the increase in the on-resistance of the HEMT. In certain embodiments, the first field plate extends continuously between the source region and the drain region and extends parallel to the source region and the drain region so that any path from the source to the drain passes under, through, or on the first field plate. In certain embodiments, the first field plate extends continuously between the source and the drain over the entire width of the surface. DETAILED DESCRIPTION

[0019] Certain embodiments provide a high electron mobility transistor (HEMT). The HEMT includes a source disposed on a surface, a drain disposed on the surface, a gate disposed on the surface between the source and the drain, and a first field plate disposed on the surface between the gate and the drain.

[0020] In certain embodiments, the first field plate comprises doped gallium nitride (GaN). In certain embodiments, the first field plate is at a floating voltage. In certain embodiments, the first field plate is not electrically connected to a voltage source. In certain embodiments, the second field plate is disposed on the surface between the gate and the first field plate. In certain embodiments, the second field plate is electrically connected to a voltage source. In certain embodiments, the second field plate is electrically connected to the source. In certain embodiments, the first field plate comprises GaN and has a different doping concentration, a different doping type, or a different doping material from the gate. In certain embodiments, the first field plate comprises a doping concentration, a doping material, a geometry, and / or a position configured to minimize the increase in the on-resistance of the HEMT. In certain embodiments, the first field plate is continuous. In certain embodiments, the first field plate extends continuously between the source region and the drain region and extends parallel to the source region and the drain region so that any path from the source to the drain passes under the first field plate, through the first field plate, or on the first field plate. In certain embodiments, the first field plate extends continuously between the source and the drain over the entire width of the surface. In some embodiments, the first field plate is closer to the gate than to the drain. In some embodiments, the first field plate comprises p-type doped GaN (P-GAN). In some embodiments, the first field plate comprises p-type doped aluminum gallium nitride GaN (AlGaN) or n-type doped AlGaN.

[0021] Certain embodiments provide a method for manufacturing a high electron mobility transistor (HEMT). A gate material is deposited on a surface between a source and a drain. A first field plate material is deposited on a surface between the gate material and the drain.

[0022] In certain embodiments, the gate material and the first field plate material include doped gallium nitride (GaN). In some embodiments, the first field plate material extends continuously across the surface between the source and the drain so that any path from the source to the drain passes under, through, or over the first field plate material. In certain embodiments, the first field plate material includes p-type doped GaN (P-GaN). In certain embodiments, the first field plate material includes p-type doped aluminum gallium nitride (AlGaN) or n-type doped AlGaN.

[0023] Various embodiments will now be described in detail, examples of which are shown in the accompanying drawings. Although the description is made in conjunction with these embodiments, it is understood that they are not intended to limit the claims to these embodiments. On the contrary, the purpose of the description is to cover alternatives, modifications and equivalents, which may be included in the spirit and scope of the description defined by the appended claims. In addition, in the following detailed description of the invention, many specific details are listed to provide a comprehensive understanding. However, those of ordinary skill in the art will recognize that various embodiments can be implemented without these specific details. In other cases, well-known methods, procedures, components and circuits are not described in detail to avoid unnecessarily obscuring various aspects of the present invention.

[0024] Certain terms used in the following description are for convenience only and are not limiting. Words such as "right", "left", "top" and "bottom" indicate directions in the accompanying drawings. Words such as "a" and "an" used in the claims and corresponding parts of the specification are defined to include one or more of the items referred to unless otherwise specifically stated. The term includes the words specifically mentioned above, their derivatives and words of similar meanings. The phrase "at least one" followed by a series of two or more items, such as "A, B or C", refers to any one of A, B or C, and any combination thereof. It should be noted that the partial transparency of some of the illustrations is for explanation, illustration and demonstration purposes only, and does not mean that the element itself is transparent in the final manufacturing form.

[0025] It is to be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this description. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0026] It will be understood that when an element (e.g., a layer, region, substrate, lead, clip, pad, or contact) is referred to as being "on" or "extending to" another element, it can be directly on or directly extending to the other element, and there may be intervening elements. Conversely, when an element is referred to as being "directly on" or "extending directly to" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. It will be understood that these terms encompass different orientations of elements in addition to any orientations depicted in the figures.

[0027] Relative terms such as "below" or "above" or "above" or "below" or "horizontally" or "vertically" may be used herein to describe the relationship of one element, layer or region to another element, layer or region. It will be understood that these terms also encompass different orientations of the device in addition to the orientations depicted in the figures.

[0028] These figures are not drawn to scale and may show only a portion of the structures and the layers that make up these structures. In general, these figures are symbolic simplified structures for understanding and are not intended to reproduce the physical structures in detail. In addition, manufacturing processes and operations may be performed in conjunction with the processes and operations discussed herein; that is, there may be some process operations before, between, and / or after the operations shown and described herein. In addition, the embodiments can be implemented in conjunction with these other (perhaps conventional) processes and operations without causing significant interference with them. In general, the embodiments can replace and / or supplement certain parts of traditional processes without significantly affecting the peripheral processes and operations.

[0029] The term "HEMT" is generally understood to be synonymous with the terms heterostructure FET (HFET) and modulation doped FET (MODFET). The term "HEMT" includes devices that are generally known or referred to as HEMT, HFET or MODFET.

[0030] The term "MOSFET" is generally understood as a synonym for the term insulated gate field effect transistor (IGFET), as many modern MOSFETs include a non-metallic gate and / or a non-oxide gate insulator. As used herein, the term "MOSFET" does not necessarily mean or require that a FET include a metal gate and / or an oxide gate insulator. Instead, the term "MOSFET" includes devices that are generally known or referred to as MOSFETs.

[0031] In the specification and claims of this application, the term "substantially" refers to design intent rather than physical results. Semiconductor technology has the ability to measure many aspects of semiconductors with high precision. Therefore, when measured with existing precision, generally speaking, any physical aspect of a semiconductor will not be exactly as designed. In addition, measurement technology can easily identify differences between structures that should be exactly the same. Therefore, terms such as "substantially equal" should be interpreted as equal by design, but subject to manufacturing variations and measurement precision.

[0032] Figure 11 is a cross-sectional view of an example HEMT 100. HEMT 100 includes a source contact 105, a drain contact 110, a gate 115, a substrate 120, a buffer layer 125, a channel layer 130, a barrier layer (blocking layer) 135, a dielectric 140, a gate contact 150, and a field plate 160. HEMT 100 is an enhancement mode device by way of example, but it should be noted that the principles described herein are also applicable to depletion mode HEMT devices. Certain embodiments include Figure 1 A subset of the example components, or other components. For example, some embodiments include a source, gate, and drain located on a substrate that includes a different combination of layers, or omits a field plate.

[0033] exist Figure 1 In the example of , when both the gate contact 150 and the source contact 105 are at ground potential, the HEMT 100 is in the off state; when the gate contact 150 is above a threshold voltage, the HEMT 100 is in the on state. The barrier layer 135 has a higher band gap than the channel layer 130, thus facilitating the formation of the 2DEG 170. In the on state, when the potential of the drain contact 110 is increased relative to the source contact 105, the electric field forces high-mobility electrons in the 2DEG 170 to flow from the source contact 105 to the drain contact 110, thereby allowing current to flow. Whether the 2DEG 170 exists below the gate contact 150 depends on the voltage applied to the gate contact 150. When above the threshold gate voltage, the 2DEG 170 is continuous between the source contact 105 and the drain contact 110. When below the threshold gate voltage, the 2DEG 170 is gradually depleted until the 2DEG 170 below the gate contact 150 breaks between the source contact 105 and the drain contact 110. When the gate contact 150 is below the threshold gate voltage, the 2DEG 170 is blocked so that it cannot flow between the drain contact 110 and the source contact 105, thereby preventing current from flowing and putting the HEMT 100 into an off state.

[0034] The substrate 120 may be made of any suitable material, such as silicon (Si), an engineered substrate (e.g., ), silicon carbide (SiC), gallium nitride (GaN), or any other suitable material or combination of materials, such as materials capable of supporting the growth of group III (group III) nitride materials. In this example, substrate 120 is made of QST. In certain embodiments, a nucleation layer (not shown) may be formed on substrate 120, for example, to reduce the lattice mismatch between the substrate and buffer layer 125 of HEMT 100. The nucleation layer may include any suitable material and may be formed on substrate 120 using any suitable semiconductor growth technique, such as metal oxide chemical vapor deposition (MOCVD), hybrid vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0035] Buffer layer 125 may be formed on substrate 120 (or a corresponding nucleation layer). In some embodiments, buffer layer 125 is or includes a high resistivity material. In this case, a high resistivity material is a material whose resistivity does not cause leakage current in the device to exceed a desired amount (e.g., exceed a threshold leakage current). In some embodiments, the doping concentration of such a material may be (or is approximately, or is on the order of) 1x10 15 / cm 3 (Intentionally doped or unintentionally doped). In some embodiments, the buffer layer 125 includes a doped or undoped layer of a Group III nitride material. In this example, the buffer layer 125 is made of a single layer or multiple layers of AlGaN, but any suitable Group III nitride material may be used. In some embodiments, the buffer layer 125 is doped with iron, carbon, or any other suitable dopant, for example, to reduce trap density. The buffer layer 125 can be formed on the substrate 120 (or a corresponding nucleation layer) using AlN or any suitable semiconductor growth technique (e.g., metal oxide chemical vapor deposition (MOCVD), hybrid vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE)).

[0036] The channel layer 130 can be formed on the buffer layer 125. In some embodiments, the channel layer 130 includes any suitable doped group III nitride material or undoped group III nitride material. In this example, the channel layer is made of GaN, but any suitable group III nitride material can also be used. The channel layer 130 can be formed on the buffer layer 125 using any suitable semiconductor growth technology (e.g., MOCVD, HVPE or MBE).

[0037] In some embodiments, the channel layer 130 has a thickness suitable for preventing the wafer from bending. In some embodiments, the channel layer 130 has a minimum thickness suitable for preventing the wafer from bending. In some embodiments, the thickness of the channel layer 130 is in the range of several hundred nanometers. In some embodiments, the channel layer 130 is a high resistance layer and can be made of an unintentionally doped or lowly doped material. In this case, the high resistance material is a material whose resistance does not cause the leakage current in the device to exceed the desired amount (e.g., exceed the threshold leakage current). In some embodiments, the doping concentration of such a material can be (or is approximately, or is on the order of) 1x10 15 / cm 3 (Intentionally doped or unintentionally doped). In some embodiments, channel layer 130 is or includes an n-type III-nitride material. Conceptually, some embodiments may use a p-type III-nitride material, where the device is configured to operate using a two-dimensional hole gas (2DHG).

[0038] The barrier layer 135 can be formed on the channel layer 130. As with the buffer layer 125, the barrier layer 135 can include a doped or undoped group III nitride material layer. The barrier layer 135 can be formed on the channel layer 130 using any suitable semiconductor growth technique (e.g., MOCVD, HVPE, or MBE). In this example, the barrier layer 135 includes AlGaN with a thickness in the range of 12-25 nm and an Al mole fraction of 0.18 to 0.23. In some embodiments, the thickness of the barrier layer 135 can vary between different regions of the device (e.g., the thickness of the barrier layer 135 under the gate 115 and / or the drain access region and / or the source contact 105 and / or the drain contact 110 can be different).

[0039] The gate 115 can be formed on the surface of the barrier layer 135. In some embodiments, the gate 115 includes any suitable III-nitride material. In this example, the gate 115 is made of doped GaN (p-type GaN in this example) grown on the barrier layer 135. In some embodiments, the gate 115 has a non-uniform doping concentration (p-type in this example). For example, this non-uniform doping concentration can be selected so as to form a specific electric field and depletion region within the gate 115.

[0040] The gate 115 can be formed on the surface of the barrier layer 135 using any suitable semiconductor growth technique (e.g., MOCVD, HVPE, or MBE). In some embodiments, the gate 115 is made of GaN (e.g., p-type GaN). In some embodiments, the doping concentration of the gate 115 is between 1×10 16 -1x10 20 cm 3 (For example, 2-3x10 19 cm 3 ), and the thickness of the gate 115 is in the range of 50-150nm.

[0041] The gate contact 150 is an electrode that makes Schottky or Ohmic contact with the gate 115 and is formed using any suitable metal deposition technique. The gate contact 150 is made of aluminum or any other suitable metal, metal stack, or any other conductor or conductor layer. In some embodiments, these materials are configured to provide an Ohmic contact or a Schottky contact. In some embodiments, such as Figure 1 As shown, gate contact 150 extends above barrier layer 135 in the direction of drain contact 110, but does not contact barrier layer 135 (e.g., is separated by a dielectric). In some such embodiments, the extended portion of gate contact 150 can be used as a field plate to shield gate 115 from electric fields (e.g., high electric fields, such as electric fields with strengths greater than a threshold field strength, or greater than a critical electric field (Ec In certain embodiments, E c Typically equal to or about 4 MV / cm.

[0042] The drain contact 110 is an electrode that exhibits ohmic characteristics at the barrier interface with the barrier layer 135, thereby forming a drain region. The drain contact 110 includes one or more metal layers disposed on the barrier layer 135 to form a drain region of the HEMT 100. The drain contact 110 is made of aluminum or any other suitable metal, metal stack or other conductor. The drain contact 110 includes one or more contact metal layers disposed on the barrier layer 135.

[0043] The source contact 105 is an electrode that exhibits ohmic characteristics at the barrier interface with the barrier layer 135, thereby forming a source region. The source contact 105 is made of aluminum or any other suitable metal, metal stack or other conductor. The source contact 105 includes one or more contact metal layers disposed on the barrier layer 135. In some embodiments, as Figure 1 As shown, source contact 105 extends above barrier layer 135 in the direction of drain contact 110, but does not contact barrier layer 135. In certain such embodiments, the extended portion of gate contact 150 can be used as a field plate to shield gate 115 from electric fields (e.g., high electric fields, such as those with a strength greater than a threshold field strength or greater than the E field strength of one or more layers of material). c In certain embodiments, E c Typically equal to or about 4 MV / cm. In certain embodiments, such as Figure 1 As shown, multiple layers of metal are deposited to form source contact 105, each metal layer having a portion extending above barrier layer 135 in the direction of drain contact 110 but not in contact with barrier layer 135. In certain such embodiments, the multiple extended portions of source contact 105 can be used as field plates to shield gate 115 from electric fields (e.g., high electric fields, such as those with a strength greater than a threshold field strength or greater than the E field strength of one or more layers of material). c In certain embodiments, E c Typically equal to or about 4 MV / cm. In certain such embodiments, dielectric 140 is deposited between the extensions of the metal layers of source contact 105 that form the field plates, between the field plates and gate contact 115, and between the field plates and barrier layer 135, e.g., as Figure 1 Shown

[0044] The dielectric 140 is a dielectric material such as silicon nitride (SiN), silicon dioxide (SiO2), aluminum oxide (Al2O3), any other suitable dielectric material, or any suitable combination of these or other dielectric materials. Figure 1As shown, dielectric 140 is deposited on HEMT 100 to electrically and physically isolate the structure of HEMT 100 from the environment and from each other. In some embodiments, dielectric 140 is deposited in multiple layers. For example, Figure 1 As shown, a first layer of dielectric 140 is deposited over barrier layer 135 and gate 115. In this example, the first layer of dielectric 140 is patterned, etched, or otherwise processed to expose gate 115 so that gate contact 150 can be deposited over gate 115. After gate contact 150 is deposited, a second layer of dielectric 140 is deposited to cover gate contact 150 and the first layer of dielectric 140. The various layers of dielectric 140 are patterned, etched, or otherwise processed so that a first layer of source contact 105 can be deposited over barrier layer 135, and a portion of source contact 105 can be deposited over the second layer of dielectric 140 to form field plate 160. Patterning, etching, and deposition of multiple layers of dielectric 140 can be repeated to produce the following examples: Figure 1 The various layers of dielectric 140 and other structures of the HEMT are shown, or any other suitable HEMT structure.

[0045] Figure 2 Yes Figure 1 A cross-sectional view of the example HEMT 100 shown and described further illustrates the electric field that exists when the HEMT 100 is in the off state. In this example, the HEMT 100 is an enhancement mode device. Thus, in the off state, the gate contact 150 and the source contact 105 are both at ground potential, while the drain contact 110 is at a relatively higher potential.

[0046] In this example, in the off state, the ground potential of the gate 115 prevents the 2DEG 170 from flowing from the source contact 105 to the drain contact 110 through the channel layer 130. Figure 2 As shown by the shading overlying the HEMT 100 in FIG. 1 , in the off state where the drain contact 110 has a positive voltage, the electric field in the region immediately adjacent to the gate 115 (i.e., at the edge of the gate 115) is strong. It is noteworthy that this is the case even though the field plate 160 moderates the electric field to some extent. In some cases, the strong electric field present at the edge of the gate 115 may cause or exacerbate inappropriate operating characteristics of the HEMT 100, and / or promote electron or hole capture, resulting in gate and device failure. For example, in some cases, such an electric field may reduce the device threshold voltage of the HEMT 100, generate drain-source leakage and / or gate-source-drain leakage in the HEMT 100, and / or cause gate failure during aging or degradation of the HEMT 100.

[0047] Figure 3A3 is a cross-sectional view of an example HEMT 300. HEMT 300 includes source contact 305, drain contact 310, gate 315, substrate 320, buffer layer 325, channel layer 330, barrier layer 335, dielectric 340, gate contact 350, and field plate 360. HEMT 300 also includes field plates 380 and 390.

[0048] HEMT 300 is similar to Figure 1 and Figure 2 The HEMT 100 shown and described is substantially similar, but the HEMT 300 includes two field plates, namely, a field plate 380 and a field plate 390 located on the surface of the barrier layer 335, and a structurally adaptive arrangement of the field plates 380 and 390. The HEMT 300 includes two such field plates, but it should be noted that in other embodiments, the HEMT may include only one such field plate, or include more than two such field plates.

[0049] HEMT 300 is an enhancement mode device for illustration, but it should be noted that the principles described herein are also applicable to depletion mode HEMT devices. Certain embodiments include Figure 3A A subset of the example components described, or additional components. For example, some embodiments include a source, gate, and drain located on a substrate that includes a different combination of layers, or omits a field plate.

[0050] exist Figure 3A In the example of , when both the gate contact 350 and the source contact 305 are at ground potential, the HEMT 300 is in the off state; when the gate contact 350 is above the threshold voltage, the HEMT 300 is in the on state. The barrier layer 335 has a higher band gap than the channel layer 330, thus facilitating the formation of the 2DEG 370. In the on state, when the potential of the drain contact 310 is increased relative to the source contact 305, the electric field forces high-mobility electrons in the 2DEG 370 to flow from the source contact 305 to the drain contact 310, thereby allowing current to flow. Whether the 2DEG 370 exists below the gate contact 350 depends on the voltage applied to the gate contact 350. When above the threshold gate voltage, the 2DEG 370 is continuous between the source contact 305 and the drain contact 310. When below the threshold gate voltage, the 2DEG 370 is gradually depleted until a break in the 2DEG 370 occurs below the gate contact 350 between the source contact 305 and the drain contact 310. When the gate contact 150 is below the threshold gate voltage, the 2DEG 370 is blocked from flowing between the drain contact 310 and the source contact 305, thereby preventing current from flowing and placing the HEMT 300 in an off state.

[0051] Substrate 320 may be made of any suitable material, such as silicon (Si), an engineered substrate (e.g., ), silicon carbide (SiC), gallium nitride (GaN), or any other suitable material or combination of materials, such as materials capable of supporting the growth of group III nitride materials. In this example, substrate 320 is made of QST. In certain embodiments, a nucleation layer (not shown) may be formed on substrate 320, for example, to reduce the lattice mismatch between the substrate and buffer layer 325 of HEMT 300. The nucleation layer may include any suitable material and may be formed on substrate 320 using any suitable semiconductor growth technique, such as metal oxide chemical vapor deposition (MOCVD), hybrid vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0052] Buffer layer 325 may be formed on substrate 320 (or a corresponding nucleation layer). In some embodiments, buffer layer 325 is or includes a high resistivity material. In this case, a high resistivity material is a material whose resistivity does not cause leakage current in the device to exceed a desired amount (e.g., exceed a threshold leakage current). In some embodiments, the doping concentration of such a material may be (or is approximately, or is on the order of) 1x10 15 / cm 3 (Intentionally doped or unintentionally doped). In some embodiments, the buffer layer 325 includes a doped or undoped III-nitride material layer. In this example, the buffer layer 325 is made of a single layer or multiple layers of AlGaN, but any suitable III-nitride material can also be used. The buffer layer 325 can be formed on the substrate 320 (or a corresponding nucleation layer) using any suitable semiconductor growth technique (e.g., MOCVD, HVPE or MBE).

[0053] The channel layer 330 can be formed on the buffer layer 325. In some embodiments, the channel layer 330 includes any suitable doped or undoped III-nitride material. In this example, the channel layer is made of GaN, but any suitable III-nitride material can also be used. The channel layer 330 can be formed on the buffer layer 325 using any suitable semiconductor growth technology (e.g., MOCVD, HVPE or MBE).

[0054] The field plate 380 can be formed on the surface of the barrier layer 335 using any suitable semiconductor growth technique (e.g., MOCVD, HVPE, or MBE). In some embodiments, the field plate 380 is made of GaN (e.g., p-type GaN). In some embodiments, the field plate 380 can be used as a field plate to shield the gate 315 from the influence of an electric field (e.g., a high electric field, such as an electric field with an intensity greater than a threshold field strength).

[0055] In certain embodiments, the field plate 380 is formed (eg, by patterning and / or etching) from the same layer of GaN (eg, P-GAN) material used to form the gate 315 .

[0056] In some embodiments, the doping concentration of the field plate 380 is different from the doping concentration of the gate 315. In some embodiments, the field plate 380 is doped with a doping material different from the doping material of the gate 315. In some embodiments, the doping concentration of the field plate 380 is between 1×10 16 -1x10 20 cm 3 (For example, 2-3x10 19 cm 3 ). In some embodiments, the field plate 380 is much thinner than the gate 315. In some embodiments, the thickness of the field plate 380 is or is about one-third to one-half the thickness of the gate 335. In some embodiments, the dimensions (e.g., length, height, width) of the field plate 380 are different from the dimensions of the gate 335. In some embodiments, the reduced thickness or different dimensions of the field plate 380 compared to the gate 315 is achieved by applying a mask and etching process to the field plate 380. In some embodiments, the field plate 380 is electrically connected or communicated with the source contact 305 through a metal, or otherwise maintains the same potential as the source contact 305. In some embodiments, the field plate 380 is formed of a material different from the material used to form the gate 315. For example, in the case where the gate 315 is formed of PGaN, the field plate 380 can be formed of AlGaN.

[0057] Field plate 390 can be formed on the surface of barrier layer 335. In some embodiments, field plate 390 includes any suitable III-nitride material. In this example, field plate 390 is made of doped GaN (P-type GaN in this example) grown on barrier layer 335. In some embodiments, field plate 390 has a non-uniform doping concentration (P-type in this example). For example, in some embodiments, such a non-uniform doping concentration can be selected so as to form a specific electric field and depletion region within field plate 390.

[0058] Field plate 390 can be formed on the surface of barrier layer 335 using any suitable semiconductor growth technique (e.g., MOCVD, HVPE, or MBE). In some embodiments, field plate 390 is made of GaN (e.g., p-type GaN). In some embodiments, field plate 380 acts as a field plate to shield gate 315 from electric fields (e.g., high electric fields, such as electric fields with strengths greater than a threshold field strength).

[0059] In some embodiments, field plate 390 is formed from the same layer of GaN (e.g., P-GaN) material (e.g., by patterning and / or etching) used to form gate 315 and / or field plate 380. In some embodiments, the doping concentration of field plate 390 is different from the doping concentration of gate 315. In some embodiments, field plate 390 is doped with a doping material different from the doping material of gate 315. In some embodiments, the doping concentration of field plate 390 is between 1x10 16 -1x10 20 cm 3 (For example, 2-3x10 19 cm 3 ). In some embodiments, field plate 390 is much thinner than gate 315. In certain embodiments, the thickness of field plate 390 is or is about one-third to one-half the thickness of gate 335. In certain embodiments, the dimensions (e.g., length, height, width) of field plate 390 are different from the dimensions of gate 335. In certain embodiments, the reduced thickness or different dimensions of field plate 390 compared to gate 315 is achieved by applying a mask and etching process to field plate 390 (e.g., the same process used to achieve the thickness of field plate 380).

[0060] In some embodiments, field plate 390 is floating and is not electrically connected or connected to source contact 105 through metal, nor is it otherwise maintained at the same potential as source contact 105. It is worth noting that field plate 390 is closer to drain 110 than field plate 380. In some embodiments with multiple such field plates, the field plate closest to the drain is floating and is not electrically connected or connected to ground through metal. In some embodiments with only one such field plate, the single field plate is floating and is not electrically connected or connected to ground through metal.

[0061] The gate contact 350 is an electrode that is in Schottky contact or ohmic contact with the gate 315 and is formed using any suitable metal deposition technique. The gate contact 350 is made of aluminum or any other suitable metal, metal stack, or any other conductor or conductor layer. In some embodiments, these materials are configured to provide an ohmic contact or a Schottky contact. In some embodiments, such as Figure 3A As shown, the gate contact 350 extends above the barrier layer 335 in the direction of the drain contact 310, but does not contact the barrier layer 335 (e.g., separated by a dielectric). In some embodiments, the extended portion of the gate contact 350 can be used as a field plate to shield the gate 315 from the influence of an electric field (e.g., a high electric field, such as an electric field with an intensity greater than a threshold field strength).

[0062] The drain contact 310 is an electrode that exhibits ohmic characteristics at a barrier interface with the barrier layer 335 to form a drain region. The drain contact 310 includes one or more metal layers disposed on the barrier layer 335 to form a drain region of the HEMT 300. The drain contact 310 is made of aluminum or any other suitable metal or other conductor. The drain contact 310 includes one or more contact metal layers disposed on the barrier layer 335.

[0063] The source contact 305 is an electrode that exhibits ohmic characteristics at the barrier interface with the barrier layer 335 to form a source region. The source contact 305 is made of aluminum or any other suitable metal or other conductor. The source contact 305 includes one or more contact metal layers disposed on the barrier layer 335. In some embodiments, the source contact 305 extends above the barrier layer 335 in the direction of the drain contact 310, but does not contact the barrier layer 335, such as Figure 3A In some embodiments, the extended portion of the gate contact 350 can function as a field plate to shield the gate 315 from an electric field (eg, a high electric field, such as an electric field having an intensity greater than a threshold field strength).

[0064] In certain embodiments, such as Figure 3A As shown, multiple layers of metal are deposited to form source contact 305, each metal layer having a portion extending above barrier layer 335 in the direction of drain contact 310 but not in contact with barrier layer 335. In some embodiments, the multiple extended portions of source contact 305 can be used as field plates to shield gate 315 from electric fields (e.g., high electric fields, such as electric fields with strengths greater than a threshold field strength). In some such embodiments, dielectric 340 is deposited between the extended portions of each metal layer of source contact 305 that form field plates, between the field plates and gate contact 315, and between the field plates and barrier layer 335, for example, as Figure 3A shown.

[0065] It is worth noting that in some embodiments, field plates 380 and 390 have the advantage of shielding gate 315 from electric fields more significantly (e.g., more effectively controlling the peak electric field at the edge of gate 315) than a field plate formed by field plate 360, for example due to proximity to gate 315. Therefore, in some embodiments, field plate 360 ​​is omitted. An advantage of omitting field plate 360 ​​is that parasitic capacitance between the metals of source contact 305 and drain contact 310 can be reduced.

[0066] The dielectric 340 is a dielectric material such as silicon nitride (SiN), silicon dioxide (SiO2), aluminum oxide (Al2O3) or any other suitable dielectric material. Figure 3AAs shown, dielectric 340 is deposited on HEMT 300 to electrically and physically isolate the structures of HEMT 300 from the environment and from each other. In certain embodiments, dielectric 340 is deposited in multiple layers. For example, Figure 3A As shown, a first layer of dielectric 340 is deposited over barrier layer 335 and gate 315. In this example, the first layer of dielectric 340 is patterned, etched, or otherwise processed to expose gate 315 so that gate contact 350 can be deposited over gate 315. After gate contact 350 is deposited, a second layer of dielectric 340 is deposited to cover gate contact 350 and the first layer of dielectric 340. The various layers of dielectric 340 are patterned, etched, or otherwise processed so that a first layer of source contact 305 can be deposited over barrier layer 335, and a portion of source contact 305 can be deposited over the second layer of dielectric 340 to form field plate 360. Patterning, etching, and deposition of multiple layers of dielectric 340 can be repeated to produce the following examples: Figure 3A The various layers of dielectric 340 and other structures of the HEMT are shown, or any other suitable HEMT structure.

[0067] Figure 3B is an enlarged view of HEMT 300 showing other structures. Figure 3B As shown, a metal contact 385 is deposited on the field plate 380. The metal contact 385 establishes an electrical connection between the field plate 380 and the source contact 305 through a metal layer (the connecting portion of the metal contact 385 is not shown).

[0068] Figure 4 3 is a cross-sectional view of the example HEMT of FIG3, further illustrating the electric field that exists when the HEMT 300 is in the off state. In this example, the HEMT 300 is an enhancement mode device. Therefore, in the off state, the gate contact 350 and the source contact 305 are both at ground potential, while the drain contact 310 is at a relatively high potential.

[0069] In this example, in the off state, the ground potential of the gate 315 prevents the 2DEG 370 from flowing from the drain contact 310 to the source contact 305 through the channel layer 330. Figure 4As shown in the shaded HEMT 300, in the off state with the drain contact 310 having a positive voltage, the electric field is strong in the region immediately adjacent to the field plate 390, but substantially absent in the region of the gate 315. In some cases, this is due to the shielding effect of the field plates 390 and / or 380. In some cases, this may be advantageous in preventing or reducing undesirable operating characteristics of the HEMT 300 and / or electron or hole capture that may otherwise be caused or exacerbated by the strong electric field present at the edge of the gate 315. For example, in some cases, this may be advantageous in preventing a decrease in the device threshold voltage of the HEMT 300, avoiding drain-source leakage and / or gate-source-drain leakage in the HEMT 300, avoiding gate damage during aging or aging of the HEMT 300, and / or avoiding electron or hole capture that may cause gate and device failure.

[0070] Figure 5 is a graph showing the HEMT 100 at the boundary between the barrier layer 135 and the dielectric 140 due to Figure 2 The electric field strength is plotted in relation to the distance from the edge of the gate 115 in the direction of the drain 110. The peak field strength 500 is marked in the figure. Figure 6 is a graph showing the HEMT 300 at the boundary of the barrier layer 335 and the dielectric 340 due to Figure 4 The electric field strength is plotted in relation to the distance from the edge of the gate 315 in the direction of the drain 310. The peak field strength 600 is marked in the figure.

[0071] It is noteworthy that the distance between gate 315 and the electric field at peak field strength 600 is greater than the distance between gate 115 and the electric field at peak field strength 500. Also, peak field strength 600 is lower than peak field strength 500. In some embodiments, this difference is due to the shielding effect of field plates 390 and / or 380. In some embodiments, the increased distance between gate 315 and peak field strength 600 has the advantage of preventing or reducing undesirable operating characteristics of HEMT 300 that might otherwise be caused or exacerbated by the presence of strong electric fields at the edges of gate 315.

[0072] Figure 7 is a graph showing the HEMT 100 at the 2DEG 170 due to Figure 2 The electric field strength is plotted in relation to the distance from the edge of the gate 115 in the direction of the drain 110. The peak field strength 700 is marked in the figure. Figure 8 is a graph showing the HEMT 300 at the 2DEG 170 due to Figure 4 The electric field strength is plotted in relation to the distance from the edge of the gate 315 in the direction of the drain 310. The peak field strength 800 is marked in the figure.

[0073] It is noted that the distance between gate 315 and the electric field at peak field strength 800 is greater than the distance between gate 115 and the electric field at peak field strength 700. In some embodiments, this difference is due to the shielding effect of field plates 390 and / or 380. In some embodiments, the increased distance between gate 315 and peak field strength 800 has the advantage of preventing or reducing undesirable operating characteristics of HEMT 300 that might otherwise be caused or exacerbated by the presence of strong electric fields at the edges of gate 315. It is noted that in some embodiments, this is true even if peak field strength 800 is higher than peak field strength 700 (e.g., due to the increased distance from gate 315).

[0074] Fig. 9 Yes Figure 3A , Figure 3B and Figure 4 A plan view of the HEMT 300 shown and described. A cross section A shows Figure 3A , Figure 3B and Figure 4 For clarity, Fig. 9 Several features of HEMT 300 are omitted. Fig. 9 As shown, field plates 380 and 390 are continuous and completely across (in the vertical direction, as shown in FIG. Fig. 9 HEMT 300 is extended so that between source 305 and drain 310 along (in the horizontal direction, as shown in FIG. Fig. 9 Any path through HEMT 300 (shown) passes under, through, or over field plates 380 and 390. In certain embodiments, the continuity of field plates 380 and 390 has the advantage of preventing or reducing the effect of a strong electric field on gate 315 when HEMT 300 is in the off state and the voltage of drain 310 is increased.

[0075] Fig.10 is a flow chart showing an example process 1000 of steps for fabricating an example HEMT. For example, some or all of the steps of process 1000 may be used to fabricate HEMT 300 as shown and described above.

[0076] In this example, the HEMT is formed on a substrate. The substrate may be a silicon (Si) substrate, a QST substrate, a silicon carbide (SiC), a gallium nitride (GaN), or any other material or combination of materials that can support the growth of a III-nitride material. In some embodiments, the substrate 120 of the HEMT 300 corresponds to such a substrate.

[0077] In step 1005, a nucleation layer is formed on the substrate material. In some embodiments, this has the advantage of reducing the lattice mismatch between the substrate and the next layer in the HEMT. The nucleation layer may include any suitable material (e.g., aluminum nitride (AlN)) and may be formed on the substrate using any suitable semiconductor growth technique (e.g., MOCVD, HVPE, or MBE). In some embodiments, the nucleation layer formed on the substrate 120 of the HEMT 300 corresponds to this step.

[0078] In step 1010, a buffer layer is formed on the nucleation layer. In some embodiments, the buffer layer is a high resistivity layer, which may include a doped or undoped III-nitride material layer. In some embodiments, the buffer layer is composed of a plurality of AlGaN layers. The buffer layer may be formed on the nucleation layer using any suitable semiconductor growth technique (e.g., MOCVD, HVPE, or MBE). In some embodiments, the buffer layer 125 of the HEMT 300 corresponds to this step.

[0079] In step 1015, a channel layer is formed on the buffer layer. In certain embodiments, the channel layer is made of a doped or undoped III-nitride material. In certain embodiments, the channel layer is made of GaN. The channel layer can be formed on the buffer layer using any suitable semiconductor growth technique (e.g., MOCVD, HVPE, or MBE). In certain embodiments, the thickness of the channel layer is in the range of several hundred nanometers. In certain embodiments, the channel layer is a high resistance layer and can be made of an unintentionally doped or low-doped material. In certain embodiments, the channel layer is or includes an n-type III-nitride material. In certain embodiments, the channel layer 130 of the HEMT 300 corresponds to this step.

[0080] In step 1020, a barrier layer is formed on the channel layer. The barrier layer may include a doped or undoped group III nitride material layer. The barrier layer may be formed on the channel layer using any suitable semiconductor growth technique (e.g., MOCVD, HVPE, or MBE). The thickness and composition of the barrier layer may be selected to obtain a positive threshold voltage. In certain embodiments, the thickness and composition of the barrier layer are selected to provide a larger band gap than the channel layer, typically the Al mole fraction of AlGaN of the barrier layer is 0.18 to 0.23. In this example, the barrier layer includes (or is composed of) AlGaN having a thickness in the range of 12-25 nm. In certain embodiments, the barrier layer 135 of the HEMT 300 corresponds to this step.

[0081] In step 1025, a GaN layer is formed on the barrier layer. In some embodiments, the GaN layer includes any suitable III-nitride material. In this example, the GaN layer is composed of doped GaN (p-type GaN in this example) grown on the barrier layer. In some embodiments, the GaN layer has a non-uniform doping concentration (p-type in this example). In some embodiments, this non-uniform doping concentration is selected to form a specific electric field and depletion region in the GaN layer.

[0082] The GaN layer can be formed on the barrier layer 135 using any suitable semiconductor growth technique (e.g., MOCVD, HVPE, or MBE). In step 1030, the GaN layer is etched to define a gate region and one or more field plate regions adjacent to but not connected to the gate. In some embodiments, a mask layer is defined and masking and etching processes are performed so that the field plate GaN region is much thinner than the gate GaN region. In some embodiments, the field plate GaN thickness is half to one-third of the gate GaN thickness. In some embodiments, the doping concentration of the gate GaN region is between 1x10 16 -1x10 20 cm 3 (For example, 2-3x10 19 cm 3 ) and the thickness is in the range of 50-150 nm. In certain embodiments, the gate region 315 and field plates 380 and 390 of the HEMT 300 correspond to this step.

[0083] In step 1035, the HEMT is electrically isolated from other inactive regions of the device or other devices on the substrate. In certain embodiments, this is achieved based on muon etching or ion implantation (e.g., nitrogen or argon) outside the active HEMT.

[0084] In step 1040, a dielectric layer is deposited on the surface of the structure. In some embodiments, the dielectric layer is a dielectric material such as silicon nitride (SiN), silicon dioxide (SiO2), aluminum oxide (Al2O3), or any other suitable dielectric material. In some embodiments, the dielectric layer is deposited on the HEMT to electrically and physically isolate the structure of the HEMT from the environment and from each other. In some embodiments, the dielectric layer is deposited in multiple layers. In some embodiments, the dielectric 340 of the HEMT 300 corresponds to this step.

[0085] In step 1045, after masking and etching the dielectric layer, metal source and drain electrodes are formed in ohmic contact with the barrier layer. In some embodiments, pre-deposition and / or post-deposition treatment and annealing processes may be used. In some embodiments, the source contact 305 and drain contact 310 of the HEMT 300 correspond to this step.

[0086] In step 1050, a metal gate electrode is formed on the GaN gate region. In some embodiments, the metal gate electrode is a Schottky or Ohmic gate metal contact formed on the GaN gate region after masking and etching the dielectric layer. In some embodiments, pre-deposition and / or post-deposition treatment and annealing processes may be used. In some embodiments, the gate contact 350 of the HEMT 300 corresponds to this step. It should be noted that in some embodiments, the order of forming the source, drain, and gate metal contacts (e.g., steps 1045 and 1050) can be reversed.

[0087] In step 1055, one or more field plates are formed on the barrier layer. In some embodiments, the field plates include any suitable III-nitride material, such as GaN or AlGaN. For example, in some embodiments, the field plates are composed of doped GaN (p-type GaN in this example) grown on the barrier layer. In some embodiments, the field plates have a non-uniform doping concentration. In some embodiments, this non-uniform doping concentration is selected to form a specific electric field and depletion region within the field plate.

[0088] In some embodiments, the field plate can be formed on the barrier layer using any suitable semiconductor growth technique (e.g., MOCVD, HVPE, or MBE). In some embodiments, the field plate is made of GaN (e.g., p-type GaN). In some embodiments, the field plate can shield the gate region and / or the gate contact from the influence of the electric field (e.g., a high electric field, such as an electric field with an intensity greater than the threshold field strength). In some embodiments, the field plate is formed of the same layer of GaN (e.g., P-GAN) material (e.g., by patterning and / or etching) used to form the GaN gate region.

[0089] In some embodiments, the doping concentration of the field plate is different from the doping concentration of the gate region. In some embodiments, the field plate is doped with a doping material different from the doping material of the gate region. In some embodiments, the doping concentration of the field plate is between 1×10 16 -1x10 20 cm 3 (For example, 2-3x10 19 cm 3 ). In some embodiments, the field plate is much thinner than the gate region. In some embodiments, the thickness of the field plate is or is about one-third to one-half the thickness of the gate region. In some embodiments, the size (e.g., length, height, width) of the field plate is different from the size of the gate region. In some embodiments, the reduced thickness or different size of the field plate compared to the gate region is achieved by applying a mask and etching process to the field plate.

[0090] In certain embodiments, field plates 380 and 390 of HEMT 300 correspond to this step.

[0091] In step 1060, one or more of the field plates are electrically connected to a voltage reference. In some embodiments, some of the field plates are electrically connected or communicated with the source contact 305 through a metal, or otherwise maintain the same potential with the source contact 305, while other field plates are floating and not connected to a fixed voltage source or reference. In some embodiments, the field plate closest to the drain region of the plurality of field plates is floating, while one or more of the other field plates are electrically connected to a voltage reference (e.g., source or ground). In some embodiments, only one field plate is floating. In some embodiments, the field plate closest to the gate is grounded (i.e., at source potential), for example, to prevent the field plate from obtaining an excessively high potential.

[0092] In step 1065, a dielectric layer (e.g., SiN, SiO2, or Al2O3) is deposited on the barrier region between the gate and the source, between the gate and the field plate, between the field plate and the drain, and locally on the source and drain. In some embodiments, the dielectric layer electrically and physically isolates the structure of the HEMT from the environment and from each other. In some embodiments, the dielectric layer is deposited in multiple layers. In some embodiments, the dielectric 340 of the HEMT 300 corresponds to this step.

[0093] It should be understood that there are many variations according to the disclosure herein. Although features and elements are described above in particular combinations, each feature or element can be used alone without other features and elements, and can also be used in various combinations with or without other features and elements.

Claims

1. A high electron mobility transistor (HEMT), comprising: a source electrode disposed on the surface; a drain electrode disposed on the surface; a gate disposed on the surface between the source and the drain; as well as A first field plate is disposed on the surface between the gate and the drain.

2. The HEMT according to claim 1, wherein: The first field plate includes doped gallium nitride (GaN).

3. The HEMT according to claim 1, wherein: The first field plate is at a floating voltage.

4. The HEMT according to claim 1, wherein: The first field plate is not electrically connected to a voltage source. 5 . The HEMT of claim 1 , further comprising a second field plate disposed on the surface between the gate and the first field plate.

6. The HEMT according to claim 5, wherein: The second field plate is electrically connected to a voltage source.

7. The HEMT according to claim 5, wherein: The second field plate is electrically connected to the source.

8. The HEMT according to claim 1, wherein: The first field plate includes GaN and has a different doping concentration, a different doping type, or a different doping material than the gate.

9. The HEMT according to claim 1, wherein: The first field plate includes a doping concentration, doping material, geometry, and / or location configured to minimize an increase in an on-resistance of the HEMT.

10. The HEMT according to claim 1, wherein: The first field plate is continuous.

11. The HEMT according to claim 1, wherein: The first field plate is continuous between and extends parallel to the source and drain regions such that any path from the source to the drain passes under, through, or on the first field plate.

12. The HEMT according to claim 1, wherein: The first field plate extends continuously between the source and the drain over an entire width of the surface.

13. The HEMT according to claim 1, wherein: The first field plate is closer to the gate than to the drain.

14. The HEMT according to claim 1, wherein: The first field plate includes p-type doped GaN (P-GaN).

15. The HEMT according to claim 1, wherein: The first field plate includes p-type doped aluminum GaN (AlGaN) or n-type doped AlGaN.

16. A method for manufacturing a high electron mobility transistor (HEMT), the method comprising: depositing a gate material on the surface between the source and drain electrodes; as well as A first field plate material is deposited on the surface between the gate material and the drain.

17. The method according to claim 16, wherein: The gate material and the first field plate material include doped gallium nitride (GaN).

18. The method according to claim 16, wherein: The first field plate material extends continuously across the surface between the source and the drain such that any path from the source to the drain passes under, through, or over the first field plate material.

19. The method according to claim 16, wherein: The first field plate material includes p-type doped GaN (P-GaN).

20. The method according to claim 16, wherein: The first field plate material includes p-type doped aluminum GaN (AlGaN) or n-type doped AlGaN.

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