Solid-state imaging element, method for manufacturing solid-state imaging element, and electronic apparatus

Abstract

The present disclosure relates to a solid-state imaging element capable of obtaining higher image quality, a method of manufacturing the solid-state imaging element, and an electronic device. The solid-state imaging element includes: a plurality of pixels; a capacitor provided for each of the plurality of pixels, the capacitor being formed in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; and a separation section that electrically separates the capacitors of the pixels adjacent to each other. In addition, the separation portion is provided for each of the plurality of pixels so as to surround the capacitor. In addition, an interlayer insulating film is provided between the separation portions of each of the pixels. The present technology can be applied, for example, to a CMOS image sensor.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging element, a method for manufacturing the solid-state imaging element, and an electronic device, and more particularly to a solid-state imaging element, a method for manufacturing the solid-state imaging element, and an electronic device capable of achieving higher image quality. Background Art

[0002] Conventionally, as the area of ​​a memory cell decreases along with the miniaturization of a dynamic random access memory (DRAM) element, development of a technology for increasing the capacitance by forming a capacitor in a three-dimensional shape has been advanced.

[0003] For example, Patent Document 1 discloses a DRAM element having a structure in which one memory cell region having a plurality of capacitor elements is separated from a peripheral circuit region by a trench formed in a peripheral portion of the memory cell region. Citation list Patent Literature

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2010-287716 Summary of the invention Technical Problems to be Solved by the Invention

[0005] By the way, for example, it has been considered to improve image quality by applying the capacitor having a three-dimensional shape used in the memory cell disclosed in the above-mentioned Patent Document 1 to a CMOS (Complementary Metal Oxide Semiconductor) image sensor. However, since there is no electrical separation between the capacitors having a three-dimensional shape, it is conceivable that the capacitors having a three-dimensional shape of pixels adjacent to each other are electrically connected to each other, and such capacitors are difficult to apply to CMOS image sensors.

[0006] The present disclosure has been made in view of the above-described situation, and the present disclosure aims to achieve higher image quality. Technical solutions to technical problems

[0007] According to one aspect of the present disclosure, a solid-state imaging element includes: a plurality of pixels; a capacitor provided for each of the plurality of pixels and formed in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; and a separation portion that electrically separates the capacitors of the pixels adjacent to each other.

[0008] According to one aspect of the present disclosure, a method for manufacturing a solid-state imaging element includes: forming a capacitor, which is provided for each of a plurality of pixels and is formed in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; and forming a separation portion, which electrically separates the capacitors of the pixels adjacent to each other.

[0009] An electronic device according to one aspect of the present disclosure includes a solid-state imaging element, which includes: a plurality of pixels; a capacitor, which is provided for each of the plurality of pixels and is formed in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; and a separation portion, which electrically separates the capacitors of the pixels adjacent to each other.

[0010] In one aspect of the present disclosure, for each of a plurality of pixels, a capacitor having a three-dimensional shape is provided between an upper wiring and a lower wiring of a wiring layer of the pixel, and capacitors of adjacent pixels are electrically isolated from each other by a separator. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a circuit diagram showing one embodiment of a pixel included in an image pickup element to which the present technology is applied. Figure 2 is a diagram showing a configuration example of a MIM capacitor in a plan view. Figure 3 is a diagram showing a configuration example of a MIM capacitor in a cross-sectional view. Figure 4 is a schematic diagram illustrating the first step. Figure 5 is a schematic diagram for explaining the second step. Figure 6 is a schematic diagram for explaining the third step. Figure 7 is a schematic diagram for explaining the fourth step. Figure 8 is a schematic diagram for explaining the fifth step. Fig. 9 is a schematic diagram for explaining the sixth step. Fig.10 is a schematic diagram for explaining the seventh step. Fig.11 is a schematic diagram for explaining the eighth step. Fig.12 is a cross-sectional view showing a modified example of the MIM capacitor. Fig.13 is a block diagram showing a configuration example of an image pickup device. Fig.14 is a diagram showing a usage example when an image sensor is used. DETAILED DESCRIPTION

[0012] Specific embodiments to which the present technology is applicable will be described in detail below with reference to the accompanying drawings.

[0013] <Pixel Structure Example> Will refer to Figures 1 to 3 An implementation scheme of pixels included in an image pickup element to which the present technology is applied will be described.

[0014] Figure 1 A circuit diagram of a pixel 11 is shown.

[0015] like Figure 1 As shown, the pixel 11 includes a photoelectric converter 12, a transfer transistor 13, a first FD (floating diffusion) section 14, a connection transistor 15, a second FD section 16, a MIM capacitor 17, a reset transistor 18, an amplifier transistor 19, and a selection transistor 20, and outputs a pixel signal via a vertical signal line 21. For example, the pixel 11 is a LOFIC (Lateral Over Flow Integration Capacitor) pixel, and has a structure in which, when light exceeding the saturation capacity of the photoelectric converter 12 is irradiated, charges overflowing from the photoelectric converter 12 are guided in the lateral direction and accumulated in the MIM capacitor 17.

[0016] The photoelectric converter 12 has a grounded anode terminal and a cathode terminal connected to the first FD portion 14 via the transfer transistor 13. The photoelectric converter 12 receives light irradiated onto the light receiving surface of the imaging element and converts the light into charges corresponding to the light amount of the light by photoelectric conversion.

[0017] The transfer transistor 13 is arranged to connect the photoelectric conversion portion 12 and the first FD portion 14. Then, the transfer transistor 13 is driven according to the transfer signal TG, and transfers the charge obtained by the photoelectric conversion portion 12 through photoelectric conversion to the first FD portion 14.

[0018] The first FD portion 14 accumulates the charge transferred from the photoelectric conversion portion 12 via the transfer transistor 13 to convert the charge into a pixel signal.

[0019] The connection transistor 15 is configured to connect the first FD portion 14 and the second FD portion 16. Then, the connection transistor 15 is driven according to the connection signal FDG, and turns on / off the connection between the first FD portion 14 and the second FD portion 16.

[0020] In a state where the connection transistor 15 is turned on, the second FD portion 16 is connected to the first FD portion 14 , and accumulates electric charge together with the first FD portion 14 .

[0021] The MIM capacitor 17 is a capacitor having a MIM (metal-insulator-metal) structure provided in the wiring layer of the imaging element, and is configured to connect the second FD portion 16 and the signal wiring MIMVDD. Thus, the MIM capacitor 17 accumulates electric charge similarly to the second FD portion 16. In addition, the MIM capacitor 17 has a plurality of cylinder shapes (as will be described later). Figure 2 and Figure 3 As described above, in the cylinder shape, a dielectric film is sandwiched between a cylindrical upper electrode and a cylindrical lower electrode.

[0022] The reset transistor 18 is arranged to connect the second FD portion 16 and the power wiring VDD. Then, the reset transistor 18 is driven according to the reset signal RST, and when both the connection transistor 15 and the reset transistor 18 are turned on, the charges accumulated in the first FD portion 14, the second FD portion 16 and the MIM capacitor 17 are discharged to the power wiring VDD, whereby the charges are reset.

[0023] The amplifying transistor 19 is arranged so that its gate electrode is connected to the first FD portion 14, and the amplifying transistor 19 connects the power supply wiring VDD and the selecting transistor 20. Thus, the amplifying transistor 19 converts the charge accumulated by the first FD portion 14 or the charge accumulated by the first FD portion 14, the second FD portion 16, and the MIM capacitor 17 into a pixel signal having a level corresponding to the charge for each capacity.

[0024] The selection transistor 20 is arranged to connect the amplifier transistor 19 and the vertical signal line 21. Then, the selection transistor 20 is driven according to the selection signal SEL, and the pixel signal converted by the amplifier transistor 19 is output to the vertical signal line 21 when the selection transistor 20 is turned on.

[0025] For example, in the pixel 11, when the connection transistor 15 is turned off according to the connection signal FDG, the charge transferred from the photoelectric conversion section 12 via the transfer transistor 13 is accumulated only in the capacity of the first FD section 14. In addition, when the connection transistor 15 is turned on according to the connection signal FDG, the charge transferred from the photoelectric conversion section 12 via the transfer transistor 13 is accumulated in the capacity obtained by combining the first FD section 14, the second FD section 16, and the MIM capacitor 17. As described above, the pixel 11 has a structure provided with the MIM capacitor 17, and the pixel 11 having such a structure can switch the capacity for accumulating the charge transferred from the photoelectric conversion section 12.

[0026] Will refer to Figure 2 and Figure 3 A configuration example of the MIM capacitor 17 will be described.

[0027] Figure 2 Schematic configuration examples of MIM capacitors 17-1 and 17-2 included in two adjacent pixels 11-1 and 11-2 are shown by observing them in a plan view. Note that the pixels 11-1 and 11-2 are similarly configured and are referred to simply as pixels 11 when there is no need to distinguish between them, and the respective parts constituting the pixels 11 are similarly referred to as such.

[0028] As described above, the MIM capacitor 17 has a structure including a plurality of cylinder shapes. Figure 2 , a plurality of circles shown in a region surrounded by a dotted line representing the MIM capacitor 17 represent a plurality of cylinder shapes. Note that the cylinder shape of the MIM capacitor 17 is not limited to a circular shape, and may be a rectangular shape, for example.

[0029] Furthermore, the pixel 11 is configured such that a separation structure 31 is provided so as to surround the outer periphery of the MIM capacitor 17, and an interlayer insulating film 32 is provided between the separation structures 31. Therefore, the MIM capacitors 17 of the adjacent pixels 11 are electrically and physically separated from each other by the separation structure 31 and the interlayer insulating film 32. That is, Figure 2 As shown, the MIM capacitor 17 - 1 of the pixel 11 - 1 and the MIM capacitor 17 - 2 of the pixel 11 - 2 are separated by separation structures 31 - 1 and 31 - 2 and an interlayer insulating film 32 .

[0030] In addition, between the pixels 11, a through electrode 33 is arranged so as to penetrate the interlayer insulating film 32. Figure 3 As described above, the slit 34 is provided in the pixel 11 .

[0031] Figure 3There is shown a schematic configuration example of the MIM capacitors 17 - 1 and 17 - 2 included in the adjacent two pixels 11 - 1 and 11 - 2 as viewed in a cross-sectional view.

[0032] like Figure 3 As shown, the MIM capacitor 17 is formed in a three-dimensional shape between the lower wiring 41 and the upper wiring 42, and the MIM capacitor 17 and the upper wiring 42 are connected via the electrode 43. For example, the MIM capacitor 17 is arranged in the wiring layer of the pixel 11 (the wiring layer on the sensor substrate side or the wiring layer on the logic substrate side). In addition, the insulating film 44 is provided at the lower end portion of the MIM capacitor 17, and the insulating film 45 is provided at the upper end portion of the MIM capacitor 17. For example, silicon nitride can be used for the insulating film 44 and the insulating film 45. In addition, the insulating film 45 is formed to be partially opened using the slit 34.

[0033] The MIM capacitor 17 is constructed by arranging the upper electrodes 53a and 53b to face the two surfaces of the lower electrode 51, respectively. Thus, the MIM capacitor 17 is constructed such that the dielectric film 52a is sandwiched between one surface of the lower electrode 51 and the upper electrode 53a, and the dielectric film 52b is sandwiched between the other surface of the lower electrode 51 and the upper electrode 53b. In addition, the lower electrode 51 is connected to the lower wiring 41, and the upper electrodes 53a and 53b are connected to the upper wiring 42 via the electrode 43.

[0034] For example, the MIM capacitor 17 is configured such that the lower electrode 51 is formed in a concave shape along each concave portion having a high aspect ratio for forming a cylinder shape, the dielectric film 52a is formed on the inner side of the lower electrode 51, and the upper electrode 53a is buried on the inner side of the dielectric film 52a. In addition, the MIM capacitor 17 is configured such that the dielectric film 52b is formed on the outer side of each lower electrode 51 for forming a cylinder shape, and the upper electrode 53b is buried on the outer side of the dielectric film 52b between the cylinder shapes adjacent to each other. For example, titanium nitride can be used for the lower electrode 51 and the upper electrode 53, and a high-k (high dielectric constant) film (for example, a ZrO / AlO / ZrO stacked film) can be used for the dielectric film 52.

[0035] Separation structures 31 are provided on the outer periphery of the MIM capacitor 17 , and an interlayer insulating film 32 is provided between the separation structures 31 adjacent to each other.

[0036] The separation structure 31 is constructed by embedding a material having a selectivity ratio with respect to SiO2 constituting the interlayer insulating film 32 in a groove formed by wet etching so as to penetrate the interlayer insulating film 32 and surrounding the MIM capacitor 17. For example, silicon nitride or silicon carbide (SiN, SiC (N) film) can be used as a material for constituting the separation structure 31. In addition, as a material for constituting the separation structure 31, a metal (for example, Ti, Ta, W, Mo, Al, Cu, Co, Ni, Ru, etc.) can be used, or a compound containing the metal (for example, TiN, TaN, WN, MoN) can be used.

[0037] The through electrode 33 is provided between the MIM capacitors 17, and the lower wiring 41-3 and the upper wiring 42-3 are electrically connected to each other through the through electrode 33. As a material for constituting the through electrode 33, tungsten can be used, for example.

[0038] The pixel 11 constructed as described above can electrically separate the MIM capacitor 17 from the MIM capacitors 17 of other pixels 11 adjacent to the pixel. That is, even when the MIM capacitor 17 is applied to a CMOS image sensor, it is possible to prevent the MIM capacitors 17 from being connected to each other. In addition, since the pixel 11 adopts the MIM capacitor 17 having a three-dimensional structure using a cylinder shape, a higher capacitance can be achieved compared to a MIM capacitor having a two-dimensional structure, for example.

[0039] Therefore, for example, an image sensor including the pixel 11 can achieve an expansion of the dynamic range when capturing a high dynamic range (HDR: high dynamic range) image, and can capture an image with higher image quality.

[0040] <Method for Manufacturing Imaging Element> Will refer to Figures 4 to 11 The steps for forming the MIM capacitor 17 in the method of manufacturing the imaging element will be described.

[0041] In the first step, if Figure 4 As shown, the lower wiring 41 and the insulating film 44 are formed on the lower side of the interlayer insulating film 32 , and the insulating film 45 is formed on the upper side of the interlayer insulating film 32 .

[0042] In the second step, if Figure 5 As shown, the insulating film 45 is opened, a trench is formed through the interlayer insulating film 32 to the insulating film 44 by wet etching, and the material having a selectivity with respect to SiO 2 as described above is buried in the trench, thereby forming the separation structure 31 .

[0043] In the third step, if Figure 6 As shown, a plurality of recesses 61 in a cylinder shape for forming the MIM capacitor 17 are formed so as to penetrate the interlayer insulating film 32, the insulating film 44, and the insulating film 45. That is, a plurality of recesses 61 are formed so that the lower wiring 41 is exposed on the bottom surface of each recess 61.

[0044] In the fourth step, if Figure 7 As shown in FIG. 1 , a plurality of lower electrodes 51 are formed by forming a titanium nitride film on the side surfaces and the bottom surface of each of the plurality of recesses 61. That is, the lower electrodes 51 are formed in a concave shape along the shape of the recesses 61.

[0045] In the fifth step, if Figure 8 As shown in the figure, after the slits 34 are processed for the insulating film 45, the interlayer insulating film 32 is selectively etched back to remove the interlayer insulating film 32 inside the separation structure 31. That is, the interlayer insulating film 32 between the plurality of lower electrodes 51 is removed through the slits 34, so that only the interlayer insulating film 32 between the interlayer insulating films 32 adjacent to each other remains. At this time, the upper end of each lower electrode 51 is supported by the insulating film 45.

[0046] In the sixth step, if Fig. 9 As shown, a dielectric is formed on both surfaces of the lower electrode 51 . Therefore, the dielectric film 52 a is formed inside the concave shape of the lower electrode 51 , and the dielectric film 52 b is formed outside the concave shape of the lower electrode 51 .

[0047] In the seventh step, if Fig.10 As shown, titanium nitride is deposited on both surfaces of the lower electrode 51. Thus, the upper electrode 53a is formed with the lower electrode 51 sandwiching the dielectric film 52a, and the upper electrode 53b is formed with the lower electrode 51 sandwiching the dielectric film 52b.

[0048] In the eighth step, if Fig.11 As shown, after the interlayer insulating film 32 is stacked, tungsten is buried in a groove formed between the adjacent separation structures 31 so as to penetrate the interlayer insulating film 32, the insulating film 44 and the insulating film 45 until the lower wiring 41-3 is exposed, thereby forming a through electrode 33. In addition, the electrode 43 is formed to be connected to the upper electrode 53a.

[0049] Thereafter, the upper wiring 42 is formed to be connected to each of the electrode 43 and the through electrode 33, thereby forming the above-mentioned Figure 3 The MIM capacitor 17 is shown.

[0050] The MIM capacitor 17 formed through the above steps can improve mechanical strength, for example, by supporting each lower electrode 51 with the insulating film 45. In addition, when selectively etching back the interlayer insulating film 32, the etching can be stopped by the separation structure 31.

[0051] <Modified Example of MIM Capacitor> Fig.12 FIG. is a cross-sectional view showing an example of a modified example of the MIM capacitor 17.

[0052] As described above, in Figure 3 the MIM capacitor 17 shown, the separation structure 31 is constructed by burying a material having a selectivity ratio with respect to SiO2 used to form the interlayer insulating film 32 into a trench formed so as to penetrate the interlayer insulating film 32.

[0053] In contrast, in Fig.12 the MIM capacitor 17A shown, the separation structure 31A is formed of the same material as the materials of the lower electrode 51, the upper electrode 53a, and the dielectric film 52a, respectively. That is, in the MIM capacitor 17A, the separation structure 31A is formed of a stacked structure in which a metal for forming the lower electrode 51, a dielectric for forming the dielectric film 52a, and a metal for forming the upper electrode 53a are stacked.

[0054] Therefore, there is no longer a need for a step only for forming the separation structure 31, but the separation structure 31A can be formed simultaneously in the steps of forming the lower electrode 51, the upper electrode 53a, and the dielectric film 52a. That is, the trench for forming the separation structure 31A is formed simultaneously with a plurality of recesses 61 having a cylinder shape for forming the MIM capacitor 17A (see Figure 6 ). Then, when forming the lower electrode 51, the upper electrode 53a, and the dielectric film 52a, a metal for forming the lower electrode 51, a dielectric for forming the dielectric film 52a, and a metal for forming the upper electrode 53a are stacked on the trench, thereby forming the separation structure 31A.

[0055] As described above, the MIM capacitor 17A can form the separation structure 31 with a part of the outer periphery of the MIM capacitor, and for example, cost reduction can be achieved by reducing the number of manufacturing steps.

[0056] Note that, as described above, the present technology is not limited to being applied to the MIM capacitor 17 used for switching the capacitance for accumulating charges transmitted from the photoelectric conversion unit 12, and can also be applied to MIM capacitors having other uses in the pixel 11.

[0057] <Example of Structure of Electronic Device> The imaging element including the above-mentioned pixel 11 can be applied to various electronic devices, such as: a photographic system such as a digital still camera or a digital video camera; a mobile phone with an imaging function; or other devices with an imaging function.

[0058] Fig.13 : is a block diagram showing a configuration example of an image pickup device mounted on an electronic device.

[0059] like Fig.13 As shown, the imaging device 101 includes an optical system 102, an imaging element 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing still images and moving images.

[0060] The optical system 102 includes one or more lenses, guides image light (incident light) from a subject to the imaging element 103 , and forms an image of the light on a light receiving surface (sensor portion) of the imaging element 103 .

[0061] As the imaging element 103, an imaging element including the above-mentioned pixels 11 can be used. Electrons are accumulated in the imaging element 103 for a certain period of time according to an image formed on the light receiving surface of the imaging element 103 via the optical system 102. Then, a signal corresponding to the electrons accumulated in the imaging element 103 is provided to the signal processing circuit 104.

[0062] The signal processing circuit 104 performs various signal processing on the pixel signal output from the imaging element 103. The image (image data) obtained by the signal processing performed by the signal processing circuit 104 is supplied to the monitor 105 for display or supplied to the memory 106 for storage (recording).

[0063] In the imaging device 101 configured as described above, for example, by using an imaging element including the above-described pixels 11 , it is possible to capture an image of higher quality.

[0064] <Use examples of image sensors> Fig.14 : is a figure which shows the usage example of the said image sensor (imaging element).

[0065] For example, the above-described image sensor may be applied to various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays as described below.

[0066] - Equipment used to capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Equipment used for transportation, such as: vehicle-mounted sensors for capturing images of the front, rear, surroundings, interior, etc. of a car for the purpose of safe driving such as automatic parking and the purpose of recognizing the driver's status; monitoring cameras for monitoring moving vehicles and roads; and ranging sensors for measuring the distance between vehicles, etc. - Devices for home appliances such as TVs, refrigerators, and air conditioners, which, for example, capture the user's gesture and perform machine operations based on the gesture. - Equipment used in medical care, such as endoscopes and devices that perform angiography by receiving infrared light. - Equipment used for security, such as surveillance cameras for anti-theft and cameras for person authentication. - Equipment used for beauty treatments, such as skin testing equipment for taking images of the skin and microscopes for taking images of the scalp. - Equipment used for sports, such as action cameras or wearable cameras for sports purposes. - Equipment used in agriculture, such as cameras for monitoring the status of fields and crops.

[0067] <Combination example of technical solutions> Note that this technology can also have the following technical solutions. (1) Solid-state imaging device, including: Multiple pixels; a capacitor provided for each of the plurality of pixels and formed in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; and A separation unit electrically separates the capacitors of the pixels adjacent to each other. (2) The solid-state imaging device according to (1) above, wherein: The separation portion is provided for each of the plurality of pixels in a manner surrounding the capacitor, and An interlayer insulating film is provided between the separation portions of the pixels. (3) The solid-state imaging device according to (2) above, further comprising: A penetrating electrode penetrates the interlayer insulating film between the separation portions and connects the upper wiring and the lower wiring. (4) The solid-state imaging device according to (2) or (3), wherein: The separation portion is formed by embedding a material having a selectivity ratio with respect to the interlayer insulating film in a trench. (5) The solid-state imaging device according to (4) above, wherein: As the material, silicon nitride or silicon carbide is used. (6) The solid-state imaging device according to (4) above, wherein: As the material, a metal or a compound containing the metal is used. (7) The solid-state imaging device according to any one of (1) to (6), wherein: The capacitor has a plurality of cylinder shapes in which a dielectric film is sandwiched between a cylindrical upper electrode connected to the upper wiring and a cylindrical lower electrode connected to the lower wiring. (8) The solid-state imaging device according to (7), wherein: The capacitor is constructed by the following process: forming the dielectric film on both surfaces of the lower electrode which is formed in a concave shape along each concave portion having a high aspect ratio to constitute the cylinder shape; and The upper electrode is provided so as to be sandwiched between the dielectric films. (9) The solid-state imaging device according to (7) or (8), wherein: The upper ends of the respective lower electrodes forming the cylinder shape are supported by an insulating film. (10) The solid-state imaging device according to any one of (7) to (9), wherein: The separation portion is formed of a stacked structure in which the same material as that of each of the upper electrode, the lower wiring, and the dielectric film constituting the capacitor is stacked. (11) A method for manufacturing a solid-state imaging element, the method comprising: forming a capacitor provided for each of a plurality of pixels and formed in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; and A separation portion is formed that electrically separates the capacitors of the pixels adjacent to each other. (12) An electronic device comprising a solid-state imaging element, wherein the solid-state imaging element comprises: Multiple pixels; a capacitor provided for each of the plurality of pixels and formed in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; and A separation unit electrically separates the capacitors of the pixels adjacent to each other.

[0068] Note that the present embodiment is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the present disclosure. In addition, the effects described herein are merely examples and are not restrictive, and there may be other effects. Description of Reference Numerals

[0069] 11: Pixel 12: Photoelectric conversion unit 13: Transfer transistor 14: First FD Division 15: Connect the transistor 16: Second FD Division 17: MIM capacitor 18: Reset transistor 19: Amplifier transistor 20: Select transistor 21: Vertical signal line 31: Separation structure 32: Interlayer insulation film 33: Through the electrode 34: Slit 41: Lower wiring 42: Upper wiring 43: Electrode 44 and 45: Insulation film 51: Lower electrode 52: Dielectric film 53: Upper electrode

Claims

1. A solid-state imaging element, comprising: Multiple pixels; a capacitor provided for each of the plurality of pixels and formed in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; and A separation unit electrically separates the capacitors of the pixels adjacent to each other.

2. The solid-state imaging element according to claim 1, wherein The separation portion is provided for each of the plurality of pixels in a manner surrounding the capacitor, and An interlayer insulating film is provided between the separation portions of the pixels.

3. The solid-state imaging element according to claim 2, further comprising: A penetrating electrode penetrates the interlayer insulating film between the separation portions and connects the upper wiring and the lower wiring.

4. The solid-state imaging element according to claim 2, wherein: The separation portion is formed by embedding a material having a selectivity ratio with respect to the interlayer insulating film in a trench.

5. The solid-state imaging element according to claim 4, wherein: As the material, silicon nitride or silicon carbide is used.

6. The solid-state imaging element according to claim 4, wherein: As the material, a metal or a compound containing the metal is used.

7. The solid-state imaging element according to claim 1, wherein The capacitor has a plurality of cylinder shapes in which a dielectric film is sandwiched between a cylindrical upper electrode connected to the upper wiring and a cylindrical lower electrode connected to the lower wiring.

8. The solid-state imaging element according to claim 7, wherein: The capacitor is constructed by the following process: forming the dielectric film on both surfaces of the lower electrode which is formed in a concave shape along each concave portion having a high aspect ratio to constitute the cylinder shape; and The upper electrode is provided so as to be sandwiched between the dielectric films.

9. The solid-state imaging element according to claim 7, wherein: The upper ends of the respective lower electrodes forming the cylinder shape are supported by an insulating film.

10. The solid-state imaging element according to claim 7, wherein: The separation portion is formed of a stacked structure in which the same material as that of each of the upper electrode, the lower wiring, and the dielectric film constituting the capacitor is stacked.

11. A method for manufacturing a solid-state imaging element, the method comprising: forming a capacitor provided for each of a plurality of pixels and formed in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; and A separation portion is formed that electrically separates the capacitors of the pixels adjacent to each other.

12. An electronic device comprising a solid-state imaging element, the solid-state imaging element comprising: Multiple pixels; a capacitor provided for each of the plurality of pixels and formed in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; and A separation unit electrically separates the capacitors of the pixels adjacent to each other.

Images