Inter-channel trigger offset control method and system based on multiple FPGAs (Field Programmable Gate Array) and oscilloscope

Abstract

The invention discloses an inter-channel trigger offset control method and system based on multiple FPGAs and an oscilloscope, and each FPGA processor is provided with a first-stage trigger processing module, a first-stage offset adjustment module and a trigger control data communication module, and is provided with multiple channels and an ADC acquisition card. The method comprises the following steps: each processor receives a trigger signal; summarizing all the trigger signals, determining a trigger source channel, and generating a control signal group; calculating a parallel offset control quantity between channels; generating an FIFO control signal according to the offset control quantity; and reading ADC data and displaying a waveform. The technical problems that in the prior art, automatic alignment of triggering offset among multiple channels of an oscilloscope cannot be achieved, offset adjustment is inaccurate, the adjustment precision is insufficient, and adjustment of the triggering offset difference among the channels in any positive and negative directions cannot be achieved are solved, accurate and rapid alignment of the triggering offset among the multiple channels of the oscilloscope is achieved, and the accuracy and the accuracy of adjustment are improved. And meanwhile, the technical effects that the positive and negative trigger offset difference can be accurately adjusted, and the adjusting precision can be improved can be achieved.

Description

Technical Field

[0001] The present application relates to the field of digital oscilloscopes, and in particular to a method and system for controlling inter-channel trigger offsets based on multiple FPGAs, and an oscilloscope. Background Art

[0002] In digital oscilloscopes, the alignment and offset adjustment of trigger positions between multiple channels are important measurement functions. When observing signals, users need to accurately align the trigger positions of multiple channels to compare signal characteristics, and also need to analyze the timing relationship between different signals by setting a specific trigger offset difference.

[0003] In the prior art, due to the different signal transmission paths of multiple channels of the oscilloscope, coupled with the influence of factors such as communication delays between processors, it is difficult to achieve the ideal accuracy requirements when aligning channels. Therefore, the trigger offsets between multiple channels of the existing oscilloscope cannot be automatically aligned. At the same time, when it is necessary to set a specific trigger offset difference, the existing oscilloscope cannot adjust the offset accurately, the adjustment accuracy is insufficient, and only one-way offset adjustment can be performed, and flexible adjustment in the positive and negative directions cannot be achieved. These problems seriously affect the measurement and analysis effects of the oscilloscope in application scenarios such as multi-channel signal timing analysis. Summary of the invention

[0004] The main purpose of the present application is to provide a method, system and oscilloscope for controlling trigger offset between channels based on multiple FPGAs, aiming to solve the technical problems in the prior art that the trigger offset between multiple channels of the oscilloscope cannot be automatically aligned, the offset adjustment is inaccurate, the adjustment accuracy is insufficient, and the trigger offset difference between channels in any positive or negative direction cannot be adjusted.

[0005] To achieve the above-mentioned purpose, the present application provides a method for trigger offset control between channels based on multiple FPGAs. The multiple FPGA parallel architecture includes a host computer and multiple FPGA processors; each FPGA processor is provided with a first-level trigger processing module, a first-level offset adjustment module and a trigger control data communication module, and there are data transmission lines between the FPGA processors; each FPGA processor is provided with at least two channels, and each of the channels has multiple ADC acquisition cards. The method comprises: each of the FPGA processors receives a trigger signal sent by an ADC acquisition card of a corresponding channel through its own first-level trigger processing module; each of the FPGA processors determines a trigger source channel according to the trigger signal and generates a trigger source FIFO control signal group, wherein the plurality of FPGA processors include a master FPGA processor and a plurality of slave FPGA processors, the slave FPGA processor sends a trigger signal to the master FPGA processor through the data transmission bus, the master FPGA processor determines a trigger source channel according to all received trigger signals and generates a trigger source FIFO control signal group and sends the trigger source FIFO control signal group to each of the slave FPGA processors through the data transmission bus; the first-level offset adjustment module of each of the FPGA processors calculates a parallel offset control amount of a corresponding channel according to the trigger source FIFO control signal group, the parallel offset control amount is used to characterize a trigger time difference between each channel and the trigger source channel; the trigger control data communication module of each of the FPGA processors generates a FIFO control signal group corresponding to the channel according to the parallel offset control amount of the corresponding channel; each of the FPGA processors reads data of the ADC acquisition card of the corresponding channel according to the FIFO control signal group of each channel, and displays the waveform through the host computer.

[0006] Optionally, the FPGA processor is further provided with a secondary trigger processing module, an inter-channel trigger phase difference detection module and a secondary offset adjustment processing module; after each of the FPGA processors reads the data of the corresponding channel ADC acquisition card according to the FIFO control signal group of each channel, the method further comprises: each of the FPGA processors performs serial processing on the read channel data to obtain serial waveform data; the secondary trigger processing module of each of the FPGA processors performs trigger judgment on the serial waveform data, generates a secondary trigger signal, and sends the secondary trigger signal to the inter-channel trigger phase difference detection module; the inter-channel trigger phase difference detection module takes the trigger source channel as a reference, performs phase deviation statistics according to the secondary trigger signal of each channel, generates a statistical result, and sends the statistical result to the host computer; the host computer performs calculation processing according to the statistical result, and feeds back the processing result to the secondary offset adjustment processing module of each of the FPGA processors; the secondary offset adjustment processing module of each of the FPGA processors generates a serial read control signal of the corresponding channel according to the processing result; each of the FPGA processors reads the serial waveform data according to the serial read control signal of each channel, and displays the waveform through the host computer.

[0007] Optionally, the FPGA processor is also provided with an interpolation processing module; after the serial processing of the read channel data, the method further includes: the interpolation processing module of each FPGA processor performs interpolation processing on the serial waveform data to obtain interpolation waveform data; the secondary trigger processing module of each FPGA processor performs trigger judgment on the interpolation waveform data to generate a secondary trigger signal.

[0008] Optionally, each of the ADC acquisition cards includes a collector and a local controller; the collector is used to collect input signals and convert them into sampled data; the local controller is internally provided with a FIFO data buffer and a first-level trigger judgment module, the FIFO data buffer is used to cache the sampled data collected by the collector, and the first-level trigger judgment module is used to perform trigger judgment on the sampled data and determine the trigger signal. Before each of the FPGA processors receives the trigger signal sent by the ADC acquisition card of the corresponding channel through its own first-level trigger processing module, the method further includes: each of the FPGA processors sends the acquisition start instruction sent by the host computer to each of the collectors, and controls each of the collectors to start collecting sampled data; each of the collectors sends the collected sampled data into the corresponding FIFO data buffer for storage; each of the collectors synchronously sends the collected sampled data into the corresponding first-level trigger judgment module for trigger judgment, and when the sampled data meets the trigger condition, the first-level trigger judgment module sends the trigger signal to the first-level trigger processing module of the corresponding FPGA processor.

[0009] Optionally, the inter-channel trigger phase difference detection module performs phase deviation statistics based on the secondary trigger signal of each channel to generate statistical results, including: obtaining the count value of each channel from the start of the write enable signal to the arrival of the secondary trigger signal, wherein the write enable signal is used to control the writing of data into the FIFO data buffer; selecting the count value of the trigger source channel as a reference, calculating the count value difference between each channel and the trigger source channel as the phase deviation value; summarizing the phase deviation values ​​of each channel and sending them to the host computer as the statistical results.

[0010] Optionally, the host computer performs calculation processing according to the statistical results, and feeds back the processing results to the secondary offset adjustment processing modules of each FPGA processor, including: the host computer determines the serial offset control amount of each channel relative to the trigger source channel according to the phase deviation value of each channel; and sends the serial offset control amount corresponding to each channel to the secondary offset adjustment processing modules of the corresponding FPGA processors.

[0011] Optionally, the secondary offset adjustment processing module of each FPGA processor generates a serial read control signal of the corresponding channel according to the processing result, including: the secondary offset adjustment processing module calculates the read deviation value of the corresponding channel relative to the trigger source channel according to the received serial offset control amount; calculates the read adjustment amount and read adjustment direction of the corresponding channel relative to the trigger source channel according to the read deviation value, wherein the read adjustment amount is determined according to the absolute value of the read deviation value, and the read adjustment direction is determined according to the positive or negative sign of the read deviation value; and generates the serial read control signal of the corresponding channel according to the read adjustment amount and the read adjustment direction.

[0012] Optionally, the working states of the FIFO data buffer include a write-only state, a read-while-write state and a read-only state, wherein the write-only state is used to store the sampled data collected by the collector after receiving a write enable signal; the read-while-write state is started after the pre-trigger depth is full and a ready signal is generated, and is used to synchronously execute the writing and reading operations of the sampled data; when the trigger signal is detected, the write-only state is re-entered until the FIFO data buffer is full; the read-only state is started after the FIFO data buffer is full, and is used to read out the stored sampled data for processing.

[0013] In addition, to achieve the above-mentioned purpose, the present application also provides a channel-to-channel trigger offset control system based on multiple FPGAs, which is used to implement a channel-to-channel trigger offset control method based on multiple FPGAs. The system includes a host computer and multiple FPGA processors. Among them, the host computer is used to issue an acquisition start instruction, process the statistical results of each channel and display the waveform; multiple FPGA processors, including a master FPGA processor and multiple slave FPGA processors, each of which has a data transmission line, and the FPGA processors are provided with at least two channels, and each of the channels has multiple ADC acquisition cards. The FPGA processor includes a first-level trigger processing module, a first-level offset adjustment module and a trigger control data communication module. Among them, the first-level trigger processing module is used to receive a trigger signal, determine the trigger source channel and generate a trigger source FIFO control signal group; the first-level offset adjustment module is used to calculate the parallel offset control amount; the trigger control data communication module is used to generate a FIFO control signal group.

[0014] In addition, the present application also provides a digital oscilloscope, including a channel-to-channel trigger offset control system based on multiple FPGAs.

[0015] The beneficial effects that this application can achieve are as follows:

[0016] A multi-FPGA parallel architecture is adopted, including a host computer and multiple FPGA processors, each of which is provided with a first-level trigger processing module, a first-level offset adjustment module and a trigger control data communication module, and data transmission lines are provided between the FPGA processors. Each FPGA processor is provided with at least two channels, and each channel has multiple ADC acquisition cards. This architecture design can realize the parallel acquisition and processing of multi-channel data.

[0017] In the specific implementation process, each FPGA processor first receives the trigger signal sent by the ADC acquisition card of the corresponding channel through its own first-level trigger processing module to realize the acquisition of the trigger signal of each channel. Then, in order to realize unified trigger control, multiple FPGA processors are divided into a master FPGA processor and multiple slave FPGA processors. The slave FPGA processor sends the trigger signal to the master FPGA processor through the data transmission bus, and the master FPGA processor uniformly determines the trigger source channel and generates a trigger source FIFO control signal group, and then sends the control signal group to each slave FPGA processor through the data transmission bus, thereby ensuring the consistency of trigger control. Afterwards, the first-level offset adjustment module of each FPGA processor calculates the parallel offset control amount of the corresponding channel according to the trigger source FIFO control signal group, and the parallel offset control amount characterizes the trigger time difference between each channel and the trigger source channel. The offset control amount obtained by calculation can be a positive value or a negative value, corresponding to the positive or negative offset of the channel relative to the trigger source channel, thereby realizing bidirectional offset adjustment. Then, the trigger control data communication module of each FPGA processor generates the FIFO control signal group corresponding to the channel according to the parallel offset control amount of the corresponding channel, and realizes the control of the trigger offset of each channel. Afterwards, each FPGA processor reads the data from the ADC acquisition card of the corresponding channel according to the FIFO control signal group of each channel, and displays the waveform through the host computer, so that the trigger offset between multiple channels of the oscilloscope can be accurately and quickly aligned. At the same time, the positive and negative trigger offset differences can be accurately adjusted, thereby improving the precision and accuracy of the offset adjustment.

[0018] Through the above technical solution, the method realizes the precise alignment of trigger offsets between multiple channels of the oscilloscope and the precise adjustment of the positive and negative trigger offset differences, which significantly improves the accuracy of waveform display. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of a flow chart of inter-channel trigger offset control provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of the structure of two FPGA parallel architectures provided in an embodiment of the present application;

[0021] Figure 3 This is a schematic diagram of the structure of the ADC acquisition card in the embodiment of the present application;

[0022] Figure 4 A schematic diagram of trigger offset according to an embodiment of the present application.

[0023] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0026] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the meaning of "and / or" appearing in the full text includes three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0028] The first embodiment of the present application provides a method for controlling the trigger offset between channels based on multiple FPGAs. The multiple FPGA parallel architecture includes a host computer and multiple FPGA processors; each FPGA processor is provided with a first-level trigger processing module, a first-level offset adjustment module, and a trigger control data communication module, and there are data transmission lines between the FPGA processors. Each FPGA processor is provided with at least two channels, and each channel has multiple ADC acquisition cards.

[0029] The inter-channel trigger offset control method includes:

[0030] S1: Each of the FPGA processors receives a trigger signal sent by the ADC acquisition card of the corresponding channel through its own first-level trigger processing module;

[0031] S2: Each of the FPGA processors determines a trigger source channel according to the trigger signal and generates a trigger source FIFO control signal group, wherein the multiple FPGA processors include a master FPGA processor and multiple slave FPGA processors, the slave FPGA processor sends the trigger signal to the master FPGA processor through the data transmission bus, the master FPGA processor determines the trigger source channel according to all received trigger signals and generates a trigger source FIFO control signal group, and then sends the trigger source FIFO control signal group to each of the slave FPGA processors through the data transmission bus;

[0032] S3: the first-level offset adjustment module of each FPGA processor calculates the parallel offset control amount of the corresponding channel according to the trigger source FIFO control signal group, and the parallel offset control amount is used to characterize the trigger time difference between each channel and the trigger source channel;

[0033] S4: The trigger control data communication module of each FPGA processor generates a FIFO control signal group corresponding to the channel according to the parallel offset control amount of the corresponding channel;

[0034] S5: Each of the FPGA processors reads the data of the ADC acquisition card of the corresponding channel according to the FIFO control signal group of each channel, and displays the waveform through the host computer.

[0035] Specifically, the multi-FPGA parallel architecture includes a host computer and multiple FPGA processors. Among them, multiple FPGA processors are interconnected through data transmission lines. Specifically, each FPGA processor includes a first-level trigger processing module, a first-level offset adjustment module and a trigger control data communication module. Among them, the first-level trigger processing module is used to receive and process trigger signals; the first-level offset adjustment module is used to calculate the parallel offset control amount; the trigger control data communication module is used to generate a FIFO control signal group. Each FPGA processor is provided with at least two channels. Each channel is configured with multiple ADC acquisition cards for realizing multi-channel parallel data acquisition. Among them, each ADC acquisition card is used to collect input signals and convert them into digital signals, that is, sampled data. Through multi-FPGA parallel processing and modular design, a hardware foundation is provided for realizing trigger offset control between multiple channels.

[0036] Reference Figure 1First, each FPGA processor receives the trigger signal sent by the ADC acquisition card of the corresponding channel through its own first-level trigger processing module. Specifically, when the ADC acquisition card of each channel detects sampling data that meets the preset trigger conditions, it generates a corresponding trigger signal and sends it to the first-level trigger processing module of the corresponding FPGA processor. This step realizes the acquisition of the trigger signal of each channel, laying the foundation for the subsequent trigger offset control.

[0037] Then, the trigger signals collected by each FPGA processor are processed using a master-slave architecture. Specifically, one of the multiple FPGA processors is determined as the master FPGA processor, and the rest are slave FPGA processors. The slave FPGA processor sends the received trigger signal to the master FPGA processor via a data transmission bus. After receiving all the trigger signals, the master FPGA processor determines the trigger source channel according to the primary trigger processing module, and generates a control signal group (i.e., a trigger source FIFO control signal group) for controlling the trigger source channel FIFO. Subsequently, the master FPGA processor sends the trigger source FIFO control signal group to each slave FPGA processor via the data transmission bus, thereby realizing unified management of trigger control.

[0038] After each FPGA processor receives the trigger source FIFO control signal group, its first-level offset adjustment module starts working. Specifically, the first-level offset adjustment module obtains a parallel offset control amount that characterizes the trigger time difference between the two by calculating the timing relationship between each channel and the trigger source channel. The control amount reflects the trigger offset degree of the current channel relative to the trigger source channel. The control amount can be a positive value or a negative value, corresponding to the positive or negative offset adjustment of the channel relative to the trigger source channel. Subsequently, the trigger control data communication module of each FPGA processor generates a control signal group for controlling the corresponding channel FIFO according to the parallel offset control amount calculated by the first-level offset adjustment module, which includes the offset adjustment information required for the corresponding channel. Afterwards, each FPGA processor controls the reading timing of the corresponding channel ADC acquisition card data according to the FIFO control signal group generated by the trigger control data communication module to realize the adjustment of the trigger offset. The read data is finally displayed as a waveform by the host computer, so that the trigger position of each channel waveform on the display interface is aligned.

[0039] Through the above-mentioned inter-channel trigger offset control method, effective control of the trigger offset of each channel in the multi-FPGA parallel architecture is achieved, so that the triggers between multiple channels of the oscilloscope are accurately and automatically aligned.

[0040] Reference Figure 2, the technical solution of the present application is described in detail in combination with specific embodiments. Among them, the multi-FPGA parallel architecture includes two FPGA processors, FPGA_A and FPGA_B, FPGA_A is set as the main FPGA processor, and FPGA_B is set as the slave FPGA processor. Each FPGA processor is provided with two channels, and each channel is configured with 4 ADC acquisition cards. Specifically, FPGA_A connects channel 1 and channel 2, and FPGA_B connects channel 3 and channel 4.

[0041] In actual applications, the first-level trigger processing module of FPGA_A receives trigger signals from the four ADC acquisition cards corresponding to channel 1 and the trigger signals from the four ADC acquisition cards corresponding to channel 2. At the same time, the first-level trigger processing module of FPGA_B receives trigger signals from the four ADC acquisition cards corresponding to channel 3 and the trigger signals from the four ADC acquisition cards corresponding to channel 4, and sends these two groups of trigger signals to FPGA_A through the data transmission line. Then, FPGA_A acts as the main FPGA processor, and its first-level trigger processing module processes all four groups of trigger signals received, determines the trigger source channel, and generates a trigger source FIFO control signal group. Subsequently, FPGA_A sends the trigger source FIFO control signal group to FPGA_B through the data transmission line. Next, the first-level offset adjustment module of FPGA_A calculates the trigger time difference between each parallel acquisition ADC acquisition card and the trigger source channel in channel 1 and channel 2 according to the trigger source FIFO control signal group, and generates the corresponding parallel offset control amount. Similarly, the first-level offset adjustment module of FPGA_B also calculates the trigger time difference between each parallel ADC acquisition card and the trigger source channel in channel 3 and channel 4 according to the received trigger source FIFO control signal group, and generates the corresponding parallel offset control amount. Subsequently, the trigger control data communication modules of FPGA_A and FPGA_B generate corresponding FIFO control signal groups according to the parallel offset control amounts calculated by each. This control signal group is used to control the data reading timing of the parallel ADC acquisition card in each channel. Afterwards, FPGA_A and FPGA_B read the data of each ADC acquisition card in the corresponding channel according to the FIFO control signal groups generated by each, and display the waveform through the host computer to achieve time alignment of the data collected by all channels.

[0042] In this embodiment, the real-time sampling rate of each ADC acquisition card is 20GSPS (20 billion sampling points per second), and the time interval of a single sampling point is 50ps. Each channel is configured with 4 ADC acquisition cards for parallel acquisition, and the data processing clock cycle corresponding to the entire channel is 4ns. When performing trigger offset control between channels, the FPGA processor will calculate and process the offset based on the above timing relationship. Because each clock cycle contains 80 data points (4ns corresponds to 80 sampling points), the trigger position adjustment in units of 4ns can be achieved through the FIFO control signal group, ensuring that the waveforms of each channel can be accurately and automatically aligned when displayed.

[0043] As an optional implementation, the FPGA processor is further provided with a secondary trigger processing module, an inter-channel trigger phase difference detection module and a secondary offset adjustment processing module; after each of the FPGA processors reads the data of the corresponding channel ADC acquisition card according to the FIFO control signal group of each channel, it also includes:

[0044] S6: Each of the FPGA processors performs serial processing on the read channel data to obtain serial waveform data;

[0045] S7: the secondary trigger processing module of each FPGA processor performs trigger judgment on the serial waveform data, generates a secondary trigger signal, and sends the secondary trigger signal to the inter-channel trigger phase difference detection module;

[0046] S8: The inter-channel trigger phase difference detection module takes the trigger source channel as a reference, performs phase deviation statistics according to the secondary trigger signal of each channel, generates a statistical result, and sends the statistical result to the host computer;

[0047] S9: the host computer performs calculation processing according to the statistical results, and feeds back the processing results to the secondary offset adjustment processing module of each FPGA processor;

[0048] S10: The secondary offset adjustment processing module of each FPGA processor generates a serial read control signal of a corresponding channel according to the processing result;

[0049] S11: Each of the FPGA processors reads the serial waveform data according to the serial read control signal of each channel, and displays the waveform through the host computer.

[0050] Specifically, after completing the first-level trigger offset adjustment, a second-level trigger offset control is also provided to achieve fine adjustment of the trigger offset between channels, further improving the accuracy of the trigger position alignment.

[0051] First, each FPGA processor serially processes the channel data read after the first-level trigger offset adjustment. Specifically, the data collected in parallel by the four ADC acquisition cards in each channel are merged and converted into serial waveform data in the reading order. Then, the secondary trigger processing module of each FPGA processor triggers the merged serial waveform data to generate a more accurate secondary trigger signal. The secondary trigger signal is then sent to the inter-channel trigger phase difference detection module. Next, the inter-channel trigger phase difference detection module uses the trigger source channel as a reference to perform phase deviation statistics on the secondary trigger signals of each channel to generate statistical results reflecting the precise trigger time difference between each channel. The statistical results are sent to the host computer for further processing. Subsequently, the host computer performs calculations based on the received statistical results to obtain more accurate trigger offset adjustment parameters, and feeds back these processing results to the secondary offset adjustment processing module of each FPGA processor. The secondary offset adjustment processing module of each FPGA processor generates a serial read control signal for fine adjustment based on the received processing results. Afterwards, each FPGA processor accurately reads the serial waveform data according to the generated serial read control signal, and displays the waveform through the host computer, thereby achieving more accurate trigger position alignment and improving the adjustment offset accuracy.

[0052] For example, the multi-FPGA parallel architecture includes FPGA_A and FPGA_B, where FPGA_A serves as the master FPGA processor and FPGA_B serves as the slave FPGA processor. Each FPGA processor is provided with two channels, each channel is configured with 4 ADC acquisition cards, and the sampling rate is 20GSPS. Specifically, FPGA_A is connected to channel 1 and channel 2, and FPGA_B is connected to channel 3 and channel 4. After completing the first-level trigger offset adjustment, FPGA_A merges the data collected in parallel by the 4 ADC acquisition cards in channel 1 into serial waveform data according to the preset reading order, and also processes the data of channel 2 in serial. FPGA_B also performs the same serial processing on the data of channel 3 and channel 4. Different from the 4ns adjustment unit in the first-level trigger offset adjustment, the serially processed data maintains the sampling rate characteristics of 20GSPS, and the sampling point interval is 50ps, which provides a basis for realizing more precise trigger offset adjustment.

[0053] The secondary trigger processing modules of FPGA_A and FPGA_B respectively perform trigger judgment on the merged serial waveform data and generate secondary trigger signals. Compared with the primary trigger control, the secondary trigger can realize trigger point positioning in units of 50ps, which greatly improves the trigger accuracy. Then, the inter-channel trigger phase difference detection module counts the phase deviations between channels based on these precise trigger points. The host computer calculates the precise adjustment parameters based on the statistical results and feeds them back to the secondary offset adjustment processing modules of the two FPGA processors. After that, FPGA_A and FPGA_B accurately read the serial waveform data according to the serial read control signals generated by their respective secondary offset adjustment processing modules, realizing the precise alignment of the waveforms of each channel when displayed. By combining the primary trigger offset control and the secondary trigger offset control, 50ps level trigger offset control can be achieved at the ns level.

[0054] As an optional implementation, the FPGA processor is further provided with an interpolation processing module; after serial processing of the read channel data, it also includes:

[0055] S12: the interpolation processing module of each FPGA processor performs interpolation processing on the serial waveform data to obtain interpolation waveform data;

[0056] S13: The secondary trigger processing module of each FPGA processor performs a trigger judgment on the interpolation waveform data to generate a secondary trigger signal.

[0057] Specifically, an interpolation processing link is added to the secondary trigger offset control. Specifically, after each FPGA processor completes the serial processing of the channel data, the interpolation processing module performs interpolation operation on the serial waveform data to obtain interpolated waveform data with denser sampling points. Then, the secondary trigger processing module performs trigger judgment based on the interpolated waveform data and generates a secondary trigger signal.

[0058] For example, based on the above embodiment, after FPGA_A and FPGA_B complete the serial processing of channel data, they respectively perform interpolation processing on the serial waveform data through their respective interpolation processing modules. Since the sampling interval of serial data is 50ps, waveform data with a smaller sampling interval can be obtained through interpolation processing. At this time, the secondary trigger processing module performs trigger judgment on the interpolated waveform data, which can achieve higher precision trigger point positioning.

[0059] By adding an interpolation link before the secondary trigger processing, the accuracy of trigger position adjustment is further improved, so that the trigger position alignment accuracy can reach the ps level.

[0060] As an optional implementation, each of the ADC acquisition cards includes a collector and a local controller; the collector is used to collect input signals and convert them into sampled data; a FIFO data buffer and a first-level trigger judgment module are provided inside the local controller, the FIFO data buffer is used to cache the sampled data collected by the collector, and the first-level trigger judgment module is used to perform trigger judgment on the sampled data and determine the trigger signal;

[0061] Before each of the FPGA processors receives the trigger signal sent by the ADC acquisition card of the corresponding channel through its own primary trigger processing module, it also includes:

[0062] S14: Each of the FPGA processors sends the acquisition start instruction sent by the host computer to each of the collectors, and controls each of the collectors to start collecting sampled data;

[0063] S15: Each collector sends the collected sampled data to a corresponding FIFO data buffer for storage;

[0064] S16: Each collector synchronously sends the collected sampling data to the corresponding first-level trigger judgment module for trigger judgment. When the sampling data meets the trigger condition, the first-level trigger judgment module sends a trigger signal to the first-level trigger processing module of the corresponding FPGA processor.

[0065] Specifically, refer to Figure 3 Each ADC acquisition card includes two main parts: the collector and the local controller. The collector is responsible for the acquisition and digital-to-analog conversion of the input signal; the local controller is internally provided with a FIFO data buffer and a first-level trigger judgment module, which are used for data buffering and trigger judgment respectively.

[0066] In the specific implementation process, the host computer first sends a collection start instruction to each FPGA processor, and the FPGA processor forwards the instruction to each collector of the corresponding channel to control the collector to start data collection.

[0067] After the collector collects the input signal and completes the digital-to-analog conversion, it sends the sampled data to two locations at the same time: one is sent to the FIFO data buffer for storage; the other is sent to the first-level trigger judgment module for trigger judgment. When the first-level trigger judgment module detects that the sampled data meets the preset trigger condition, it generates a trigger signal and sends it to the first-level trigger processing module of the corresponding FPGA processor.

[0068] For example, in the above embodiment, after FPGA_A and FPGA_B receive the acquisition start instruction from the host computer, they control the 4 ADC acquisition cards of their corresponding channels to start data acquisition. Each collector collects data at a sampling rate of 20GSPS and sends the data to the corresponding FIFO data buffer and the first-level trigger judgment module at the same time. When the sampled data of a channel meets the trigger condition, the corresponding first-level trigger judgment module sends a trigger signal to the FPGA processor to which it belongs.

[0069] Through the structural design and workflow of the above-mentioned ADC acquisition card, real-time storage and trigger judgment of sampling data are realized, laying the foundation for subsequent trigger offset control.

[0070] As an optional implementation, the inter-channel trigger phase difference detection module takes the trigger source channel as a reference, performs phase deviation statistics according to the secondary trigger signal of each channel, and generates statistical results, including:

[0071] S81: Obtaining the count value of each channel from the start of the write enable signal to the arrival of the secondary trigger signal, wherein the write enable signal is used to control the data writing of the FIFO data buffer;

[0072] S82: Select the count value of the trigger source channel as a reference, and calculate the count value difference between each channel and the trigger source channel as a phase deviation value;

[0073] S83: Summarize the phase deviation values ​​of each channel and send them to the host computer as the statistical result.

[0074] Specifically, after the host computer sends the acquisition start instruction, each channel starts data acquisition, and the FIFO data buffer writes data under the control of the write enable signal. After obtaining the secondary trigger signal of each channel, the inter-channel trigger phase difference detection module reads the count value of each channel from the start of the write enable signal to the arrival of the secondary trigger signal. These count values ​​have been recorded by the FIFO data buffer of each channel during the acquisition process. Then, based on the count value of the trigger source channel, the count value difference between other channels and the trigger source channel is calculated respectively, and these differences are used as the phase deviation value of each channel. Afterwards, the calculated phase deviation values ​​of each channel are summarized and sent to the host computer as statistical results.

[0075] For example, in the above embodiment, assuming that channel 1 is the trigger source channel, after obtaining the secondary trigger signal of each channel, the inter-channel trigger phase difference detection module reads the count value recorded in each channel. Based on the count value of channel 1, the difference between the count value of channel 2, channel 3 and channel 4 and the count value of channel 1 is calculated respectively to obtain the phase deviation value of these channels relative to the trigger source channel. These deviation values ​​will eventually be summarized and sent to the host computer for subsequent offset adjustment.

[0076] By means of counting comparison, accurate quantification of the trigger time difference of each channel is achieved, providing a data basis for achieving accurate trigger position alignment.

[0077] As an optional implementation, the host computer performs calculation processing according to the statistical results and feeds back the processing results to the secondary offset adjustment processing module of each FPGA processor, including:

[0078] S91: The host computer determines the serial offset control amount of each channel relative to the trigger source channel according to the phase deviation value of each channel;

[0079] S92: Send the serial offset control amount corresponding to each channel to the secondary offset adjustment processing module of the corresponding FPGA processor respectively.

[0080] Specifically, the host computer first calculates the serial offset control amount that needs to be adjusted for each channel relative to the trigger source channel based on the received phase deviation value of each channel. This control amount is used to indicate the precise offset adjustment that needs to be made for each channel when reading serial data. Then, the host computer sends the calculated serial offset control amount to the secondary offset adjustment processing module of the FPGA processor to which the corresponding channel belongs, providing a control basis for the subsequent precise trigger position adjustment.

[0081] For example, in the above embodiment, after receiving the phase deviation values ​​of channel 2, channel 3 and channel 4 relative to the trigger source channel 1, the host computer calculates the serial offset control amount required for these channels. Subsequently, the serial offset control amount of channel 1 and channel 2 is sent to the secondary offset adjustment processing module of FPGA_A, and the serial offset control amount of channel 3 and channel 4 is sent to the secondary offset adjustment processing module of FPGA_B, thereby realizing the accurate calculation of the trigger offset of each channel and the distribution of the control amount.

[0082] As an optional implementation, the secondary offset adjustment processing module of each FPGA processor generates a serial read control signal of the corresponding channel according to the processing result, including:

[0083] S101: The secondary offset adjustment processing module calculates a reading deviation value of a corresponding channel relative to a trigger source channel according to a received serial offset control amount;

[0084] S102: Calculating a read adjustment amount and a read adjustment direction of a corresponding channel relative to a trigger source channel according to the read deviation value, wherein the read adjustment amount is determined according to an absolute value of the read deviation value, and the read adjustment direction is determined according to a positive or negative sign of the read deviation value;

[0085] S103: Generate a serial read control signal of a corresponding channel according to the read adjustment amount and the read adjustment direction.

[0086] Specifically, the secondary offset adjustment processing module first calculates the read deviation value of the corresponding channel relative to the trigger source channel based on the received serial offset control value. The deviation value characterizes the difference in trigger position between the current channel and the trigger source channel. Then, based on the calculated read deviation value, two key parameters are determined: the read adjustment amount and the read adjustment direction. Among them, the read adjustment amount is determined based on the absolute value of the read deviation value, indicating the specific value that needs to be adjusted; the read adjustment direction is determined based on the positive or negative of the read deviation value, indicating whether the data needs to be moved forward or backward when reading. Afterwards, the secondary offset adjustment processing module generates a control signal for controlling serial data reading based on the determined read adjustment amount and read adjustment direction.

[0087] For example, in the above embodiment, after receiving the serial offset control amount of channel 2, the secondary offset adjustment processing module of FPGA_A first calculates the reading deviation value relative to the trigger source channel 1. Then, the number of points to be adjusted is determined according to the absolute value of the deviation value, and whether to adjust forward or backward is determined according to the positive or negative of the deviation value. Finally, based on these parameters, a control signal for controlling the data reading of channel 2 is generated, thereby realizing precise control of serial data reading and ensuring precise alignment of the trigger position.

[0088] Reference Figure 4 , the phase deviation detection, calculation and adjustment process are explained.

[0089] The first is the detection stage, where the channel-to-channel trigger phase difference detection module obtains the count value of each channel from the write enable signal to the secondary trigger signal. Figure 4 As shown on the left, each channel records the count values ​​cnt1, cnt2, cnt3, and cnt4. The inter-channel trigger phase difference detection module calculates the phase deviation according to the selected trigger source and sends these deviation values ​​to the host computer as statistical results.

[0090] For example, when channel 1 is the trigger source channel, the inter-channel trigger phase difference detection module calculates: the deviation of channel 1: cnt1-cnt1=0; the deviation of channel 2: cnt2-cnt1; the deviation of channel 3: cnt3-cnt1; the deviation of channel 4: cnt4-cnt1. When channel 3 is the trigger source channel, the inter-channel trigger phase difference detection module calculates: the deviation of channel 1: cnt1-cnt3; the deviation of channel 2: cnt2-cnt3; the deviation of channel 3: cnt3-cnt3=0; the deviation of channel 4: cnt4-cnt3. Among them, the calculated deviation value can be positive or negative, indicating the positive or negative offset relative to the trigger source channel, respectively. Through this calculation method, the precise offset value of any channel relative to the trigger source channel can be obtained, and bidirectional offset adjustment can be achieved.

[0091] Then comes the calculation phase, where the host computer determines the serial offset control amount required for each channel based on the received statistical results, and sends these control amounts to the secondary offset adjustment processing module of the corresponding FPGA processor. Then comes the adjustment phase, where the secondary offset adjustment processing module of each FPGA processor uses the received serial offset control amount as the specific read deviation value, determines the adjustment amount based on the absolute value of the deviation value, and determines the adjustment direction based on the positive or negative value of the deviation value, and generates the corresponding serial read control signal. Figure 4 As shown on the right, through the action of these control signals, the precise alignment of the trigger position of each channel is finally achieved.

[0092] As an optional implementation, the working states of the FIFO data buffer include a write-only state, a read-while-write state and a read-only state, wherein the write-only state is used to store the sampled data collected by the collector after receiving a write enable signal; the read-while-write state is started after the pre-trigger depth is full and a ready signal is generated, and is used to synchronously execute the writing and reading operations of the sampled data; when the trigger signal is detected, the write-only state is re-entered until the FIFO data buffer is full; the read-only state is started after the FIFO data buffer is full, and is used to read out the stored sampled data for processing.

[0093] Specifically, the FIFO data buffer in the local controller of each ADC acquisition card has three working states: write-only state, read-while-write state, and read-only state. After receiving the write enable signal sent by the host computer, the FIFO data buffer first enters the write-only state and only performs the storage operation of the sampled data collected by the collector.

[0094] When the data stored in the FIFO data buffer reaches the pre-trigger depth and generates a ready signal, its working state is converted to a read-while-write state. In this state, the FIFO data buffer synchronously performs write and read operations on the sampled data. At the same time, the first-level trigger judgment module performs a trigger judgment on the sampled data.

[0095] When the first-level trigger judgment module detects the trigger signal, the FIFO data buffer re-enters the write-only state and continues to store the sampled data until it is full. When the FIFO data buffer is full, its working state is converted to the read-only state, at which time only the data read operation is performed, and the stored sampled data is read out for subsequent serial processing and second-level trigger judgment.

[0096] For example, in the above embodiment, the FIFO data buffer of the four ADC acquisition cards of each channel in FPGA_A and FPGA_B starts to store the sampled data after receiving the write enable signal. When the pre-trigger depth is reached, it enters the read-while-write state; after detecting the trigger signal, it continues to write until it is full, and finally reads out all the data for subsequent trigger offset control.

[0097] Through the conversion mechanism of the working state of the FIFO data buffer, effective management of the sampled data is achieved, providing a data basis for achieving accurate trigger offset control.

[0098] The second embodiment of the present application provides a channel-to-channel trigger offset control system based on multiple FPGAs, which is used to implement a channel-to-channel trigger offset control method based on multiple FPGAs, and the system includes a host computer and multiple FPGA processors. Among them, the host computer is used to issue an acquisition start instruction, process the statistical results of each channel, and display the waveform; multiple FPGA processors, including a master FPGA processor and multiple slave FPGA processors, each of the FPGA processors has a data transmission line, each FPGA processor is provided with at least two channels, and each of the channels has multiple ADC acquisition cards. Among them, each FPGA processor includes a first-level trigger processing module, a first-level offset adjustment module, and a trigger control data communication module. Among them, the first-level trigger processing module is used to receive a trigger signal, determine the trigger source channel, and generate a trigger source FIFO control signal group; the first-level offset adjustment module is used to calculate the parallel offset control amount; the trigger control data communication module is used to generate a FIFO control signal group.

[0099] As a feasible implementation, each FPGA processor also includes a secondary trigger processing module, an inter-channel trigger phase difference detection module, a secondary offset adjustment processing module and an interpolation processing module. Among them, the secondary trigger processing module is used to perform trigger judgment on serial waveform data; the inter-channel trigger phase difference detection module is used to perform phase deviation statistics; the secondary offset adjustment processing module is used to generate a serial read control signal; the interpolation processing module is used to perform interpolation processing on the serial waveform data;

[0100] As a feasible implementation, each ADC acquisition card includes a collector and a local controller, and the local controller includes a FIFO data buffer and a first-level trigger judgment module. The collector is used to collect input signals and convert them into sampled data; the local controller is used to control the storage and trigger judgment of the sampled data; the FIFO data buffer is used to cache the sampled data collected by the collector; and the first-level trigger judgment module is used to perform trigger judgment on the sampled data.

[0101] A third embodiment of the present application provides a digital oscilloscope, including a multi-FPGA-based inter-channel trigger offset control system.

[0102] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for controlling channel-to-channel trigger offset based on multiple FPGAs, characterized in that: The multi-FPGA parallel architecture includes a host computer and multiple FPGA processors; the FPGA processor is provided with a first-level trigger processing module, a first-level offset adjustment module and a trigger control data communication module, and there is a data transmission line between each of the FPGA processors; each of the FPGA processors is provided with at least two channels, and each of the channels has multiple ADC acquisition cards; the method includes: Each of the FPGA processors receives a trigger signal sent by the ADC acquisition card of the corresponding channel through its own first-level trigger processing module; Each of the FPGA processors determines a trigger source channel according to the trigger signal and generates a trigger source FIFO control signal group, wherein the multiple FPGA processors include a master FPGA processor and multiple slave FPGA processors, the slave FPGA processor sends the trigger signal to the master FPGA processor through the data transmission bus, the master FPGA processor determines the trigger source channel according to all received trigger signals and generates a trigger source FIFO control signal group, and sends the trigger source FIFO control signal group to each of the slave FPGA processors through the data transmission bus; The first-level offset adjustment module of each FPGA processor calculates the parallel offset control amount of the corresponding channel according to the trigger source FIFO control signal group, and the parallel offset control amount is used to characterize the trigger time difference between each channel and the trigger source channel; The trigger control data communication module of each FPGA processor generates a FIFO control signal group corresponding to the channel according to the parallel offset control amount of the corresponding channel; Each of the FPGA processors reads data from the ADC acquisition card of the corresponding channel according to the FIFO control signal group of each channel, and displays the data in waveform through the host computer.

2. The method according to claim 1, characterized in that: The FPGA processor is also provided with a secondary trigger processing module, an inter-channel trigger phase difference detection module and a secondary offset adjustment processing module; after each of the FPGA processors reads the data of the corresponding channel ADC acquisition card according to the FIFO control signal group of each channel, the method further includes: Each of the FPGA processors performs serial processing on the read channel data to obtain serial waveform data; The secondary trigger processing module of each FPGA processor performs trigger judgment on the serial waveform data, generates a secondary trigger signal, and sends the secondary trigger signal to the inter-channel trigger phase difference detection module; The inter-channel trigger phase difference detection module takes the trigger source channel as a reference, performs phase deviation statistics according to the secondary trigger signal of each channel, generates statistical results, and sends the statistical results to the host computer; The host computer performs calculation processing according to the statistical results, and feeds back the processing results to the secondary offset adjustment processing module of each FPGA processor; The secondary offset adjustment processing module of each FPGA processor generates a serial read control signal of the corresponding channel according to the processing result; Each of the FPGA processors reads the serial waveform data according to the serial read control signal of each channel, and displays the waveform through the host computer.

3. The method according to claim 2, characterized in that The FPGA processor is also provided with an interpolation processing module; after the serial processing of the read channel data, the method further includes: The interpolation processing module of each FPGA processor performs interpolation processing on the serial waveform data to obtain interpolation waveform data; The secondary trigger processing module of each FPGA processor performs trigger judgment on the interpolation waveform data to generate a secondary trigger signal.

4. The method according to claim 1, characterized in that: Each of the ADC acquisition cards includes a collector and a local controller; the collector is used to collect input signals and convert them into sampled data; a FIFO data buffer and a first-level trigger judgment module are provided inside the local controller, the FIFO data buffer is used to cache the sampled data collected by the collector, and the first-level trigger judgment module is used to perform trigger judgment on the sampled data and determine the trigger signal; Before each of the FPGA processors receives a trigger signal sent by an ADC acquisition card of a corresponding channel through its own primary trigger processing module, the method further includes: Each of the FPGA processors sends the collection start instruction sent by the host computer to each of the collectors, and controls each of the collectors to start collecting sampled data; Each of the collectors sends the collected sampled data to a corresponding FIFO data buffer for storage; Each collector synchronously sends the collected sampling data to the corresponding first-level trigger judgment module for trigger judgment. When the sampling data meets the trigger condition, the first-level trigger judgment module sends a trigger signal to the first-level trigger processing module of the corresponding FPGA processor.

5. The method according to claim 2, characterized in that: The inter-channel trigger phase difference detection module takes the trigger source channel as a reference, performs phase deviation statistics according to the secondary trigger signal of each channel, and generates statistical results, including: Obtaining the count value of each channel from the start of a write enable signal to the arrival of a secondary trigger signal, wherein the write enable signal is used to control data writing into the FIFO data buffer; The count value of the trigger source channel is selected as a reference, and the count value difference between each channel and the trigger source channel is calculated as a phase deviation value; The phase deviation values ​​of each channel are summarized and sent to the host computer as the statistical result.

6. The method according to claim 5, characterized in that The host computer performs calculation processing according to the statistical results, and feeds back the processing results to the secondary offset adjustment processing module of each FPGA processor, including: The host computer determines the serial offset control amount of each channel relative to the trigger source channel according to the phase deviation value of each channel; The serial offset control amount corresponding to each channel is sent to the secondary offset adjustment processing module of the corresponding FPGA processor.

7. The method according to claim 6, characterized in that The secondary offset adjustment processing module of each FPGA processor generates a serial read control signal of the corresponding channel according to the processing result, including: The secondary offset adjustment processing module calculates a reading deviation value of a corresponding channel relative to a trigger source channel according to the received serial offset control amount; Calculating a read adjustment amount and a read adjustment direction of a corresponding channel relative to a trigger source channel according to the read deviation value, wherein the read adjustment amount is determined according to an absolute value of the read deviation value, and the read adjustment direction is determined according to a positive or negative sign of the read deviation value; A serial read control signal of a corresponding channel is generated according to the read adjustment amount and the read adjustment direction.

8. The method according to claim 4, characterized in that The working states of the FIFO data buffer include a write-only state, a write-while-read state and a read-only state, wherein the write-only state is used to store the sampled data collected by the collector after receiving a write enable signal; the write-while-read state is started after the pre-trigger depth is full and a ready signal is generated, and is used to synchronously execute the writing and reading operations of the sampled data; when the trigger signal is detected, the write-only state is re-entered until the FIFO data buffer is full; the read-only state is started after the FIFO data buffer is full, and is used to read out the stored sampled data for processing.

9. A multi-FPGA based channel-to-channel trigger offset control system, characterized in that: The system is used to implement the method for controlling the trigger offset between channels based on multiple FPGAs according to any one of claims 1 to 8, the system comprising: The host computer is used to issue acquisition start instructions, process the statistical results of each channel and display the waveform; Multiple FPGA processors, including a master FPGA processor and multiple slave FPGA processors, each of the FPGA processors has a data transmission line, each of the FPGA processors is provided with at least two channels, and each of the channels has multiple ADC acquisition cards; The FPGA processor comprises: A first-level trigger processing module, used for receiving a trigger signal, determining a trigger source channel and generating a trigger source FIFO control signal group; A first-level offset adjustment module, used to calculate the parallel offset control amount; The trigger control data communication module is used to generate a FIFO control signal group.

10. A digital oscilloscope, characterized in that: Including the multi-FPGA-based channel-to-channel trigger offset control system as described in claim 9.

Images