LiDAR Chip, Its Operating Method, and LiDAR

Abstract

The present application discloses a lidar chip, an operating method thereof, and a lidar. The lidar chip includes a bus, a first data reading module, a first processor, a second data reading module, a second processor, a status configuration module, and a functional status determination module. The first processor receives and processes the data output by the first data reading module to obtain a first processing result. The status configuration module configures the second processor to switch between a first working state and a second working state. In the first working state, the second processor receives and processes the data output by the second data reading module. In the second working state, the second processor receives and processes the data output by the first data reading module to obtain a verification result. The functional status determination module determines whether the functions of the first processor and the second processor are normal based on the comparison result between the first processing result and the verification result. In the above manner, it is possible to meet the functional safety requirements and the high-performance requirements with one chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and particularly to a lidar chip, an operating method thereof, and a lidar. Background Art

[0002] The lidar chip is the core component of the lidar, responsible for the acquisition, processing, and transmission of all lidar information. Among them, in the vehicle-mounted system, the lidar chip undertakes an important object sensing function. Once the function fails, the consequences will directly affect the safety of the driver and passengers, that is, the chip needs to meet the functional safety requirements; for lidars used in some low-intensity application scenarios outside the vehicle-mounted system, such as the lidar used in a sweeping robot, functional safety is not required, but higher computing power is needed, that is, the chip needs to meet higher performance requirements. Summary of the Invention

[0003] The embodiments of the present application provide a lidar chip, an operating method thereof, and a lidar, which can meet the functional safety requirements and higher performance requirements through one chip.

[0004] In a first aspect, the embodiments of the present application provide a lidar chip, including a bus, a first data reading module, a first processor, a second data reading module, a second processor, a status configuration module, and a functional status determination module; the first data reading module is used to obtain data from a memory; the first processor is respectively connected to the bus and the first data reading module, and is used to receive and process the data output by the first data reading module to obtain a first processing result; the second data reading module is used to obtain data from the memory; the status configuration module is used to configure the second processor to switch between a first working state and a second working state. In the first working state, the second processor is connected to the bus, and the second processor is used to receive and process the data output by the second data reading module to obtain a second processing result and output it to the bus. In the second working state, the second processor is used to receive and process the data output by the first data reading module to obtain a verification result; the functional status determination module is respectively connected to the first processor and the second processor, and the functional status determination module is used to obtain the first processing result and the verification result when the second processor is in the second working state, and determine whether the functions of the first processor and the second processor are normal based on the comparison result of the first processing result and the verification result.

[0005] Configuring the second processor to switch between the first working state and the second working state enables the lidar chip to be applicable to application scenarios with high performance requirements and application scenarios with functional safety requirements, thus achieving the satisfaction of both functional safety requirements and high performance requirements with a single chip.

[0006] In one or more embodiments, the first data reading module and / or the second data reading module includes logic circuits; the first data reading module and the second data reading module are used to read data from different address regions of the memory; the lidar chip includes the memory, or the memory is a memory outside the lidar chip.

[0007] In one or more embodiments, the state configuration module includes: a multiplexing module having a first input, a second input, and a first output, the first input being connected to the first data reading module for receiving the data output by the first data reading module, the second input being connected to the second data reading module for receiving the data output by the second data reading module, and the first output being connected to the second processor; and a configuration register for configuring the multiplexing module to gate one of the first input and the second input of the multiplexing module to the first output.

[0008] In one or more embodiments, the multiplexing module includes: a first multiplexer connected to the configuration register, having a first input terminal, a second input terminal, and a first output terminal. The first input terminal is connected to the first data reading module and is configured to receive a first reading instruction obtained by the first data reading module from the memory. The second input terminal is connected to the second data reading module and is configured to receive a second reading instruction obtained by the second data reading module from the memory. The first output terminal is connected to the second processor. And a second multiplexer connected to the configuration register, having a third input terminal, a fourth input terminal, and a second output terminal. The third input terminal is connected to the first data reading module and is configured to receive first data obtained by the first data reading module from the memory. The fourth input terminal is connected to the second data reading module and is configured to receive second data obtained by the second data reading module from the memory. The second output terminal is connected to the second processor. The first input terminal and the third input terminal together form the first input part. The second input terminal and the fourth input terminal together form the second input part. The first output terminal and the second output terminal together form the first output part. The configuration register is configured to configure the first multiplexer and the second multiplexer such that: the first input terminal and the first output terminal are gated, and the third output terminal and the second output terminal are gated; or, the second input terminal and the first output terminal are gated, and the fourth input terminal and the second output terminal are gated.

[0009] In one or more embodiments, the multiplexing module further includes a third multiplexer connected to the configuration register. The third multiplexer has a fifth input terminal, a sixth input terminal, and a third output terminal. The fifth input terminal is connected to the second processor and is configured to receive a second processing result or the verification result output by the second processor. The sixth input terminal is configured to obtain preset information. The third output terminal is connected to the bus. The configuration register is configured to configure the third multiplexer such that: when the second processor is in the first working state, the fifth input terminal and the third output terminal are gated; and when the second processor is in the second working state, the sixth input terminal and the third output terminal are gated.

[0010] In one or more embodiments, the functional state determination module includes: a comparison unit respectively connected to the first processor and the second processor to obtain the first processing result and the verification result, and output a comparison result of the first processing result and the verification result; and a state determination unit connected to the comparison unit, configured to obtain the comparison result and determine whether the functions of the first processor and the second processor are normal based on the comparison result.

[0011] In one or more embodiments, the lidar chip includes a plurality of the first processors, a plurality of first data reading modules, a plurality of the second processors, and a plurality of the second data reading modules. The status configuration module includes a plurality of the multiplexing modules, and the function status determination module includes a plurality of comparison units. Each of the first processors corresponds to one of the first data reading modules, one of the second processors, one of the second data reading modules, one of the multiplexing modules, and one of the comparison units. Each of the multiplexing modules is respectively connected to the configuration register, and each of the comparison units is respectively connected to the status determination unit.

[0012] Setting a plurality of first processors is beneficial to increasing the computing power of the lidar chip and improving performance. For each first processor, a corresponding second processor is provided, which can further increase the computing power of the lidar chip or perform functional safety verification on each first processor and each second processor, so as to improve the safety and reliability of the lidar chip. In addition, by setting a plurality of second processors and switching the working states of the second processors according to the actual computing power load, it can be realized that the lidar chip can provide sufficient computing power for the actual computing power load. And, on the basis of having surplus computing power, the redundant second processors can also be used to implement verification of functional safety to improve the safety and reliability of the lidar chip.

[0013] In one or more embodiments, the lidar chip further includes a monitoring module. The monitoring module is respectively connected to the bus and the status configuration module. The monitoring module is configured to determine the current computing power load through the bus and output a feedback signal to the status configuration module based on the current computing power load and a preset computing power load. The status configuration module is further configured to control at least one of the second processors to be in the first working state when it is determined based on the feedback signal that the current computing power load is greater than or equal to the preset computing power load, and control each of the second processors to be in the second working state when it is determined based on the feedback signal that the current computing power load is less than the preset computing power load.

[0014] In one or more embodiments, the lidar chip further includes a reset module. The reset module is respectively connected to the status configuration module and the second processor, and the reset module is configured to reset the second processor under the control of the status configuration module.

[0015] Second aspect, an embodiment of the present application provides an operation method for a lidar chip, which is applied to the lidar chip as described above. The method includes: determining the current computing power load of the lidar chip; if the current computing power load is higher than a preset multiple of the total computing power of each computing processor, controlling at least one of the second processors to switch from the second working state to the first working state, so that the preset multiple of the total computing power of each computing processor is higher than the current computing power load, where the computing processor includes a first processor and a second processor in the first working state; if the current computing power load is lower than the preset multiple of the total computing power of each computing processor, controlling at least one of the second processors to switch from the first working state to the second working state, so that the preset multiple of the total computing power of each computing processor is still higher than the current computing power load.

[0016] Third aspect, an embodiment of the present application provides a lidar, including the lidar chip as described above.

[0017] The beneficial effects of the present application are as follows: The lidar chip of the embodiment of the present application includes a bus, a first data reading module, a first processor, a second data reading module, a second processor, a status configuration module, and a functional status determination module. The first data reading module obtains data from the memory. The second data reading module obtains data from the memory. The first processor is respectively connected to the bus and the first data reading module. The first processor receives and processes the data output by the first data reading module to obtain a first processing result. When a higher performance requirement needs to be met, the status configuration module configures the second processor to be in the first working state. At this time, the second processor is connected to the bus, and the second processor receives and processes the data output by the second data reading module to obtain a second processing result and outputs it to the bus. It can be seen that at this time, both the first processor and the second processor are used to process data to meet higher performance requirements. When a functional safety requirement is needed, the status configuration module configures the second processor to be in the second working state. At this time, the second processor receives and processes the data output by the first data reading module to obtain a verification result. Subsequently, when the second processor is in the second working state, the functional status determination module obtains the first processing result and the verification result, and determines whether the functions of the first processor and the second processor are normal based on the comparison result of the first processing result and the verification result, thereby meeting the functional safety requirement. Description of the Drawings

[0018] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplary illustrations are not intended to limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements.

[0019] Figure 1 Schematic diagram of the composition block diagram of the lidar chip provided by the embodiment of the present applicationFigure 1 ;

[0020] Figure 2 is Figure 1 a simplified schematic diagram of the composition block diagram of the lidar chip shown Figure 1 ;

[0021] Figure 3 is Figure 2 a simplified schematic diagram of the composition block diagram of the lidar chip shown Figure 2 ;

[0022] Figure 4 is a schematic diagram of the composition block diagram of the lidar chip provided by an embodiment of the present application Figure 2 ;

[0023] Figure 5 is a schematic diagram of the composition block diagram of the lidar chip provided by an embodiment of the present application Figure 3 ;

[0024] Figure 6 is a schematic diagram of the composition block diagram of the lidar chip provided by an embodiment of the present application Figure 4 ;

[0025] Figure 7 is a schematic diagram of the composition block diagram of the lidar chip provided by an embodiment of the present application Figure 5 ;

[0026] Figure 8 is a schematic diagram of the composition block diagram of the lidar chip provided by an embodiment of the present application Figure 6 ;

[0027] Figure 9 is a schematic diagram of the composition block diagram of the lidar chip provided by an embodiment of the present application Figure 7 ;

[0028] Figure 10 is a schematic diagram of the composition block diagram of the lidar chip provided by an embodiment of the present application Figure 8 ;

[0029] Figure 11 is a schematic diagram of the composition block diagram of the lidar chip provided by an embodiment of the present application Figure 9 ;

[0030] Figure 12 is a flowchart of the operation method of the lidar chip provided by an embodiment of the present application;

[0031] Figure 13 is a schematic structural diagram of the lidar applied to a vehicle provided by an embodiment of the present application. Detailed implementation manners

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and detailedly described below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0033] It should be noted that when an element is expressed as "connected" to another element, it can be directly connected to the other element, or there can be one or more intermediate elements therebetween.

[0034] In addition, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0035] Please refer to Figure 1 , Figure 1 which is a schematic diagram of the composition block diagram of the lidar chip provided by the embodiment of this application. As Figure 1 shown, the lidar chip 100 includes a bus 10, a first data reading module 20, a first processor 30, a second data reading module 40, a second processor 50, a status configuration module 60, and a function status determination module 70.

[0036] Among them, the first data reading module 20 is used to obtain data from the memory M1. The first processor 30 is respectively connected to the bus 10 and the first data reading module 20. The first processor 30 is used to receive the data D1 output by the first data reading module 20 and process it to obtain a first processing result DA1, and output it to the bus 10. The second data reading module 40 is used to obtain data from the memory M1. The status configuration module 60 is used to configure the second processor 50 to switch between a first working state and a second working state. In the first working state, the second processor 50 is connected to the bus 10. The second processor 50 is used to receive and process the data D2 output by the second data reading module 40 to obtain a second processing result DA2, and output it to the bus 10. In the second working state, the second processor 50 is used to receive and process the data D1 output by the first data reading module 20 to obtain a verification result DB1. The function status determination module 70 is respectively connected to the first processor 30 and the second processor 50. The function status determination module 70 is used to obtain the first processing result DA1 and the verification result DB1 when the second processor 50 is in the second working state, and determine whether the functions of the first processor 30 and the second processor 50 are normal based on the comparison result between the first processing result DA1 and the verification result DB1.

[0037] Among them, the data D1 output by the first data reading module 20 and the data D2 output by the second data reading module 40 can be the same data or different data. In practical applications, the first data reading module 20 and the second data reading module 40 can read data from different address areas of the memory, or can read data from the same address area of the memory. By configuring the first data reading module 20 and the second data reading module 40 to read data from different address areas of the memory, the first processor 30 and the second processor 50 can process data in different address areas respectively, which is beneficial to improving work efficiency.

[0038] The processing of data by the processor (including the first processor 30 processing the data D1 and the second processor 50 processing the data D2) includes but is not limited to numerical calculation, instruction parsing, resource scheduling, error detection and recovery, and other aspects of work. In some embodiments, each processor (including the first processor 30 and the second processor 50) is configured as a Central Processing Unit (CPU).

[0039] When the status configuration module 60 configures the second processor 50 to switch to the first working state, Figure 1 The shown block diagram can be simplified as Figure 2 The shown block diagram. As Figure 2 As shown, the first processor 30 receives the data D1 output by the first data reading module 20 and processes it to obtain the first processing result DA1, and outputs it to the bus 10. The second processor 50 receives and processes the data D2 output by the second data reading module 40 to obtain the second processing result DA2, and outputs it to the bus 10. At this time, both the first processor 30 and the second processor 50 are used to process data, and it can be applied to application scenarios with high performance requirements.

[0040] When the status configuration module 60 configures the second processor 50 to switch to the second working state, Figure 1 The shown block diagram can be simplified as Figure 3 The shown block diagram. As Figure 3As shown, the first processor 30 receives the data D1 output by the first data reading module 20, processes it to obtain the first processing result DA1, and outputs it to the bus 10 and the function status determination module 70. The second processor 50 receives and processes the data D1 output by the first data reading module 20, obtains the verification result DB1, and outputs it to the function status determination module 70. The function status determination module 70 determines whether the functions of the first processor 30 and the second processor 50 are normal based on the comparison result between the first processing result DA1 and the verification result DB1. At this time, the first processor 30 is used to process data, and the second processor 50 is used to verify whether the functions of the first processor 30 and the second processor 50 are normal, which can be applied to application scenarios with functional safety requirements. It can be understood that in this embodiment, when the second processor 50 is in the second working state, both the first processor 30 and the second processor 50 receive the data D1, and the processing methods for the data D1 are exactly the same. Based on this, if the comparison result between the first processing result DA1 and the verification result DB1 is that the first processing result DA1 is the same as the verification result DB1, it can be determined that the functions of the first processor 30 and the second processor 50 are normal; conversely, if the comparison result between the first processing result DA1 and the verification result DB1 is that the first processing result DA1 is different from the verification result DB1, it can be determined that the function of the first processor 30 and / or the second processor 50 is abnormal.

[0041] In summary, for this lidar chip 100, by configuring the second processor 50 to switch between the first working state and the second working state, it can be applied to application scenarios with high performance requirements and functional safety requirements, that is, it realizes meeting the functional safety requirements and high performance requirements with one chip. For example, when the lidar is a vehicle-mounted lidar, it requires strong computing power to cope with complex and changeable scenarios; at this time, the second processor 50 can be configured to the first working state through the state configuration module 60, and both the first processor 30 and the second processor 50 act as processors providing computing power, which is beneficial to improving the overall computing power of the lidar. When the lidar is a lidar carried by devices such as a sweeping robot or a delivery robot, since the application scenario is relatively limited, there is no need for excessive computing power for signal processing, but higher reliability needs to be ensured to ensure the safety and reliability of the product during use; at this time, the second processor 50 can be configured to the second working state through the state configuration module 60, the first processor 30 serves as the processor providing computing power, and the second processor 50 serves as the functional safety processor to verify whether the first processor 30 or the second processor 50 is normal; when at least one of the first processor 30 and the second processor 50 is abnormal, an instruction indicating the lidar abnormality can be uploaded to the host computer to pause the work of some modules or the whole of the lidar.

[0042] It can be understood that in Figures 1 - 3In the lidar chip 100 shown, the memory M1 is taken as an example of a memory outside the lidar chip 100. In other embodiments, the memory M1 may also be provided inside the lidar chip 100, as Figure 4 shown.

[0043] In some embodiments, the first data reading module and / or the second data reading module include logic circuits. Among them, the logic circuit is an electronic circuit used to process and operate digital signals. It works based on the binary principle, that is, it transmits information through high and low levels (usually represented as 0 or 1) and performs logical operations. The core components of the logic circuit are logic gates (such as AND gates), and these logic gates can generate corresponding output signals according to different combinations of input signals.

[0044] In some embodiments, as Figure 5 shown, the status configuration module 60 includes a multiplexing module 61 and a configuration register 62.

[0045] Among them, the multiplexing module 61 has a first input part I1, a second input part I2 and a first output part O1. The first input part I1 is connected to the first data reading module 20, and the first input part I1 is used to receive the data D1 output by the first data reading module 20; the second input part I2 is connected to the second data reading module 40, and the second input part I2 is used to receive the data D2 output by the second data reading module 40, and the first output part O1 is connected to the second processor 50. The configuration register 62 is used to configure the multiplexing module 61 so that one of the first input part I1 and the second input part I2 of the multiplexing module 61 is gated with the first output part O1. The configuration register 62 is also connected to the second processor 50 to configure the second processor 50 to be in a first working state or a second working state.

[0046] When the configuration register 62 configures the second processor 50 to be in the first working state, the configuration register 62 configures the second input part I2 and the first output part O1 to be gated, so that the second processor 50 receives and processes the data D2 output by the second data reading module 40. At this time, the second processor 50 is used to process data to improve the overall performance of the lidar chip 100, which is beneficial to meeting higher performance requirements.

[0047] When the configuration register 62 configures the second processor 50 to be in the second working state, the configuration register 62 configures the first input part I1 and the first output part O1 to be gated, so that the second processor 50 receives and processes the data D1 output by the first data reading module 20. At this time, the second processor 50 is used to verify whether the functions of the first processor 30 and the second processor 50 are normal, which is beneficial to meeting the requirements of functional safety.

[0048] In some embodiments, as Figure 6As shown, the multiplexing module 61 includes a first multiplexer 611 and a second multiplexer 612.

[0049] The first multiplexer 611 is connected to the configuration register 62. The first multiplexer 611 has a first input terminal I1_1, a second input terminal I2_1, and a first output terminal O1_1. The first input terminal I1_1 is connected to the first data reading module 20, and the first input terminal I1_1 is used to receive a first reading instruction D1_1 obtained by the first data reading module 20 from the memory M1; the second input terminal I2_1 is connected to the second data reading module 40, and the second input terminal I2_1 is used to receive a second reading instruction D2_1 obtained by the second data reading module 40 from the memory M1; the first output terminal O1_1 is connected to the second processor 50. The second multiplexer 612 is connected to the configuration register 62. The second multiplexer 612 has a third input terminal I1_2, a fourth input terminal I2_2, and a second output terminal O1_2. The third input terminal I1_2 is connected to the first data reading module 20, and the third input terminal I1_2 is used to receive a first data D1_2 obtained by the first data reading module 20 from the memory M1; the fourth input terminal I2_2 is connected to the second data reading module 40, and the fourth input terminal I2_2 is used to receive a second data D2_2 obtained by the second data reading module 40 from the memory M1; the second output terminal O1_2 is connected to the second processor 50.

[0050] Among them, the first input terminal I1_1 and the third input terminal I1_2 together constitute a first input part I1, the second input terminal I2_1 and the fourth input terminal I2_2 together constitute a second input part I2, and the first output terminal O1_1 and the second output terminal O1_2 together constitute a first output part O1. The data D1 output by the first data reading module 20 includes a first reading instruction D1_1 and a first data D1_2; the data D2 output by the second data reading module 40 includes a second reading instruction D2_1 and a second data D2_2.

[0051] The configuration register 62 is used to configure the first multiplexer 611 and the second multiplexer 612, so that: the first input terminal I1_1 is gated with the first output terminal O1_1, and the third input terminal I1_2 is gated with the second output terminal O1_2; or, the second input terminal I2_1 is gated with the first output terminal O1_1, and the fourth input terminal I2_2 is gated with the second output terminal O1_2. When the first input terminal I1_1 is gated with the first output terminal O1_1, and the third input terminal I1_2 is gated with the second output terminal O1_2, it corresponds to the first input part I1 being gated with the first output part O1. At this time, the configuration register 62 configures the second processor 50 to be in the second working state; when the second input terminal I2_1 is gated with the first output terminal O1_1, and the fourth input terminal I2_2 is gated with the second output terminal O1_2, it corresponds to the second input part I2 being gated with the first output part O1. At this time, the configuration register 62 configures the second processor 50 to be in the first working state.

[0052] In some embodiments, such as Figure 7 shown, the multiplexing module 61 further includes a third multiplexer 613, and the third multiplexer 613 is connected to the configuration register 62. The third multiplexer 613 has a fifth input terminal I3, a sixth input terminal I4, and a third output terminal O2. The fifth input terminal I3 is connected to the second processor 50, and the fifth input terminal I3 is used to receive the second processing result DA2 or the verification result DB1 output by the second processor 50; the sixth input terminal I4 is used to obtain preset information DC1, and the preset information DC1 can be set based on the actual application scenario. The embodiments of the present application do not make specific limitations on this. For example, in some embodiments, the preset information DC1 is configured to be 0; the third output terminal O2 is connected to the bus 10.

[0053] The configuration register 62 is used to configure the third multiplexer 613, so that: when the second processor 50 is in the first working state, the fifth input terminal I3 is gated with the third output terminal O2; and when the second processor 50 is in the second working state, the sixth input terminal I4 is gated with the third output terminal O2. In other words, when the second processor 50 is in the first working state, it is used to obtain the second data D2_2 through the second data reading module 40. When the fifth input terminal I3 of the third multiplexer 613 is gated with the third output terminal O2, the second processor 50 is connected to the bus 10, and the second processing result DA2 output by the second processor 50 is output to the bus 10. When the second processor 50 is in the second working state, it is used to obtain the first data D1_2 through the first data reading module 20. When the sixth input terminal I4 of the third multiplexer 613 is gated with the third output terminal O2, the second processor 50 is not connected to the bus 10, and the preset information DC1 is output to the bus 10; at the same time, the verification result DB1 output by the second processor 50 is output to the function status determination module 70.

[0054] In some embodiments, such as Figure 8 shown, the function status determination module includes a comparison unit and a status determination unit 72.

[0055] Among them, the comparison unit 71 is respectively connected to the first processor 30 and the second processor 50 to obtain the first processing result DA1 and the verification result DB1, and output the comparison result of the first processing result DA1 and the verification result DB1. In some embodiments, the comparison unit 71 may include a comparator circuit; of course, in other embodiments of the present application, the comparison unit 71 may also be any other element capable of performing a comparison operation, such as a processor, and the present application does not limit this. The status determination unit 72 is connected to the comparison unit 71. The status determination unit 72 is used to obtain the comparison result and determine whether the functions of the first processor 30 and the second processor 50 are normal based on the comparison result. Specifically, if the status determination unit 72 determines that the comparison result is that the first processing result DA1 is the same as the verification result DB1, it can be determined that the functions of the first processor 30 and the second processor 50 are normal; conversely, if the status determination unit 72 determines that the comparison result is that the first processing result DA1 is different from the verification result DB1, it can be determined that the function of the first processor 30 and / or the second processor 50 is abnormal. In some embodiments, the status determination unit 72 includes a microcontroller unit (MCU); of course, in other embodiments of the present application, the status determination unit 72 may also be any other circuit element capable of indexing or determining the corresponding status according to the input comparison result, and the present application does not limit this.

[0056] In some embodiments, after the status determination unit 72 determines whether the functions of the first processor 30 and the second processor 50 are normal based on the comparison result, it can report the determination result to a superior device (such as the processor of the host computer) so that the superior device can perform corresponding operations according to the received determination result. For example, in a specific embodiment, if the superior device determines that the function of the first processor 30 is abnormal according to the determination result, the superior device controls the first processor 30 to stop working and outputs an alarm signal.

[0057] It can be understood that when the status configuration module 60 configures the second processor 50 to be in the second working state, the comparison unit 71 starts to work and outputs a comparison result, and then the status determination unit 72 determines whether the first processor 30 and the second processor 50 are normal according to the comparison result. When the status configuration module 60 configures the second processor 50 to be in the first working state, the comparison unit 71 and the status determination unit 72 stop working.

[0058] In some embodiments, such as Figure 9As shown, the lidar chip 100 includes a plurality of first processors 30, a plurality of first data reading modules 20, a plurality of second processors 50, and a plurality of second data reading modules 40. The status configuration module 60 includes a plurality of multiplexing modules 61, and the function status determination module 70 includes a plurality of comparison units 71. Each first processor 30 corresponds to a first data reading module 20, a second processor 50, a second data reading module 40, a multiplexing module 61, and a comparison unit 71. Each multiplexing module 61 is respectively connected to a configuration register 62, and each comparison unit 71 is respectively connected to a status determination unit 72.

[0059] Specifically, the plurality of first processors 30 include a first first processor 30, a second first processor 30, …, an Nth first processor 30, where N is an integer greater than 1. The plurality of first data reading modules 20 include a first first data reading module 20, a second first data reading module 20, …, an Nth first data reading module 20. The plurality of second processors 50 include a first second processor 50, a second second processor 50, …, an Nth second processor 50. The plurality of second data reading modules 40 include a first second data reading module 40, a second second data reading module 40, …, an Nth second data reading module 40. The plurality of multiplexing modules 61 include a first multiplexing module 61, a second multiplexing module 61, …, an Nth multiplexing module 61. The plurality of comparison units 71 include a first comparison unit 71, a second comparison unit 71, …, an Nth comparison unit 71.

[0060] The first first processor 30 corresponds to the first first data reading module 20, the first second processor 50, the first second data reading module 40, the first multiplexing module 61, and the first comparison unit 71; the second first processor 30 corresponds to the second first data reading module 20, the second second processor 50, the second second data reading module 40, the second multiplexing module 61, and the second comparison unit 71; …; the Nth first processor 30 corresponds to the Nth first data reading module 20, the Nth second processor 50, the Nth second data reading module 40, the Nth multiplexing module 61, and the Nth comparison unit 71. The first multiplexing module 61, the second multiplexing module 61, …, the Nth multiplexing module 61 are connected to the configuration register 62, and the first comparison unit 71, the second comparison unit 71, …, the Nth comparison unit 71 are connected to the status determination unit 72. It should be noted that each multiplexing module 61 includes a third multiplexer 613, but considering that the third multiplexer 613 and the first / second multiplexers are distributed on both sides of the second processor 50 and are not convenient to display, so Figure 9 it is not shown in the figure.

[0061] It can be understood that, in addition to the memory M1 and the bus 10, Figure 9 the other parts in the illustrated embodiments can be regarded as being composed of N embodiments as Figures 1 - 8 illustrated, and the specific implementation process of each is the same. For example, Figure 9 the first first processor 30, the first first data reading module 20, the first second processor 50, the first second data reading module 40, the first multiplexing module 61, and the first comparison unit 71 in Figures 1 - 8 can correspond to any of the embodiments as Figures 1 - 8 illustrated, and the specific implementation process can refer to the description for

[0062] In this embodiment, on the one hand, setting multiple first processors 30 is beneficial to increasing the computing power of the lidar chip 100 and improving the performance; on the other hand, for each first processor 30, a corresponding second processor 50 is set to further increase the computing power of the lidar chip 100, or, functional safety verification is performed on each group of corresponding first processors 30 and second processors 50 to improve the safety and reliability of the lidar chip 100.

[0063] It should be noted that the signals output by different first data reading modules 20 can be the same or different; the first processing results output by different first processors 30 can be the same or different; the signals output by different second data reading modules 40 can be the same or different; the second processing results output by different second processors 50 can be the same or different; the verification results output by different second processors 50 can be the same or different; the addresses at which different data reading modules (including each first data reading module 20 and each second data reading module 40) read data from the memory M1 can be the same or different.

[0064] It should be noted that, in this embodiment, the case where the first processors 30 and the second processors 50 are in one-to-one correspondence is taken as an example. In other embodiments, any number of first processors 30 can also be set to correspond to second processors of any data. For example, in a specific embodiment, setting one first processor 30 to correspond to multiple second processors 50 can verify functional safety through multiple second processors 50 together, and can more effectively improve safety; in another specific embodiment, setting multiple first processors 30 to correspond to one second processor 50 can verify the functions of multiple first processors 30 through one second processor 50 at the same time to save costs.

[0065] In some embodiments, as Figure 10As shown, the lidar chip 100 further includes a monitoring module 80. The monitoring module 80 is respectively connected to the bus 10 and the status configuration module 60.

[0066] Among them, the monitoring module 80 is used to determine the current computing power load through the bus 10, and output a feedback signal to the status configuration module 60 based on the comparison between the current computing power load and the preset computing power load. The status configuration module 60 is further used to control at least one second processor 50 to be in the first working state when it is determined based on the feedback signal that the current computing power load is greater than or equal to the preset computing power load, and to control each second processor 50 to be in the second working state when it is determined based on the feedback signal that the current computing power load is less than the preset computing power load.

[0067] Specifically, the current computing power load is the total computing power that each first processor 30 and each second processor 50 currently need to provide for the load. The preset computing power load is the total computing power that each first processor 30 and each second processor 50 are preset to provide for a preset load. For example, in some embodiments, the preset computing power load can be a preset multiple of the total computing power of all first processors 30; taking the lidar chip 100 including four first processors 30 as an example, the preset computing power load can be 1 times, 0.95 times, 0.85 times or 1.05 times the total computing power of the four first processors 30, etc.

[0068] If the current computing power load is greater than or equal to the preset computing power load, it is determined that the total computing power preset to be provided by each first processor 30 and each second processor 50 is less than the total computing power required by the current load, that is, the total computing power preset to be provided by each first processor 30 and each second processor 50 cannot meet the demand, and the total computing power needs to be increased. Based on this, at least one second processor 50 can be controlled to be in the first working state to use at least one second processor 50 to process data, thereby increasing the total computing power to meet the total computing power required by the current load.

[0069] If the current computing power load is less than the preset computing power load, it is determined that the total computing power preset to be provided by each first processor 30 and each second processor 50 is greater than the total computing power required by the current load, that is, the total computing power preset to be provided by each first processor 30 and each second processor 50 can meet the demand. Based on this, each second processor 50 can be controlled to be in the second working state to use each second processor 50 for checking functional safety, thereby improving the safety and reliability of the lidar chip 100. Specifically, if at least one second processor 50 was in the first working state before, at least some of the second processors 50 can be switched to the second working state to perform functional safety monitoring work.

[0070] It should be understood that even though the above embodiments illustrate the switching principle of the second processor 50 with a preset computing power load as a fixed value, the present application is not limited thereto. In other embodiments of the present application, the preset computing power load may also be variable. For example, in some other embodiments of the present application, the preset computing power load may be a preset multiple of the total computing power of all current first processors 30 and the second processors 50 in the first working state. In this way, the lidar chip 100 can gradually switch at least one second processor 50 in the second working state to the first working state, so that the total computing power of the current lidar chip 100 gradually increases from lower than the current computing power load to slightly higher than the current computing power load to meet the corresponding computing power requirements; or, gradually switch at least one second processor 50 in the first working state to the second working state, so that the total computing power of the current lidar gradually decreases from significantly higher than the current computing power load to slightly higher than the current computing power load to meet the corresponding computing power requirements, while avoiding computing power surplus, and also being able to provide high-quality functional safety monitoring.

[0071] In some embodiments, as Figure 11 shown, the lidar chip 100 further includes a reset module 90. The reset module 90 is respectively connected to the state configuration module 60 and the second processor 50.

[0072] Specifically, the reset module 90 is configured to reset the second processor 50 under the control of the state configuration module 60. When the state configuration module 60 configures the second processor 50 to switch from the first working state to the second working state or from the second working state to the first working state, the state configuration module 60 can control the reset module 90 to reset the second processor 50 to clear all registers, caches, and other internal state information inside the second processor 50, so as to ensure that the second processor 50 can start running from the correct state after switching the working state, thereby avoiding the occurrence of uncertain behaviors or error states.

[0073] In some embodiments, when controlling the second processor 50 to switch from one of the first working state and the second working state to the other, the state configuration module 60 can control the reset module 90 to reset the second processor 50, and the configuration register 62 controls the corresponding multiplexing module 61 to perform the corresponding gating operation according to the working state after the second processor 50 switches; then, after waiting for a preset duration, it is determined that the reset operation of the second processor 50 is completed, that is, all registers, caches, and other internal state information inside the second processor 50 have been cleared, then the state configuration module 60 controls the reset module 90 to no longer reset the second processor 50.

[0074] In summary, for the lidar chip 100, by configuring the second processor 50 to switch between the first working state and the second working state, the lidar chip 100 can be applicable to application scenarios with high performance requirements and application scenarios with functional safety requirements. Thus, it is realized that a single chip can meet the functional safety requirements and high performance requirements. Secondly, setting multiple first processors 30 is beneficial to increasing the computing power of the lidar chip 100 and improving the performance. Furthermore, for each first processor 30, a corresponding second processor 50 is set to further increase the computing power of the lidar chip 100 or perform functional safety verification on each first processor 30 and each second processor 50, which is beneficial to improving the safety and reliability of the lidar chip 100. In addition, by setting multiple second processors 50 and switching the working state of the second processors 50 according to the actual computing power load, it is possible to ensure that the lidar chip 100 can provide sufficient computing power for the actual computing power load. Moreover, on the basis of having surplus computing power, the surplus second processors 50 (i.e., the second processors 50 that do not need to provide computing power) can be used to implement the verification of functional safety to improve the safety and reliability of the lidar chip 100.

[0075] Please refer to Figure 12 , Figure 12 which is a flowchart of the operation method of the lidar chip provided by the embodiment of the present application. Among them, this method is applied to Figures 9 - 11 the lidar chip 100 shown as follows. As Figure 12 shown, the operation method of this lidar chip includes the following method steps:

[0076] Step 1201: Determine the current computing power load of the lidar chip.

[0077] Step 1202: If the current computing power load is higher than a preset multiple of the total computing power of each computing processor, control at least one second processor to switch from the second working state to the first working state, so that the preset multiple of the total computing power of each computing processor is higher than the current computing power load, where the computing processor includes the first processor and the second processor in the first working state.

[0078] Step 1203: If the current computing power load is lower than a preset multiple of the total computing power of each computing processor, control at least one second processor to switch from the first working state to the second working state, so that the preset multiple of the total computing power of each computing processor is still higher than the current computing power load.

[0079] Specifically, when the current computing power load is higher than a preset multiple of the total computing power of each computing processor, the actual workload (i.e., load) allocated to each computing processor has exceeded a certain predetermined ratio or multiple of the maximum theoretical computing power that each computing processor can provide. Such a situation may lead to problems such as performance degradation, increased latency, and impaired quality of service (QoS). In this case, controlling at least one second processor to switch from the second working state to the first working state, so that the preset multiple of the total computing power of each computing processor is higher than the current computing power load, can relieve the computing pressure of each computing processor, so that each computing processor can operate stably and efficiently.

[0080] When the current computing power load is lower than a preset multiple of the total computing power of each computing processor, the actual workload allocated to each computing processor does not reach a certain predetermined ratio or multiple of the maximum theoretical computing power that each computing processor can provide, which will result in a waste of resources. In this case, at least one second processor switches from the first working state to the second working state, so that the preset multiple of the total computing power of each computing processor is still higher than the current computing power load, which not only ensures that each computing processor can still operate stably and efficiently, but also utilizes the redundant second processor 50 for checking functional safety to improve the safety and reliability of the lidar chip 100.

[0081] The embodiment of the present application also provides a lidar, which includes the lidar chip 100 in any embodiment of the present application.

[0082] The lidar can be a mechanical lidar, a solid-state lidar, a semi-solid-state lidar, etc., and the present application does not make a unique limitation thereto. The lidar can be applied to any device that needs to perform laser detection, such as a mobile robot, a ship, or a vehicle 1301 as shown in Figure 13 When the lidar 1302 is applied to the vehicle 1301, the lidar 1302 can detect parameters such as the distance and speed between the vehicle 1301 and the obstacle. The vehicle 1301 detects nearby moving or approaching obstacles through the lidar 1302, such as taller vehicles, static objects on the roadside, and suddenly approaching hovering flying objects, so that the vehicle 1301 can plan a path that can avoid obstacles according to the detected information, so that the vehicle 1301 can avoid colliding with obstacles. The vehicle 1301 can be an autonomous vehicle or an ordinary vehicle, and the present application does not make a unique limitation thereto.

[0083] The above are only the embodiments of the present application, and do not limit the patent scope of the present application accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be similarly included in the patent protection scope of the present application.

[0084] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order. Those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A laser radar chip, characterized in that: It includes a bus, a first data reading module, a first processor, a second data reading module, a second processor, a state configuration module and a function state determination module; The first data reading module is used to obtain data from the memory; The first processor is connected to the bus and the first data reading module respectively, and is used to receive and process the data output by the first data reading module to obtain a first processing result; The second data reading module is used to obtain data from the memory; The state configuration module is used to configure the second processor to switch between a first working state and a second working state. In the first working state, the second processor is connected to the bus. The second processor is used to receive and process the data output by the second data reading module to obtain a second processing result and output it to the bus. In the second working state, the second processor is used to receive and process the data output by the first data reading module to obtain a verification result. In the second working state, the data received by the second processor is the same as the data received by the first processor, and the second processor and the first processor process the data in the same manner. The functional status determination module is connected to the first processor and the second processor respectively. The functional status determination module is used to obtain the first processing result and the verification result when the second processor is in the second working state, and determine whether the functions of the first processor and the second processor are normal based on the comparison result between the first processing result and the verification result.

2. The laser radar chip according to claim 1, characterized in that: The first data reading module and / or the second data reading module comprises a logic circuit; The first data reading module and the second data reading module are used to read data from different address areas of the memory; The laser radar chip includes the memory, or the memory is a memory outside the laser radar chip.

3. The laser radar chip according to claim 1, characterized in that: The state configuration module includes: a multiplexing module having a first input portion, a second input portion and a first output portion, wherein the first input portion is connected to the first data reading module for receiving data output by the first data reading module, the second input portion is connected to the second data reading module for receiving data output by the second data reading module, and the first output portion is connected to the second processor; and The configuration register is used to configure the multiplexing module so that one of the first input part and the second input part of the multiplexing module is connected to the first output part.

4. The laser radar chip according to claim 3, characterized in that: The multiplexing module comprises: a first multiplexer connected to the configuration register, having a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is connected to the first data reading module and is used to receive a first read instruction acquired from the memory by the first data reading module, the second input terminal is connected to the second data reading module and is used to receive a second read instruction acquired from the memory by the second data reading module, and the first output terminal is connected to the second processor; and a second multiplexer connected to the configuration register, having a third input terminal, a fourth input terminal and a second output terminal, wherein the third input terminal is connected to the first data reading module and is used to receive the first data acquired from the memory by the first data reading module, the fourth input terminal is connected to the second data reading module and is used to receive the second data acquired from the memory by the second data reading module, and the second output terminal is connected to the second processor; The first input end and the third input end together constitute the first input part, the second input end and the fourth input end together constitute the second input part, and the first output end and the second output end together constitute the first output part; The configuration register is used to configure the first multiplexer and the second multiplexer so that: The first input terminal is connected to the first output terminal, and the third output terminal is connected to the second output terminal; or, The second input terminal is gated to the first output terminal, and the fourth input terminal is gated to the second output terminal.

5. The laser radar chip according to claim 3, characterized in that: The multiplexing module further comprises a third multiplexer, wherein the third multiplexer is connected to the configuration register; The third multiplexer has a fifth input terminal, a sixth input terminal and a third output terminal, the fifth input terminal is connected to the second processor and is used to receive the second processing result or the verification result output by the second processor, the sixth input terminal is used to obtain preset information, and the third output terminal is connected to the bus; The configuration register is used to configure the third multiplexer so that: When the second processor is in the first working state, the fifth input terminal and the third output terminal are switched on; as well as When the second processor is in the second working state, the sixth input terminal and the third output terminal are selected.

6. The laser radar chip according to claim 3, characterized in that: The functional status determination module includes: a comparison unit, connected to the first processor and the second processor respectively, to obtain the first processing result and the verification result, and output a comparison result between the first processing result and the verification result; and A state determination unit is connected to the comparison unit, and is used to obtain the comparison result, and determine whether the functions of the first processor and the second processor are normal based on the comparison result.

7. The laser radar chip according to claim 6, characterized in that: The laser radar chip includes a plurality of the first processors, a plurality of the first data reading modules, a plurality of the second processors and a plurality of the second data reading modules, the state configuration module includes a plurality of the multiplexing modules, the functional state determination module includes a plurality of comparison units, and each of the first processors corresponds to a first data reading module, a second processor, a second data reading module, a multiplexing module and a comparison unit; Each of the multiplexing modules is connected to the configuration register respectively, and each of the comparing units is connected to the state determining unit respectively.

8. The laser radar chip according to claim 7, characterized in that: The laser radar chip also includes a monitoring module; The monitoring module is connected to the bus and the state configuration module respectively, and the monitoring module is used to determine the current computing load through the bus, and output a feedback signal to the state configuration module based on the current computing load and the preset computing load; The state configuration module is also used to control at least one of the second processors to be in the first working state when it is determined based on the feedback signal that the current computing power load is greater than or equal to the preset computing power load, and to control each of the second processors to be in the second working state when it is determined based on the feedback signal that the current computing power load is less than the preset computing power load.

9. The laser radar chip according to claim 3, characterized in that: The laser radar chip also includes a reset module; The reset module is connected to the state configuration module and the second processor respectively, and the reset module is configured to be controlled by the state configuration module to reset the second processor.

10. A method for operating a laser radar chip, characterized in that: Applied to the laser radar chip as claimed in claim 7 or 8, the method comprises: Determining the current computing load of the lidar chip; If the current computing power load is higher than a preset multiple of the total computing power of each computing processor, control at least one of the second processors to switch from the second working state to the first working state, so that the preset multiple of the total computing power of each computing processor is higher than the current computing power load, wherein the computing processor includes a first processor and a second processor in the first working state; If the current computing power load is lower than a preset multiple of the total computing power of each computing processor, control at least one of the second processors to switch from the first working state to the second working state so that the preset multiple of the total computing power of each computing processor is still higher than the current computing power load.

11. A laser radar, characterized in that: Comprising a laser radar chip as described in any one of claims 1 to 9.

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