Data processing method, device and system, computing equipment and storage medium

Abstract

The invention discloses a data processing method, which comprises the following steps of: acquiring an instruction sequence of an application program by a processor, identifying an execution sequence of read-write instructions in the instruction sequence according to the instruction sequence, and executing the read-write instructions according to the identified execution sequence so as to access a memory in computing equipment, so that the processor can normally execute the application program.

Description

[0001] This application is a divisional application. The application number of the original application is 202210238254.1, and the original application date is March 11, 2022. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a data processing method, apparatus, system, computing device and storage medium. Background Art

[0003] The application includes read and write instructions for performing read or write operations on the memory. When the processor executes the application, it inevitably performs read and write operations on the memory by executing the read and write instructions in the application. However, during the process of the processor performing read and write operations on the memory, the processor may not be able to execute the application normally. Summary of the invention

[0004] The present application provides a data processing method, apparatus, system, computing device, and storage medium, which can enable a processor to run an application program normally. The technical solution is as follows:

[0005] In a first aspect, a data processing method is provided, which is executed by a processor of a computing device, and the method includes: obtaining an instruction sequence of an application, identifying an execution order of read and write instructions in the instruction sequence according to the instruction sequence, and executing the read and write instructions according to the identified execution order, wherein the instruction sequence includes multiple instructions, and the multiple instructions include read and write instructions for performing read operations or write operations on the memory of the computing device, and the application is deployed in the computing device.

[0006] The method obtains an instruction sequence of an application by a processor, identifies an execution order of read and write instructions in the instruction sequence according to the instruction sequence, and executes the read and write instructions according to the identified execution order to access the memory in the computing device, so that the processor can execute the application normally.

[0007] In a possible implementation, identifying the execution order of the read and write instructions in the instruction sequence according to the instruction sequence includes: identifying the arrangement order of the read and write instructions in the instruction sequence as the execution order of the read and write instructions.

[0008] Based on the above possible implementation methods, the arrangement order of read and write instructions in the instruction sequence is forcibly identified as the execution order of the read and write instructions, so that the arrangement order of the read and write instructions in the instruction sequence is consistent with the execution order of the read and write instructions. Accordingly, when the processor executes the read and write instructions according to the execution order of the read and write instructions, it can avoid the situation where the access order of the memory is inconsistent with the arrangement order of the read and write instructions in the application, thereby avoiding memory consistency problems.

[0009] In another possible implementation, the order in which the read and write instructions are arranged in an instruction sequence is identified as the execution order of the read and write instructions, including: according to a sequential memory access mode, the order in which the read and write instructions are arranged in the instruction sequence is identified as the execution order of the read and write instructions; wherein the sequential memory access mode requires that the execution order of the read and write instructions is consistent with the order in which the read and write instructions are arranged in the instruction sequence.

[0010] Based on the above possible implementation methods, since the sequential memory access mode requires that the execution order of read and write instructions be consistent with the arrangement order of read and write instructions in the instruction sequence, therefore, according to the sequential memory access mode, the processor forcibly recognizes the arrangement order of read and write instructions in the instruction sequence as the execution order of read and write instructions. Accordingly, when the processor executes read and write instructions according to the execution order of read and write instructions, it can avoid the situation where the access order of memory is inconsistent with the arrangement order of read and write instructions in the application, thereby avoiding memory consistency problems.

[0011] In another possible implementation, the read and write instructions include a read instruction for performing a read operation on the memory or a write instruction for performing a write operation on the memory, the read instruction has a first semantics, and the write instruction has a second semantics; wherein the first semantics is used to indicate that the first instruction in the instruction sequence is executed after the read instruction is executed, and the second semantics is used to indicate that the second instruction in the instruction sequence is executed before the write instruction is completed, and the first instruction is arranged in an order after the read instruction in the instruction sequence, and the second instruction is arranged in an order before the write instruction in the instruction sequence.

[0012] Based on the above possible implementation methods, since the read instruction has the first semantics and the write instruction has the second semantics, the processor can be automatically triggered to identify the execution order of the read and write instructions according to the instruction sequence. Accordingly, when the processor executes the read and write instructions according to the execution order of the read and write instructions, it can avoid the situation where the access order of the memory is inconsistent with the arrangement order of the read and write instructions in the application.

[0013] In another possible implementation, the read instruction is compiled based on an extended memory read instruction, the extended memory read instruction has a first semantics, and the extended memory read instruction is an instruction added to the processor's instruction set for instructing the reading of memory data; the write instruction is compiled based on an extended memory write instruction, the extended memory write instruction has a second semantics, and the extended memory write instruction is an instruction added to the processor's instruction set for instructing the writing of memory data.

[0014] Based on the above possible implementations, since the extended memory read instruction has the first semantics, the read instruction compiled from the extended memory read instruction also has the first semantics, so that the processor can execute the read instruction in the instruction sequence in order. In addition, since the extended memory write instruction has the second semantics, the write instruction compiled from the extended memory write instruction also has the second semantics, so that the processor can execute the write instruction in the instruction sequence in order.

[0015] In another possible implementation, the extended memory read instruction includes at least one of a first extended memory read instruction, a second extended memory read instruction, a third extended memory read instruction, and a fourth extended memory read instruction, and the extended memory write instruction includes at least one of a first extended memory write instruction and a second extended memory write instruction; wherein the addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction do not include a non-scaled immediate addressing mode, and the third extended memory read instruction, the fourth extended memory read instruction, and the second extended memory write instruction all support a non-scaled immediate addressing mode; the first extended memory read instruction is used to indicate that a storage address in a memory is determined based on the supported addressing mode, and data of a first byte number in the determined storage address is read to a first destination register; the second extended memory read instruction is used to indicate that a storage address in a memory is determined based on the supported addressing mode, and data of a second byte number in the determined storage address is read to a first destination register. The data is read into the second destination register, and the sign bit of the read data is used to fill the remaining bits of the second destination register; the third extended memory read instruction is used to indicate that the storage address in the memory is determined based on the non-scaled immediate addressing method, and the data of the first byte number in the determined storage address is read into the third destination register; the fourth extended memory read instruction is used to indicate that the storage address in the memory is determined based on the non-scaled immediate addressing method, and the data of the second byte number in the determined storage address is read into the fourth destination register, and the sign bit of the read data is used to fill the remaining bits of the fourth destination register; the first extended memory write instruction is used to indicate that the storage address in the memory is determined based on the supported addressing method, and the data of the third byte number in the first source register is written to the determined storage address; the second extended memory write instruction is used to indicate that the storage address in the memory is determined based on the non-scaled immediate addressing method, and the data of the third byte number in the second source register is written to the determined storage address.

[0016] Based on the above possible implementation methods, a variety of extended memory read / write instructions are provided to meet the needs of multiple application scenarios for extended memory read / write instructions.

[0017] In another possible implementation, the first byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes, the second byte number includes 1 byte, 2 bytes or 4 bytes, and the third byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes; the addressing modes supported by the first extended memory read instruction, the second extended memory read instruction and the first extended memory write instruction include a scaled immediate addressing mode, a tag addressing mode or a register addressing mode, and the immediate number used when the scaled immediate addressing mode is used for address offset is the scaled operand in the corresponding instruction; the immediate number used when the non-scaled immediate addressing mode is used for address offset is the operand in the corresponding instruction, and the value range of the operand is -256 to 256.

[0018] Based on the above possible implementation methods, a variety of first byte numbers, second byte numbers and supported addressing methods are provided to meet the requirements of different application scenarios for the number of bytes and addressing methods supported by extended memory read / write instructions.

[0019] In another possible implementation, the read instruction is compiled based on an extended memory read instruction, which is an instruction obtained by adding a first semantic to a general memory read instruction in the instruction set of the processor; the write operation instruction is compiled based on an extended memory write instruction, which is an instruction obtained by adding a second semantic to a general memory write instruction in the instruction set.

[0020] Based on the above possible implementations, by adding the first semantics to the general memory read instruction in the instruction set, an extended memory read instruction can be obtained, which expands the function of the general memory read instruction and makes the general memory read instruction applicable to more application scenarios. By adding the second semantics to the general memory write instruction in the instruction set, an extended memory write instruction can be obtained, which expands the function of the general memory write instruction and makes the general memory write instruction applicable to more application scenarios.

[0021] In another possible implementation, the read and write instructions include read instructions for performing read operations on the memory or write instructions for performing write operations on the memory, the read instructions are compiled based on general memory read instructions in the instruction set of the processor, and the write instructions are compiled based on general memory write instructions in the instruction set of the processor.

[0022] Based on the above possible implementation methods, general memory read instructions and general memory writes do not have special semantics (such as the first semantics or the second semantics). Accordingly, the read and write instructions compiled from these two general memory instructions do not have special semantics. The processor still identifies the execution order of the read and write instructions based on the instruction sequence. Accordingly, when the processor executes the read and write instructions according to the execution order of the read and write instructions, the processor can also execute the application normally.

[0023] In a second aspect, a data processing system is provided, the data processing system comprising a first computing device and a second computing device, the first computing device comprising a processor;

[0024] The second computing device is used to compile the application source program to obtain the application program, and send the application program to the first computing device;

[0025] A processor, configured to receive an application program and obtain an instruction sequence of the application program, wherein the instruction sequence includes a plurality of instructions, and the plurality of instructions include a read and write instruction for performing a read operation or a write operation on a memory of the first computing device;

[0026] The processor is also used to identify the execution order of the read and write instructions according to the instruction sequence, and execute the read and write instructions according to the execution order of the read and write instructions.

[0027] In a possible implementation, the processor is further configured to: identify the arrangement order of the read and write instructions in the instruction sequence as the execution order of the read and write instructions.

[0028] In another possible implementation, the processor is also used to: identify the arrangement order of the read and write instructions in the instruction sequence as the execution order of the read and write instructions according to a sequential memory access mode, wherein the sequential memory access mode requires that the execution order of the read and write instructions is consistent with the arrangement order of the read and write instructions in the instruction sequence.

[0029] In another possible implementation, the read and write instructions include a read instruction for performing a read operation on the memory or a write instruction for performing a write operation on the memory, the read instruction has a first semantics, and the write instruction has a second semantics; wherein the first semantics is used to indicate that the first instruction in the instruction sequence is executed after the read instruction is executed, and the second semantics is used to indicate that the second instruction in the instruction sequence is executed before the write instruction is completed, and the first instruction is arranged in an order after the read instruction in the instruction sequence, and the second instruction is arranged in an order before the write instruction in the instruction sequence.

[0030] In another possible implementation, the read instruction is compiled based on an extended memory read instruction, the extended memory read instruction has a first semantics, and the extended memory read instruction is an instruction added to the processor's instruction set for instructing the reading of memory data; the write instruction is compiled based on an extended memory write instruction, the extended memory write instruction has a second semantics, and the extended memory write instruction is an instruction added to the processor's instruction set for instructing the writing of memory data.

[0031] In another possible implementation, the extended memory read instruction includes at least one of a first extended memory read instruction, a second extended memory read instruction, a third extended memory read instruction and a fourth extended memory read instruction, and the extended memory write instruction includes at least one of a first extended memory write instruction and a second extended memory write instruction; wherein the addressing modes supported by the first extended memory read instruction, the second extended memory read instruction and the first extended memory write instruction do not include a non-scaled immediate addressing mode, and the third extended memory read instruction, the fourth extended memory read instruction and the second extended memory write instruction all support a non-scaled immediate addressing mode; the first extended memory read instruction is used to indicate that a storage address in a memory is determined based on the supported addressing mode, and data of a first byte number in the determined storage address is read to a first destination register; the second extended memory read instruction is used to indicate that a storage address in a memory is determined based on the supported addressing mode, and data of a second byte number in the determined storage address is read to a first destination register. The data is read into the second destination register, and the sign bit of the read data is used to fill the remaining bits of the second destination register; the third extended memory read instruction is used to indicate that the storage address in the memory is determined based on the non-scaled immediate addressing method, and the data of the first byte number in the determined storage address is read into the third destination register; the fourth extended memory read instruction is used to indicate that the storage address in the memory is determined based on the non-scaled immediate addressing method, and the data of the second byte number in the determined storage address is read into the fourth destination register, and the sign bit of the read data is used to fill the remaining bits of the fourth destination register; the first extended memory write instruction is used to indicate that the storage address in the memory is determined based on the supported addressing method, and the data of the third byte number in the first source register is written to the determined storage address; the second extended memory write instruction is used to indicate that the storage address in the memory is determined based on the non-scaled immediate addressing method, and the data of the third byte number in the second source register is written to the determined storage address.

[0032] In another possible implementation, the first byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes, the second byte number includes 1 byte, 2 bytes or 4 bytes, and the third byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes; the addressing modes supported by the first extended memory read instruction, the second extended memory read instruction and the first extended memory write instruction include a scaled immediate addressing mode, a tag addressing mode or a register addressing mode, and the immediate number used when the scaled immediate addressing mode is used for address offset is the scaled operand in the corresponding instruction; the immediate number used when the non-scaled immediate addressing mode is used for address offset is the operand in the corresponding instruction, and the value range of the operand is -256 to 256.

[0033] In another possible implementation, the read instruction is compiled based on an extended memory read instruction, which is an instruction obtained by adding a first semantic to a general memory read instruction in the instruction set of the processor; the write operation instruction is compiled based on an extended memory write instruction, which is an instruction obtained by adding a second semantic to a general memory write instruction in the instruction set.

[0034] In another possible implementation, the read and write instructions include read instructions for performing read operations on the memory or write instructions for performing write operations on the memory, the read instructions are compiled based on general memory read instructions in the instruction set of the processor, and the write instructions are compiled based on general memory write instructions in the instruction set of the processor.

[0035] In a third aspect, a data processing device is provided, which is used to execute the above data processing method. Specifically, the data processing device includes a functional module for executing the data processing method provided by the above first aspect or any optional manner of the above first aspect.

[0036] According to a fourth aspect, a computing device is provided, the computing device comprising a processor, the processor being configured to execute the method provided in the first aspect or any optional manner of the first aspect.

[0037] In a fifth aspect, a computer-readable storage medium is provided, in which at least one program code is stored. The program code is read by a processor in a computing device so that the processor executes the method provided in the first aspect or any optional manner of the first aspect.

[0038] In a sixth aspect, a computer program product is provided, which includes at least one program code, wherein the at least one program code is stored in a computer-readable storage medium, and the at least one program code is read by a processor in a computing device so that the processor executes the method provided in the above-mentioned first aspect or various optional implementations of the first aspect.

[0039] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a structural diagram of a data processing system 100 provided in an embodiment of the present application;

[0041] Figure 2 is a flow chart of a data processing method provided in an embodiment of the present application;

[0042] Figure 3 is a schematic diagram of a data processing process of a processor provided in an embodiment of the present application;

[0043] Figure 4 is a structural schematic diagram of a data processing device provided in an embodiment of the present application;

[0044] Figure 5 It is a structural diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] For ease of understanding, some of the terms involved in the embodiments of the present application are first explained as follows:

[0046] Application: A sequence of instructions developed and executed on an operating system to complete at least one specific task.

[0047] Instruction sequence: includes multiple instructions. Optionally, the multiple instructions are arranged in sequence to form the instruction sequence, and each instruction corresponds to an arrangement order in the instruction sequence.

[0048] The multiple instructions in the instruction sequence: include read instructions or write instructions. If the multiple instructions include read instructions, there is at least one read instruction in the multiple instructions. If the multiple instructions include write instructions, there is at least one write instruction in the multiple instructions, wherein the read instruction is used to indicate a read operation on the main memory, and the read operation is an operation of reading data in the main memory. The write instruction is used to indicate a write operation on the main memory, and the write operation is an operation of writing data to the main memory. For the convenience of description, the read instruction or the write instruction may also be collectively referred to as a read-write instruction.

[0049] First semantics: used to indicate that the first instruction in an instruction sequence is executed after the read instruction is executed, wherein, for a read instruction in the instruction sequence, the first instruction is the instruction in the instruction sequence that is located after the read instruction. For example, the instruction sequence includes 100 instructions, and the second instruction of the 100 instructions is a read instruction. Then, for the read instruction, the third instruction to the 100th instruction of the 100 instructions are all the first instructions. Since the first semantics indicates that the first instruction in the instruction sequence is executed after the read instruction is executed, the first semantics can prevent the instructions in the instruction sequence that are arranged after the read instruction from being executed before the read instruction. In some embodiments, the first semantics is also called acquire semantics.

[0050] Second semantics: used to indicate that the second instruction in the instruction sequence is executed before the write instruction is executed, wherein, for a write instruction in the instruction sequence, the second instruction is the instruction in the instruction sequence that is located before the write instruction. For example, the instruction sequence includes 100 instructions, and the third instruction among the 100 instructions is a write instruction. Then, for the write instruction, the first instruction and the second instruction among the 100 instructions are both second instructions. Since the second semantics indicates that the second instruction in the instruction sequence is executed before the write instruction is executed, the second semantics can prevent the instruction in the instruction sequence that is arranged before the write instruction from being executed after the write instruction. In some embodiments, the second semantics is also called release semantics.

[0051] Sequential memory access mode: requires that the execution order of read and write instructions in the instruction sequence be consistent with the order in which the read and write instructions are arranged in the instruction sequence.

[0052] Memory model: used to define the way the processor executes read and write instructions. The memory model includes a weakly-ordered memory model.

[0053] Weak memory model: When the processor executes an application, it can swap the execution order of read and write instructions in the application without changing the behavior of the application.

[0054] The embodiments of the present application propose that when executing an application, the execution order of read and write instructions in the application is identified according to the instruction sequence in the application, and the read and write instructions in the application are executed according to the execution order of the read and write instructions, so that the processor can execute the application normally. Accordingly, the occurrence of adverse situations such as random crashes, restarts or erroneous running results of the application is reduced, and the credibility of the processor that supports the weak memory model is increased, so as to further improve the reputation and market sales of the processor that supports the weak memory model.

[0055] The implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0056] Figure 1 1 is a structural diagram of a data processing system 100 provided in an embodiment of the present application, and the data processing system 100 includes a first computing device 101 and a second computing device 102. The first computing device 101 and the second computing device 102 are directly or indirectly connected in communication via wired or wireless communication. The user using the first computing device 101 is referred to as a first user, and the user using the second computing device 102 is referred to as a second user.

[0057] Compilation software is deployed in the second computing device 102, and the compilation software is used to provide a function of compiling an application source program. The second computing device 102 compiles the application source program through the compilation software to obtain a compiled application program, wherein the application source program and the compiled application program are both used to implement customized functions. The application source program is a source code written in a high-level language to implement customized functions. By compiling the application source program, an instruction sequence that can be recognized by the processor is obtained, and the instruction sequence is called an application program. The instruction sequence is, for example, an instruction sequence composed of binary data.

[0058] The first computing device 101 obtains the compiled application from the second computing device 102, and the first computing device 101 deploys the obtained application, for example, the first computing device 101 installs the application. The first user issues an execution instruction to the first computing device 101 to execute the application, and the first computing device executes the application (i.e., runs the application) in response to the execution instruction to the application.

[0059] The first computing device 101 includes a processor 11 and a memory 12. When the first computing device 101 executes the application, each instruction in the application is executed by the processor 11 in the first computing device 101, and the temporary data during the execution of the application is stored in the memory 12. Therefore, the processor 11 performs read and write operations on the memory 12 in the process of executing the instructions to read data from the memory and write data to the memory. In order to enable the processor 11 to better interact with the memory 12, the execution mode of the read and write instructions (for example, a memory model) is defined for the processor 11. Accordingly, the processor 11's read and write operations on the memory 12 need to follow the defined memory model, otherwise a memory access error will occur.

[0060] Accordingly, in order to enable a certain processor to run an application normally, developers will consider the requirements of the memory model supported by the processor for the execution order of read and write instructions when developing applications for the processor. Accordingly, the application developed for the processor also supports the memory model supported by the processor, and the arrangement order of read and write instructions in the application meets the requirements of the memory model for the execution order of read and write instructions.

[0061] Processors of different architectures may support the same memory model. For example, processors of the advanced RISC machines (ARM) architecture and processors of the performance optimization with enhanced RISC (POWER) architecture both support a weak memory model. Applications developed for ARM architecture processors and applications developed for POWER architecture processors also support a weak memory model.

[0062] In an embodiment of the present application, the instruction set supported by the processor of the first computing device includes at least one of a general instruction set, an extended instruction set 1, and an extended instruction set 2, as shown in Table 1 below. Continuing to refer to Table 1, the instructions for accessing memory in the general instruction set include general memory read instructions and general memory write instructions, wherein the general memory read instruction includes at least one of general memory read instructions 1-4, and the general memory write instruction includes at least one of general memory write instructions 1-2. The instructions for accessing memory in the extended instruction set 1 include extended memory read instructions 1 and extended memory write instructions 1, wherein the extended memory read instruction 1 includes at least one of extended memory read instructions 11-14, and the extended memory write instruction 1 includes at least one of extended memory write instructions 11-12. The instructions for accessing memory in the extended instruction set 2 include extended memory read instructions 2 and extended memory write instructions 2, wherein the extended memory read instruction 2 includes at least one of extended memory read instructions 21-12, and the extended memory write instruction 2 includes at least one of extended memory write instructions 21-22.

[0063] Table 1

[0064]

[0065]

[0066] In conjunction with Table 1, various instruction sets supported by the processor of the first computing device are introduced as follows:

[0067] The first instruction set: general instruction set

[0068] The general instruction set is the instruction set originally supported by the processor. For example, if the processor is an ARM64 architecture processor, the general instruction set is the ARM64 instruction set. The general memory (i.e., memory) read instruction in the general instruction set is used to indicate that the storage address to be read in the memory is determined based on the supported addressing method, and the data of a specific number of bytes in the storage address is read to the destination register, wherein the specific number of bytes is the bit width of the data to be read indicated by the general memory read instruction.

[0069] The general memory read instruction supports at least one of an immediate addressing mode, a tag addressing mode and a register addressing mode. The immediate addressing mode has two types, namely a scaled immediate addressing mode and an unscaled (U) immediate addressing mode.

[0070] Among them, the scaled immediate addressing mode is used to indicate the operands in the scaling corresponding instructions, and the scaled operands are used for addressing. The scaling multiple of the operand can be set according to the scene requirements, and the scaling multiple is 1, 4 or 8, for example. When the scaling multiple is 1, the operands before and after the scaling remain unchanged. Here, the embodiments of the present application do not limit the scaling multiple of the operands. For example, for a general memory read instruction that supports the scaled immediate addressing mode, when the processor executes the general memory read instruction, the operands in the general memory read instruction are scaled, and the scaled operands are used to perform an address offset on the address stored in the base register to determine the storage address to be read in the memory.

[0071] The non-scaled immediate addressing mode indicates that the operands in the corresponding instruction with a value range of -256 to 256 are used for addressing without scaling the operands in the corresponding instruction. For example, for a general memory read instruction that supports the non-scaled immediate addressing mode, the operands in the general memory read instruction have a value range of -256 to 256. When the processor executes the general memory read instruction, the operands in the general memory read instruction are summed with the address stored in the base register to obtain the storage address to be read. For the immediate addressing mode, the operands used when performing address offsets are collectively referred to as immediate numbers.

[0072] As shown in Table 2 below, the specific number of bytes includes the first number of bytes or the second number of bytes. Based on the supported addressing modes and the specific number of bytes, the general memory read instruction includes at least one of general memory read instructions 1-4.

[0073] Table 2

[0074]

[0075] Among them, “ / ” in Table 2 represents none.

[0076] The following is a detailed explanation of how each instruction in Table 2 is processed:

[0077] The general memory read instruction 1 is used to instruct to determine a storage address in the memory based on a supported addressing mode, and read the data of the first number of bytes in the determined storage address to a first destination register.

[0078] In a possible implementation, the first byte number includes 1 byte, 2 bytes, 4 bytes, or 8 bytes. As shown in Table 2, according to different values ​​of the first byte number, the general memory read instruction 1 includes at least one of the general memory read instructions 11-13. For the general memory read instruction 13, when the length of the first destination register is greater than or equal to 4 bytes and less than 8 bytes, the first byte number is 4 bytes. When the length of the first destination register is greater than or equal to 8 bytes, the first byte number is 8 bytes.

[0079] Different general memory read instructions 1 have different encoding formats and reference methods. In one possible implementation, byte load (Load Register Byte, LDRB), halfword load (Load Register Halfword, LDRH) and word or doubleword load (Load Register, LDR) are used to refer to general memory read instructions 11-13 respectively. Alternatively, UR11, UR12 and UR13 are used to refer to general memory read instructions 11-13 respectively to distinguish different general memory read instructions 1.

[0080] General memory read instruction 2, used to indicate determining a storage address in the memory based on a supported addressing method, reading a second number of bytes of data in the determined storage address into a second destination register, and filling the remaining bits of the second destination register with the sign bit of the read data.

[0081] The length of the second destination register is greater than the second number of bytes, and the read data includes a sign bit (sing, S) and a value bit. In a possible implementation, the general memory instruction 2 is also used to support filling the read data in order from low to high bits of the second destination register, and accordingly, the remaining bits of the second destination register are the remaining high bits of the second destination register, and the remaining high bits are filled with the sign bit of the read data.

[0082] In one possible implementation, the second number of bytes includes 1 byte, 2 bytes or 4 bytes. As shown in Table 2, according to different values ​​of the second byte data, the general memory read instruction 2 includes at least one of the general memory read instructions 21-23. The encoding format and reference method of different general memory read instructions 2 are different. In one possible implementation, signed byte load (Load Register Signed Byte, LDRSB), signed halfword load (Load Register Signed Halfword, LDRSH) and signed word load (Load Register Signed Word, LDRSW) are used to refer to general memory read instructions 21-23 respectively. Alternatively, UR21, UR22 and UR23 are used to refer to general memory read instructions 21-23 respectively to distinguish different general memory read instructions 2.

[0083] The general memory read instruction 3 is used to instruct to determine a storage address in the memory based on a non-scaled immediate addressing mode, and read the data of the first byte number in the determined storage address to a third destination register.

[0084] As shown in Table 2, according to different values ​​of the first byte number, the general memory read instruction 3 includes at least one of the general memory read instructions 31-33. For the general memory read instruction 33, when the length of the third target register is greater than or equal to 4 bytes and less than 8 bytes, the first byte number is 4 bytes. When the length of the third target register is greater than or equal to 8 bytes, the first byte number is 8 bytes.

[0085] Different general memory read instructions 3 have different encoding formats and reference methods. In one possible implementation, unscaled byte load (Load Register Byte Unscaled, LDURB), unscaled halfword load (Load Register Halfword Unscaled, LDURH) and unscaled word or doubleword load (Load Register Unscaled, LDUR) are used to refer to general memory read instructions 31-33 respectively. Alternatively, UR31, UR32 and UR33 are used to refer to general memory read instructions 31-33 respectively to distinguish different general memory read instructions 3.

[0086] General memory read instruction 4 is used to indicate that a storage address in the memory is determined based on a non-scaled immediate addressing method, the second byte number of data in the determined storage address is read to a fourth destination register, and the remaining bits of the fourth destination register are filled with the sign bit of the read data.

[0087] The length of the fourth destination register is greater than the second number of bytes, and the read data includes a sign bit and a value bit. In a possible implementation, the general memory instruction 4 is also used to support filling the read data in sequence from the fourth destination register from low to high, and accordingly, the remaining bits of the fourth destination register are the remaining high bits of the fourth destination register, and the remaining high bits are filled with the sign bit of the read data.

[0088] As shown in Table 2, according to different values ​​of the second byte number, the general memory read instruction 4 includes general memory read instructions 41-43.

[0089] Different general memory read instructions 4 have different encoding formats and reference methods. In one possible implementation, unscaled signed byte load (Load Register Signed Byte Unscaled, LDURSB), unscaled signed halfword load (Load Register Signed Halfword Unscaled, LDURSH) and unscaled signed word load (Load Register Signed Word Unscaled, LDURSW) are used to refer to general memory read instructions 41-43 respectively. Alternatively, UR41, UR42 and UR43 are used to refer to general memory read instructions 41-43 respectively to distinguish different general memory read instructions 4.

[0090] The general memory write instruction in the general instruction set is used to indicate that a storage address to be written in the memory is determined based on the supported addressing mode, and the data of the third byte number in the source register is written to the determined storage address, wherein the third byte number is the bit width of the data to be written indicated by the general memory write instruction. The general memory write instruction supports at least one of the immediate addressing mode, the tag addressing mode and the register addressing mode.

[0091] As shown in the following Table 3, based on the different supported addressing modes, the general memory write instruction includes at least one of the general memory write instructions 1-2.

[0092] Table 3

[0093]

[0094]

[0095] The following is a detailed description of the processing of each instruction in Table 3:

[0096] The general memory write instruction 1 is used to instruct to determine a storage address in the memory based on a supported addressing mode, and write the data of the third byte number in the first source register into the determined storage address.

[0097] In a possible implementation, the third byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes. As shown in Table 3, according to different values ​​of the third byte number, the general memory write instruction 1 includes general memory write instructions 11-13. For the general memory write instruction 13, when the length of the first source register is greater than or equal to 4 bytes and less than 8 bytes, the third byte number is 4 bytes. When the length of the first source register is greater than or equal to 8 bytes, the third byte number is 8 bytes.

[0098] Different universal memory write instructions 1 have different encoding formats and reference methods. In one possible implementation, byte storage (Store Register Byte, STRB), half-word storage (Store Register Halfword, STRH) and word or double-word storage (Store Register, STR) are used to refer to universal memory write instructions 11-13 respectively. Alternatively, UW11, UW12 and UW13 are used to refer to universal memory write instructions 11-13 respectively to distinguish different universal memory write instructions 11-13.

[0099] The general memory write instruction 2 is used to indicate that a storage address in the memory is determined based on a non-scaled immediate addressing mode, and the data of the third byte number in the second source register is written to the determined storage address.

[0100] As shown in Table 3, according to different values ​​of the third byte number, the general memory write instruction 2 includes general memory write instructions 21-23. For the general memory write instruction 23, when the length of the second source register is greater than or equal to 4 bytes and less than 8 bytes, the third byte number is 4 bytes. When the length of the second source register is greater than or equal to 8 bytes, the third byte number is 8 bytes.

[0101] Different general memory write instructions 2 have different encoding formats and reference methods. In one possible implementation, unscaled byte storage (Store Register Byte Unscaled, STURB), unscaled halfword storage (Store Register Halfword Unscaled, STURH) and unscaled word or doubleword storage (Store Register Unscaled, STUR) are used to refer to general memory write instructions 21-23 respectively. Alternatively, UW21, UW22 and UW23 are used to refer to general memory write instructions 21-23 respectively to distinguish different general memory write instructions 21-23.

[0102] In one possible implementation, the general instruction set also includes at least one other functional instruction, and the at least one other functional instruction is used to implement other functions besides accessing memory. Here, the embodiment of the present application does not limit the at least one other functional instruction.

[0103] The second instruction set: extended instruction set 1

[0104] Among them, the extended instruction set 1 is an instruction set extended for the processor of the first computing device. The extended memory read instruction 1 and the extended memory write instruction 1 in the extended instruction set 1 are instructions for performing read and write operations on the memory added to the general instruction set of the processor. For example, the general memory read instruction in the general instruction set is replaced with the extended memory read instruction 1, and the general memory write instruction in the general instruction set is replaced with the extended memory write instruction 1, so as to obtain the extended instruction set 1.

[0105] The following introduces the extended memory read instruction 1 and the extended memory write instruction 1 respectively. Here, the extended memory read instruction 1 is first introduced as follows:

[0106] The extended memory read instruction 1 is used to indicate that a storage address to be read in the memory is determined based on a supported addressing mode, and a specific number of bytes of data in the storage address is read to a destination register, and the extended memory read instruction 1 also has a first semantics.

[0107] Among them, the extended memory read instruction 1 supports at least one of the immediate addressing mode, the tag addressing mode and the register addressing mode. For example, as shown in Table 4 below, based on the difference in supported addressing modes and specific byte numbers, the extended memory read instruction 1 includes at least one of the extended memory read instructions 11-14.

[0108] Table 4

[0109]

[0110]

[0111] Among them, “ / ” in Table 4 represents none.

[0112] The following is a detailed description of the processing of each instruction in Table 4:

[0113] The extended memory read instruction 11 is used to indicate that a storage address in the memory is determined based on a supported addressing mode, and data of a first number of bytes in the determined storage address is read to a first destination register, and the extended memory read instruction 11 also has a first semantics.

[0114] Among them, the extended memory read instruction 11 is a memory read instruction extended based on the function of the general memory read instruction 1. The extended memory read instruction 11 has the function of the general memory read instruction 1 and also has the first semantics. The instruction format of the extended memory read instruction 11 can be the same as or different from that of the general memory read instruction 1, but is different from the encoding format of the general memory read instruction 1.

[0115] As shown in Table 4, according to different values ​​of the first number of bytes, the extended memory read instruction 11 includes at least one of the extended memory read instructions 111-113. Among them, the extended memory read instructions 111-113 are memory read instructions newly added according to the general memory read instructions 11-13. Compared with the general memory read instructions 11-13, the extended memory read instructions 111-113 respectively have the functions of the general memory read instructions 11-13, and the extended memory read instructions 111-113 all have the first semantics, while the general memory read instructions 11-13 do not have the first semantics.

[0116] Different extended memory read instructions 11 have different encoding formats and reference methods. In one possible implementation, LDRBE1, LDRHE1, and LDRE1 are used to refer to extended memory read instructions 111-113, respectively, where "E1" refers to the first extended form of the general extended memory read instruction. Alternatively, ER111, ER112, and ER113 are used to refer to extended memory read instructions 111-113, respectively, to distinguish different extended memory read instructions 11.

[0117] The extended memory read instruction 12 is used to indicate that a storage address in the memory is determined based on a supported addressing method, and the data of the second byte number in the determined storage address is read to a second destination register, and the remaining bits of the second destination register are filled with the sign bit of the read data. The extended memory read instruction 12 also has a first semantics.

[0118] Among them, the extended memory read instruction 12 is a memory read instruction extended based on the function of the general memory read instruction 2. The extended memory read instruction 12 has the function of the general memory read instruction 2 and also has the first semantics. The instruction format of the extended memory read instruction 12 can be the same as or different from that of the general memory read instruction 2, but is different from the encoding format of the general memory read instruction 2.

[0119] As shown in Table 4, according to different values ​​of the second number of bytes, the extended memory read instruction 12 includes at least one of the extended memory read instructions 121-123. Among them, the extended memory read instructions 121-123 are memory read instructions newly added according to the general memory read instructions 21-23. Compared with the general memory read instructions 21-23, the extended memory read instructions 121-123 respectively have the functions of the general memory read instructions 21-23, and the extended memory read instructions 121-123 all have the first semantics, while the general memory read instructions 21-23 do not have the first semantics.

[0120] Different extended memory read instructions 11 have different encoding formats and reference methods. In a possible implementation, LDRSBE1, LDRSHE1, and LDRSWE1 are used to refer to extended memory read instructions 121-123, respectively. Alternatively, ER121, ER122, and ER123 are used to refer to extended memory read instructions 121-123, respectively, to distinguish different extended memory read instructions 12.

[0121] The extended memory read instruction 13 is used to indicate that a storage address in the memory is determined based on a non-scaled immediate addressing mode, and data of a first byte number in the determined storage address is read to a third destination register, and the extended memory read instruction 13 also has a first semantics.

[0122] Among them, the extended memory read instruction 13 is a memory read instruction extended from the function of the general memory read instruction 3. The extended memory read instruction 13 has the function of the general memory read instruction 3 and also has the first semantics. The instruction format of the extended memory read instruction 13 can be the same as or different from that of the general memory read instruction 3, but is different from the encoding format of the general memory read instruction 3.

[0123] As shown in Table 4, according to different values ​​of the first byte number, the extended memory read instruction 13 includes at least one of the extended memory read instructions 131-133. Among them, the extended memory read instructions 131-133 are respectively memory read instructions newly added according to the general memory read instructions 31-33. Compared with the general memory read instructions 31-33, the extended memory read instructions 131-133 respectively have the functions of the general memory read instructions 31-33. The extended memory read instructions 131-133 all have the first semantics, while the general memory read instructions 31-33 do not have the first semantics.

[0124] Different extended memory read instructions 13 have different encoding formats and reference methods. In a possible implementation, LDURBE1, LDURHE1, and LDURE1 are used to refer to extended memory read instructions 131-133, respectively. Alternatively, ER131, ER132, and ER133 are used to refer to extended memory read instructions 131-133, respectively, to distinguish different extended memory read instructions 13.

[0125] The extended memory read instruction 14 is used to indicate that a storage address in the memory is determined based on a non-scaled immediate addressing method, the data of the second byte number in the determined storage address is read to a fourth destination register, and the remaining bits of the fourth destination register are filled with the sign bit of the read data, and the extended memory read instruction 14 also has the first semantics.

[0126] Among them, the extended memory read instruction 14 is a memory read instruction extended based on the function of the general memory read instruction 4. The extended memory read instruction 14 has the function of the general memory read instruction 4 and also has the first semantics. The instruction format of the extended memory read instruction 14 can be the same as or different from that of the general memory read instruction 4, but is different from the encoding format of the general memory read instruction 4.

[0127] As shown in Table 4 above, according to different values ​​of the second number of bytes, the extended memory read instruction 14 includes at least one of the extended memory read instructions 141-143. Among them, the extended memory read instructions 141-143 are memory read instructions newly added according to the general memory read instructions 31-33, and compared with the general memory read instructions 31-33, the extended memory read instructions 141-143 respectively have the functions of the general memory read instructions 31-33, and the extended memory read instructions 141-143 all have the first semantics, while the extended memory read instructions 31-33 do not have the first semantics.

[0128] Different extended memory read instructions 14 have different encoding formats and reference methods. In a possible implementation, LDURSBE1, LDURSHE1, and LDURSWE1 are used to refer to extended memory read instructions 141-143, respectively. Alternatively, ER141, ER142, and ER143 are used to refer to extended memory read instructions 141-143, respectively, to distinguish different extended memory read instructions 14.

[0129] It should be noted that, for each extended memory read instruction 1 and the corresponding general memory read instruction, each extended memory read instruction 1 is a memory read instruction newly added for the corresponding general memory read instruction, and also has the first semantics. Accordingly, the encoding formats corresponding to each extended memory read instruction 1 and the corresponding general memory read instruction are different. For example, a semantic bit is set in the encoding format corresponding to an extended memory read instruction 1, and the value on the semantic bit is used to identify the first semantics, while the encoding format corresponding to the corresponding general memory read instruction may be set with a semantic bit or may not be set with a semantic bit. If the encoding format corresponding to the general memory read instruction is set with a semantic bit, but the value on the semantic bit is different from the value on the semantic bit in the encoding format corresponding to the extended memory read instruction 1, and is not used to identify the first semantics.

[0130] Here, the extended memory write instruction 1 in the extended instruction set 1 is introduced as follows:

[0131] The extended memory write instruction 1 is used to indicate that a storage address to be written in the memory is determined based on a supported addressing mode, and the data of the third byte number in the source register is written to the determined storage address, and the extended memory write instruction 1 also has a second semantics.

[0132] Among them, the extended memory write instruction 1 supports at least one of the immediate addressing mode, the tag addressing mode and the register addressing mode. For example, as shown in the following Table 5, based on the different supported addressing modes, the extended memory write instruction 1 includes at least one of the extended memory write instructions 11-12.

[0133] Table 5

[0134]

[0135] The following is a detailed description of the processing of each instruction in Table 5:

[0136] The extended memory write instruction 11 is used to indicate that a storage address in the memory is determined based on a supported addressing mode, and the data of the third byte number in the first source register is written to the determined storage address, and the extended memory write instruction 11 has a second semantics.

[0137] Among them, the extended memory write instruction 11 is a memory write instruction extended from the function of the general memory write instruction 1. The extended memory read instruction 11 has the function of the general memory write instruction 1 and also has a second semantics. The instruction format of the extended memory write instruction 11 can be the same as or different from that of the general memory write instruction 1, but is different from the encoding format of the general memory write instruction 1.

[0138] As shown in Table 5, according to different values ​​of the third byte number, the extended memory write instruction 11 includes at least one of the extended memory write instructions 111-113. Among them, the extended memory write instructions 111-113 are respectively memory write instructions newly added according to the general memory write instructions 11-13. Compared with the general memory write instructions 11-13, the extended memory write instructions 111-113 respectively have the functions of the general memory write instructions 11-13, and the extended memory write instructions 111-113 also have the second semantics, while the general memory write instructions 11-13 do not have the second semantics.

[0139] Different extended memory write instructions 11 have different encoding formats and reference methods. In a possible implementation, STRBE1, STRHE1, and STRE1 are used to refer to extended memory write instructions 111-113, respectively. Alternatively, EW111, EW112, and EW113 are used to refer to extended memory write instructions 111-113, respectively, to distinguish different extended memory write instructions 11.

[0140] The extended memory write instruction 12 is used to indicate that a storage address in the memory is determined based on a non-scaled immediate addressing mode, and the data of the third byte number in the second source register is written to the determined storage address, and the extended memory write instruction 12 has a second semantics.

[0141] Among them, the extended memory write instruction 12 is a memory write instruction extended from the function of the general memory write instruction 2. The extended memory read instruction 12 has the function of the general memory write instruction 2 and also has a second semantics. The instruction format of the extended memory write instruction 12 can be the same as or different from that of the general memory write instruction 2, but is different from the encoding format of the general memory write instruction 2.

[0142] As shown in Table 5, according to different values ​​of the third byte number, the extended memory write instruction 12 includes at least one of the extended memory write instructions 121-123. Among them, the extended memory write instructions 121-123 are respectively memory write instructions newly added according to the general memory write instructions 21-23, and compared with the general memory write instructions 21-23, the extended memory write instructions 121-123 respectively have the functions of the general memory write instructions 21-23, and the extended memory write instructions 121-123 also have the second semantics, while the general memory write instructions 21-23 do not have the second semantics.

[0143] Different extended memory write instructions 12 have different encoding formats and reference methods. In a possible implementation, STURBE1, STURHE1, and STURE1 are used to refer to extended memory write instructions 121-123, respectively. Alternatively, EW121, EW122, and EW123 are used to refer to extended memory write instructions 121-123, respectively, to distinguish different extended memory write instructions 12.

[0144] It should be noted that, for each extended memory write instruction 1 and the corresponding general memory write instruction, each extended memory write instruction 1 is a memory write instruction newly added for the corresponding general memory write instruction, and also has a second semantics. Accordingly, the encoding formats corresponding to each extended memory write instruction 1 and the corresponding general memory write instruction are different. For example, a semantic bit is set in the encoding format corresponding to an extended memory write instruction 1, and the value on the semantic bit is used to identify the second semantics, while the encoding format corresponding to the corresponding general memory write instruction may be set with a semantic bit or may not be set with a semantic bit. If the encoding format corresponding to the general memory write instruction is set with a semantic bit, but the value on the semantic bit is different from the value on the semantic bit in the encoding format corresponding to the extended memory write instruction 1, and is not used to identify the second semantics.

[0145] In a possible implementation, the extended instruction set 1 also includes at least one other functional instruction, and the at least one other functional instruction is used to implement other functions besides accessing memory. Here, the embodiment of the present application does not limit the at least one other functional instruction.

[0146] The third instruction set: Extended instruction set 2

[0147] Among them, extended instruction set 2 is another instruction set extended for the processor. Compared with extended instruction set 1, extended instruction set 2 is an instruction set obtained by adding special semantics (first semantics or second semantics) to the general memory read and write instructions (i.e., general memory read instructions or general memory write instructions) in the general instruction set, while extended instruction set 1 is a new instruction set developed based on the functions of the general memory read and write instructions in the general instruction set. In order to distinguish extended instruction sets 1 and 2, the encoding formats corresponding to the instructions in extended instruction sets 1 and 2 are different.

[0148] As shown in Table 1, the extended memory read instruction 2 in the extended instruction set 2 has a first semantics, and the extended memory read instruction 2 is an instruction obtained by adding the first semantics to the general memory read instruction in the general instruction set of the processor. The extended memory write instruction 2 in the extended instruction set 2 is an instruction obtained by adding the second semantics to the general memory write instruction in the general instruction set. For example, the first semantics is added to the general memory read instruction in the general instruction set to obtain the memory extended memory read instruction 2, the second semantics is added to the general memory write instruction in the general instruction set to obtain the memory extended memory write instruction 2, the general memory read instruction in the general instruction set is replaced with the extended memory read instruction 2, and the general memory write instruction in the general instruction set is replaced with the extended memory write instruction 2 to obtain the extended instruction set 2.

[0149] The following introduces the extended memory read instruction 2 and the extended memory write instruction 2 respectively. Here, the extended memory read instruction 2 is first introduced as follows:

[0150] The extended memory read instruction 2 is used to indicate that a storage address to be read in the memory is determined based on a supported addressing mode, and data of a specific number of bytes in the storage address is read to a destination register, and the extended memory read instruction 2 also has a first semantics.

[0151] Among them, the extended memory read instruction 2 supports at least one of the immediate addressing mode, the tag addressing mode and the register addressing mode. For example, as shown in the following Table 6, based on the difference in supported addressing modes and specific byte numbers, the extended memory read instruction 2 includes at least one of the extended memory read instructions 22-24.

[0152] Table 6

[0153]

[0154]

[0155] Among them, “ / ” in Table 6 represents none.

[0156] The processing of each instruction in Table 6 is described in detail below.

[0157] The extended memory read instruction 21 is used to indicate that a storage address in the memory is determined based on a supported addressing mode, and data of a first number of bytes in the determined storage address is read to a first destination register. The extended memory read instruction 21 also has a first semantic meaning.

[0158] The extended memory read instruction 21 is an instruction obtained by adding the first semantics to the general memory read instruction 1. The extended memory read instruction 21 has the same instruction format as the general memory read instruction 1, but has a different encoding format from the general memory read instruction 1.

[0159] As shown in Table 6, according to different values ​​of the first number of bytes, the extended memory read instruction 21 includes at least one of the extended memory read instructions 211-213. Among them, the extended memory read instructions 211-213 are memory read instructions obtained by adding the first semantics to the general memory read instructions 11-13. Compared with the general memory read instructions 11-13, the extended memory read instructions 211-213 have the functions of the general memory read instructions 11-13, and the extended memory read instructions 211-213 all have the first semantics, while the general memory read instructions 11-13 do not have the first semantics.

[0160] Different extended memory read instructions 21 have different encoding formats and reference methods. In a possible implementation, LDRBE2, LDRHE2 and LDRE2 are used to refer to extended memory read instructions 211-213 respectively. Here, "E2" refers to an extended form of a general extended memory read instruction. Alternatively, ER211, ER212 and ER213 are used to refer to extended memory read instructions respectively, or ER211, ER212 and ER213 are used to refer to extended memory read instructions 211-213 respectively, so as to distinguish different extended memory read instructions 21.

[0161] The extended memory read instruction 22 is used to indicate that a storage address in the memory is determined based on a supported addressing method, and the data of the second byte number in the determined storage address is read into a second destination register, and the remaining bits of the second destination register are filled with the sign bit of the read data, and the extended memory read instruction 22 also has the first semantics.

[0162] The extended memory read instruction 22 is an instruction obtained by adding the first semantics to the general memory read instruction 2. The extended memory read instruction 22 has the same instruction format as the general memory read instruction 2, but has a different encoding format from the general memory read instruction 2.

[0163] As shown in Table 6, according to different values ​​of the second number of bytes, the extended memory read instruction 22 includes at least one of the extended memory read instructions 221-223. Among them, the extended memory read instructions 221-223 are instructions obtained by adding the first semantics to the general memory read instructions 21-23. Compared with the general memory read instructions 21-23, the extended memory read instructions 221-223 have the functions of the general memory read instructions 21-23, and the extended memory read instructions 221-223 all have the first semantics, while the general memory read instructions 21-23 do not have the first semantics.

[0164] Different extended memory read instructions 23 have different encoding formats and reference methods. In a possible implementation, LDRSBE2, LDRSHE2, and LDRSWE2 are used to refer to extended memory read instructions 221-223, respectively. Alternatively, ER221, ER222, and ER223 are used to refer to extended memory read instructions 221-223, respectively, to distinguish different extended memory read instructions 22.

[0165] The extended memory read instruction 23 is used to indicate that a storage address in the memory is determined based on a non-scaled immediate addressing mode, and data of the first byte number in the determined storage address is read to a third destination register, and the extended memory read instruction 23 also has a first semantics.

[0166] The extended memory read instruction 23 is an instruction obtained by adding the first semantics to the general memory read instruction 3. The extended memory read instruction 23 has the same instruction format as the general memory read instruction 3, but has a different encoding format from the general memory read instruction 3.

[0167] As shown in Table 6, according to different values ​​of the first number of bytes, the extended memory read instruction 23 includes at least one of the extended memory read instructions 231-233. Among them, the extended memory read instructions 231-233 are instructions obtained by adding the first semantics to the general memory read instructions 31-33. Compared with the general memory read instructions 31-33, the extended memory read instructions 231-233 have the functions of the general memory read instructions 31-33, and the extended memory read instructions 231-233 all have the first semantics, while the general memory read instructions 31-33 do not have the first semantics.

[0168] Different extended memory read instructions 23 have different encoding formats and reference methods. In a possible implementation, LDURBE2, LDURHE2, and LDURE2 are used to refer to extended memory read instructions 231-233, respectively. Alternatively, ER231, ER132, and ER233 are used to refer to extended memory read instructions 231-233, respectively, to distinguish different extended memory read instructions 23.

[0169] The extended memory read instruction 24 is used to indicate that a storage address in the memory is determined based on a non-scaled immediate addressing method, the data of the second byte number in the determined storage address is read to a fourth destination register, and the remaining bits of the fourth destination register are filled with the sign bit of the read data, and the extended memory read instruction 24 also has the first semantics.

[0170] The extended memory read instruction 24 is an instruction obtained by adding the first semantics to the general memory read instruction 4. The extended memory read instruction 24 has the same instruction format as the general memory read instruction 4, but has a different encoding format from the general memory read instruction 4.

[0171] As shown in Table 6, according to different values ​​of the second number of bytes, the extended memory read instruction 24 includes at least one of the extended memory read instructions 241-243. Among them, the extended memory read instructions 241-243 are instructions obtained by adding the first semantics to the general memory read instructions 41-43. Compared with the general memory read instructions 41-43, the extended memory read instructions 241-243 have the functions of the general memory read instructions 41-43, and the extended memory read instructions 241-243 all have the first semantics, while the general memory read instructions 41-43 do not have the first semantics.

[0172] Different extended memory read instructions 24 have different encoding formats and reference methods. In a possible implementation, LDURSBE2, LDURSHE2, and LDURSWE2 are used to refer to extended memory read instructions 241-243, respectively. Alternatively, ER241, ER242, and ER243 are used to refer to extended memory read instructions 241-243, respectively, to distinguish different extended memory read instructions 24.

[0173] Here, the extended memory write instruction 2 in the extended instruction set 2 is introduced as follows:

[0174] The extended memory write instruction 2 determines the storage address to be written in the memory based on the supported addressing mode, writes the data of the third byte number in the source register to the determined storage address, and the extended memory write instruction 2 also has a second semantics.

[0175] The extended memory write instruction 2 supports at least one of the immediate addressing mode, the tag addressing mode and the register addressing mode. For example, as shown in Table 7 below, based on the different supported addressing modes, the extended memory write instruction 2 includes at least one of the extended memory write instructions 21-22.

[0176] Table 7

[0177]

[0178] The processing of each instruction in Table 7 is described in detail below.

[0179] The extended memory write instruction 21 is used to indicate that a storage address in the memory is determined based on a supported addressing mode, and data of a number of bytes in the first source register is written to the determined storage address, and the extended memory write instruction 21 also has a second semantics.

[0180] The extended memory write instruction 21 is an instruction obtained by adding the second semantics to the general memory write instruction 1. The extended memory write instruction 21 has the same instruction format as the general memory write instruction 1, but has a different encoding format from the general memory write instruction 1.

[0181] As shown in Table 7, according to different values ​​of the third byte number, the extended memory write instruction 21 includes at least one of the extended memory write instructions 211-213. Among them, the extended memory write instructions 211-213 are instructions obtained by adding the second semantics to the general memory write instructions 11-13. Compared with the general memory write instructions 11-13, the extended memory write instructions 211-213 have the functions of the general memory write instructions 11-13, and the extended memory write instructions 211-213 all have the second semantics, while the general memory write instructions 11-13 do not have the second semantics.

[0182] Different extended memory write instructions 21 have different encoding formats and reference methods. In a possible implementation, STRBE2, STRHE2, and STRE2 are used to refer to extended memory write instructions 211-213, respectively. Alternatively, EW211, EW212, and EW213 are used to refer to extended memory write instructions 211-213, respectively, to distinguish different extended memory write instructions 21.

[0183] The extended memory write instruction 22 is used to indicate that a storage address in the memory is determined based on a non-scaled immediate addressing mode, and the data of the third byte number in the second source register is written to the determined storage address, and the extended memory write instruction 22 has a second semantics.

[0184] The extended memory write instruction 22 is an instruction obtained by adding the second semantics to the general memory write instruction 2. The extended memory write instruction 22 has the same instruction format as the general memory write instruction 2, but has a different encoding format from the general memory write instruction 2.

[0185] As shown in Table 7, according to different values ​​of the third byte number, the extended memory write instruction 22 includes at least one of the extended memory write instructions 221-223. Among them, the extended memory write instructions 221-223 are instructions obtained by adding the second semantics to the general memory write instructions 21-23, and compared with the general memory write instructions 21-23, the extended memory write instructions 221-223 have the functions of the general memory write instructions 21-23, and the extended memory write instructions 221-223 all have the second semantics, while the general memory write instructions 21-23 do not have the second semantics.

[0186] Different extended memory write instructions 22 have different encoding formats and reference methods. In a possible implementation, STURBE2, STURHE2, and STURE2 are used to refer to extended memory write instructions 221-223, respectively. Alternatively, EW221, EW222, and EW223 are used to refer to extended memory write instructions 2221-223, respectively, to distinguish different extended memory write instructions 22.

[0187] In one possible implementation, the extended instruction set 2 also includes at least one other functional instruction, and the at least one other functional instruction is used to implement other functions besides accessing memory. Here, the embodiment of the present application does not limit the at least one other functional instruction.

[0188] It should be noted that the general instruction set, extended instruction set 1 and extended instruction set 2 supported by processors of different architectures are different. Accordingly, the encoding format and reference method of memory read and write instructions (i.e., general memory read instructions, general memory write instructions, extended memory read instructions or extended memory write instructions) in different instruction sets are different. Here, the embodiment of the present application does not limit the encoding format and reference method of each memory read and write instruction in the various instruction sets supported by the processor of the first computing device.

[0189] The general instruction set, extended instruction set 1, and extended instruction set 2 are all instruction sets supported by the processor of the first computing device. The second computing device can use the general instruction set, extended instruction set 1, or extended instruction set 2 to compile the application source program into an application program, so that the processor of the first computing device can recognize and execute the application program. In order to further reflect the process of the second computing device using the instruction set supported by the processor of the first computing device to compile the application source program and the process of the first computing device executing the application program, see Figure 2A flowchart of a data processing method provided in an embodiment of the present application is shown.

[0190] 201. A second computing device displays a compiling interface, where the compiling interface is used to provide a compiling function for a processor of a target type.

[0191] The target type of processor includes a processor in the first computing device. The compilation function includes compiling an application that can be recognized and executed by the processor. The target type of processor supports an access order to memory when executing an application that is inconsistent with the order of read and write instructions in the application. Alternatively, it can also be understood that the target type of processor supports a weak memory model, such as an ARM64 architecture processor or a Power architecture processor.

[0192] The compilation interface is provided by the compilation software deployed in the second computing device, and the second computing device displays the compilation interface by running the compilation software. For example, the second computing device runs the compilation software and displays the main interface of the compilation software, and the main interface includes a processor selection box, and the processor selection box is used to provide at least one processor option, and each processor option corresponds to a type of processor. The second user selects the processor option corresponding to the target type of processor in the processor selection box, and the second computing device displays the compilation interface in response to the option operation on the processor option.

[0193] 202. In response to the compiling operation on the application source program in the compiling interface, the second computing device compiles the application source program to obtain an application program, where the application program includes an instruction sequence, where the instruction sequence includes multiple instructions, and the multiple instructions include read and write instructions for performing read operations or write operations on the memory.

[0194] The memory is the memory of the computing device that executes the application. For example, if the application is executed by a first computing device other than the second computing device, the memory is the memory of the first computing device. The application source program is any source code that implements customized functions, and the application is the compilation result of the application source program, and the target type of processor can recognize and run it.

[0195] In one possible implementation, the application source program is an application source program developed for a processor that supports a non-weak memory model, wherein the non-weak memory model includes supporting a global write consistency (total store ordering, TSO) model, and all cores in the processor that supports the TSO model have only one global order for performing read and write operations on the memory.

[0196] The compiling interface includes a compiling option, and the compiling option is used to provide a function of compiling the application source program. The second user selects the compiling option to implement the compiling operation of the application source program. The second computing device responds to the compiling operation of the application source program in the compiling interface and compiles the application source program using the instruction set provided for the processor to obtain the application program.

[0197] The instruction set provided by the compiler software in the second computing device for the processor includes at least one of a general instruction set, a first extended instruction set and a second extended instruction set, wherein the first extended instruction set is the above-mentioned extended instruction set 1 and the second extended instruction set is the above-mentioned extended instruction set 2.

[0198] When the instruction set provided for the processor includes one of a general instruction set, a first extended instruction set and a second extended instruction set, the second computing device responds to a compile operation on the application source program by using an instruction set provided for the processor to compile the application source program to obtain an application program.

[0199] For example, when the instruction set provided by the compiler software for the processor is a general instruction set, the second computing device responds to the compilation operation of the application source program and compiles the application source program using the general instruction set to obtain the application program. At this time, the read instruction in the application program is compiled from the general memory read instruction in the general instruction set, and the write instruction in the application program is compiled from the general memory write instruction in the general instruction set.

[0200] For another example, when the compilation software provides an extended instruction set (a first extended instruction set or a second extended instruction set) for the processor, the second computing device responds to the compilation operation of the application source program and compiles the application source program using the extended instruction set to obtain an application program. At this time, the read instruction in the application program is compiled from the extended memory read instruction in the extended instruction set, and the write instruction in the application program is compiled from the extended memory write instruction in the extended instruction set.

[0201] When the instruction set provided for the processor includes a plurality of instruction sets including a general instruction set, a first extended instruction set, and a second extended instruction set, the second user selects the instruction set, and the second computing device compiles the application source program using the instruction set selected by the second user in response to the compiling operation of the application source program to obtain the application program. For example, the following three situations:

[0202] In the first case, when the instruction set provided for the processor includes a general instruction set and an extended instruction set, the compilation interface further includes an instruction set option, and the instruction set option is used to provide the extended instruction set.

[0203] If the second user selects the instruction option and the compile option, the second computing device compiles the application source program using the extended instruction set in response to the selection of the instruction option and the selection of the compile option to obtain an application program. If the extended instruction set is a first extended instruction set, the read instruction in the application program is compiled from the extended memory read instruction in the first extended instruction set, and the write instruction in the application program is compiled from the extended memory write instruction in the first extended instruction set. If the extended instruction set is a second extended instruction set, the read instruction in the application program is compiled from the extended memory read instruction in the second extended instruction set, and the write instruction in the application program is compiled from the second extended memory write instruction in the second extended instruction set.

[0204] Alternatively, the instruction set option in the compilation interface includes a first instruction set option and a second instruction set option, wherein the first instruction set option is used to provide a first extended instruction set, and the second instruction set option is used to provide a second extended instruction set. If the second user selects the first instruction set option and the compilation option, the second computing device responds to the selection of the first instruction set option and the selection of the compilation option, and uses the first extended instruction set to compile the application source program to obtain the application program. If the second user selects the second instruction set option and the compilation option, the second computing device responds to the selection of the second instruction set option and the selection of the compilation option, and uses the second extended instruction set to compile the application source program to obtain the application program.

[0205] In the second case, when the instruction set provided for the processor includes a first extended instruction set and a second extended instruction set, the compilation interface also includes a first instruction set option but does not include a second instruction set option.

[0206] If the second user selects the first instruction set option and the compilation option, the second computing device compiles the application source program using the first extended instruction set in response to the selection of the first instruction set option and the selection of the compilation option to obtain the application program.

[0207] If the second user does not select the first instruction set option but selects the compile option, the second computing device compiles the application source program using the second extended instruction set in response to the selection of the compile option to obtain the application program.

[0208] In a third case, when the instruction set provided for the processor includes a first extended instruction set and a second extended instruction set, the instruction set options in the compilation interface include a first instruction set option and a second instruction set option.

[0209] If the second user selects the first instruction set option and the compilation option, the second computing device compiles the application source program using the first extended instruction set in response to the selection of the first instruction set option and the selection of the compilation option to obtain the application program.

[0210] If the second user selects the second instruction set option and the compilation option, the second computing device compiles the application source program using the second extended instruction set in response to the selection of the second instruction set option and the compilation option to obtain the application program.

[0211] 203. The second computing device sends the application to the first computing device.

[0212] It should be noted that the second computing device only needs to send the application to the first computing device once, and there is no need to send it multiple times.

[0213] 204. The first computing device receives the application.

[0214] After the first computing device receives the application, the first computing device stores the application, for example, storing the application in a computer-readable storage medium of the first computing device. If the first user issues a deployment command for the application to the first computing device, the first computing device responds to the deployment command for the application and deploys the application, which can also be understood as installing the application.

[0215] 205. The processor of the first computing device obtains an instruction sequence of an application program.

[0216] The instruction sequence is a certain instruction sequence in the application, or is the application.

[0217] In one possible implementation, if the first user issues an execution command for the instruction sequence in the application to the first computing device, the first computing device obtains the instruction sequence in the application in response to the execution command for the instruction sequence.

[0218] If the instruction sequence is a certain section of the instruction sequence in the application, the instruction sequence is used to implement at least one function of the application, and the operation of the first user opening the at least one function on the first computing device is an execution command issued to the first computing device. If the instruction sequence is the entire application, the operation of the first user opening the application on the first computing device is an execution command issued to the first computing device.

[0219] The instruction sequence includes a plurality of instructions arranged in sequence. For example, the instruction sequence includes 100 instructions, and the 100 instructions are arranged in sequence from 1 to 100.

[0220] Accordingly, when the first computing device obtains the instruction sequence, it also obtains it in order. Still taking the instruction sequence including 100 instructions as an example, the first computing device first obtains the first instruction of the 100 instructions, then obtains the second instruction of the 100 instructions, and so on, until the last instruction of the 100 instructions is obtained.

[0221] Alternatively, it can be understood that the processor reads each instruction in the instruction sequence in sequence to obtain the read instruction sequence. Still taking the instruction sequence including 100 instructions as an example, the first computing device first reads the first instruction in the 100 instructions, then reads the second instruction in the 100 instructions, and so on, until the last instruction in the 100 instructions is read, and the read 100 instructions constitute the instruction sequence.

[0222] 206. The processor identifies the execution order of the read and write instructions according to the instruction sequence.

[0223] After the processor obtains the instruction sequence, it sequentially identifies multiple instructions in the instruction sequence. For ease of description, taking the identification of one instruction in the multiple instructions as an example, this step 206 is introduced as follows:

[0224] Each memory read and write instruction in each instruction set of the processor corresponds to a coding format, and a read and write instruction in an application program is encoded by the coding format corresponding to a memory read and write instruction in the instruction set.

[0225] When the processor identifies whether an instruction among multiple instructions is a read-write instruction, it determines whether the order of each character in the instruction is in the encoding format corresponding to the read-write instruction. If it is consistent, the instruction is identified as a read-write instruction. If it is not consistent, the instruction is not identified as a read-write instruction.

[0226] When the instruction is identified as a read instruction among read-write instructions, the processor parses the instruction according to the encoding format corresponding to the read instruction to parse the operands from the instruction, and determines the address of the destination register and the source storage address in the memory based on the parsed operands. At this time, the destination register is a register for storing the data to be read, and the source storage address is the address in the memory where the data to be read is stored.

[0227] When the instruction is identified as a write instruction among read-write instructions, the processor parses the instruction according to the encoding format corresponding to the write instruction to parse the operands from the instruction, and determines the address of the source register and the destination storage address in the memory based on the parsed operands. At this time, the source register is a register for storing data to be written, and the destination storage address is the storage address of the data to be written in the memory.

[0228] After the processor identifies any read-write instruction, the processor identifies the order in which the read-write instruction is arranged in the instruction sequence as the execution order of the read-write instruction. In one possible implementation, the processor operates in a sequential memory access mode, wherein the sequential memory access mode is an operating mode in which the processor accesses memory, and the sequential memory access mode is also called an "ordered" mode. The sequential memory access mode requires that the execution order of the read-write instructions is consistent with the arrangement order of the read-write instructions in the instruction sequence. After the processor identifies a read-write instruction, the processor identifies the arrangement order of the read-write instruction in the instruction sequence as the execution order of the read-write instruction in accordance with the sequential memory access mode.

[0229] The processor starts from the first instruction in the instruction sequence, and identifies and parses each instruction in the instruction sequence in turn. Therefore, the recognition order and decoding order of each instruction in the instruction sequence are the arrangement order of the corresponding instructions in the instruction sequence. When the processor identifies the execution order of each read-write instruction according to the instruction sequence, the processor identifies the recognition order or decoding order of each read-write instruction as the execution order of the corresponding read-write instruction.

[0230] In a possible implementation, after identifying any read-write instruction, the processor also allocates a register for the read-write instruction, so that when the read-write instruction is subsequently executed, the read-write operation can be performed on the memory based on the allocated register.

[0231] For example, when the processor identifies a read instruction for performing a read operation on the memory, the processor queries whether the destination register is in an idle state based on the address of the parsed destination register. If the destination register is in an idle state, the processor assigns the destination register to the read operation corresponding to the read instruction. If the destination register is not in an idle state, the processor uses other registers in an idle state as destination registers and assigns them to the read operation corresponding to the read instruction.

[0232] For another example, when the processor identifies a write instruction for a write operation to the memory, the processor queries whether the source register is in an idle state based on the address of the parsed source register. If the source register is in an idle state, the processor assigns the source register to the write operation corresponding to the write instruction. If the source register is not in an idle state, the processor uses other registers in an idle state as source registers and assigns them to the write operation corresponding to the write instruction.

[0233] 207. The processor executes the read and write instructions according to the execution order of the read and write instructions.

[0234] Since the execution order of the read-write instructions is the arrangement order of the read-write instructions in the instruction sequence, when the processor executes the read-write instructions according to the execution order of the read-write instructions, it first executes the instructions that are arranged in the instruction sequence before the read-write instruction, then executes the read-write instruction, and then executes the instructions that are arranged in the instruction sequence after the read-write instruction, thereby realizing the sequential execution of the read-write instructions in the instruction sequence to ensure the consistency of the processor's access to the memory.

[0235] If the application source program of the application is developed for a processor that supports a non-weak memory model, the arrangement of the read and write instructions in the application meets the requirements of the non-weak memory model for the execution order of the read and write instructions. If the application is executed by a processor that supports a non-weak memory model, the execution order of the read and write instructions in the application is not exchanged, so that the memory consistency of the read and write operations of the memory is maintained. Therefore, if the application is to be run normally, the memory consistency of the read and write operations of the memory needs to be maintained. However, the order of access to the memory when the processor of the first computing device supports the execution of the application is inconsistent with the arrangement order of the read and write instructions in the application. In the related art, when the processor of the first computing device executes the application, it may exchange the execution order of the read and write instructions in the application, thereby causing a memory consistency problem, causing the application to fail to run normally. In the embodiment of the present application, the processor of the first computing device recognizes the arrangement order of the read and write instructions in the instruction sequence as the execution order of the read and write instructions, and executes the read and write instructions in the instruction sequence in sequence, thereby avoiding memory consistency problems and enabling the application to run normally.

[0236] When executing a recognized read instruction, the processor performs a read operation on the memory based on the destination register assigned to the corresponding read operation. For example, the processor reads data from the source storage address based on the address of the destination register assigned to the corresponding read operation and the source storage address parsed from the read instruction, and stores the read data in the destination register to perform a read operation on the source storage address of the memory.

[0237] When executing any recognized write instruction, the processor performs a write operation on the memory based on the source register assigned to the corresponding write operation. For example, the processor obtains data from the source register based on the address of the source register assigned to the corresponding write operation and the destination storage address in the memory parsed from the write instruction, and stores the obtained data to the destination storage address to perform a write operation on the destination storage address of the memory.

[0238] The method provided in the embodiment of the present application obtains the instruction sequence of the application through the processor, identifies the execution order of the read and write instructions in the instruction sequence according to the instruction sequence, and executes the read and write instructions according to the identified execution order to access the memory in the computing device, so that the processor can execute the application normally, and accordingly, the occurrence of adverse situations such as random crashes, restarts or erroneous execution results of the application is reduced, the credibility of the processor is increased, and the reputation and market sales of the processor are further improved.

[0239] To further illustrate the process shown in the above steps 204-207, see Figure 3 The schematic diagram of a data processing process of a processor provided in an embodiment of the present application is shown. The process includes the following steps 301-306.

[0240] 301. The second computing device compiles the application source program using compilation software to obtain an application program executable by the processor of the first computing device.

[0241] 302. After the first computing device obtains the application, the processor of the first computing device obtains instructions (instruction fetch) from the application.

[0242] For example, the processor sequentially reads multiple instructions in the application according to the arrangement order of the instructions in the application.

[0243] 303. The processor decodes multiple instructions.

[0244] In a possible implementation, the processor includes a core and a decoder, the core transmits a plurality of instructions to the decoder, and the decoder decodes the plurality of instructions.

[0245] For example, the decoder identifies the read instruction and the write instruction in the multiple instructions. The decoder parses the source storage address and the address of the destination register from the read instruction, and uses the source storage address and the address of the destination register as the parsing result of the read instruction. If the read instruction also includes a read micro-operation, the decoder can also parse the read micro-operation from the read instruction, and uses the source storage address, the address of the destination register and the read micro-operation. Among them, the read micro-operation is an operation that assists in completing the read operation of the memory, such as data verification and other operations.

[0246] The decoder parses the source register address and the destination storage address from the write instruction, and uses the source register address and the destination storage address as the parsing result of the write instruction. If the write instruction also includes a write micro-operation, the decoder can also parse the write micro-operation from the write instruction, and uses the source register address, the destination storage address and the write micro-operation as the decoding result of the write instruction. Among them, the write micro-operation is an operation that assists in completing the write operation to the memory, such as data verification and other operations.

[0247] After the decoder obtains the parsing results of multiple instructions, it sends and returns the parsing results of multiple instructions to the kernel.

[0248] 304. The processor allocates registers for corresponding read and write operations according to the parsing results of the read and write instructions.

[0249] When the core of the processor receives the parsing result of the read instruction, the core of the processor obtains the address of the destination register from the parsing result of the read instruction, and inquires whether the destination register is in an idle state. If the destination register is in an idle state, the processor assigns the destination register to the read operation corresponding to the read instruction. If the destination register is not in an idle state, the processor uses other registers in an idle state as the destination register, and assigns the other registers to the read operation corresponding to the read instruction to implement register renaming.

[0250] When the core of the processor receives the parsing result of the write instruction, the core of the processor obtains the address of the source register from the parsing result of the write instruction, and queries whether the source register is in an idle state. If the source register is in an idle state, the processor assigns the source register to the write operation corresponding to the write instruction. If the source register is not in an idle state, the processor uses other registers in an idle state as source registers, and assigns the other registers to the write operation corresponding to the write instruction to implement register renaming.

[0251] 305. The core of the processor dispatches the read operation and the write operation to the memory read-write unit.

[0252] In a possible implementation, the processor further includes a memory read and write unit (load & store unit, LSU), which is used to process read and write operations on the memory. After the core of the processor allocates registers for the read instruction and the write instruction, the read operation indicated by the read instruction and the write operation indicated by the write instruction are sent to the LSU. If the read operation also includes a read micro-operation, and the write operation also includes a write micro-operation, the core also sends the read micro-operation in the parsing result of the read instruction and the write operation in the parsing result of the write instruction to the LSU.

[0253] 306. The memory read / write unit uses a sequential memory access mode (ordered) to perform the read operation and the write operation.

[0254] In a possible implementation, the memory read / write unit performs a read operation or a write operation on the memory by a write back method when the sequential memory access mode is used. Of course, the memory read / write unit can also perform a read operation or a write operation on the memory by other methods.

[0255] The method provided in the embodiment of the present application obtains the instruction sequence of the application through the processor, and uses the sequential memory access mode to execute the read and write instructions in the instruction sequence to access the memory in the computing device, thereby avoiding memory consistency problems and enabling the processor to execute the application normally. Accordingly, the occurrence of adverse situations such as random crashes, restarts, or erroneous execution results of the application is reduced, the credibility of the processor is increased, and the reputation and market sales of the processor are further improved.

[0256] It should be noted that the above Figure 2 and Figure 3 The data processing process shown is described by taking the second computing device compiling the application source program and the first computing device executing the application compiled by the second computing device as an example, but in another possible implementation, the application source program does not need to be compiled by the second computing device, but is compiled by the first computing device, and the compiled application is executed by the first computing device. In this case, the first computing device executes the above steps 201-204 and 205-207.

[0257] Combination of the above Figures 1 to 3 The data processing method provided by this application is introduced. Next, Figures 4 to 5 The apparatus and computing device of the embodiments of the present application are introduced as examples.

[0258] See also Figure 4 , an embodiment of the present application provides a structural schematic diagram of a data processing device, the data processing device is configured as a processor of a computing device, the processor supports the access order of the memory when executing an application program and the arrangement order of the read and write instructions in the application program is inconsistent, wherein the read and write instructions are instructions for read and write operations on the memory, and the data processing device includes:

[0259] An acquisition module 401 is used to acquire an instruction sequence of an application program, wherein the instruction sequence includes a plurality of instructions, wherein the plurality of instructions include a read / write instruction for performing a read operation or a write operation on a memory of the computing device, and the application program is deployed in the computing device;

[0260] An identification module 402, used to identify the execution order of the read and write instructions according to the instruction sequence;

[0261] The execution module 403 is used to execute the read and write instructions according to the execution order.

[0262] In a possible implementation, the identification module 402 is used to:

[0263] The arrangement order of the read and write instructions in the instruction sequence is identified as the execution order of the read and write instructions.

[0264] In another possible implementation, the identification module 402 is used to:

[0265] According to the sequential memory access mode, the arrangement order of the read and write instructions in the instruction sequence is identified as the execution order of the read and write instructions. The sequential memory access mode requires that the execution order of the read and write instructions is consistent with the arrangement order of the read and write instructions in the instruction sequence.

[0266] In another possible implementation, the read and write instructions include a read instruction for performing a read operation on the memory or a write instruction for performing a write operation on the memory, the read instruction has a first semantics, and the write instruction has a second semantics;

[0267] Among them, the first semantics is used to indicate that the first instruction in the instruction sequence is executed after the read instruction is executed, and the second semantics is used to indicate that the second instruction in the instruction sequence is executed before the write instruction is completed. The arrangement order of the first instruction in the instruction sequence is after the read instruction, and the arrangement order of the second instruction in the instruction sequence is before the write instruction.

[0268] In another possible implementation, the read instruction is compiled based on an extended memory read instruction, the extended memory read instruction has the first semantics, and the extended memory read instruction is an instruction added to an instruction set of the processor for instructing to read memory data;

[0269] The write instruction is compiled based on an extended memory write instruction, the extended memory write instruction has the second semantics, and the extended memory write instruction is an instruction added to the instruction set for instructing writing memory data.

[0270] In another possible implementation, the extended memory read instruction includes at least one of a first extended memory read instruction, a second extended memory read instruction, a third extended memory read instruction, and a fourth extended memory read instruction, and the extended memory write instruction includes at least one of a first extended memory write instruction and a second extended memory write instruction; wherein the addressing modes supported by the first extended memory read instruction, the second extended memory read instruction, and the first extended memory write instruction do not include a non-scaled immediate addressing mode, and the third extended memory read instruction, the fourth extended memory read instruction, and the second extended memory write instruction all support the non-scaled immediate addressing mode;

[0271] The first extended memory read instruction is used to instruct to determine a storage address in the memory based on a supported addressing mode, and read a first number of bytes of data in the determined storage address into a first destination register;

[0272] The second extended memory read instruction is used to instruct to determine a storage address in the memory based on a supported addressing mode, read a second number of bytes of data in the determined storage address into a second destination register, and fill the remaining bits of the second destination register with a sign bit of the read data;

[0273] The third extended memory read instruction is used to instruct to determine a storage address in the memory based on a non-scaled immediate addressing mode, and read the data of the first byte number in the determined storage address into a third destination register;

[0274] The fourth extended memory read instruction is used to instruct to determine a storage address in the memory based on a non-scaled immediate addressing mode, read a second number of bytes of data in the determined storage address into a fourth destination register, and fill the remaining bits of the fourth destination register with the sign bit of the read data;

[0275] The first extended memory write instruction is used to instruct to determine a storage address in the memory based on a supported addressing mode, and write the data of the third byte number in the first source register into the determined storage address;

[0276] The second extended memory write instruction is used to instruct to determine a storage address in the memory based on the non-scaled immediate addressing mode, and write the data of the third byte number in the second source register into the determined storage address.

[0277] In a possible implementation, the first byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes, the second byte number includes 1 byte, 2 bytes or 4 bytes, and the third byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes;

[0278] The addressing modes supported by the first extended memory read instruction, the second extended memory read instruction and the first extended memory write instruction include a scaled immediate addressing mode, a tag addressing mode or a register addressing mode, and the immediate number used when the scaled immediate addressing mode performs address offset is a scaled operand in the corresponding instruction;

[0279] The immediate number used when performing address offset in the non-scaled immediate number addressing mode is the operand in the corresponding instruction, and the value range of the operand is -256 to 256.

[0280] In another possible implementation, the read instruction is compiled based on an extended memory read instruction, and the extended memory read instruction is an instruction obtained by adding the first semantics to a general memory read instruction in an instruction set of the processor;

[0281] The instruction of the write operation is compiled based on an extended memory write instruction, and the extended memory write instruction is an instruction obtained by adding the second semantics to a general memory write instruction in the instruction set.

[0282] In another possible implementation, the read and write instructions include read instructions for reading operations performed on the memory or write instructions for writing operations performed on the memory, the read instructions are compiled based on general memory read instructions in the instruction set of the processor, and the write instructions are compiled based on general memory write instructions in the instruction set of the processor.

[0283] It should be understood that the data processing device corresponds to the processor of the first computing device in the above method embodiment, and the modules in the data processing device and the above other operations and / or functions are respectively various steps and methods implemented by the processor in the method embodiment. For specific details, please refer to the above method embodiment. For the sake of brevity, they will not be repeated here. In addition, when processing data, the data processing device only uses the division of the above functional modules as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the data processing device is divided into different functional modules to complete all or part of the functions described above. In addition, the data processing device provided in the above embodiment belongs to the same concept as the above method embodiment. Its specific implementation process is detailed in the above method embodiment, which will not be repeated here.

[0284] Figure 5 It should be understood that the device described below can implement any function of the first computing device in any of the above methods.

[0285] Optionally, Figure 5The computing device shown is configured as the computing device described above, and includes at least one processor 501 , a communication bus 502 , a memory 503 , and at least one communication interface 504 .

[0286] The processor 501 may be a general-purpose central processing unit (CPU), a network processor (NP), a microprocessor, a microcontroller unit (MCU), a digital signal processor (DSP), or an artificial intelligence processor, etc., and each computing device may include one or more cores for executing software instructions to perform operations or processing. The processor may be built into a system on chip (SoC), or may be one or more integrated circuits for implementing the solution of the present application, such as an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0287] The communication bus 502 is used to transmit information between the above components. The communication bus 502 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0288] The memory 503 may include a read-only memory and a random access memory, and provide instructions and data to the processor 501. The memory 503 may also include a non-volatile random access memory. For example, the memory 503 may also store information of the device type.

[0289] The memory 503 may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories. Among them, the nonvolatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0290] The memory 503 may exist independently and be connected to the processor 501 via the communication bus 502. The memory 503 may also be integrated with the processor 501.

[0291] The communication interface 504 uses any transceiver-like device for communicating with other devices or communication networks. The communication interface 504 includes a wired communication interface and may also include a wireless communication interface. Among them, the wired communication interface may be, for example, an Ethernet interface. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. The wireless communication interface may be a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof, etc.

[0292] In a specific implementation, as an embodiment, the processor 501 may include one or more CPUs, such as Figure 5 CPU0 and CPU1 are shown in the figure.

[0293] In a specific implementation, as an embodiment, the computing device may include multiple processors, such as Figure 5501 and 505 are shown in FIG. Each of these processors may be a single-CPU or a multi-CPU. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0294] In a specific implementation, as an embodiment, the computing device may further include an output device and an input device. The output device communicates with the processor 501 and may display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 501 and may receive user input in a variety of ways. For example, the input device may be a PCIE device, a mouse, a keyboard, a touch screen device, or a sensor device.

[0295] In some embodiments, the memory 503 is used to store the program code 510 for executing the solution of the present application, and the processor 501 can execute the program code 510 stored in the memory 503 to implement the above data processing method. In other embodiments, based on the hardware structure of the processor 501, the processor 501 can implement the above data processing method.

[0296] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including at least one program code, and the at least one program code can be executed by a processor in a computing device to complete the data processing method in the above embodiment. For example, the computer-readable storage medium is a non-temporary computer-readable storage medium, such as a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0297] An embodiment of the present application also provides a computer program product, which includes at least one program code, and the at least one program code is stored in a computer-readable storage medium. The processor of the computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the processor executes the above-mentioned data processing method.

[0298] Among them, the device, equipment, computer-readable storage medium, and computer program product provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0299] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0300] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (such as program code). When the computer instructions are loaded or executed on a computer, the process or function described in the embodiment of the present application of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center containing one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium may be a solid state disk (SSD).

[0301] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data processing method, characterized in that: The method comprises: The processor obtains an instruction sequence of an application, the instruction sequence comprising a plurality of instructions, the plurality of instructions comprising a read and write instruction for performing a read operation or a write operation on a memory of a computing device, the application being deployed in the computing device, the computing device comprising the processor; The processor identifies the execution order of the read and write instructions according to the instruction sequence; The processor executes the read and write instructions according to the execution order.

2. The method according to claim 1, characterized in that The step of identifying the execution order of the read and write instructions according to the instruction sequence includes: The arrangement order of the read and write instructions in the instruction sequence is identified as the execution order of the read and write instructions.

3. The method according to claim 2, characterized in that The step of identifying the arrangement order of the read-write instructions in the instruction sequence as the execution order of the read-write instructions includes: According to the sequential memory access mode, the arrangement order of the read and write instructions in the instruction sequence is identified as the execution order of the read and write instructions. The sequential memory access mode requires that the execution order of the read and write instructions is consistent with the arrangement order of the read and write instructions in the instruction sequence.

4. The method according to any one of claims 1 to 3, characterized in that The read and write instructions include a read instruction for performing a read operation on the memory or a write instruction for performing a write operation on the memory, the read instruction has a first semantic meaning, and the write instruction has a second semantic meaning; Among them, the first semantics is used to indicate that the first instruction in the instruction sequence is executed after the read instruction is executed, and the second semantics is used to indicate that the second instruction in the instruction sequence is executed before the write instruction is completed. The arrangement order of the first instruction in the instruction sequence is after the read instruction, and the arrangement order of the second instruction in the instruction sequence is before the write instruction.

5. The method according to claim 4, characterized in that The read instruction is compiled based on an extended memory read instruction, the extended memory read instruction has the first semantics, and the extended memory read instruction is an instruction added to the instruction set of the processor for instructing to read memory data; The write instruction is compiled based on an extended memory write instruction, the extended memory write instruction has the second semantics, and the extended memory write instruction is an instruction added to the instruction set for instructing writing memory data.

6. The method according to claim 5, characterized in that The extended memory read instruction includes at least one of a first extended memory read instruction, a second extended memory read instruction, a third extended memory read instruction, and a fourth extended memory read instruction, and the extended memory write instruction includes at least one of a first extended memory write instruction and a second extended memory write instruction; The addressing modes supported by the first extended memory read instruction, the second extended memory read instruction and the first extended memory write instruction do not include a non-scaled immediate addressing mode, and the third extended memory read instruction, the fourth extended memory read instruction and the second extended memory write instruction all support the non-scaled immediate addressing mode; The first extended memory read instruction is used to instruct to determine a storage address in the memory based on a supported addressing mode, and read a first number of bytes of data in the determined storage address into a first destination register; The second extended memory read instruction is used to instruct to determine a storage address in the memory based on a supported addressing mode, read a second number of bytes of data in the determined storage address into a second destination register, and fill the remaining bits of the second destination register with the sign bit of the read data; The third extended memory read instruction is used to instruct to determine a storage address in the memory based on the non-scaled immediate addressing mode, and read the data of the first byte number in the determined storage address into a third destination register; The fourth extended memory read instruction is used to instruct to determine a storage address in the memory based on the non-scaled immediate addressing mode, read the second byte of data in the determined storage address into a fourth destination register, and fill the remaining bits of the fourth destination register with the sign bit of the read data; The first extended memory write instruction is used to instruct to determine a storage address in the memory based on a supported addressing mode, and write the data of the third byte number in the first source register into the determined storage address; The second extended memory write instruction is used to instruct to determine a storage address in the memory based on the non-scaled immediate addressing mode, and write the data of the third byte number in the second source register into the determined storage address.

7. The method according to claim 6, characterized in that The first byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes, the second byte number includes 1 byte, 2 bytes or 4 bytes, and the third byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes; The addressing modes supported by the first extended memory read instruction, the second extended memory read instruction and the first extended memory write instruction include a scaled immediate addressing mode, a tag addressing mode or a register addressing mode, and the immediate number used when the scaled immediate addressing mode performs address offset is a scaled operand in the corresponding instruction; The immediate number used when performing address offset in the non-scaled immediate number addressing mode is the operand in the corresponding instruction, and the value range of the operand is -256 to 256.

8. The method according to claim 4, characterized in that The read instruction is compiled based on an extended memory read instruction, where the extended memory read instruction is an instruction obtained by adding the first semantics to a general memory read instruction in an instruction set of the processor; The write instruction is compiled based on an extended memory write instruction, and the extended memory write instruction is an instruction obtained by adding the second semantics to a general memory write instruction in the instruction set.

9. The method according to any one of claims 1 to 3, characterized in that: The read and write instructions include a read instruction for performing a read operation on the memory or a write instruction for performing a write operation on the memory, the read instruction is compiled based on a general memory read instruction in the instruction set of the processor, and the write instruction is compiled based on a general memory write instruction in the instruction set of the processor.

10. A data processing device, characterized in that: The device comprises: an acquisition module, configured to acquire an instruction sequence of an application, the instruction sequence comprising a plurality of instructions, the plurality of instructions comprising a read / write instruction for performing a read operation or a write operation on a memory of a computing device, the application being deployed in the computing device; An identification module, used for identifying the execution order of the read and write instructions according to the instruction sequence; An execution module, used for executing the read and write instructions according to the execution order; Wherein, the apparatus is configured as a processor of a computing device.

11. The device according to claim 10, characterized in that The identification module is specifically used for: The arrangement order of the read and write instructions in the instruction sequence is identified as the execution order of the read and write instructions.

12. The device according to claim 11, characterized in that The identification module is specifically used for: According to the sequential memory access mode, the arrangement order of the read and write instructions in the instruction sequence is identified as the execution order of the read and write instructions. The sequential memory access mode requires that the execution order of the read and write instructions is consistent with the arrangement order of the read and write instructions in the instruction sequence.

13. The device according to any one of claims 10 to 12, characterized in that The read and write instructions include a read instruction for performing a read operation on the memory or a write instruction for performing a write operation on the memory, the read instruction has a first semantic meaning, and the write instruction has a second semantic meaning; Among them, the first semantics is used to indicate that the first instruction in the instruction sequence is executed after the read instruction is executed, and the second semantics is used to indicate that the second instruction in the instruction sequence is executed before the write instruction is completed. The arrangement order of the first instruction in the instruction sequence is after the read instruction, and the arrangement order of the second instruction in the instruction sequence is before the write instruction.

14. The device according to claim 13, characterized in that The read instruction is compiled based on an extended memory read instruction, the extended memory read instruction has the first semantics, and the extended memory read instruction is an instruction added to the instruction set of the processor for instructing to read memory data; The write instruction is compiled based on an extended memory write instruction, the extended memory write instruction has the second semantics, and the extended memory write instruction is an instruction added to the instruction set for instructing writing memory data.

15. The device according to claim 14, characterized in that The extended memory read instruction includes at least one of a first extended memory read instruction, a second extended memory read instruction, a third extended memory read instruction, and a fourth extended memory read instruction, and the extended memory write instruction includes at least one of a first extended memory write instruction and a second extended memory write instruction; The addressing modes supported by the first extended memory read instruction, the second extended memory read instruction and the first extended memory write instruction do not include a non-scaled immediate addressing mode, and the third extended memory read instruction, the fourth extended memory read instruction and the second extended memory write instruction all support the non-scaled immediate addressing mode; The first extended memory read instruction is used to instruct to determine a storage address in the memory based on a supported addressing mode, and read a first number of bytes of data in the determined storage address into a first destination register; The second extended memory read instruction is used to instruct to determine a storage address in the memory based on a supported addressing mode, read a second number of bytes of data in the determined storage address into a second destination register, and fill the remaining bits of the second destination register with the sign bit of the read data; The third extended memory read instruction is used to instruct to determine a storage address in the memory based on the non-scaled immediate addressing mode, and read the data of the first byte number in the determined storage address into a third destination register; The fourth extended memory read instruction is used to instruct to determine a storage address in the memory based on the non-scaled immediate addressing mode, read the second byte of data in the determined storage address into a fourth destination register, and fill the remaining bits of the fourth destination register with the sign bit of the read data; The first extended memory write instruction is used to instruct to determine a storage address in the memory based on a supported addressing mode, and write the data of the third byte number in the first source register into the determined storage address; The second extended memory write instruction is used to instruct to determine a storage address in the memory based on the non-scaled immediate addressing mode, and write the data of the third byte number in the second source register into the determined storage address.

16. The device according to claim 15, characterized in that The first byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes, the second byte number includes 1 byte, 2 bytes or 4 bytes, and the third byte number includes 1 byte, 2 bytes, 4 bytes or 8 bytes; The addressing modes supported by the first extended memory read instruction, the second extended memory read instruction and the first extended memory write instruction include a scaled immediate addressing mode, a tag addressing mode or a register addressing mode, and the immediate number used when the scaled immediate addressing mode performs address offset is a scaled operand in the corresponding instruction; The immediate number used when performing address offset in the non-scaled immediate number addressing mode is the operand in the corresponding instruction, and the value range of the operand is -256 to 256.

17. The device according to claim 13, characterized in that The read instruction is compiled based on an extended memory read instruction, where the extended memory read instruction is an instruction obtained by adding the first semantics to a general memory read instruction in an instruction set of the processor; The instruction of the write operation is compiled based on an extended memory write instruction, and the extended memory write instruction is an instruction obtained by adding the second semantics to a general memory write instruction in the instruction set.

18. The device according to any one of claims 10 to 12, characterized in that The read and write instructions include a read instruction for performing a read operation on the memory or a write instruction for performing a write operation on the memory, the read instruction is compiled based on a general memory read instruction in the instruction set of the processor, and the write instruction is compiled based on a general memory write instruction in the instruction set of the processor.

19. A computing device, characterized in that The computing device comprises a processor configured to execute the method of any one of claims 1 to 9.

20. A computer-readable storage medium, characterized in that: At least one program code is stored in the storage medium, and the at least one program code is read by a processor in the computing device so that the processor executes the method according to any one of claims 1 to 9.

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