Memory access control circuit and method, electronic equipment and medium

Abstract

The invention discloses a memory access control circuit and method, electronic equipment and a medium, and belongs to the technical field of computers. The memory access control circuit comprises a memory tag extension (MTE) module, and a processor and a first buffer which are connected with the MTE module, the MTE module is used for acquiring a virtual address and an access tag of a to-be-accessed memory unit in the memory from a memory access request transmitted by the processor; obtaining a memory label of the memory unit to be accessed from a first buffer according to the virtual address; comparing the access tag with the memory tag; the comparison result is transmitted to the processor; and the processor is used for processing an access result of the storage unit according to the comparison result, and the storage unit is a to-be-accessed memory unit or a cache unit corresponding to the virtual address.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and specifically relates to a memory access control circuit, method, electronic device and medium. Background Art

[0002] Memory Tagging Extension (MTE) is a new feature introduced in the Armv8.5-A architecture, which aims to improve the security of the system by detecting and preventing memory access violations through hardware mechanisms.

[0003] In the related art, when the central processing unit (CPU) initiates an access request to the memory through the MTE method, it is necessary to first convert the virtual address of the memory unit to be accessed in the access request into a physical address through the address conversion module, and then obtain the tag of the memory unit to be accessed from the tag storage area of ​​the memory according to the physical address, and compare it with the access tag in the access request. If the access tag in the access request matches the tag of the unit to be accessed, the CPU can access the memory unit to be accessed according to the physical address.

[0004] However, each time the CPU accesses the memory, it needs to convert the virtual address of the memory into a physical address before performing subsequent label comparison, which increases the memory access time. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a memory access control circuit, method, electronic device and medium, which can improve the access efficiency of the memory.

[0006] In a first aspect, an embodiment of the present application provides a memory access control circuit, the memory access control circuit comprising:

[0007] A memory tag extension (MTE) module, and a processor and a first buffer connected to the MTE module;

[0008] The MTE module is used to obtain a virtual address and an access tag of a memory unit to be accessed in the memory from a memory access request transmitted by the processor; and obtain a memory tag of the memory unit to be accessed from the first buffer according to the virtual address; and compare the access tag and the memory tag; and transmit the comparison result to the processor;

[0009] The processor is used to process the access result to the storage unit according to the comparison result, and the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.

[0010] In a second aspect, an embodiment of the present application provides an electronic device, comprising a memory access control circuit as described in any one of the first aspects.

[0011] In a third aspect, an embodiment of the present application provides a memory access control method, which is applied to the memory access control circuit described in the first aspect, and the method includes:

[0012] Obtaining a virtual address and an access tag of a memory unit to be accessed in the memory from the memory access request;

[0013] According to the virtual address, obtain the memory tag of the memory unit to be accessed;

[0014] Comparing the access tag with the memory tag to obtain a comparison result;

[0015] According to the comparison result, the access result to the storage unit is processed, and the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.

[0016] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the memory access control method described in the third aspect are implemented.

[0017] In a fifth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the memory access control method described in the third aspect are implemented.

[0018] In a sixth aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the memory access control method as described in the first aspect.

[0019] In a seventh aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the memory access control method as described in the first aspect.

[0020] In an embodiment of the present application, a memory access control circuit includes a memory tag extension MTE module, a processor connected to the MTE module, and a first buffer; since the MTE module can obtain the virtual address and access tag of the memory unit to be accessed in the memory from the memory access request transmitted by the processor; and obtain the memory tag of the memory unit to be accessed from the first buffer according to the virtual address; and compare the access tag and the memory tag; and transmit the comparison result to the processor. Therefore, the processor can process the access result of the storage unit according to the comparison result, and the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address. In this way, when accessing the memory, the MTE module only needs to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request, and according to the virtual address, it can obtain the memory tag of the memory unit to be accessed from the first buffer, and compare the access tag and the memory tag. Therefore, by using the memory access control circuit of the present application, the tag comparison can be performed without converting the virtual address into a physical address, thereby effectively reducing the access time of the memory, thereby improving the memory access efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a structural diagram of a memory access control circuit provided in an embodiment of the present application;

[0022] Figure 2 is a structural diagram of a memory access control circuit provided in an embodiment of the present application;

[0023] Figure 3 is a structural diagram of a memory access control circuit provided in an embodiment of the present application;

[0024] Figure 4 is a structural diagram of a memory access control circuit provided in an embodiment of the present application;

[0025] Figure 5 is a structural diagram of a memory access control circuit provided in an embodiment of the present application;

[0026] Figure 6 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0027] Figure 7 It is a flowchart of a memory access control method provided by an embodiment of the present application;

[0028] Figure 8 It is a flowchart of a memory access control method provided by an embodiment of the present application;

[0029] Fig. 9 It is a flowchart of a memory access control method provided by an embodiment of the present application;

[0030] Fig.10 It is a flowchart of a memory access control method provided by an embodiment of the present application;

[0031] Fig.11 It is a flowchart of a memory access control method provided by an embodiment of the present application;

[0032] Fig.12 is a structural diagram of a memory access control circuit provided in an embodiment of the present application;

[0033] Fig.13 It is a flowchart of a memory access control method provided by an embodiment of the present application;

[0034] Fig.14 It is a structural diagram of a memory access control device provided in an embodiment of the present application;

[0035] Fig.15 It is a structural diagram of a memory access control device provided in an embodiment of the present application;

[0036] Fig.16 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0037] Fig.17 It is a schematic diagram of the hardware structure of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0039] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0040] The terms "at least one (item)", "at least one of" and the like in the specification and claims of the present application refer to any one, any two or a combination of more than two of the objects included therein. For example, at least one (item) of a, b, and c can be represented by: "a", "b", "c", "a and b", "a and c", "b and c" and "a, b and c", where a, b, and c can be single or multiple. Similarly, "at least two (items)" refers to two or more, and its meaning is similar to that of "at least one (item)".

[0041] The memory access control circuit, method, electronic device and medium provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0042] The terms involved in the embodiments of the present application are explained below.

[0043] 1) Memory Management Unit (MMU) is a computer hardware responsible for processing memory access requests from the central processing unit (CPU). Its main functions include virtual address to physical address conversion, memory protection, CPU cache control, and bus arbitration and memory bank switching in simpler computer architectures.

[0044] 2) Translation Look Aside Buffer (TLB), also translated as page table cache and translation bypass cache, is a CPU cache used by the memory management unit to improve the speed of translating virtual addresses to physical addresses. All desktop and server processors (such as x86) use TLB. TLB has a fixed number of space slots for storing tag page table entries that map virtual addresses to physical addresses. It is a typical combined storage (Content-Addressable Memory, CAM). Its search keyword is the virtual memory address, and its search result is the physical address. If the requested virtual address exists in the TLB, the CAM will give a very fast match result, and then the obtained physical address can be used to access the memory. If the requested virtual address is not in the TLB, the tag page table will be used for virtual-to-real address conversion, and the access speed of the tag page table is much slower than that of the TLB. Some systems allow the tag page table to be swapped to secondary storage, so the virtual-to-real address conversion may take a very long time.

[0045] 3) Advanced eXtensible Interface (AXI) is a bus protocol. It is the most important part of the Advanced Microcontroller Bus Architecture (AMBA) protocol proposed by ARM. It is an on-chip bus for high performance, high bandwidth, and low latency. In chip systems with high performance requirements, the AXI bus is often used to connect multiple master devices and slave devices to achieve address and data transmission between multiple memory-mapped devices.

[0046] 4) AXI Coherency Extensions (ACE) is a bus protocol designed by ARM to provide system-level cache coherence. It is based on the AXI protocol and supports cache coherence by adding additional signals and channels, so that multiple processors or agents can share data efficiently without software intervention to maintain cache coherence.

[0047] In the memory access control circuit provided in the embodiment of the present application, by adding an MTE module connected to the processor in the memory access control circuit, the MTE module can obtain the virtual address and access tag of the memory unit to be accessed in the memory from the memory access request transmitted by the processor; and obtain the memory tag of the memory unit to be accessed from the first buffer according to the virtual address; and compare the access tag and the memory tag; and transmit the comparison result to the processor. Therefore, the processor can process the access result of the storage unit according to the comparison result, and the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address. In this way, when accessing the memory, the MTE module only needs to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request, and obtain the memory tag of the memory unit to be accessed from the first buffer according to the virtual address, and compare the access tag and the memory tag. Therefore, by using the memory access control circuit of the present application, the tag comparison can be performed without converting the virtual address into a physical address, thereby effectively reducing the access time of the memory, thereby improving the memory access efficiency.

[0048] The present application embodiment provides a memory access control circuit. Figure 1 FIG. 1 is a schematic diagram showing the structure of a memory access control circuit 100 provided in an embodiment of the present application. Figure 1 As shown, the memory access control circuit 100 provided in the embodiment of the present application may include:

[0049] A memory tag extension (MTE) module 11 , and a processor 12 and a first buffer 13 connected to the MTE module 11 .

[0050] The MTE module 11 is used to obtain the virtual address and access tag of the memory unit to be accessed in the memory from the memory access request transmitted by the processor 12; and obtain the memory tag of the memory unit to be accessed from the first cache 13 according to the virtual address; and compare the access tag and the memory tag; and transmit the comparison result to the processor 12; the processor 12 is used to process the access result of the storage unit according to the comparison result, and the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.

[0051] In some embodiments of the present application, the first buffer 13 is used to cache memory tags of some memory units in the memory.

[0052] In some embodiments of the present application, the processor 12 may be a CPU or a core of a CPU, and the specific processor 12 may be determined according to actual needs, and this embodiment does not impose any specific limitation here.

[0053] In some embodiments of the present application, the memory may be a double data rate synchronous dynamic random access memory (DDR) or a static random access memory (SRAM), and this embodiment does not impose any specific limitation on this.

[0054] In some embodiments of the present application, the MTE module 11 may determine a tag address corresponding to the virtual address, and then obtain a memory tag of the memory unit to be accessed from a cache unit in the first cache 13 whose address is the tag address.

[0055] In some embodiments of the present application, when the comparison result indicates that the access tag and the memory tag match, the processor 12 can determine that the access to the storage unit is a legal access based on the comparison result, and the processor 12 can perform subsequent data processing on the access result.

[0056] In some embodiments of the present application, when the comparison result indicates that the access tag and the memory tag do not match, the processor 12 may determine, based on the comparison result, that the access to the storage unit is an illegal access, and the processor 12 may not perform subsequent data processing on the access result, and may record the illegal access to the storage unit.

[0057] It should be noted that, when the processor 12 determines that the access to the above-mentioned storage unit is an illegal access based on the above-mentioned comparison results, it can also record the illegal access to the above-mentioned storage unit and perform subsequent data processing on the above-mentioned access results. When the number of recorded illegal accesses reaches a preset number, no subsequent data processing is performed on the above-mentioned access results.

[0058] In some embodiments of the present application, the comparison result indicates that the access tag and the memory tag match, which can be understood as the access tag and the memory tag are the same. The comparison result indicates that the access tag and the memory tag do not match, which can be understood as the access tag and the memory tag are not the same.

[0059] For example, when the access tag is 0X07 and the memory tag is 0X07, the MTE module 11 may determine that the access tag matches the memory tag, and the MTE module 11 may send the comparison result of the access tag and the memory tag to the processor 12. The processor 12 may determine that the access to the storage unit is a legal access based on the comparison result of the access tag and the memory tag, and the processor 12 may perform subsequent data processing on the access result.

[0060] For another example, when the access tag is 0X07 and the memory tag is 0X08, the MTE module 11 may determine that the access tag and the memory tag do not match, and the MTE module 11 may send the comparison result of the access tag and the memory tag not matching to the processor 12. The processor 12 may determine that the access to the storage unit is an illegal access based on the comparison result of the access tag and the memory tag not matching, and the processor 12 may not perform subsequent data processing on the access result, and record the illegal access to the storage unit.

[0061] In the memory access control circuit provided in the embodiment of the present application, by adding an MTE module connected to the processor in the memory access control circuit, the MTE module can obtain the virtual address and access tag of the memory unit to be accessed in the memory from the memory access request transmitted by the processor; and obtain the memory tag of the memory unit to be accessed from the first buffer according to the virtual address; and compare the access tag and the memory tag; and transmit the comparison result to the processor. Therefore, the processor can process the access result of the storage unit according to the comparison result, and the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address. In this way, when accessing the memory, the MTE module only needs to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request, and obtain the memory tag of the memory unit to be accessed from the first buffer according to the virtual address, and compare the access tag and the memory tag. Therefore, by using the memory access control circuit of the present application, the tag comparison can be performed without converting the virtual address into a physical address, which can effectively reduce the access time of the memory, thereby improving the memory access efficiency.

[0062] In some embodiments of the present application, Figure 1 ,like Figure 2 As shown, the MTE module may include a separation module 111 and a comparison module 112 connected to the separation module 111 , the separation module 111 is connected to the processor 12 and the first buffer 13 , and the comparison module 112 is connected to the processor 12 .

[0063] In some embodiments of the present application, the separation module 111 is used to separate the virtual address and the access tag from the memory access request, and obtain the memory tag from the first buffer 13 according to the virtual address, and transmit the access tag and the memory tag to the comparison module 112;

[0064] The comparison module 112 is used to compare the access tag and the memory tag, and transmit the comparison result to the processor 12.

[0065] In some embodiments of the present application, the length of the memory access request may be 16 bits, wherein the data corresponding to the 4 high bits in the memory access request is the access tag, and the data corresponding to the 12 low bits in the memory access request is the virtual address.

[0066] In some embodiments of the present application, after receiving the above-mentioned memory access request transmitted by the processor 12, the separation module 111 can separate the above-mentioned access tag from the 4 high bits in the above-mentioned memory access request, and separate the above-mentioned virtual address from the 12 low bits in the above-mentioned memory access request.

[0067] In some embodiments of the present application, the separation module 111 determines a tag address corresponding to the virtual address, and then obtains a memory tag of the memory unit to be accessed from a cache unit in the first cache 13 whose address is the tag address.

[0068] In some embodiments of the present application, when the access tag and the memory tag are the same, the comparison module 112 determines that the access tag and the memory tag match, and transmits the comparison result of the access tag and the memory tag matching to the processor 12.

[0069] In some embodiments of the present application, when the access tag and the memory tag are the same, the comparison module 112 determines that the access tag and the memory tag match, and transmits the comparison result that the access tag and the memory tag do not match to the processor 12.

[0070] In this way, by adding a separation module and a comparison module to the MTE module, the separation module can separate the above-mentioned virtual address access tag from the memory access request, and obtain the memory tag from the first buffer according to the virtual address, and transmit the access tag to the comparison module; the comparison module can compare the access tag and the memory tag, and transmit the comparison result to the processor. When accessing the memory, the separation module only needs to separate the virtual address and the access tag of the memory unit to be accessed from the memory access request, and obtain the memory tag of the memory unit to be accessed from the first buffer according to the virtual address, so that the comparison module can compare the access tag and the memory tag transmitted by the separation module. Therefore, by adopting the memory access control circuit of the present application, it is possible to perform tag comparison without converting the virtual address into a physical address, thereby effectively reducing the memory access time and improving the memory access efficiency.

[0071] In some embodiments of the present application, the separation module 111 is specifically used to determine the tag address corresponding to the above virtual address according to a preset address mapping relationship; and obtain the above memory tag from the cache unit in the first cache 13 whose address is the above tag address.

[0072] In some embodiments of the present application, the first cache 13 includes at least one cache unit, each cache unit is used to cache a memory tag of a memory unit, and the address of the cache unit and the virtual address of the memory unit where the memory tag cached by the cache unit is located satisfy the above-mentioned address mapping relationship.

[0073] In some embodiments of the present application, the address mapping relationship may include a one-to-one mapping relationship between M virtual addresses and M tag addresses. The separation module 111 may first search for the virtual address from the M virtual addresses in the address mapping relationship. After finding the virtual address, the tag address corresponding to the virtual address is determined according to the mapping relationship, where M is a positive integer.

[0074] In some embodiments of the present application, since the above-mentioned virtual address is the virtual address of the above-mentioned memory unit to be accessed, the memory tag stored in the cache unit whose address is the tag address corresponding to the above-mentioned virtual address in the first cache 13 is the memory tag of the above-mentioned memory unit to be accessed, so that the separation unit 111 can obtain the above-mentioned memory tag from the cache unit whose address is the above-mentioned tag address.

[0075] In this way, the separation module determines the tag address corresponding to the virtual address according to the preset address mapping relationship, and obtains the memory tag from the cache unit whose address is the tag address in the first cache. Therefore, the separation module can obtain the memory tag without converting the virtual address into a physical address, which can effectively reduce the time for obtaining the memory tag, thereby improving the memory access efficiency.

[0076] In some embodiments of the present application, the separation module 111 is further used to obtain the upper memory tag from the memory unit with the address of the above-mentioned tag address in the tag storage area of ​​the memory if it is determined that there is no cache unit with the address of the above-mentioned tag address in the first cache 113.

[0077] In some embodiments of the present application, if it is determined that there is no cache unit with an address as the above-mentioned tag address in the first cache 113, it means that the memory tag of the above-mentioned memory unit to be accessed is not cached in the first cache 113, then the separation module 111 can obtain the upper memory tag from the tag storage unit with an address as the above-mentioned tag address in the tag storage area of ​​the memory.

[0078] In some embodiments of the present application, the tag storage area includes multiple tag storage units, the tag storage area can store memory tags of all memory units in the memory, and each tag storage unit in the tag storage area stores the memory tag of a memory unit.

[0079] In some embodiments of the present application, the address of each tag storage unit and the virtual address of the memory unit where the memory tag cached by the tag storage unit is located satisfy the above-mentioned address mapping relationship. The separation module 111 can obtain the upper memory tag from the tag storage unit whose address in the tag storage area is determined to be the tag address corresponding to the above-mentioned virtual address according to the above-mentioned address mapping relationship.

[0080] For example, there are 10 memory units in total in the memory, namely, memory unit 1, memory unit 2, ..., memory unit 9 and memory unit 10, and the first buffer 113 buffers the memory tag of memory unit 1, the memory tag of memory unit 2 and the memory tag of memory unit 3 in the memory. Assuming that the memory unit to be accessed is memory unit 4 in the memory, there is no cache unit in the first buffer 113 whose address is the tag address corresponding to the virtual address of memory unit 4, and the separation module 111 can obtain the memory tag from the tag storage unit whose address is the tag address in the tag storage area of ​​the memory, and the memory tag stored in the tag storage unit is the memory tag of memory unit 4.

[0081] In this way, the separation module obtains the memory tag from the memory unit with the address as the tag address in the tag storage area of ​​the memory when it determines that there is no cache unit with the address as the tag address in the first cache. As a result, the separation module does not need to convert the virtual address into a physical address, and the comparison module can also perform tag comparison, which can effectively reduce the access time of the memory and thus improve the memory access efficiency.

[0082] In some embodiments of the present application, Figure 1 ,like Figure 3 As shown, the memory access control circuit 10 provided in the embodiment of the present application may further include: an address conversion module 14 connected to the processor 12 and the MTE module 11;

[0083] The MTE module 111 is also used to transmit the above virtual address to the address translation module 14;

[0084] An address conversion module 14, used to convert the above virtual address into a physical address;

[0085] The processor 112 is further configured to access the storage unit corresponding to the physical address.

[0086] In some embodiments of the present application, the storage unit corresponding to the physical address can be understood as a storage unit having an address equal to the physical address.

[0087] In some embodiments of the present application, when the address conversion module 14 converts the virtual address into a physical address, the processor 112 may read the physical address from the address conversion module 14 and then access a storage unit having the address of the physical address.

[0088] In some embodiments of the present application, Figure 3 As shown, the address conversion module 14 may include a TLB module 141 and an MMU module 142 connected to the TLB module 141 , and the TLB module 141 is connected to the MTE module 11 .

[0089] In some embodiments of the present application, the TLB module 141 is used to receive the virtual address transmitted by the MTE module 11, and query the physical address mapped by the tag page table entry through the tag page table entry.

[0090] In some embodiments of the present application, if the TLB module 141 queries the above physical address, the TLB module 141 may transmit the above virtual address to the MMU module 142, and the MMU module 142 may convert the above virtual address transmitted by the TLB module 141 into a virtual address.

[0091] In this way, by adding an address translation module to the memory access control circuit, the MTE module can transmit the virtual address to the address translation module, and the address translation module can convert the virtual address into a physical address, so that the processor can quickly access the storage unit corresponding to the physical address, thereby improving the processor's access efficiency to the memory.

[0092] In some embodiments of the present application, Figure 3 ,like Figure 4 As shown, the memory access control circuit provided in the embodiment of the present application may further include: a second cache 15 connected to the processor 12 and the address conversion module 14.

[0093] The processor 12 is specifically used to access the above-mentioned cache unit when there is a cache unit with the address of the above-mentioned physical address in the second cache 15; or, when there is no cache unit with the address of the physical address in the second cache 15, access the above-mentioned memory unit to be accessed corresponding to the above-mentioned physical address in the memory.

[0094] In some embodiments of the present application, the second cache 15 may be a CPU cache for caching data in some memory units in the memory.

[0095] In some embodiments of the present application, the CPU cache may include N cache units, each of the N cache units is used to cache data in a memory unit in the memory, and N is an integer greater than or equal to 1.

[0096] In some embodiments of the present application, the address of each cache unit may be a physical address of a memory unit corresponding to data cached by the cache unit.

[0097] In some embodiments of the present application, if there is a cache unit in the second cache 15 whose address is the above-mentioned physical address, then the cache data of the above-mentioned cache unit is the data of the above-mentioned memory unit to be accessed, and the processor 12 can obtain the data in the above-mentioned memory unit to be accessed by accessing the above-mentioned cache unit.

[0098] In some embodiments of the present application, if there is no cache unit in the second cache 15 whose address is the above-mentioned physical address, it means that the data in the above-mentioned memory unit to be accessed is not cached in the second cache 15, and the processor 12 can access the above-mentioned memory unit to be accessed in the memory whose address is the above-mentioned physical address.

[0099] In this way, by adding a second cache in the memory access control circuit, the processor can access the cache unit when there is a cache unit with an address that is a physical address in the second cache, so that the processor can access the memory unit to be accessed without accessing the memory, thereby improving the processor's access efficiency to the memory.

[0100] In some embodiments of the present application, the first buffer 13 may be a buffer in the second buffer 15 .

[0101] In some embodiments of the present application, in order to save the space occupied by the cache, the first cache 13 can be set in the second cache 15 so that the first cache 13 becomes a cache in the second cache 15, thereby merging the first cache 13 and the second cache 15 into one cache.

[0102] In this way, since the first cache is a cache in the second cache, the first cache and the second cache can be merged into one cache, thereby effectively saving the space occupied by the cache. In addition, since the first cache is a cache in the second cache, the processor does not need to access different caches separately to obtain memory tags and access cache units, but only needs to access the second cache to obtain memory tags and access cache units, thereby greatly improving the computing efficiency of the processor.

[0103] Figure 5 Schematic diagram of a memory access control circuit provided by an embodiment of the present application. Figure 5 , the memory access control circuit provided in the embodiment of the present application is specifically described:

[0104] The MTE module 11 is used to obtain the virtual address and access tag of the memory unit to be accessed in the memory from the memory access request transmitted by the processor 12; and according to the above virtual address, obtain the memory tag of the above memory unit to be accessed from the first cache 13; and compare the above access tag with the above memory tag; and transmit the comparison result to the processor 12.

[0105] The processor 12 is used to process the access result of the storage unit according to the above comparison result, and the above storage unit is the above memory unit to be accessed or the cache unit corresponding to the above virtual address.

[0106] Specifically, the separation module 111 in the MTE module 11 is used to separate the virtual address and access tag of the memory unit to be accessed from the memory access request of the processor 12, and obtain the memory tag of the accessed memory unit from the first cache 13 according to the virtual address, and transmit the access tag and the memory tag to the comparison module 112 in the MTE module, and transmit the virtual address to the address conversion module 14.

[0107] The comparison module 112 is used to compare the access tag and the memory tag, and transmit the comparison result to the processor 12.

[0108] Specifically, the separation module 111 is used to determine the tag address corresponding to the virtual address according to a preset address mapping relationship; and obtain the memory tag from the cache unit in the first cache 13 whose address is the tag address.

[0109] The separation module 111 is further configured to obtain the memory tag from the tag unit with the address of the tag address in the tag storage area of ​​the memory if it is determined that there is no cache unit with the address of the tag address in the first cache 13 .

[0110] The comparison module 112 is used to compare the access tag and the memory tag, and transmit the comparison result to the processor 12.

[0111] Specifically, the comparison module 112 is used to compare the access tag with the memory tag to see if they match, and transmit the comparison result of whether the access tag and the memory tag match to the processor 12.

[0112] The address conversion module 14 is used to convert the above virtual address into a physical address.

[0113] Specifically, the TLB module 141 in the address conversion module 14 is used to receive the virtual address transmitted by the separation module 111, and query the physical address mapped by the tag page table entry through the tag page table entry.

[0114] If the TLB module 141 does not query the physical address, the TLB module 141 is further configured to transmit the virtual address to the MMU module 142 in the address translation module 14 .

[0115] The MMU module 142 is used to convert the virtual address transmitted by the TLB module 141 into a virtual address.

[0116] The processor 12 is further configured to read the physical address from the address conversion module 14 and access the storage unit corresponding to the physical address.

[0117] Specifically, the processor 12 is used to access the cache unit when there is a cache unit with the address of the above-mentioned physical address in the second cache; or to access the above-mentioned memory unit to be accessed corresponding to the above-mentioned physical address in the memory when there is no cache unit with the address of the above-mentioned physical address in the above-mentioned second cache.

[0118] In summary, by using the memory access control circuit provided by the present application, when accessing the memory, the MTE module only needs to obtain the virtual address and access tag of the memory unit to be accessed in the memory from the memory access request, and according to the virtual address, it can obtain the memory tag of the memory unit to be accessed from the first buffer, and compare the access tag with the memory tag. Therefore, by using the memory access control circuit of the present application, it is possible to perform tag comparison without converting the virtual address into a physical address, thereby effectively reducing the memory access time and improving the memory access efficiency.

[0119] An electronic device provided in an embodiment of the present application is Figure 6 As shown, the electronic device 600 includes Figures 1 to 5 The memory access control circuit shown.

[0120] In the electronic device in the embodiment of the present application, the memory access control circuit in the electronic device is added by adding an MTE module connected to the processor in the memory access control circuit, so that the MTE module can obtain the virtual address and access tag of the memory unit to be accessed in the memory from the memory access request transmitted by the processor; and obtain the memory tag of the memory unit to be accessed from the first buffer according to the virtual address; and compare the access tag and the memory tag; and transmit the comparison result to the processor. Therefore, the processor can process the access result of the storage unit according to the comparison result, and the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address. In this way, when accessing the memory, the MTE module only needs to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request, and obtain the memory tag of the memory unit to be accessed from the first buffer according to the virtual address, and compare the access tag and the memory tag. Therefore, by adopting the memory access control circuit of the present application, the tag comparison can be performed without converting the virtual address into a physical address, thereby effectively reducing the access time of the memory, thereby improving the memory access efficiency.

[0121] It should be noted that, since the electronic device includes the above-mentioned memory access control circuit, when the electronic device is used to access the memory, the same technical effect as the memory access control circuit described above can be achieved, and in order to avoid repetition, it will not be described in detail here.

[0122] Figure 7FIG. 1 is a schematic diagram of a memory access control method provided in an embodiment of the present application, and the memory access control method can be applied to the memory access control circuit in the above embodiment. Figure 7 As shown, the memory access control method provided in the embodiment of the present application may include the following steps 101 to 104.

[0123] S101, obtaining a virtual address and an access tag of a memory unit to be accessed in the memory from a memory access request;

[0124] S102, obtaining a memory tag of a memory unit to be accessed according to the virtual address;

[0125] S103, comparing the access tag and the memory tag to obtain a comparison result;

[0126] S104. Process the access result to the storage unit according to the comparison result, where the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.

[0127] In the memory access control method provided by the present application, the virtual address and access tag of the memory unit to be accessed are obtained from the memory access request, and the memory tag of the memory unit to be accessed can be obtained according to the virtual address, and the access tag and the memory tag are compared. Therefore, by using the memory access control circuit of the present application, the tag comparison can be performed without converting the virtual address into a physical address, thereby effectively reducing the memory access time and improving the memory access efficiency.

[0128] In some embodiments of the present application, Figure 7 ,like Figure 8 As shown, the above step S101 can be implemented by the following step 101a:

[0129] Step 101a: Separate the virtual address and access tag from the memory access request.

[0130] In this way, when accessing the memory, it is only necessary to separate the virtual address and access tag of the memory unit to be accessed from the memory access request, and according to the virtual address, the memory tag of the memory unit to be accessed can be obtained from the first buffer, and the access tag and the memory tag can be compared. Therefore, by adopting the memory access control method of the present application, it is possible to perform tag comparison without converting the virtual address into a physical address, thereby effectively reducing the memory access time and improving the memory access efficiency.

[0131] In some embodiments of the present application, Figure 7 ,like Fig. 9 As shown, the above step 102 can be implemented by the following step 102a and the following step 102b:

[0132] Step 102a: Determine the label address corresponding to the virtual address according to the preset address mapping relationship.

[0133] Step 10ba: Obtain a memory tag from a cache unit whose address is the tag address.

[0134] In this way, the tag address corresponding to the virtual address is determined according to the preset address mapping relationship; and the memory tag is obtained from the cache unit whose address is the tag address in the first cache. Therefore, the memory tag can be obtained without converting the virtual address into a physical address, which can effectively reduce the time for obtaining the memory tag and thus improve the memory access efficiency.

[0135] In some embodiments of the present application, Fig. 9 ,like Fig.10 As shown, the memory access control method provided in the embodiment of the present application may also include the following step 105:

[0136] Step 105: If it is determined that there is no cache unit with the address being the tag address, a memory tag is obtained from the memory unit with the address being the tag address.

[0137] In this way, by obtaining the memory tag from the memory unit with the address being the tag address when it is determined that there is no cache unit with the address being the tag address, tag comparison can be performed without converting the virtual address into a physical address, which can effectively reduce the memory access time and thus improve memory access efficiency.

[0138] In some embodiments of the present application, Figure 8 ,like Fig.11 As shown, before the above step 104, the memory access control method provided in the embodiment of the present application may also include the following step 106a and the following step 106b:

[0139] Step 106a: Convert the virtual address to a physical address.

[0140] Step 106b: Access the storage unit corresponding to the physical address.

[0141] In this way, the virtual address is transmitted to the address conversion module, and the address conversion module can convert the virtual address into a physical address, and can quickly access the storage unit corresponding to the physical address, thereby improving the access efficiency to the memory.

[0142] In some embodiments of the present application, Fig.11 ,like Fig.12 As shown, the above step 106b can be implemented by the following step 106b1 or the following step 106b2:

[0143] Step 106b1: If there is a cache unit whose address is the physical address, access the cache unit.

[0144] Step 106b2: When there is no cache unit with the address being the physical address, access the memory unit to be accessed corresponding to the physical address in the memory.

[0145] In this way, by accessing the cache unit when there is a cache unit with an address that is a physical address in the second cache, the processor can access the memory unit to be accessed without accessing the memory, thereby improving the processor's access efficiency to the memory.

[0146] Next, combine Fig.12 , the memory access control circuit provided in the embodiment of the present application is further described in detail. Fig.12 As shown, the memory access control circuit 120 may include: an MTE split logic module (equivalent to the above-mentioned separation module) 121, an MTE check logic module (equivalent to the above-mentioned comparison module) 122 connected to the MTE split logic module 121, a processor core CPU core 123, a tag cache tag cache (equivalent to the above-mentioned first cache) 124 and a TLB (equivalent to the above-mentioned TLB module) 125, an MMU (equivalent to the above-mentioned MMU module) 126 connected to the TLB 125, and a CPU cache (equivalent to the second cache) 128 connected to the MMU 126 via a bus 127.

[0147] In some embodiments of the present application, Fig.13 As shown, the memory access control process of the memory access control circuit 120 of the present application may include the following steps 1301 to 1305:

[0148] Step 1301, CPU core 123 issues an access request to the memory DDR (relative to the above memory access request).

[0149] Exemplarily, CPUcore 123 issues an access to the memory, which is an access request issued according to the virtual address of the memory unit to be accessed in the memory DDR. The access request includes the virtual address of the memory unit to be accessed and the tag key tag key corresponding to the virtual address (relative to the above access tag).

[0150] Step 1302: The MTE split logic module 121 separates the virtual address and the tag key in the access request, and continues to access the data in the memory unit to be accessed through the bus 127 according to the virtual address.

[0151] For example, Fig.12 As shown, bus 127 may be an AXI bus or an ACE bus.

[0152] Step 1303 : The MTE split logic module 121 simultaneously passes the tag key to the MTE check logic module 122 , and passes the tag lock address (equivalent to the above-mentioned label address) to the tag cache 124 .

[0153] Exemplarily, the MTE split logic module 121 may determine a tag address corresponding to the virtual address according to a preset address mapping relationship.

[0154] Step 1304 , Tag cache 124 obtains a tag lock (equivalent to the above-mentioned memory tag) from the memory according to the corresponding tag key address and caches it.

[0155] Exemplarily, the tag cache 124 may obtain the tag lock from the tag zone (equivalent to the tag storage area) in the memory according to the corresponding tag key address.

[0156] Step 1305 , the MTE check logic 122 obtains the corresponding tag lock from the tag cache 124 , compares the tag key with the tag lock, and returns a check result (equivalent to the above comparison result) to the CPU core 123 .

[0157] Exemplarily, if the check result in step 1305 is false, that is, the tag key and the tag lock do not match, then the data access process in step 1302 will not proceed. If the check result in step 1302 is true, that is, the tag key and the tag lock match, then the data access process in step 1302 can continue, and the virtual address is converted into a physical address for access through TLB125 and MMU126.

[0158] Exemplarily, when the CPU core 123 accesses the memory through the MTE split logic module 121, it first searches in the CPU cache 128 whether there is a cache unit with the address of the physical address. If so, the data in the cache unit is accessed. If not, the data in the memory unit to be accessed with the address of the physical address is accessed.

[0159] By adopting the memory access control circuit of the present application, on the one hand, if the comparison is unsuccessful, the subsequent access process can be saved, which effectively solves the time-consuming address translation problem in the prior art, thereby greatly improving the memory access efficiency. On the other hand, since the tags of the MTE in the prior art are all tags corresponding to the physical address, the virtual address support for the user space is not very friendly, and the address translation is required to find the tag, so the memory access efficiency is low. After supporting the virtual address tag, the virtual address can be used directly to find the tag, thereby improving the memory access efficiency.

[0160] It should be noted that the specific implementation process of the above steps can refer to the relevant description of the above embodiment. To avoid repetition, this embodiment will not be described again here.

[0161] It should be noted that the above-mentioned method embodiments, or various possible implementation methods in each method embodiment, can be executed separately, or any two or more can be executed in combination with each other. The specific implementation method can be determined according to actual usage requirements, and the embodiments of the present application do not impose any restrictions on this.

[0162] The memory access control method provided in the embodiment of the present application can be executed by a memory access control device. In the embodiment of the present application, the memory access control device executing the memory access control method is taken as an example to illustrate the memory access control device provided in the embodiment of the present application.

[0163] Fig.14 1 is a schematic diagram of the structure of a memory access control device 1400 provided in an embodiment of the present application. The memory access control device 1400 includes: an acquisition module 1401 and a processing module 1402.

[0164] The acquisition module 1401 is used to acquire the virtual address and access tag of the memory unit to be accessed in the memory from the memory access request transmitted by the processor; and acquire the memory tag of the memory unit to be accessed from the first buffer according to the virtual address; and compare the access tag with the memory tag; and transmit the comparison result to the processor;

[0165] The processing module 1402 is used to process the access result of the storage unit according to the comparison result, and the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.

[0166] In some embodiments of the present application, the acquisition module 1401 is specifically used to:

[0167] Used to separate the virtual address and the access tag from the memory access request, and obtain the memory tag from the first buffer according to the virtual address, and transmit the access tag and the memory tag to the comparison module;

[0168] The access tag and the memory tag are compared, and the comparison result is transmitted to the processor.

[0169] In some embodiments of the present application, the acquisition module 1401 is specifically used to:

[0170] According to a preset address mapping relationship, a tag address corresponding to the virtual address is determined; and the memory tag is obtained from a cache unit in the first cache whose address is the tag address.

[0171] In some embodiments of the present application, the acquisition module 1401 is specifically used to:

[0172] The separation module is further configured to obtain the memory tag from a tag unit with an address of the tag address in a tag storage area of ​​the memory if it is determined that there is no cache unit with an address of the tag address in the first cache.

[0173] In some embodiments of the present application, Fig.14 ,like Fig.15 As shown, the memory access control device 1400 further includes: a conversion module 1403, an acquisition module 1401, and is further used to transmit the virtual address to the address conversion module;

[0174] The conversion module 1403 is used to convert the virtual address into a physical address;

[0175] The processing module 1402 is further configured to access the storage unit corresponding to the physical address.

[0176] In some embodiments of the present application, the processing module 1402 is specifically configured to:

[0177] If there is a cache unit with the address of the physical address in the second cache, the cache unit is accessed; or if there is no cache unit with the address of the physical address in the second cache, the memory unit to be accessed corresponding to the physical address in the memory is accessed.

[0178] In some embodiments of the present application, the first buffer is a buffer in the second buffer.

[0179] In the memory access control device provided in the embodiment of the present application, the memory access control device obtains the virtual address and access tag of the memory unit to be accessed in the memory from the memory access request, and can obtain the memory tag of the memory unit to be accessed according to the virtual address, and compare the access tag with the memory tag. Therefore, by using the memory access control device of the present application, it is possible to perform tag comparison without converting the virtual address into a physical address, thereby effectively reducing the memory access time and improving the memory access efficiency.

[0180] The memory access control device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or a device other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device, an augmented reality / virtual reality device, a robot, a wearable device, a super mobile personal computer, a netbook or a personal digital assistant, etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0181] The memory access control device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0182] The memory access control device provided in the embodiment of the present application can implement each process implemented by each embodiment of the above-mentioned memory access control method, and will not be described again here to avoid repetition.

[0183] Alternatively, if Fig.16 As shown, an embodiment of the present application also provides an electronic device 1600, including a processor 1601 and a memory 1602, wherein the memory 1602 stores programs or instructions that can be executed on the processor 1601, and when the program or instructions are executed by the processor 1601, the various steps of the above-mentioned memory access control method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, they are not repeated here.

[0184] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0185] Fig.17 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of the present application.

[0186] The electronic device 1700 includes, but is not limited to, components such as a radio frequency unit 1701, a network module 1702, an audio output unit 1703, an input unit 1704, a sensor 1705, a display unit 1706, a user input unit 1707, an interface unit 1708, a memory 1709, and a processor 1710. In addition, the electronic device 500 also includes a memory access control circuit 10. It should be noted that the functions and connection relationships of the modules in the above-mentioned memory access control circuit 10 can refer to the above description and will not be repeated here.

[0187] Those skilled in the art will appreciate that the electronic device 1700 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 1710 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Fig.17 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0188] The processor 1710 is used to obtain a virtual address and an access tag of a memory unit to be accessed in the memory from a memory access request;

[0189] According to the virtual address, obtaining a memory tag of the memory unit to be accessed;

[0190] Comparing the access tag with the memory tag to obtain a comparison result;

[0191] According to the comparison result, the access result to the storage unit is processed, and the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.

[0192] In some embodiments of the present application, the processor 1710 is specifically configured to:

[0193] The virtual address and the access tag are separated from the memory access request.

[0194] In some embodiments of the present application, the processor 1710 is specifically configured to:

[0195] Determine the label address corresponding to the virtual address according to a preset address mapping relationship;

[0196] The memory tag is obtained from a cache unit whose address is the tag address.

[0197] In some embodiments of the present application, the processor 1710 is further configured to:

[0198] If it is determined that there is no cache unit with the address being the tag address, the memory tag is obtained from the memory unit with the address being the tag address.

[0199] In some embodiments of the present application, the processor 1710 is further configured to:

[0200] According to the comparison result, before processing the access result to the storage unit, converting the virtual address into a physical address;

[0201] The storage unit corresponding to the physical address is accessed.

[0202] In some embodiments of the present application, the processor 1710 is specifically configured to:

[0203] If there is a cache unit with an address equal to the physical address, the cache unit is accessed; or if there is no cache unit with an address equal to the physical address, the memory unit to be accessed corresponding to the physical address in the memory is accessed.

[0204] In the electronic device provided in the present application, the electronic device obtains the virtual address and access tag of the memory unit to be accessed in the memory from the memory access request; obtains the memory tag of the memory unit to be accessed according to the virtual address; compares the access tag and the memory tag to obtain a comparison result; and processes the access result of the storage unit according to the comparison result, wherein the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address. In this way, when accessing the memory, the electronic device only needs to obtain the virtual address and access tag of the memory unit to be accessed from the memory access request, and can obtain the memory tag of the memory unit to be accessed according to the virtual address, and compare the access tag and the memory tag. Therefore, the electronic device using the present application can effectively reduce the access time of the memory, thereby improving the memory access efficiency.

[0205] It should be understood that in the embodiment of the present application, the input unit 1704 may include a graphics processor (Graphics Processing Unit, GPU) 17041 and a microphone 17042, and the graphics processor 17041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 1706 may include a display panel 17061, and the display panel 17061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1707 includes a touch panel 17071 and at least one of other input devices 17072. The touch panel 17071 is also called a touch screen. The touch panel 17071 may include two parts: a touch detection device and a touch controller. Other input devices 17072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0206] The memory 1709 can be used to store software programs and various data. The memory 1709 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 1709 may include a volatile memory or a non-volatile memory, or the memory 1709 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 1709 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0207] The processor 1710 may include one or more processing units; optionally, the processor 1710 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 1710.

[0208] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned memory access control method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0209] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0210] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned memory access control method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0211] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0212] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned memory access control method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0213] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0214] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0215] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A memory access control circuit, characterized in that: The memory access control circuit comprises: A memory tag extension (MTE) module, and a processor and a first buffer connected to the MTE module; The MTE module is used to obtain a virtual address and an access tag of a memory unit to be accessed in the memory from a memory access request transmitted by the processor; and obtain a memory tag of the memory unit to be accessed from the first buffer according to the virtual address; and compare the access tag with the memory tag; and transmit the comparison result to the processor; The processor is used to process the access result of the storage unit according to the comparison result, and the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.

2. The memory access control circuit according to claim 1, characterized in that: The MTE module includes a separation module and a comparison module connected to the separation module, the separation module is connected to the processor and the first buffer, and the comparison module is connected to the processor; The separation module is used to separate the virtual address and the access tag from the memory access request, obtain the memory tag from the first buffer according to the virtual address, and transmit the access tag and the memory tag to the comparison module; The comparison module is used to compare the access tag and the memory tag, and transmit the comparison result to the processor.

3. The memory access control circuit according to claim 2, characterized in that: The separation module is specifically configured to determine a tag address corresponding to the virtual address according to a preset address mapping relationship; and obtain the memory tag from a cache unit in the first cache whose address is the tag address.

4. The memory access control circuit according to claim 3, characterized in that: The separation module is further configured to obtain the memory tag from a tag unit with an address of the tag address in a tag storage area of ​​the memory if it is determined that there is no cache unit with an address of the tag address in the first cache.

5. The memory access control circuit according to claim 1, characterized in that: The memory access control circuit further includes: an address conversion module connected to the processor and the MTE module; The MTE module is further used to transmit the virtual address to the address conversion module; The address conversion module is used to convert the virtual address into a physical address; The processor is further configured to access the storage unit corresponding to the physical address.

6. The memory access control circuit according to claim 5, characterized in that: The memory access control circuit further includes: a second buffer connected to the processor and the address translation module; The processor is specifically used to access the cache unit when there is a cache unit with an address of the physical address in the second cache; or to access the to-be-accessed memory unit corresponding to the physical address in the memory when there is no cache unit with an address of the physical address in the second cache.

7. The circuit according to claim 6, characterized in that The first buffer is a buffer in the second buffer.

8. An electronic device, characterized in that: A memory access control circuit comprising any one of claims 1 to 7.

9. A memory access control method, characterized in that: The memory access control circuit according to any one of claims 1 to 7, the method comprising: Obtaining a virtual address and an access tag of a memory unit to be accessed in the memory from the memory access request; According to the virtual address, obtaining a memory tag of the memory unit to be accessed; Comparing the access tag with the memory tag to obtain a comparison result; According to the comparison result, the access result to the storage unit is processed, and the storage unit is the memory unit to be accessed or the cache unit corresponding to the virtual address.

10. The method according to claim 9, characterized in that The acquiring, according to the virtual address, a memory tag of the memory unit to be accessed comprises: The virtual address and the access tag are separated from the memory access request.

11. The method according to claim 9, characterized in that The acquiring, according to the virtual address, a memory tag of the memory unit to be accessed comprises: Determine the label address corresponding to the virtual address according to a preset address mapping relationship; The memory tag is obtained from a cache unit whose address is the tag address.

12. The method according to claim 11, characterized in that The method further comprises: If it is determined that there is no cache unit with the address being the tag address, the memory tag is obtained from the memory unit with the address being the tag address.

13. The method according to claim 9, characterized in that Before processing the access result to the storage unit according to the comparison result, the method further includes: Converting the virtual address to a physical address; The storage unit corresponding to the physical address is accessed.

14. The method according to claim 13, characterized in that The accessing the storage unit corresponding to the physical address includes: If there is a cache unit with an address equal to the physical address, the cache unit is accessed; or if there is no cache unit with an address equal to the physical address, the memory unit to be accessed corresponding to the physical address in the memory is accessed.

15. An electronic device, characterized in that: It comprises a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the memory access control method as described in any one of claims 8 to 14 are implemented.

16. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the memory access control method as described in any one of claims 8 to 14 are implemented.

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