A method for optimizing process parameters of ceramic chip packaging based on machine learning

Abstract

The present invention relates to the technical field of machine learning, and discloses an optimization method for ceramic chip packaging process parameters based on machine learning. The method includes: collecting first historical data during the packaging process of a target ceramic chip and preprocessing it to extract second historical data; constructing a chip stress prediction model based on the second historical data; collecting real-time data and, after preprocessing, combining the prediction model to predict the stress level of the chip in a future time period; if the predicted stress level is a warning or danger level, dynamically adjusting the packaging process parameters of the ceramic chip. The present invention predicts the future stress risk level of the chip through a machine learning method, and dynamically optimizes and adjusts the packaging process parameters according to the prediction results, thereby effectively reducing the stress failure risk during the ceramic chip packaging process and significantly improving the reliability and yield of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of machine learning. More specifically, the present invention relates to a method for optimizing the process parameters of ceramic chip packaging based on machine learning. Background Art

[0002] With the continuous development of electronic information technology, the application fields of ceramic chips are becoming more and more extensive. During the ceramic chip packaging process, various process parameters need to be optimized and controlled to ensure the performance and reliability of ceramic chips. At present, there are already some methods for optimizing the process parameters of chip packaging.

[0003] Chinese Patent Application with Publication No. CN117634263A discloses a method for optimizing the process parameters of multi-target chip plastic packaging. This method establishes a finite element model of the chip for the transfer molding process, designs experiments using the response surface method and the optimal Latin hypercube sampling, and uses a multi-target optimization algorithm for optimization to obtain the best process parameters. However, this method mainly targets the plastic packaging process and does not consider the particularity during the ceramic chip packaging process. In addition, this method does not use historical data and real-time data to predict the stress level of the chip, lacking dynamic monitoring and control of the chip stress risk.

[0004] Chinese Patent with Authorization Announcement No. CN117234171B discloses a method and system for controlling process parameters for chip production. This method adjusts the tolerance threshold of a preset process parameter set by obtaining the equipment reliability factor and the quality deviation factor, and performs parameter optimization to obtain the target optimal process parameters. However, this method mainly targets the chip dicing process and does not consider the characteristics of the ceramic chip packaging process. In addition, this method does not use machine learning technology to predict the stress risk level of the chip, lacking intelligent decision-making support capabilities.

[0005] In summary, the existing methods for optimizing the process parameters of chip packaging do not consider the particularity of the ceramic chip packaging process and lack targeted optimization measures; they fail to dynamically adjust the packaging process parameters according to the predicted stress risk level and cannot effectively reduce the stress failure risk of ceramic chips. Summary of the Invention

[0006] In order to overcome the above-mentioned defects of the prior art, the present invention provides a method for optimizing the process parameters of ceramic chip packaging based on machine learning.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A method for optimizing the process parameters of ceramic chip packaging based on machine learning, comprising:

[0009] Collecting first historical data of the target ceramic chip during the packaging process; preprocessing the first historical data and extracting second historical data;

[0010] According to the second historical data, a chip stress prediction model is constructed; first real-time data of the ceramic chip packaging process is collected, and the first real-time data is preprocessed to obtain second real-time data; according to the second real-time data and the chip stress prediction model, a chip stress prediction time series is obtained, and the chip stress prediction time series includes a future time period n chip stress prediction values within the package; based on the chip stress prediction time sequence, determine the future time period of the ceramic chip during the packaging process The stress level within the device includes a safety level, a warning level, and a danger level; n is a positive integer;

[0011] If the stress level is a warning level or a danger level, the packaging process parameters of the ceramic chip are dynamically adjusted.

[0012] Furthermore, the first historical data includes environmental state time series data and chip state time series data; the environmental state time series data includes environmental temperature time series data, environmental pressure time series data and environmental humidity time series data; the chip state time series data includes chip stress time series data and chip temperature time series data;

[0013] The second historical data includes environmental state change rate time series data and chip state change rate time series data; the environmental state change rate time series data includes environmental temperature change rate time series data, environmental pressure change rate time series data, and environmental humidity change rate time series data; the chip state change rate time series data includes chip stress change rate time series data and chip temperature change rate time series data;

[0014] The preprocessing of the first historical data to extract the second historical data includes:

[0015] Differentiate the ambient temperature time series data to obtain the ambient temperature change rate time series data;

[0016] Differentiate the ambient pressure time series data to obtain the ambient pressure change rate time series data;

[0017] Differentiate the ambient humidity time series data to obtain the ambient humidity change rate time series data;

[0018] Differentiate the chip stress time series data to obtain the chip stress change rate time series data;

[0019] The chip temperature time series data is differentiated to obtain the chip temperature change rate time series data.

[0020] Furthermore, the constructing of the chip stress prediction model includes:

[0021] Perform feature engineering on the second historical data to obtain a historical comprehensive time series feature set; the historical comprehensive time series feature set includes historical environmental statistical time series features, historical chip statistical time series features, historical environmental energy time series features, historical chip energy time series features, and correlation time series features;

[0022] Construct a chip stress prediction model based on the historical comprehensive time series feature set.

[0023] Furthermore, the performing feature engineering on the second historical data includes:

[0024] Extract the statistical features of the time series data of the environmental state change rate to generate historical environmental statistical time series features;

[0025] Extract the statistical features of the time series data of the chip state change rate to generate historical chip statistical time series features;

[0026] Extract the energy distribution of the time series data of the environmental state change rate on different time scales to obtain historical environmental energy time series features;

[0027] Extract the energy distribution of the time series data of the chip state change rate on different time scales to obtain historical chip energy time series features;

[0028] Calculate the cross-correlation coefficient between the time series data of the environmental state change rate and the time series data of the chip state change rate to obtain correlation time series features.

[0029] Furthermore, the determining the stress level of the ceramic chip in the future time period during the packaging process based on the chip stress prediction time series includes:

[0030] Calculate the mean μ i ,

[0030] , n , σ , , i , n , σ , ,

[0031] , i , i , n , , σ , ,

[0029] , <' n , , i ,σ n )] of the chip stress prediction time series [(t1,σ1),(t2,σ2),…,(t σ and the standard deviation σ σ ; where, t n is the nth moment in the future time period , and σ n is the chip stress prediction value at the nth moment in the future time period ;

[0031] Calculate the structural mutual information PSI i of the chip stress prediction value σ i at the future ith moment in the chip stress prediction time series; when PSI i ≥λ', take the mean μ σ as the chip stress prediction correction value σ' i at the future ith moment, that is, σ' i =μσ ; When PSI i < λ', then σ' i =(1 - w)μ σ + w×σ i-1 ; σ i-1 is the predicted value of the chip stress at the (i - 1)-th future moment, w is the weight of σ i-1 , 2 ≤ i ≤ n, and λ' is the structural mutual information threshold;

[0032] The predicted correction value σ' of the chip stress at the i-th future moment i constitutes the chip stress prediction correction time series [(t1, σ'1), (t2, σ'2), …, (t n , σ' n )]; where σ' n is the predicted correction value of the chip stress at the n-th future moment;

[0033] Based on the chip stress prediction correction time series, determine the stress level of the ceramic chip during the packaging process in the future time period .

[0034] Furthermore, the determining the stress level of the ceramic chip during the packaging process in the future time period based on the chip stress prediction correction time series includes:

[0035] If σ w ≤ σ' i < σ s , then the stress level of the ceramic chip at the i-th future moment during the packaging process is the safety level, where σ s is the safety upper limit and σ w is the warning upper limit;

[0036] If σ d ≤ σ' i < σ w , then the stress level of the ceramic chip at the i-th future moment during the packaging process is the warning level, where σ d is the danger upper limit and σ s [[ID=6o]]> σ w > σ d ;

[0037] If σ' i < σ d , then the stress level of the ceramic chip at the i-th future moment during the packaging process is the danger level.

[0038] Furthermore, the determining the stress level of the ceramic chip during the packaging process in the future time period based on the chip stress prediction correction time series further includes:

[0039] Traverse all chip stress prediction and correction values in the chip stress prediction and correction time series, and count the future time periods separately The number of times the internal stress level is at the safety level is n2, the number of times the stress level is at the warning level is n3, and the number of times the stress level is at the danger level is n4; n2+n3+n4=n;

[0040] Set the weight coefficient w at the security level moment s , the weight coefficient w at the warning level w and the weight coefficient w at the moment of danger level d , according to n2, n3, n4, w s 、w w and w d , calculate the future time period The weighted proportion of the internal warning level moments P w and the weighted proportion of the dangerous level moment P d ;

[0041] According to P w and P d Determine the future time period of the ceramic chip during the packaging process The stress level inside is the dangerous level.

[0042] Furthermore, according to P w and P d Determine the future time period of the ceramic chip during the packaging process The stress levels within the hazardous levels include:

[0043] If P d >α, then determine the future time period of the ceramic chip during the packaging process The stress level within is the danger level; where α is the danger ratio threshold;

[0044] If P d ≤α and P w >β, then determine the future time period of the ceramic chip during the packaging process The stress level within is the warning level; where β is the warning ratio threshold;

[0045] If P d ≤α and P w ≤β, then determine the future time period of the ceramic chip during the packaging process The stress level within is the safety level.

[0046] Furthermore, the packaging process parameters include heating rate, cooling rate and pressure fluctuation range;

[0047] The dynamic adjustment of the packaging process parameters of the ceramic chip includes:

[0048] If the stress level is the warning level, the heating rate is adjusted from the standard heating rate value to the first heating rate value , the cooling rate is adjusted from the standard cooling rate value to the first cooling rate value , and the pressure fluctuation range is reduced from the standard pressure fluctuation range to the first pressure fluctuation range , where , , ;

[0049] If the stress level is the dangerous level, the heating rate is adjusted from the standard heating rate value to the second heating rate value , the cooling rate is adjusted from the standard cooling rate value to the second cooling rate value , and the pressure fluctuation range is reduced from the standard pressure fluctuation range to the second pressure fluctuation range , where , , .

[0050] A system for optimizing process parameters of ceramic chip packaging based on machine learning, which is used to implement the above-mentioned method for optimizing process parameters of ceramic chip packaging based on machine learning. The system includes:

[0051] Historical data acquisition module: used to collect the first historical data during the packaging of the target ceramic chip; preprocess the first historical data to extract the second historical data;

[0052] Chip stress prediction module: used to construct a chip stress prediction model according to the second historical data; collect the first real-time data during the ceramic chip packaging process, preprocess the first real-time data to obtain the second real-time data; obtain the chip stress prediction time series according to the second real-time data and the chip stress prediction model, and the chip stress prediction time series includes n chip stress prediction values within a future time period ; n is a positive integer;

[0053] Chip stress level determination module: used to determine the stress level of the ceramic chip within the future time period during the packaging process based on the chip stress prediction time series; the stress level includes a safety level, a warning level, and a dangerous level;

[0054] Parameter optimization module: if the stress level is the warning level or the dangerous level, dynamically adjust the packaging process parameters of the ceramic chip.

[0055] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0056] The method for optimizing the process parameters of ceramic chip packaging based on machine learning provided by the present invention can make full use of historical data to mine the internal relationship between environmental factors and chip performance parameters during the packaging process, and establish an accurate stress prediction model. Through the analysis of real-time collected data, this method can dynamically estimate the stress level of the chip in the future period of time, and discover potential high-stress risks in advance. When the predicted stress level exceeds the safe range, this method can automatically adjust key process parameters such as the heating rate, cooling rate, and pressure fluctuation amplitude of the packaging process according to the level of risk. By reducing thermal stress, reducing pressure fluctuations and other measures, the chip stress can be controlled at a reasonable level. This forward-looking risk warning and proactive process optimization strategy can maximize the avoidance of packaging stress failure, reduce scrap and rework losses, and comprehensively improve the yield and reliability level of ceramic chips. In addition, this method uses intelligent means of machine learning, can continuously learn and optimize the prediction model from new data to adapt to changes in process conditions, and has good self-adaptability and robustness. Therefore, the present invention can not only significantly improve the packaging effect of a single device, but also support the consistency control of product performance in mass production, which is of great significance for improving the level of ceramic chip packaging technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0058] Figure 1 It is a principle flowchart of a method for optimizing the process parameters of ceramic chip packaging based on machine learning in the present invention;

[0059] Figure 2 It is a method flowchart for preprocessing the first historical data and extracting the second historical data in a method for optimizing the process parameters of ceramic chip packaging based on machine learning in the present invention;

[0060] Figure 3 It is a method flowchart for performing feature engineering processing on the second historical data in a method for optimizing the process parameters of ceramic chip packaging based on machine learning in the present invention;

[0061] Figure 4 It is a method for determining the future time period of a ceramic chip during the packaging process based on the chip stress prediction correction time series in a method for optimizing the process parameters of ceramic chip packaging based on machine learning in the present invention Flow chart of method for stress level within

[0062] Figure 5 In an optimization method for ceramic chip packaging process parameters based on machine learning according to the present invention, according to P w and P d Judgment of the stress level of the ceramic chip during the packaging process in the future time period Flow chart of method for dangerous level;

[0063] Figure 6 Functional module diagram of an optimization system for ceramic chip packaging process parameters based on machine learning according to the present invention. Specific embodiments

[0064] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0065] Embodiment 1

[0066] Please refer to Figure 1 As shown, this embodiment provides an optimization method for ceramic chip packaging process parameters based on machine learning, including:

[0067] Step S1000, collecting first historical data of the target ceramic chip during the packaging process; preprocessing the first historical data to extract second historical data.

[0068] Further, step S1000 includes:

[0069] Step S1100, collecting first historical data of the target ceramic chip during the packaging process; the first historical data includes environmental state time series data and chip state time series data; the environmental state time series data includes environmental temperature time series data, environmental pressure time series data, and environmental humidity time series data; the chip state time series data includes chip stress time series data and chip temperature time series data;

[0070] Specifically, the environmental state time-series data reflects the dynamic changes of environmental factors during the ceramic chip packaging process, mainly including the data sequences of environmental temperature, environmental pressure, and environmental humidity changing over time. These environmental factors have an important impact on the stress state of the ceramic chip. For example, an increase in environmental temperature will lead to an increase in internal thermal stress of the chip, fluctuations in environmental pressure will cause uneven stress on the chip, and changes in environmental humidity will affect the hygroscopic expansion of the chip surface. Therefore, by collecting the environmental state time-series data, the external conditions of the ceramic chip can be comprehensively characterized.

[0071] The chip state time-series data, on the other hand, reflects the dynamic changes of the ceramic chip's own performance parameters, mainly including the data sequences of chip stress and chip temperature changing over time. Among them, chip stress is a key indicator for evaluating chip reliability, and excessive stress will lead to failure modes such as chip cracking and delamination. Chip temperature is closely related to the internal thermal stress of the chip, and uneven temperature distribution will exacerbate stress concentration. By collecting the chip state time-series data, the health state of the chip can be monitored in real time, and potential risks can be detected in a timely manner.

[0072] Aggregating the environmental state and chip state data to form the first historical data can establish the correlation between environmental factors and chip performance, providing a data basis for subsequent modeling and analysis. This time-series data collection method fully considers the dynamic characteristics of the packaging process, can truly reflect the evolution laws of various parameters, and has high data quality and reliability. By learning and mining the historical data, empirical laws can be summarized to guide process optimization, thereby improving the packaging quality of ceramic chips.

[0073] Step S1200: Preprocess the first historical data to extract the second historical data; the second historical data includes environmental state change rate time-series data and chip state change rate time-series data; the environmental state change rate time-series data includes environmental temperature change rate time-series data, environmental pressure change rate time-series data, and environmental humidity change rate time-series data; the chip state change rate time-series data includes chip stress change rate time-series data and chip temperature change rate time-series data;

[0074] Furthermore, as Figure 2 shown, step S1200 includes:

[0075] Step S1210: Differentiate the environmental temperature time-series data to obtain the environmental temperature change rate time-series data;

[0076] Step S1220: Differentiate the environmental pressure time-series data to obtain the environmental pressure change rate time-series data;

[0077] Step S1230: Differentiate the environmental humidity time-series data to obtain the environmental humidity change rate time-series data;

[0078] Step S1240: Differentiate the chip stress time series data to obtain the chip stress change rate time series data;

[0079] Step S1250: Differentiate the chip temperature time series data to obtain the chip temperature change rate time series data.

[0080] Specifically, preprocess the first historical data with the aim of extracting the implicit environmental-chip coupling effect information to prepare for subsequent feature engineering and modeling analysis. The core of the preprocessing is to transform the original state time series data into state change rate time series data. The state change rate reflects the change speed and intensity of the state parameter over time and can more sensitively capture the impact of environmental disturbances on chip performance.

[0081] The state change rate data can reflect the instantaneous change characteristics of environmental factors and chip performance, and explore the dynamic coupling law between the environment and the chip. Through the data conversion from state to change rate, the redundant information in the time series data can be reduced, highlighting the key change patterns and providing more targeted features for subsequent modeling analysis. At the same time, the change rate data also has scale invariance, which can eliminate the influence of different state parameter dimensions and facilitate comprehensive evaluation and comparative analysis.

[0082] This step realizes the conversion from state to change rate through a difference operator. Differencing is a commonly used numerical algorithm that approximately calculates the instantaneous change rate by dividing the difference between the state values at two adjacent times by the time interval. The difference operator has a simple form and high calculation efficiency, and can quickly complete the preprocessing of large-scale time series data. Perform differencing on the original state data sequences such as temperature, pressure, humidity, and stress respectively to obtain the corresponding change rate data sequences. These change rate data form the second historical data, providing a basis for subsequent feature engineering and modeling analysis.

[0083] It should be noted that the difference operator is sensitive to data noise and is prone to amplifying the influence of random errors. Therefore, before applying the difference operator, the original data can be smoothed and filtered to remove high-frequency noise. At the same time, in actual engineering, algorithms such as central differencing and high-order differencing can also be selected according to specific requirements to improve the accuracy of change rate calculation. The selection of the difference order needs to balance the calculation efficiency and information loss. Although a too high order can depict more complex change patterns, it may also introduce cumulative errors.

[0084] In summary, in this step, the data conversion from state to change rate is achieved through the difference operator, highlighting the instantaneous change characteristics of environmental factors and chip performance. This preprocessing method is simple and efficient, capable of effectively mining the environmental-chip coupling laws contained in the time-series data, laying a foundation for subsequent modeling and analysis. At the same time, the change rate data also has good scale invariance and noise resistance, facilitating comprehensive evaluation and comparative analysis. The second historical data extracted through preprocessing can comprehensively characterize the dynamic characteristics of the ceramic chip packaging process, providing reliable data support for process optimization.

[0085] Step S2000: Based on the second historical data, construct a chip stress prediction model; collect the first real-time data during the ceramic chip packaging process, preprocess the first real-time data to obtain the second real-time data; according to the second real-time data and the chip stress prediction model, obtain the chip stress prediction time series, where the chip stress prediction time series includes n chip stress prediction values within a future time period Based on the chip stress prediction time series, determine the stress level of the ceramic chip within the future time period The stress level includes a safety level, a warning level, and a danger level.

[0086] Further, step S2000 includes:

[0087] Step S2100: Based on the second historical data, construct a chip stress prediction model;

[0088] Further, step S2100 includes:

[0089] Step S2110: Perform feature engineering processing on the second historical data to obtain a historical comprehensive time series feature set; the historical comprehensive time series feature set includes historical environmental statistical time series features, historical chip statistical time series features, historical environmental energy time series features, historical chip energy time series features, and correlation time series features;

[0090] Further, as Figure 3 shown, step S2110 includes:

[0091] Step S2111: Extract the statistical features of the environmental state change rate time series data to generate historical environmental statistical time series features;

[0092] Step S2112: Extract the statistical features of the chip state change rate time series data to generate historical chip statistical time series features;

[0093] Step S2113: Extract the energy distribution of the environmental state change rate time series data on different time scales to obtain historical environmental energy time series features;

[0094] Step S2114: Extract the energy distribution of the chip state change rate time series data at different time scales to obtain the historical chip energy time series characteristics;

[0095] Step S2115: Calculate the cross - correlation coefficient between the environmental state change rate time series data and the chip state change rate time series data to obtain the associated time series characteristics.

[0096] Specifically, step S2110 performs multi - level feature extraction on the second historical data to form a feature set with rich information. The comprehensive time series feature set consists of five types of features, which depict the association patterns between environmental factors and chip performance from different perspectives.

[0097] The historical environmental statistical time series characteristics and the historical chip statistical time series characteristics reflect the overall distribution characteristics of the environmental state change rate and the chip state change rate. By calculating statistics such as the mean, variance, maximum value, minimum value, peak - to - peak value, etc. of each state change rate time series, the fluctuation levels of environmental factors and chip performance can be quantitatively evaluated. These statistical features depict the central tendency and dispersion degree of the state change rate data, which helps to judge the stability of environmental conditions and chip states. In addition, higher - order moments such as skewness and kurtosis of the state change rate can also be calculated to evaluate the skewness and sharpness of the data distribution, further refining the description of environmental perturbations and chip responses. The historical chip statistical time series characteristics include the historical chip temperature statistical time series characteristics and the historical chip stress statistical time series characteristics; the historical chip temperature statistical time series characteristics are extracted from the chip temperature change rate time series data; the historical chip stress statistical time series characteristics are extracted from the chip stress change rate time series data.

[0098] The historical environmental energy time series characteristics and historical chip energy time series characteristics analyze the energy distribution pattern of the state change rate data from a time-frequency perspective. Using time-frequency analysis methods such as short-time Fourier transform and wavelet transform, the energy intensity of the state change rate at different time and frequency scales can be extracted. Although the environmental state change rate and chip state change rate data here differ from the signal form used in traditional signal analysis, in essence, any time-varying data series can be considered a generalized signal. In the context of the present invention, the temporal variations of environmental state change rates (such as the ambient temperature change rate, the ambient pressure change rate, etc.) and chip state change rates (such as the chip stress change rate, the chip temperature change rate) also contain rich information. These variations are closely related to the physical phenomena in the ceramic chip packaging process. Taking the ambient temperature change rate as an example, during the ceramic chip packaging process, when the heating or cooling system of the packaging equipment is operating, the ambient temperature change rate will change. This change exhibits a certain fluctuation pattern in the time series, just like the fluctuation of the signal. From a physical perspective, these fluctuations in rate of change are caused by various factors in the packaging process, such as the adjustment of heating power and changes in heat dissipation conditions. Their changing patterns reflect the dynamic characteristics of the packaging environment.

[0099] The core principle of time-frequency analysis methods such as the short-time Fourier transform and wavelet transform is to decompose time series data into two dimensions: time and frequency. For environmental and chip state change rate data, these methods can decompose complex variations into components at different time and frequency scales. For example, the wavelet transform offers multi-resolution analysis capabilities, enabling observation of data at different scales. At smaller scales, it can capture rapid fluctuations in the rate of change data, which may reflect sudden environmental changes during the packaging process or microscopic physical changes within the chip. At larger scales, it can reveal overall trends in the rate of change data, such as the general trend of the ambient temperature change rate throughout the entire packaging cycle. By calculating the energy of these decomposed components, the energy intensity at different time and frequency scales can be determined. For example, if the ambient temperature change rate exhibits a high energy intensity within a specific frequency range, this indicates that the ambient temperature variation is significant at the time scale corresponding to that frequency, and this significant variation may have a significant impact on chip stress. By analyzing the energy distribution at different frequency scales, it is possible to identify the frequency components that have the greatest impact on environmental changes and chip performance—those critical frequency components. These energy signatures reveal the multi-scale variations in environmental factors and chip performance, reflecting the strength distribution of the disturbance signal across different frequency bands. By analyzing the energy time series, we can identify the key frequency components of environmental changes and determine the dominant time scale of environmental-chip coupling, providing a targeted basis for optimizing process parameters.

[0100] The correlation time series features measure the similarity between two types of time series data by calculating the cross - correlation coefficient of the environmental state change rate and the chip state change rate. Cross - correlation analysis can reveal the delay effect between environmental factor changes and chip performance responses, that is, the dynamic response law of chip state to environmental perturbations. By calculating the cross - correlation coefficients at different time lags, the strength of the causal relationship and the action time delay between the environment and the chip can be quantified. The cross - correlation features help to understand the multi - physical - field coupling mechanism during the packaging process and consider the cumulative effect and lag impact of environmental factor changes when optimizing process parameters.

[0101] It should be noted that although the historical environmental statistical time series features, historical chip statistical time series features, and correlation time series features are not continuous time series data in the traditional sense, they are closely related to time series. The historical environmental statistical time series features and historical chip statistical time series features are obtained by statistically calculating the time series data of environmental and chip state change rates. These statistical values reflect the overall trend and fluctuation of environmental factors and chip performance changes over a period of time. For example, the mean value can reflect the average level of environmental temperature or chip stress changes in a certain stage, and the variance can reflect its fluctuation degree. This statistical information of historical data actually contains features in the time dimension. It is the result of the accumulation of changes in time series data at different moments and can provide information about the long - term change trends of environmental and chip states for the LSTM model, helping the model better grasp the overall law of the environment - chip coupling effect. The correlation time series features measure the temporal correlation and delay effect between environmental and chip state changes by calculating the cross - correlation coefficients between different time series data. It reveals the temporal relationship between environmental factor changes and chip performance responses from another angle and provides dynamic time information about the environment - chip coupling effect for the model. Although these features are not in the form of simple time series, the time - related information they carry is crucial for the LSTM model to understand the changes in the environment - chip coupling system in the time dimension and is an indispensable part of building an accurate prediction model.

[0102] In summary, step S2110 adopts a multi - level feature engineering method, starting from aspects such as statistical features, energy features, and correlation features, to deeply explore the internal relationship between environmental factors and chip performance, forming a feature set rich in information. These time series features provide comprehensive prior knowledge for the chip stress prediction model, helping to improve the generalization ability and prediction accuracy of the model. The modeling analysis based on the comprehensive time series feature set can reveal the multi - scale dynamic laws of the environment - chip coupling effect during the packaging process, provide a quantitative basis for process parameter optimization, and improve the reliability level of ceramic chips.

[0103] The calculation of the cross - correlation coefficient between the environmental state change rate time series data and the chip state change rate time series data includes:

[0104] Let the time-series data of the environmental state change rate , where represents the time-series data of the change rate of the th environmental state parameter (such as environmental temperature, pressure, humidity, etc.). The time-series data of the chip state change rate , where represents the time-series data of the change rate of the th chip state parameter (such as chip stress, temperature, etc.).

[0105] To analyze the correlation strength and lag effect between the th environmental state parameter and the th chip state parameter , the cross-correlation coefficient between them at time delay [[ID=J27]]is defined as:

[0106]

[0107] where:

[0108] represents the cross-correlation coefficient between the th environmental state parameter and the th chip state parameter at time delay .

[0109] respectively represent and means.

[0110] represents the total length of the time series.

[0111] represents the time index of the time series, .

[0112] represents the time delay, and the value range is .

[0113] is the time-delay penalty coefficient, which can be set according to experience to control the attenuation speed of the cross-correlation coefficient with time delay. It can be set according to the historical experience of the packaging process or optimized through the validation set to obtain the best value.

[0114] This formula comprehensively considers the influence of two factors on the cross-correlation coefficient:

[0115] (1) The estimation bias caused by the limited length of the time series: Multiply by for correction.

[0116] (2) The correlation decays naturally as the time delay increases: multiply by to impose a penalty.

[0117] Cross-correlation coefficient measures, at a time delay of the correlation strength between the time series data of the environmental state change rate and the time series data of the chip state change rate . Its value range is , and the larger the absolute value, the stronger the correlation:

[0118] When , it means a positive correlation with a lag of time units, that is, an increase / decrease in often causes an increase / decrease in afterwards.

[0119] When , it means a negative correlation with a lag of time units, that is, an increase / decrease in often causes a decrease / increase in afterwards.

[0120] When is close to 0, it means is uncorrelated with .

[0121] This cross-correlation coefficient formula characterizes the dynamic relationship and lag effect between the environmental state change rate and the chip state change rate: it helps to understand how environmental disturbances affect chip stress. The cross-correlation coefficient shows a trend of first increasing and then decreasing with the time delay: the peak position can indicate the characteristic time scale of the influence of the environmental change rate on the chip change rate. By setting the time delay penalty coefficient , the decay rate of the cross-correlation coefficient with the time delay can be flexibly controlled to match the physical mechanism. The correction term can better eliminate the bias in cross-correlation estimation caused by the limited time series length.

[0122] This cross-correlation coefficient formula can quantitatively evaluate the time characteristics of the environment-chip coupling effect, provide key correlation features for constructing a more accurate chip stress prediction model, and is of great significance for guiding the optimization of packaging process parameters. Cross-correlation analysis helps process engineers understand the action paths and effect magnitudes of various environmental factors on chip stress formation, providing a theoretical basis for active regulation and suppression of chip stress. The cross-correlation coefficient formula can quantitatively evaluate the time characteristics of the environment-chip coupling effect, provide key correlation features for constructing a more accurate chip stress prediction model, and is of great significance for guiding the optimization of packaging process parameters. Cross-correlation analysis helps process engineers understand the action paths and effect magnitudes of various environmental factors on chip stress formation, providing a theoretical basis for active regulation and suppression of chip stress.

[0123] Step S2120: construct a chip stress prediction model based on the historical comprehensive timing feature set.

[0124] Specifically, the chip stress prediction model uses the Long Short-Term Memory (LSTM) algorithm to effectively model long-term dependencies in time series data. LSTM is a specialized recurrent neural network specifically designed for processing and predicting time series data. Compared to traditional feedforward neural networks, LSTM is able to learn long-term dependencies in data and, in chip stress prediction tasks, can capture the complex nonlinear relationship between environmental changes and chip stress.

[0125] The LSTM model consists of four main components: an input gate, a forget gate, an output gate, and a memory unit. Each component performs its own function and works in tandem. The input gate controls the intensity with which new environmental features enter the memory unit, determining the model's sensitivity to new information. The forget gate controls the intensity with which old information is forgotten in the memory unit, determining the speed at which the model forgets historical information. The memory unit stores the long-term memory representation of the environment-chip coupling extracted by the LSTM model, embodying causal relationships and correlation patterns across time.

[0126] During the model training phase, the LSTM model takes as input the historical environmental statistical time series features, historical chip temperature statistical time series features, historical chip energy time series features, historical environmental energy time series features, and related time series features from the comprehensive time series feature set. It uses the historical chip stress statistical time series features at the corresponding moment as a supervisory signal and optimizes model parameters using a backpropagation algorithm. By minimizing the error function between the predicted and true values, the LSTM model gradually learns the inherent laws of the environment-chip coupling. The trained LSTM model takes as input the environmental state change rate features at the current moment and outputs a series of predicted chip stress change rates for a period of time in the future.

[0127] When the historical chip stress statistical time series features are used as supervisory signals for LSTM model training, a loss function is constructed based on these statistical features to guide model learning. The predicted output of the LSTM model is compared point by point with the historical chip stress statistical time series features. Taking the mean value of the historical chip stress statistical time series features as an example, assuming that at a certain moment, the chip stress change rate predicted by the LSTM model is converted to the predicted stress value , and the corresponding mean value in the historical chip stress statistical timing characteristics is , the common mean square error (MSE) loss function can be used to measure the difference between the two, that is, ,in is the number of training samples, is the index of the training sample. Similarly, for other statistical features such as variance, maximum value, minimum value, etc., loss functions can be constructed in a similar manner. For example, the loss function constructed for variance can be , where is the value related to the stress variance predicted by the model, is the variance value in the historical chip stress statistical time series features. By weighted summing multiple loss functions constructed based on different statistical features, the total loss function is obtained, where is the weight of the th loss function, 1 ≤ ≤ z, which can be adjusted according to the actual situation. During the training process of the LSTM model, using the backpropagation algorithm, this total loss function is minimized to update the weights and biases of the model. For example, when is large, it indicates that the difference between the model prediction value and the historical chip stress statistical time series features is large. The backpropagation algorithm will adjust the model parameters to make the prediction value closer to the true statistical feature value, so that the model gradually learns the internal law of the environment-chip coupling effect.

[0128] The historical environmental energy time series features are obtained through time-frequency analysis methods, which reflect the energy distribution of the environmental state change rate at different time scales and frequency scales. Although the frequency sequence of the change rate is different from the sequence form of the change rate itself, it contains rich information. During the training process, the LSTM model does not directly predict the future change rate based on the frequency sequence, but learns the environmental change pattern represented by the frequency sequence. For example, when there is an energy fluctuation in the environmental temperature change rate within a certain specific frequency range, it may indicate that the environmental temperature is about to change significantly, which in turn affects the chip stress. The LSTM model can capture the correlation between this frequency energy distribution and the subsequent environmental state change, as well as the connection between the environmental change and the chip stress change. By learning such frequency features in a large amount of historical data, the model can understand the response law of the chip stress under different environmental energy frequency patterns. This learning process is not a simple linear mapping, but uses the powerful non-linear learning ability of the LSTM model to uncover the complex causal relationship between the environmental energy frequency features and the future chip stress change rate. Theoretically speaking, according to the principles of time-frequency analysis such as Fourier transform and wavelet transform, frequency information is a deep-level characterization of signal changes, containing the change trends of the signal at different time scales. The LSTM model can learn the trend information contained in these frequency features, so as to predict the future chip stress change rate.

[0129] The historical chip energy time-series characteristics also contain the energy distribution information of the chip state change rate in the time-frequency domain. During the chip packaging process, the physical changes inside the chip will exhibit energy fluctuations at different frequencies. For example, when stress concentration or structural changes occur inside the chip, energy changes will occur within a specific frequency range. These frequency characteristics are closely related to the development trend of chip stress. When the LSTM model is trained, by learning the historical chip energy time-series characteristics, it can identify the patterns of energy changes inside the chip and the relationships between these patterns and chip stress changes. Although the frequency sequence is different from the direct change rate sequence, it provides key information about the physical processes inside the chip. From actual cases, it is found that when analyzing the data of a large number of ceramic chip packaging processes, when the energy in a certain frequency band of the historical chip energy time-series characteristics continuously rises, the chip stress often shows corresponding changes at subsequent moments. The LSTM model can learn this empirical pattern, so as to effectively predict the future chip stress change rate using the historical chip energy time-series characteristics. This is not simply to directly obtain the future change rate from the frequency sequence, but through the model's learning and induction of the relationship between frequency characteristics and chip stress changes in a large amount of historical data.

[0130] The LSTM model has strong learning ability and can process various types of input data. For historical environmental statistical time-series characteristics, historical chip temperature statistical time-series characteristics, correlation time-series characteristics, etc., the LSTM model does not simply treat them as isolated data independent of time. Taking the historical environmental statistical time-series characteristics as an example, during the training process of the model, these statistical values will be combined with other time-related input features (such as historical environmental energy time-series characteristics) to learn the relationship between environmental factors and chip stress from multiple dimensions. The time cumulative information contained in these statistical features will complement other time-series features, helping the model capture the complex time-dependent relationships in the environment-chip coupling effect. The correlation time-series characteristics provide dynamic time information for the model by reflecting the time correlation of environmental and chip state changes. The LSTM model can utilize this information to understand how environmental changes affect chip stress at different time points, so as to better learn the internal laws of the environment-chip coupling effect. In this way, the LSTM model organically integrates these seemingly non-time-series features with time-series features, so as to accurately predict future chip stress changes. The trained LSTM model takes the environmental state change rate characteristics at the current moment as input and outputs the predicted time series of chip stress within a future period of time.

[0131] Step S2100 aims to establish a machine learning model that can predict future chip stress changes by utilizing the coupling relationship between environmental factors and chip state contained in the second historical data. The key to constructing the prediction model lies in two aspects: feature engineering and algorithm selection.

[0132] Feature engineering refers to the process of extracting key features that have a significant impact on the prediction target from the original data and quantitatively representing these features. Through feature engineering, complex time-series data can be transformed into structured feature vectors, providing suitable inputs for model training. In this embodiment, a multi-level and multi-angle feature extraction strategy is adopted to characterize the environment-chip coupling effect from three dimensions: statistical features, energy features, and correlation features, forming a feature set rich in information. Such a comprehensive feature representation helps to capture the influence law of environmental factor changes on chip performance, providing sufficient prior knowledge for subsequent modeling analysis.

[0133] In terms of algorithm selection, this embodiment uses the long short-term memory network (LSTM) as the core structure of the chip stress prediction model. Using LSTM for chip stress modeling and prediction can capture the long-term dependence relationships in time-series data, characterize the lag effect and cumulative impact between environmental factors and chip stress; has long-term memory ability, can learn the physical mechanism behind the environment-chip coupling effect, and form an internal representation of knowledge; has a strong ability to characterize the change trend and fluctuation pattern of time-series data, and can predict the dynamic changes of chip stress; the model has strong generalization ability, can adapt to different chip types and packaging processes, and has good migration and scalability.

[0134] Generally speaking, step S2100 transforms the original time-series data into a chip stress model with prediction ability through the methods of feature engineering and LSTM modeling. This data-driven modeling paradigm makes full use of the statistical laws and causal mechanisms contained in historical data and can overcome the limitations of traditional physical models under complex working conditions. The chip stress prediction based on machine learning provides new ideas and means for packaging process optimization and is expected to significantly improve the reliability and yield levels of ceramic chips.

[0135] Step S2200: Collect the first real-time data during the ceramic chip packaging process, and preprocess the first real-time data to obtain the second real-time data;

[0136] The first real-time data includes real-time environmental state data and real-time chip state data;

[0137] The real-time environmental state data includes real-time environmental temperature sequence data, real-time environmental pressure time-series data, and real-time environmental humidity time-series data; the real-time chip state time-series data includes real-time chip stress time-series data and real-time chip temperature time-series data;

[0138] The second real-time data includes real-time environmental state change rate time series data and real-time chip state change rate time series data; the real-time environmental state change rate time series data includes real-time environmental temperature change rate time series data, real-time environmental pressure change rate time series data, and real-time environmental humidity change rate time series data; the real-time chip state change rate time series data includes real-time chip stress change rate time series data and real-time chip temperature change rate time series data;

[0139] Specifically, step S2200 is essentially the application of the historical data acquisition and preprocessing method in step S1000 in a real-time scenario. The two are highly consistent in terms of data types, preprocessing algorithms, etc. The difference is that step S2200 processes real-time data streams rather than historical data sets.

[0140] The first real-time data includes two parts: real-time environmental state data and real-time chip state data, which have the same composition as the historical data. Among them, the real-time environmental state data includes time series data of real-time environmental temperature, pressure, and humidity, reflecting the current state and instantaneous changes of the environmental conditions where the chip is located. The real-time chip state data includes time series data of real-time chip stress and temperature, reflecting the current level and dynamic response of the chip performance parameters. The acquisition of the first real-time data can be achieved by deploying a sensor system on the packaging device, and the collected data is aggregated to the data processing platform through a real-time transmission channel for preprocessing such as normalization and synchronization.

[0141] The preprocessing process of the first real-time data is basically the same as that of step S1000, including performing differential operations on various state data to obtain the corresponding state change rate data. The preprocessed second real-time data includes real-time environmental state change rate time series data and real-time chip state change rate time series data, which have the same structure and semantics as the second historical data. It should be noted that real-time data preprocessing has higher requirements for computing timeliness and resource consumption, and an efficient streaming computing framework needs to be designed to balance the time consumption of data processing and model inference to achieve real-time prediction of chip stress.

[0142] Step S2200 is the data basis for realizing real-time prediction of chip stress. Through an efficient and stable real-time data acquisition and preprocessing system, continuous feature inputs can be provided for the LSTM prediction model, ensuring the real-time and continuity of the prediction results. This is a key link in constructing a closed-loop feedback intelligent packaging optimization system and is of great significance for improving chip production efficiency and quality.

[0143] Step S2300, according to the second real-time data and the chip stress prediction model, obtain the chip stress prediction time series [(t1,σ1),(t2,σ2),…,(t n ,σ n )]; the chip stress prediction time series includes the future time period The predicted values of the stresses of n chips within; n is a positive integer; t n is the nth moment within a future time period ; σ n is the predicted value of the chip stress at the nth moment within a future time period .

[0144] Specifically, S2300 is the online inference process of the chip stress prediction model. By receiving the second real-time data output by step S2200 in real time, it drives the LSTM model to perform continuous rolling prediction.

[0145] In specific implementation, first, the feature engineering method in step S2100 is adopted to extract features from the second real-time data, and then the prediction time series is generated by means of a sliding time window. Assume that the current moment is ', the time span of the chip stress prediction time series is the future , and the time granularity is , then the length of the prediction time series can be expressed as:

[0146]

[0147] where represents the integer operation.

[0148] At moment t', taking the feature extraction result of the second real-time data as the input of the LSTM model, the chip stress prediction time series [(t1,σ1),(t2,σ2),…,(t n ,σ n )] is obtained; as time goes by, the prediction window slides forward continuously, and a prediction time series with a future time span of Δt is generated at each time step, realizing the real-time outlook of the chip stress evolution trend. By adjusting the parameters Δt and δt of the prediction time series, the future time range and prediction granularity of the prediction can be flexibly set to meet different process optimization requirements.

[0149] The generation of the chip stress prediction time series is an important basis for chip stress early warning and active control. By analyzing the prediction time series, the signs of abnormal fluctuations in chip stress can be discovered in advance, and potential failure risks can be predicted. In addition, the prediction time series can also be used as the input for the dynamic optimization of packaging process parameters. By establishing the mapping relationship between the predicted stress values and process parameters through machine learning algorithms, the control variables of the packaging equipment are adaptively adjusted to achieve the closed-loop control of the chip stress level, and the effects of suppressing abnormal stress fluctuations and balancing stress distribution are achieved.

[0150] In summary, based on the LSTM prediction model and real-time preprocessed data, step S2300 generates a chip stress prediction time series within a certain time range, revealing the dynamic evolution law of chip stress. The prediction time series, as a quantitative description of the future chip stress change trend, is an important starting point for realizing active warning, intelligent control, and dynamic optimization. Through measures such as real-time warning and feedback control, the impact of environmental stress on chip performance and reliability can be minimized, and the ceramic packaging process level can be improved. The prediction-driven intelligent packaging optimization mode provides a subversive alternative to the traditional passive process adjustment, which is of great significance for cost reduction, efficiency improvement, quality improvement, and speed increase, representing the future development direction of advanced packaging technology.

[0151] Step S2400, based on the chip stress prediction time series, determines the stress level of the ceramic chip in the future time period during the packaging process.

[0152] Furthermore, step S2400 includes:

[0153] Step S2410, calculate the mean μ σ and standard deviation σ σ of the chip stress prediction time series;

[0154] Step S2420, calculate the structural mutual information PSI i of the predicted chip stress value σ i at the i-th future moment in the chip stress prediction time series; when PSI i ≥λ', take the mean μ σ as the predicted chip stress correction value σ' i at the i-th future moment, that is, σ' i =μ σ ; when PSI i <λ', then σ' i =(1 - w)μ σ +w×σ i-1 ; σ i-1 is the predicted chip stress value at the (i - 1)-th future moment, w is the weight of σ i-1 , 2≤i≤n, and λ' is the structural mutual information threshold;

[0155] Step S2430, form the chip stress prediction correction time series [(t1,σ'1),(t2,σ'2),…,(t i ,σ' n ,σ' n )] from the predicted chip stress correction values σ' n at the n-th future moment; where σ'

[0156] Step S2440: Based on the chip stress prediction and timing correction, determine the stress level of the ceramic chip during the packaging process in the future time period. within.

[0157] Furthermore, as Figure 4 shown, Step S2440 includes:

[0158] Step S2441: If σ w ≤σ' i <σ s , then the stress level of the ceramic chip at the i-th future moment during the packaging process is the safe level, where σ s is the upper safety limit and σ w is the upper warning limit;

[0159] Step S2442: If σ d ≤σ' i <σ w , then the stress level of the ceramic chip at the i-th future moment during the packaging process is the warning level, where σ d is the upper danger limit, σ s >σ w >σ d ;

[0160] Step S2443: If σ' i <σ d , then the stress level of the ceramic chip at the i-th future moment during the packaging process is the danger level;

[0161] Step S2444: Traverse all the chip stress prediction and correction values in the chip stress prediction and correction timing sequence, and respectively count the number of moments n2 with the stress level of the safe level, the number of moments n3 with the stress level of the warning level, and the number of moments n4 with the stress level of the danger level within the future time period ; n2 + n3 + n4 = n;

[0162] Step S2445: Set the weight coefficient w s for the safe level moments, the weight coefficient w w for the warning level moments, and the weight coefficient w d for the danger level moments. According to n2, n3, n4, w s , w w and w d , calculate the weighted proportion P of the warning level moments and the weighted proportion P w of the danger level moments within the future time period d ;

[0163]

[0164]

[0165] Step S2446, according to P w and P d determine that the stress level of the ceramic chip during the packaging process in the future time period is a dangerous level.

[0166] Furthermore, as Figure 5 shown, step S2446 includes:

[0167] Step S24461, if P d > α, then determine that the stress level of the ceramic chip during the packaging process in the future time period is a dangerous level; where α is the dangerous proportion threshold;

[0168] Step S24462, if P d ≤ α and P w > β, then determine that the stress level of the ceramic chip during the packaging process in the future time period is a warning level; where β is the warning proportion threshold;

[0169] Step S24463, if P d ≤ α and P w ≤ β, then determine that the stress level of the ceramic chip during the packaging process in the future time period is a safe level.

[0170] Specifically, step S2400 is based on the chip stress prediction time series data, comprehensively considers the stress states at different future times, and finally determines the overall stress level of the ceramic chip during the packaging process in the future time period . The core of this step is to conduct an overall assessment of the future stress change trend, judge the stress risk level of the chip in a future period of time, and provide a decision-making basis for the subsequent optimization of process parameters.

[0171] Step S2410 calculates the mean μ σ and the standard deviation σ σ of the chip stress prediction time series, which characterizes the overall distribution characteristics of the future stress level. The mean μ σ reflects the average level of the future stress, while the standard deviation σ σ measures the fluctuation range of the future stress relative to the mean. Through these two statistics, the central tendency and dispersion degree of the stress in a future period of time can be quantitatively evaluated, and the stress state of the chip can be initially judged.

[0172] Step S2420 introduces the Permutation Structural Information (PSI) metric to measure the structural similarity between the stress prediction values at each future time point and the historical data. The permutation structural information originates from the field of information theory and measures the structural correlation between two sets of data through permutation techniques and mutual information theory. The larger the PSI value, the closer the prediction value at that time is to the change pattern of the historical data, and the higher the prediction credibility. By setting the threshold of permutation structural information λ', the reliability of each prediction value can be judged: when PSI ≥ λ', the overall mean μ σ is directly used as the predicted correction value σ' at this time point, ignoring local fluctuations; when PSI < λ', the local predicted value σ<s i and the overall mean μ σ， are linearly weighted to obtain a compromise predicted correction value σ'. The weight w reflects the importance of local information and is generally taken as an empirical value. This adaptive correction strategy can take into account both the overall trend and local characteristics, improving the smoothness and accuracy of the predicted value.

[0173] Step S2430 generates a chip stress prediction correction time series, which consists of the predicted correction value σ' at each future time point and the corresponding timestamp t i . The correction time series reflects the dynamic change trend of the future stress level over time and provides a time series data basis for subsequent stress level determination.

[0174] Step S2440 is the core step of stress level determination; steps S2441 - S2443 judge the stress state of the ceramic chip at a certain future time point. By setting three stress thresholds σ s , σ w , σ d , the chip stress prediction correction value σ' i is divided into three levels: safe, warning, and dangerous. σ s is the safety upper limit, σ w is the warning upper limit, and σ d is the danger upper limit. Setting multiple stress thresholds can achieve a fine-grained division of the chip stress state. Discretizing continuous stress values into a finite number of levels is easier for process personnel to intuitively understand. At the same time, different levels correspond to different risk levels, providing a clear optimization direction for subsequent process parameter adjustment. For example, when it is predicted that the stress will enter the dangerous range at a certain future time point, measures need to be taken in a timely manner to lower the stress level during the packaging process to avoid chip cracking and failure.

[0175] Steps S2444 - S2446 further evaluate the comprehensive risk level within the entire future time period based on the single-time risk judgment. Step S2444 counts The number of moments n2, n3, and n4 for each of the three stress levels reflects the overall distribution of the chip stress state during this time period. However, the degrees of influence of different risk levels on chip reliability vary, and only considering the number of moments cannot accurately evaluate the comprehensive risk. Therefore, step S2445 introduces the weight coefficients w s 、w w and w d , which respectively represent the risk weights for the safe, warning, and dangerous levels. Generally, the values are taken to satisfy w s <w w <w d . Multiplying the number of moments for each level by the corresponding weight can obtain the weighted number of moments, and further calculate the weighted proportions P w 、P d of the warning and dangerous level moments. The weighted proportions P w 、P d comprehensively consider the duration and risk degree of each level and can more comprehensively reflect the overall risk level in the future time period.

[0176] Finally, in step S2446, the weighted proportions P w 、P d are compared with the preset thresholds α and β to obtain the final comprehensive risk level. By setting the two thresholds α and β, the strictness of risk judgment can be flexibly controlled. The smaller the threshold, the easier it is to judge as a high-risk level, and the more sensitive the early warning will be; conversely, the larger the threshold, the looser the risk judgment. For example, α = 0.2 and β = 0.5 can be set, that is, when the dangerous proportion exceeds 20% or the warning proportion exceeds 50%, it is necessary to be vigilant, closely monitor the chip state, and timely optimize the packaging process parameters.

[0177] The above steps convert the predicted stress data of the timing chip into intuitive risk level information, which is convenient for process personnel to quickly understand the changing trend of the future chip stress state. By weighted calculation, the influence differences of different risk levels are considered, and risk judgment thresholds are set, enabling multi-level early warning of the chip state, thereby guiding the active control and optimization adjustment of the packaging process. Compared with the stress value at a single moment, the comprehensive risk level in the future time period can better reflect the overall effect of process parameter settings over a period of time. Process personnel can formulate targeted optimization strategies with reference to the comprehensive level and make a trade-off between reliability and cost.

[0178] This machine learning-based stress prediction method provides a new idea for evaluating the reliability of chips. Traditional methods often can only detect problems after chip failure, while the prediction model can prospectively predict the health status of chips, thus gaining more time windows for preventive maintenance. Through timely warning and dynamic optimization, the out-of-control rise of chip stress can be maximally suppressed, thereby reducing the failure rate of ceramic chips and improving the yield rate. The stress prediction method combines big data analysis with process experience, overcoming the subjectivity and uncertainty of empirical judgment, and driving the intelligent upgrade of traditional packaging processes with data. This is of great significance for building an intelligent chip manufacturing process and realizing flexible quality control.

[0179] In summary, steps S2441 - S2446 construct a multi-level risk warning mechanism by setting parameters such as stress thresholds, weighted ratios, and risk criteria. This method makes full use of time series prediction data to dynamically evaluate the chip stress state from both time and space dimensions, being able to judge the instantaneous risk at a single moment and evaluate the comprehensive risk level over a period of time. The quantitative risk information facilitates packaging process personnel to intuitively understand the chip state and grasp the timing and direction of parameter adjustment and optimization. Through timely warning and active control, this machine learning method can guide the prevention of stress out-of-control, thereby improving the reliability and yield rate of ceramic chips. The multi-level risk warning mechanism and expert experience complement each other, providing a new idea for intelligent chip manufacturing and dynamic quality control.

[0180] Steps S24461 - S24463 further refine the determination rules for the comprehensive risk level. This determination rule follows the basic principle of "giving priority to short-term risks and taking into account long-term risks", and focuses on the dangerous state in the future time period. When the weighted ratio P of the dangerous state d exceeds the preset threshold α, the comprehensive risk level within this time period is directly determined to be dangerous, and in this case, the situation of the warning state does not need to be considered. This is because the dangerous state corresponds to a high risk of chip stress out-of-control, and once it occurs, it often leads to irreparable losses. To ensure chip reliability, the probability of the occurrence of the dangerous state must be controlled at a low level. The setting of the threshold α needs to balance the timeliness of risk prevention and control and the cost investment, and factors such as the yield rate requirements of the process and quality cost accounting can be referred to. Generally, it can take 0.1 - 0.2.

[0181] When the dangerous ratio P d does not exceed α, the weighted ratio P of the warning state is further considered w . If P wIf the preset threshold β is exceeded, the overall risk level for that period is determined to be a warning. This indicates that while the critical risk is under control, the chip stress level remains high, requiring close monitoring of its dynamic changes so that timely optimization measures can be taken. The threshold β can be set slightly higher than α, such as 0.3-0.5, to avoid triggering warnings too frequently while also leaving room for stress runaway.

[0182] When the risk ratio P d and warning ratio P w If neither threshold is exceeded, the chip's stress state is generally controllable for the foreseeable future, and the overall risk level is considered safe. At this point, the packaging process is generally stable, stress levels are acceptable, and the short-term impact on yield is minimal. However, it is still necessary to track and monitor long-term stress trends, assess the rationality of process parameters through big data analysis, and implement preventive optimization as necessary.

[0183] The above judgment rules form a hierarchical early warning system, ranging from strict to relaxed. By setting the danger threshold α and warning threshold β, risk control intensity can be dynamically adjusted. When the risk of chip stress runaway is high, the α and β values can be appropriately lowered to trigger an early warning based on sensitive parameters. When process levels are stable, the thresholds can be appropriately raised to avoid excessive production intervention. Optimizing threshold settings can be verified using historical data and simulations to strike a balance between risk control and production efficiency.

[0184] In summary, steps S24461-S24463 provide a comprehensive risk assessment method based on weighted proportion thresholds. This method fully considers the time proportion and severity of different risk levels, forming a multi-level early warning mechanism. By properly setting danger and warning thresholds, risk management efforts can be dynamically adjusted according to process requirements, optimizing the balance between chip reliability and production efficiency. Compared with a single stress threshold, this method can more comprehensively assess the overall risk level over a period of time, providing a basis for dynamic optimization of packaging process parameters. Process personnel can refer to the comprehensive risk level and take timely preventive or corrective measures to avoid the accumulation and deterioration of undesirable stress conditions. Scientific threshold setting requires determination through data analysis and simulation experiments, and dynamic adjustment based on expert experience. Risk warning methods based on big data and machine learning inject intelligence into traditional chip manufacturing processes, providing a new means of actively controlling stress runaway, which is of great significance for improving the reliability and yield of ceramic chips.

[0185] Exemplarily, it is assumed that through steps S2420 - S2430, stress prediction correction values once every 10 seconds within the next 10 minutes are obtained. After the statistics in steps S2441 - S2444, within the next 10 hours, 20% of the time is in the dangerous level, 30% of the time is in the warning level, and 50% of the time is in the safe level. The weight coefficients for the three levels of dangerous, warning, and safe are set to 5, 3, and 1 respectively, representing the degree of risk. The threshold α for the dangerous proportion is set to 15%, and the threshold β for the warning proportion is set to 25%. Calculate the weighted proportion. The dangerous proportion is 20%×5 / (20%×5 + 30%×3 + 50%×1) = 38.5% > α. Therefore, according to step S2446, it is determined that the stress level of the chip packaging process within the next 10 minutes is the dangerous level, and the process parameters need to be adjusted in a timely manner to reduce the risk.

[0186] In summary, step S2400 adopts a method combining adaptive time - series prediction and multi - level risk assessment, fully considering the characteristics of time - series correlation, local volatility, uncertainty, etc. of stress data, comprehensively analyzing the future stress changes in two dimensions of time and risk, and finally giving a stress level warning for the chip packaging process within a future period of time. This evaluation result is intuitive and reliable, can reflect the future health status of the chip, and has guiding significance for process optimization. By timely detecting the dangerous level, key parameters such as temperature and pressure can be adjusted in advance to avoid quality problems caused by excessive chip stress, thereby improving the yield and reliability of ceramic chips. In addition, when the future stress level is a warning, the production status also needs to be closely monitored, and the process should be optimized in a timely manner to control the risk within an acceptable range. When the future stress level is safe, the current process can be maintained to ensure the stability of production. This risk - graded control mode is conducive to balancing efficiency and quality, maximizing the effect of machine - learning prediction, and providing a scientific basis for intelligent process optimization decisions.

[0187] Step S3000, if the stress level is the warning level or the dangerous level, then dynamically adjust the packaging process parameters of the ceramic chip.

[0188] Furthermore, step S3000 includes:

[0189] Step S3100, if the stress level is the warning level or the dangerous level, then dynamically adjust the packaging process parameters of the ceramic chip; the packaging process parameters include the heating rate, the cooling rate, and the pressure fluctuation range;

[0190] Furthermore, step S3100 includes:

[0191] Step S3110, if the stress level is the warning level, then adjust the heating rate from the standard heating rate value to the first heating rate value , adjust the cooling rate from the standard cooling rate value to the first cooling rate value , and narrow the pressure fluctuation range from the standard pressure fluctuation range to the first pressure fluctuation range , where , , ;

[0192] Step S3120, if the stress level is the dangerous level, then adjust the heating rate from the standard heating rate value to the second heating rate value , adjust the cooling rate from the standard cooling rate value to the second cooling rate value , and narrow the pressure fluctuation range from the standard pressure fluctuation range to the second pressure fluctuation range , where , , .

[0193] Specifically, step S3100 aims to dynamically adjust the key process parameters in the ceramic chip packaging process, including the heating rate, cooling rate, and pressure fluctuation range, according to the predicted stress level, in order to reduce the risk of stress concentration inside the chip and avoid the occurrence of failure modes such as chip cracking and delamination. Different stress levels correspond to different degrees of parameter adjustment amplitudes, and corresponding process optimization measures need to be taken for the warning level and the dangerous level.

[0194] In step S3110, when the predicted stress level is the warning level, it indicates that the chip faces a certain risk of stress instability and the packaging process parameters need to be moderately adjusted. , , respectively represent the standard heating rate, cooling rate, and pressure fluctuation range under normal working conditions, which are optimized process parameters determined according to product requirements and equipment capabilities. , , represent the new values after adjusting the standard parameters when the stress level is the warning level. By reducing the heating rate and cooling rate, the thermal stress caused by the temperature difference between the inside and outside of the chip can be slowed down; by narrowing the pressure fluctuation range, the uniformity of the force on the chip can be improved. , , reflects the direction and amplitude of the parameter adjustment.

[0195] In step S3120, when the predicted stress level is the dangerous level, it indicates that the chip is in a high-stress state and faces a serious risk of instability, and significant adjustment of the packaging process parameters is required. , , It shows that the parameter adjustment range under the dangerous level is larger. By significantly reducing the heating rate, cooling rate, and pressure fluctuation range, the internal stress level of the chip can be minimized to avoid the occurrence of failure accidents. This hierarchical adjustment strategy can customize optimization measures according to the severity of stress warning, taking into account production efficiency while ensuring the reliability of the chip.

[0196] Step S3200: Repeat steps S2000 - S3000 until the ceramic chip packaging process is completed.

[0197] Step S3200 is an iterative optimization process, that is, repeat steps S2000 - S3000 until the entire packaging process of the ceramic chip is completed. This closed-loop control method can achieve real-time monitoring and regulation of chip stress. By continuously collecting and analyzing the environmental state and chip state, the stress prediction model is dynamically updated, and the process parameters are adjusted in a timely manner according to the prediction results, forming an intelligent packaging control logic of environmental perception - prediction warning - optimization decision - effect feedback. Each iteration will generate new state data and optimization measures to support the next round of prediction and optimization tasks, continuously improving the control accuracy.

[0198] The above optimization method can relieve the internal stress distribution of the chip from two dimensions: time and space. In the time dimension, by reducing the heating rate and cooling rate, the time gradient of temperature can be reduced, and the action time of thermal stress can be extended, enabling the stress to be fully relaxed; in the space dimension, by narrowing the pressure fluctuation range, the uniformity of the internal stress distribution of the chip can be improved, avoiding local stress concentration. The collaborative optimization of the two can control the stress level of the chip from both macroscopic and microscopic levels, taking precautions. At the same time, this solution is both targeted and adaptable, and can customize optimization strategies according to the real-time stress state of different chips, handling both common working conditions and extreme situations, with strong robustness. In addition, the closed-loop iterative operation mode can continuously accumulate process knowledge and optimization experience, and through the autonomous iteration of machine learning algorithms, achieve the continuous evolution of the packaging control level.

[0199] In summary, the dynamic optimization method based on stress prediction proposed in this step integrates mechanisms such as multi-parameter regulation, hierarchical response, and closed-loop iteration. It can accurately perceive the stress state of the chip, take targeted measures in a timely manner, and while ensuring process stability, maximize the suppression of chip failure risks, providing new ideas and methods for improving the quality of the ceramic packaging process. Compared with traditional empirical parameter tuning, this method has predictability and intelligence, can significantly improve the efficiency and reliability of process optimization, and is of great significance for further improving the performance and service life of ceramic chips.

[0200] Embodiment 2

[0201] Based on Embodiment 1, this embodiment provides a system for optimizing the process parameters of a ceramic chip packaging based on machine learning, as Figure 6 shown, including:

[0202] Historical data acquisition module: used to collect the first historical data during the packaging process of the target ceramic chip; preprocess the first historical data to extract the second historical data;

[0203] Chip stress prediction module: used to construct a chip stress prediction model according to the second historical data; collect the first real-time data during the packaging process of the ceramic chip, preprocess the first real-time data to obtain the second real-time data; according to the second real-time data and the chip stress prediction model, obtain the chip stress prediction time series, and the chip stress prediction time series includes n chip stress prediction values within a future time period ;

[0204] Chip stress level determination module: used to determine the stress level of the ceramic chip during the packaging process within a future time period ; the stress level includes a safety level, a warning level, and a danger level; n is a positive integer;

[0205] Parameter optimization module: if the stress level is a warning level or a danger level, dynamically adjust the packaging process parameters of the ceramic chip.

[0206] In the historical data acquisition module, the preprocessing of the first historical data to extract the second historical data includes:

[0207] Step S1210, perform differencing on the environmental temperature time series data to obtain the environmental temperature change rate time series data;

[0208] Step S1220, perform differencing on the environmental pressure time series data to obtain the environmental pressure change rate time series data;

[0209] Step S1230, perform differencing on the environmental humidity time series data to obtain the environmental humidity change rate time series data;

[0210] Step S1240: Differentiate the chip stress time series data to obtain the chip stress change rate time series data;

[0211] Step S1250: Differentiate the chip temperature time series data to obtain the chip temperature change rate time series data.

[0212] In the chip stress prediction module, the construction of the chip stress prediction model includes:

[0213] Step S2110: Perform feature engineering processing on the second historical data to obtain a historical comprehensive time series feature set; the historical comprehensive time series feature set includes historical environmental statistical time series features, historical chip statistical time series features, historical environmental energy time series features, historical chip energy time series features, and correlation time series features;

[0214] Step S2120: Construct a chip stress prediction model based on the historical comprehensive time series feature set.

[0215] The step S2110 includes:

[0216] Step S2111: Extract the statistical features of the environmental state change rate time series data to generate historical environmental statistical time series features;

[0217] Step S2112: Extract the statistical features of the chip state change rate time series data to generate historical chip statistical time series features;

[0218] Step S2113: Extract the energy distribution of the environmental state change rate time series data on different time scales to obtain historical environmental energy time series features;

[0219] Step S2114: Extract the energy distribution of the chip state change rate time series data on different time scales to obtain historical chip energy time series features;

[0220] Step S2115: Calculate the cross-correlation coefficient between the environmental state change rate time series data and the chip state change rate time series data to obtain correlation time series features.

[0221] In the chip stress prediction module, the first real-time data includes real-time environmental state data and real-time chip state data;

[0222] The real-time environmental state data includes real-time environmental temperature sequence data, real-time environmental pressure time series data, and real-time environmental humidity time series data; the real-time chip state time series data includes real-time chip stress time series data and real-time chip temperature time series data;

[0223] The second real-time data includes real-time environmental state change rate time series data and real-time chip state change rate time series data; the real-time environmental state change rate time series data includes real-time environmental temperature change rate time series data, real-time environmental pressure change rate time series data, and real-time environmental humidity change rate time series data; the real-time chip state change rate time series data includes real-time chip stress change rate time series data and real-time chip temperature change rate time series data;

[0224] In the chip stress level determination module, determining the stress level of the ceramic chip in the future time period during the packaging process based on the chip stress prediction time series includes: within includes:

[0225] Step S2410, calculate the mean μ σ and standard deviation σ σ ;

[0226] Step S2420, calculate the structural mutual information PSI i of the predicted chip stress value σ i at the i-th future moment in the chip stress prediction time series; when PSI i ≥λ', take the mean μ σ as the predicted chip stress correction value σ' i at the i-th future moment, that is, σ' i =μ σ ; when PSI i <λ', then σ' i =(1 - w)μ σ +w×σ i-1 ; σ i-1 is the predicted chip stress value at the (i - 1)-th future moment, w is the weight of σ i-1 , 2≤i≤n, and λ' is the structural mutual information threshold;

[0227] Step S2430, form the chip stress prediction correction time series [(t1,σ'1),(t2,σ'2),…,(t i ,σ' n ,σ' n )] from the predicted chip stress correction values σ' n at the i-th future moment; where σ'

[0228] Step S2440, based on the chip stress prediction correction time series, determine the stress level of the ceramic chip in the future time period during the packaging process.

[0229] Said step S2440 includes:

[0230] Step S2441, if σ w≤σ' i <σ s , then the stress level of the ceramic chip at the i-th future moment during the encapsulation process is the safety level, where σ s is the safety upper limit, and σ w is the warning upper limit;

[0231] Step S2442, if σ d ≤σ' i <σ w , then the stress level of the ceramic chip at the i-th future moment during the encapsulation process is the warning level, where σ d is the danger upper limit, and σ s >σ w >σ d ;

[0232] Step S2443, if σ' i <σ d , then the stress level of the ceramic chip at the i-th future moment during the encapsulation process is the danger level;

[0233] Step S2444, traverse all the chip stress prediction and correction values in the chip stress prediction and correction time sequence, and respectively count the number of moments n2 with the stress level of safety level, the number of moments n3 with the stress level of warning level, and the number of moments n4 with the stress level of danger level within the future time period ; n2 + n3 + n4 = n;

[0234] Step S2445, set the weight coefficient w s for the safety level moments, the weight coefficient w w for the warning level moments, and the weight coefficient w d for the danger level moments. According to n2, n3, n4, w s , w w , and w d , calculate the weighted proportion P of the warning level moments and the weighted proportion P w of the danger level moments within the future time period d ;

[0235] Step S2446, determine the stress level of the ceramic chip as the danger level within the future time period w and P d during the encapsulation process of the ceramic chip .

[0236] The said Step S2446 includes:

[0237] Step S24461, if P d >α, then determine that the stress level of the ceramic chip is the danger level within the future time period The stress level within is a dangerous level; where α is the dangerous proportion threshold;

[0238] Step S24462, if P d ≤α and P w >β, then it is determined that the stress level of the ceramic chip during the encapsulation process in the future time period is a warning level; where β is the warning proportion threshold;

[0239] Step S24463, if P d ≤α and P w ≤β, then it is determined that the stress level of the ceramic chip during the encapsulation process in the future time period is a safe level.

[0240] In the parameter optimization module, the dynamic adjustment of the encapsulation process parameters of the ceramic chip includes:

[0241] Step S3100, if the stress level is a warning level or a dangerous level, then dynamically adjust the encapsulation process parameters of the ceramic chip; the encapsulation process parameters include the heating rate, the cooling rate, and the pressure fluctuation range;

[0242] Step S3200, repeatedly execute chip stress prediction, chip stress level determination, and parameter optimization until the ceramic chip encapsulation process is completed.

[0243] The said Step S3100 includes:

[0244] Step S3110, if the stress level is a warning level, then adjust the heating rate from the standard heating rate value to the first heating rate value , adjust the cooling rate from the standard cooling rate value to the first cooling rate value , and narrow the pressure fluctuation range from the standard pressure fluctuation range to the first pressure fluctuation range , where , , ;

[0245] Step S3120, if the stress level is a dangerous level, then adjust the heating rate from the standard heating rate value to the second heating rate value , adjust the cooling rate from the standard cooling rate value to the second cooling rate value , and narrow the pressure fluctuation range from the standard pressure fluctuation range to the second pressure fluctuation range , where , , 。

[0246] In addition, the parts of the above technical solutions provided in the embodiments of the present application that are consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail to avoid excessive elaboration.

[0247] As described above in the specific embodiments, the purpose, technical solutions, and beneficial effects of the present invention have been further described in detail. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for optimizing the process parameters of ceramic chip packaging based on machine learning, characterized in that The method includes: Collecting first historical data during the encapsulation process of the target ceramic chip; preprocessing the first historical data to extract second historical data; Construct a chip stress prediction model based on the second historical data; collect the first real-time data during the ceramic chip packaging process, preprocess the first real-time data to obtain the second real-time data; according to the second real-time data and the chip stress prediction model, obtain the chip stress prediction time series, and the chip stress prediction time series includes n chip stress prediction values within a future time period t; based on the chip stress prediction time series, determine the stress level of the ceramic chip within the future time period t; the stress level includes a safety level, a warning level, and a danger level; n is a positive integer; The method for determining the stress level of a ceramic chip within a future time period t during the packaging process based on chip stress prediction timing includes: Calibrate the chip stress prediction timing to obtain the calibrated chip stress prediction timing; based on the calibrated chip stress prediction timing, determine the stress level at each moment in the future time period t during the packaging process of the ceramic chip; count the number of moments n2 with a safety stress level, the number of moments n3 with a warning stress level, and the number of moments n4 with a dangerous stress level within the future time period t; n2 + n3 + n4 = n; obtain the weighted proportion P of warning-level moments and the weighted proportion P w of dangerous-level moments within the future time period d ; based on P w and P d determine the stress level of the ceramic chip during the future time period t during the packaging process; If the stress level is a warning level or a dangerous level, dynamically adjusting the encapsulation process parameters of the ceramic chip; the encapsulation process parameters include heating rate, cooling rate, and pressure fluctuation range; The method for correcting the chip stress prediction time series to obtain the corrected chip stress prediction time series includes: Calculate the mean value μ n and standard deviation σ n of the stress prediction time series [(t1, σ1), (t2, σ2), …, (t σ , σ σ ); where t n is the nth moment within the future time period t, and σ n is the predicted value of the chip stress at the nth moment within the future time period t; Calculate the predicted value of the chip stress σ at the i-th future moment in the chip stress prediction timing i The structural mutual information PSI i ; When PSI i ≥λ', take the mean μ σ as the predicted correction value σ' of the chip stress at the i-th future moment i , that is, σ' i =μ σ ; When PSI i <λ', then σ' i =(1 - w)μ σ +w×σ i-1 ; σ i-1 is the predicted value of the chip stress at the (i - 1)-th future moment, w is the weight of σ i-1 , 2 ≤ i ≤ n, λ' is the structural mutual information threshold; The predicted correction value σ' of the chip stress at the future i-th moment i constitutes the predicted correction time series of the chip stress [(t1, σ'1), (t2, σ'2), …, (t n , σ' n )]; where σ' n is the predicted correction value of the chip stress at the future n-th moment; The dynamically adjusting the encapsulation process parameters of the ceramic chip includes: If the stress level is the warning level, the heating rate is adjusted from the standard heating rate value to the first heating rate value , the cooling rate is adjusted from the standard cooling rate value to the first cooling rate value , and the pressure fluctuation range is reduced from the standard pressure fluctuation range to the first pressure fluctuation range , where , , ; If the stress level is a dangerous level, the heating rate is adjusted from the standard heating rate value to the second heating rate value , the cooling rate is adjusted from the standard cooling rate value to the second cooling rate value , and the pressure fluctuation range is reduced from the standard pressure fluctuation range to the second pressure fluctuation range , where , , .

2. The optimization method for ceramic chip packaging process parameters based on machine learning according to claim 1, characterized in that The first historical data includes environmental state time series data and chip state time series data; the environmental state time series data includes environmental temperature time series data, environmental pressure time series data, and environmental humidity time series data; the chip state time series data includes chip stress time series data and chip temperature time series data; The second historical data includes environmental state change rate time series data and chip state change rate time series data; the environmental state change rate time series data includes environmental temperature change rate time series data, environmental pressure change rate time series data, and environmental humidity change rate time series data; the chip state change rate time series data includes chip stress change rate time series data and chip temperature change rate time series data; The preprocessing the first historical data to extract second historical data includes: Differencing the environmental temperature time series data to obtain environmental temperature change rate time series data; Differencing the environmental pressure time series data to obtain environmental pressure change rate time series data; Differencing the environmental humidity time series data to obtain environmental humidity change rate time series data; Differencing the chip stress time series data to obtain chip stress change rate time series data; Differencing the chip temperature time series data to obtain chip temperature change rate time series data.

3. The optimization method for ceramic chip packaging process parameters based on machine learning according to claim 1, characterized in that The constructing the chip stress prediction model includes: Performing feature engineering processing on the second historical data to obtain a historical comprehensive time series feature set; the historical comprehensive time series feature set includes historical environmental statistical time series features, historical chip statistical time series features, historical environmental energy time series features, historical chip energy time series features, and correlation time series features; Constructing a chip stress prediction model according to the historical comprehensive time series feature set.

4. A method for optimizing the process parameters of ceramic chip packaging based on machine learning according to claim 3, characterized in that, The performing feature engineering processing on the second historical data includes: Extracting statistical features of the environmental state change rate time series data to generate historical environmental statistical time series features; Extracting statistical features of the chip state change rate time series data to generate historical chip statistical time series features; Extracting the energy distribution of the environmental state change rate time series data at different time scales to obtain historical environmental energy time series features; Extracting the energy distribution of the chip state change rate time series data at different time scales to obtain historical chip energy time series features; Calculating the cross-correlation coefficient between the environmental state change rate time series data and the chip state change rate time series data to obtain correlation time series features.

5. A method for optimizing process parameters of ceramic chip packaging based on machine learning according to claim 1, characterized in that, The method for determining the stress level at each moment in the future time period t during the packaging process of the ceramic chip based on chip stress prediction and correction of timing includes: If σ w ≤σ' i <σ s , then the stress level of the ceramic chip at the future i-th moment during the packaging process is the safety level, where σ s is the safety upper limit, and σ w is the warning upper limit; If σ d ≤ σ' i <σ w , then the stress level of the ceramic chip at the future i-th moment during the encapsulation process is the warning level, where σ d is the upper limit of danger, σ s >σ w >σ d ; If σ' i <σ d , then the stress level of the ceramic chip at the i-th future moment during the encapsulation process is a dangerous level.

6. The optimization method for ceramic chip packaging process parameters based on machine learning according to claim 5, characterized in that, The method for obtaining the weighted proportion P of the warning level moment and the weighted proportion P of the danger level moment within the future time period t according to n2, n3, and n4 includes: t w and the weighted proportion P of the danger level moment d is as follows: Set the weight coefficients \(w\) at the security level moments respectively s and the weight coefficient \(w\) at the warning level moments w and the weight coefficient \(w\) at the danger level moments d . According to \(n2\), \(n3\), \(n4\), \(w\) s , \(w\) w and \(w\) d , calculate the weighted proportion \(P\) of the warning level moments and the weighted proportion \(P\) w of the danger level moments within the future time period \(t\). d .

7. A method for optimizing the process parameters of ceramic chip packaging based on machine learning according to claim 6, characterized in that, Said according to P w and P d Determine the stress level of the ceramic chip during the future time period t during the encapsulation process includes: If P d > α, it is determined that the stress level of the ceramic chip in the future time period t is a dangerous level; where α is the dangerous proportion threshold; If P d ≤ α and P w > β, it is determined that the stress level of the ceramic chip during the future time period t is the warning level; where β is the warning ratio threshold; If P d ≤ α and P w ≤ β, then it is determined that the stress level of the ceramic chip during the future time period t is the safe level.

8. A ceramic chip packaging process parameter optimization system based on machine learning, which is used to implement a ceramic chip packaging process parameter optimization method according to any one of claims 1-7, characterized in that, The system includes: A historical data acquisition module: used for collecting first historical data during the encapsulation process of the target ceramic chip; preprocessing the first historical data to extract second historical data; Chip stress prediction module: used to construct a chip stress prediction model based on second historical data; collect first real-time data during the ceramic chip packaging process, preprocess the first real-time data to obtain second real-time data; and obtain a chip stress prediction time series according to the second real-time data and the chip stress prediction model, where the chip stress prediction time series includes n chip stress prediction values within a future time period t; n is a positive integer; Chip stress level determination module: used to determine the stress level of a ceramic chip within a future time period t during the packaging process based on chip stress prediction timing; the stress levels include a safety level, a warning level, and a danger level; A parameter optimization module: if the stress level is a warning level or a dangerous level, dynamically adjusting the encapsulation process parameters of the ceramic chip.

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