Driving method and driving circuit

Abstract

The application discloses a driving method and a driving circuit. The driving method is used for driving a display panel. A plurality of data lines are divided into a plurality of data line groups. Each data line group includes at least two data lines. The driving method includes the following steps. The refresh rate of a next frame is detected, and it is determined whether the refresh rate is greater than a preset refresh rate. If the refresh rate of the next frame is less than or equal to the preset refresh rate, a double-data-line input mode is not started, different analog voltages are respectively input to the data lines in the data line group, and the analog voltages are output to the pixel electrodes of corresponding pixels. If the refresh rate of the next frame is greater than the preset refresh rate, the double-data-line input mode is started, the same analog voltage is input to all the data lines in the data line group, and the analog voltage is output to the pixel electrodes of corresponding pixels. The application inputs the same analog voltage to adjacent data lines, reduces the data transmission amount in a half frame, and makes the refresh rate at least doubled under the same transmission rate, so that the dynamic picture quality of product display is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving method and driving circuit. Background Technology

[0002] Currently, TFT-LCD (Thin Film Transistor Liquid Crystal Display) has the largest market share, followed by OLED (Organic Light-Emitting Diode) panels, also known as organic electroluminescence display or organic light-emitting semiconductor (OLED). Improving the display effect of LCD remains one of the main directions for product improvement.

[0003] To save on chip costs, triple gates are currently the primary method used. In this method, three RGB subpixels of a single pixel are arranged vertically, tripling the number of gate lines and reducing the number of source lines to one-third. For example, with a UD resolution of 3840*2160, existing panel designs require 3840*3 source lines and 2160 gate lines. Assuming each source driver IC outputs 960 channels, this would require 12 source driver ICs. With triple gates, only 3840 source lines are needed, equivalent to the output channels of 4 source driver ICs, while still requiring 2160*3 gate lines. However, since gate lines are generated by progressive scan circuits, there isn't a significant increase in cost. The reduction of 8 source driver ICs significantly lowers costs, but the refresh rate remains unchanged, resulting in poor dynamic image quality. Summary of the Invention

[0004] The purpose of this application is to provide a driving method and driving circuit for improving the dynamic image quality of a display panel by increasing the refresh rate.

[0005] This application discloses a driving method for driving a display panel, the display panel including multiple scan lines and data lines, and multiple pixels connected to the scan lines and data lines. The multiple data lines are divided into multiple data line groups, each data line group including at least two data lines. The driving method includes the following steps: S1: Detect the refresh rate of the next frame and determine whether the refresh rate of the next frame is greater than the preset refresh rate; S2: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled. Different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled. The same analog voltage is input to all data lines in the data line group to output to the pixel electrode of the corresponding pixel.

[0006] Optionally, the data line group includes two data lines, namely a first data line and a second data line. A switch control circuit is provided between the first data line and the second data line in each data line group. The switch control circuit is located at one end close to the data driver chip. Each data line in the data line group is connected to a different pin of the data driver chip. Step S2 includes: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, a first control signal is generated, and the switch control circuit is deactivated. Different pins of the data driver chip input different analog voltages to the data lines in the data line group, so as to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled, the switch control circuit is activated, and the pins on the data driver chip connected to the first data line output analog voltages to the first data line and to the second data line through the switch control circuit, so as to output to the pixel electrode of the corresponding pixel.

[0007] Optionally, the data line group includes two data lines, namely a first data line and a second data line. The first data line and the second data line are respectively connected to different pins of the data driver chip. The data driver chip includes a digital-to-analog conversion module and a data copying module. Step S2 includes: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled. Different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled. Digital voltages are output to the data driver chip and stored in the register area. When all the digital voltages of the current row are output to the data driver chip, the data driver chip generates a data latch signal. During the rising edge of the data latch signal, the data copying module copies the digital voltages stored in the register area to store them in the temporary storage area of ​​the data driver chip. During the falling edge of the data latch signal, the digital-to-analog converter converts the digital voltages into analog voltages and outputs them to the first data line and the second data line.

[0008] Optionally, the data cable group includes a first data cable group, a second data cable group, and a third data cable group. The second data cable group is disposed between the first data cable group and the third data cable group. The number of second data cable groups is greater than the number of the first and third data cable groups. The number of data cables in all second data cable groups is greater than the sum of the number of data cables in all first data cable groups and the number of data cables in all second data cable groups. The area where the first data cable group is disposed is the first area of ​​the display area of ​​the display panel. The area where the second data cable group is disposed is the second area of ​​the display area of ​​the display panel. The area where the third data cable group is disposed is the third area of ​​the display area of ​​the display panel. Step S1 includes: Detect the refresh rate of the next frame in the second area of ​​the display panel and determine whether the refresh rate of the next frame in the second area is greater than the preset refresh rate; Step S2 includes: If the refresh rate of the next frame in the second region is less than or equal to the preset refresh rate, the dual data line input mode is not enabled. Instead, different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame in the second region is greater than the preset refresh rate, the dual data line input mode is enabled. Instead, the same analog voltage is input to all the data lines in the data line group to output to the pixel electrode of the corresponding pixel. The first and third regions do not enable the dual data line input mode. Instead, different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel.

[0009] Optionally, the data driving chip includes a judgment module, which detects whether the refresh rate of the next frame is greater than a preset refresh rate and generates a corresponding control signal to output to the switch control circuit to control the switch control circuit to connect the first data line and the second data line. The switch control circuit includes a first transistor, the input terminal of the first transistor is connected to the first data line and the pin connected to the first data line, the output terminal is connected to the second data line, and the control terminal is connected to the judgment module. Along the scan line direction, the threshold value of the transistor in the middle of the display area of ​​the display panel is greater than the threshold value of the transistors on both sides.

[0010] Optionally, the switch control circuit further includes a second transistor, which is disposed between the second data line and the pin of the data driver chip corresponding to the second data line. When the dual data line input mode is enabled, the judgment module generates a corresponding control signal to control the first transistor to turn on, and the judgment module generates a corresponding control signal to control the second transistor to turn off.

[0011] Optionally, the step of detecting the refresh rate of the next frame and determining whether the refresh rate of the next frame is greater than a preset refresh rate includes: Based on the acquired frame rate signal, monitor the blank duration of the blank area in the next frame, determine the refresh rate of the next frame based on the blank duration, and determine whether the refresh rate of the next frame is greater than the preset refresh rate. The driving method further includes the following steps: Determine the refresh rate range in which the next frame's refresh rate falls, and set different compensation ranges based on different refresh rate ranges; The refresh rate ranges below the preset refresh rate are divided into the first refresh rate range and the second refresh rate range, while the refresh rate ranges above the preset refresh rate are divided into the third refresh rate range and the fourth refresh rate range. The compensation value corresponding to the refresh rate value in the first refresh rate range and the second refresh rate range is less than the compensation value corresponding to the refresh rate value in the third refresh rate range and the fourth refresh rate range. The difference in compensation values ​​corresponding to adjacent refresh rate values ​​in the third refresh rate range is less than the difference in compensation values ​​corresponding to adjacent refresh rate values ​​in the fourth refresh rate range.

[0012] Optionally, the pixels connected by the data lines in each data line group have the same pixel polarity and color in the same row, while the pixels in adjacent rows have different colors and polarities.

[0013] This application also discloses a driving circuit that drives a display panel using any of the driving methods described above. The driving circuit includes a timing control chip and a data driving chip. The timing control chip outputs a digital voltage to the data driving chip. The display panel includes multiple scan lines and data lines, as well as multiple pixels connected to the scan lines and data lines. The multiple data lines are divided into multiple data line groups, each including at least two data lines. The data driver chip detects the refresh rate of the next frame and determines whether the refresh rate of the next frame is greater than the preset refresh rate. If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, and different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled, and the digital Diana is converted into an analog circuit. The same analog voltage is input to all data lines in the data line group to output to the pixel electrode of the corresponding pixel.

[0014] Optionally, the data driver chip includes a judgment module. The data line group includes two data lines, namely a first data line and a second data line. A switch control circuit is provided between the first data line and the second data line in each data line group. The switch control circuit includes a first transistor and a second transistor. The input terminal of the first transistor is connected to the first data line and the pin connected to the first data line, the output terminal is connected to the second data line, and the control terminal is connected to the judgment module. The second transistor is disposed between the second data line and the pin of the data driver chip corresponding to the second data line. When the dual data line input mode is enabled, the judgment module generates a corresponding control signal to control the first transistor to turn on and the judgment module generates a corresponding control signal to control the second transistor to turn off.

[0015] Compared to the current triple gate solution, this application divides multiple data lines into multiple data line groups, with each group containing at least two data lines. It detects the refresh rate of the next frame and determines whether it exceeds a preset refresh rate. If the refresh rate is less than or equal to the preset refresh rate, the dual data line input mode is not activated; instead, different analog voltages are input to the data lines within the data line group to output to the corresponding pixel electrode. If the refresh rate is greater than the preset refresh rate, the dual data line input mode is activated, and the same analog voltage is input to all data lines within the data line group to output to the corresponding pixel electrode. This reduces the data transmission volume per frame by half. At the same transmission rate, reducing the data volume per frame increases the frame rate, meaning the refresh rate is at least doubled, thereby improving the dynamic image quality of the product display. Attached Figure Description

[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings: Figure 1 This is a schematic flowchart of the driving method of the first embodiment of this application; Figure 2 This is a schematic flowchart of the driving method according to the second embodiment of this application; Figure 3 This is a schematic diagram of the display panel structure according to the second embodiment of this application; Figure 4 This is a schematic diagram of the driving circuit structure according to the third embodiment of this application; Figure 5This is a schematic flowchart of the driving method according to the fourth embodiment of this application; Figure 6 This is a schematic diagram of the display panel structure according to the fourth embodiment of this application; Figure 7 This is a data transmission diagram of the fourth embodiment of this application; Figure 8 This is a schematic flowchart of the driving method according to the fifth embodiment of this application; Figure 9 This is a schematic diagram of the structure of the display panel according to the fifth embodiment of this application; Figure 10 This is a schematic flowchart of the driving method according to the sixth embodiment of this application; Figure 11 This is a schematic diagram of the drive circuit according to the seventh embodiment of this application; Figure 12 This is a schematic diagram of the drive circuit of the eighth embodiment of this application.

[0017] Among them, 100 is the display panel; 110 is the data line group; 111 is the first data line group; 112 is the second data line group; 113 is the third data line group; 120 is the display area; 121 is the first area; 122 is the second area; 123 is the third area; 200 is the driving circuit; 210 is the switch control circuit; 211 is the first transistor; 212 is the second transistor; 220 is the data driver chip; 221 is the digital-to-analog conversion module; 222 is the data copying module; 223 is the judgment module; 300 is the timing control chip; G1-Gn are the scan lines; S1 is the first data line; S2 is the second data line; TP is the data latch signal. Detailed Implementation

[0018] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0019] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0020] refer to Figure 1 As shown, as a first embodiment of this application, a driving method is disclosed. The driving method is used to drive a display panel, the display panel including multiple scan lines and data lines, and multiple pixels connected to the scan lines and data lines. The multiple data lines are divided into multiple data line groups, each data line group including at least two data lines. The driving method includes: S1: Detect the refresh rate of the next frame and determine whether the refresh rate of the next frame is greater than the preset refresh rate; S2: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled. Different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled. The same analog voltage is input to all data lines in the data line group to output to the pixel electrode of the corresponding pixel.

[0021] For high-resolution display products, the amount of data required for each frame is relatively large due to the high resolution. Further increasing the refresh rate necessitates data driver chips (driver ICs) with even higher transmission rates, posing a significant challenge to existing IC specifications. Moreover, faster transmission rates increase the cost of the IC. Therefore, to improve the specifications of high-resolution products, the refresh rate can be increased by enabling DLS (dual line source) mode. Before enabling DLS mode, the refresh rate of the next frame is checked to determine if it meets the threshold. If the refresh rate is less than or equal to the preset refresh rate, the dual line source mode is not enabled; instead, different analog voltages are input to the data lines within the data line group to output to the corresponding pixel electrodes. If the refresh rate is greater than the preset refresh rate, the dual line source mode is enabled, inputting the same analog voltage to all data lines within the data line group to output to the corresponding pixel electrodes. This reduces the amount of data transmitted per frame, thus increasing the refresh rate while maintaining the same transmission rate.

[0022] like Figure 2 As shown, the second embodiment of this application is a further refinement and improvement of the first embodiment described above. (Refer to...) Figure 2 and Figure 3 As shown, the data line group 110 includes two data lines, namely a first data line S1 and a second data line S2. A switch control circuit 210 is provided between the first data line S1 and the second data line S2 in each data line group 110. The switch control circuit 210 is located at one end close to the data driver chip 220. Each data line in the data line group 110 is connected to a different pin of the data driver chip 220. The pixels in the same row connected by the data lines in each data line group 110 have the same pixel polarity and the same color. The pixels in adjacent rows have different colors and different polarities. Step S2 includes: S221: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, a first control signal is generated, and the switch control circuit is not turned on. Different pins of the data driver chip input different analog voltages to the data lines in the data line group, so as to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled, the switch control circuit is turned on, and the pins of the data driver chip connected to the first data line S1 output analog voltage to the first data line S1 and output to the second data line S2 through the switch control circuit, so as to output to the pixel electrode of the corresponding pixel.

[0023] A switch control circuit 210 is set between the pins of the data driver chip 220 and the odd / even column data lines. The switch control circuit 210 is normally closed. When DLS mode is enabled, that is, when it is determined that the refresh rate of the next frame is greater than the preset refresh rate, the switch control circuit 210 is turned on. The pins of the data driver chip 220 connected to the first data line S1 output analog voltage to the first data line S1 and output to the second data line S2 through the switch control circuit 210, so that the odd / even column data lines of two adjacent columns are shorted together, so as to output the same voltage to the pixel electrode of the corresponding pixel to drive the liquid crystal deflection.

[0024] Furthermore, the data driving chip 220 includes a judgment module 223, which detects and judges whether the refresh rate of the next frame is greater than a preset refresh rate, and generates a corresponding control signal to output to the switch control circuit 210 to control the switch control circuit 210 to connect the first data line S1 and the second data line S2. The switch control circuit 210 includes a first transistor 211, the input terminal of the first transistor 211 is connected to the first data line S1 and the pin connected to the first data line S1, the output terminal is connected to the second data line S2, and the control terminal is connected to the judgment module 223. Along the scan line direction, the threshold value of the transistor in the middle of the display area 120 of the display panel 100 is greater than the threshold value of the transistors on both sides.

[0025] By detecting the refresh rate of the next frame and comparing it with the preset refresh rate through the judgment module 223, a control signal is generated. This signal then controls the switch control circuit 210 to connect the first data line S1 and the second data line S2. This allows for flexible adjustment of refresh rate-related operations according to actual needs, helping to optimize display effects and power consumption performance in different scenarios. For example, it can respond promptly when a high refresh rate is needed to display dynamic images, while the refresh rate can be appropriately reduced to save energy in relatively static image scenarios. Considering that the threshold value of the transistors in the middle of the display area 120 of the display panel 100 is greater than that of the transistors on both sides, combined with the control of the data line connection by the switch control circuit 210, the working state of transistors in different positions can be adjusted to a certain extent. This improves the uniformity of the display in the entire display area 120, reduces unevenness in display brightness and color caused by differences in transistor thresholds, improves crosstalk problems, and enhances the overall display quality.

[0026] like Figure 4 As shown, as a third embodiment of this application, it is a further improvement on the second embodiment described above. The switch control circuit 210 further includes a second transistor 212. The second transistor 212 is disposed between the second data line S2 and the pin of the data driver chip 220 corresponding to the second data line S2. When the dual data line input mode is enabled, the judgment module 223 generates a corresponding control signal to control the first transistor 211 to turn on, and the judgment module 223 generates a corresponding control signal to control the second transistor 212 to turn off.

[0027] This solution expands upon the existing switch control circuit 210 by adding a second transistor 212. The second transistor 212 is located between the second data line S2 and the pin of the corresponding data driver chip 220. When in the specific working state of dual data line input mode, the judgment module 223 performs its function, generating a corresponding control signal to turn on the first transistor 211 and a corresponding control signal to turn off the second transistor 212. By generating different control signals based on whether the dual data line input mode is enabled, the judgment module 223 controls the first transistor 211 to turn on and the second transistor 212 to turn off, respectively. This allows for smooth switching between the dual data line input mode and other possible modes, meeting the different data transmission requirements in different application scenarios and enhancing the flexibility and adaptability of the entire circuit system in dealing with multiple working modes.

[0028] In dual data line input mode, precise control of the first transistor 211 ensures that data can be transmitted through the appropriate path, while timely shutdown of the second transistor 212 effectively avoids unnecessary signal interference or short circuits, ensuring the accuracy and stability of data transmission, improving the efficiency and quality of overall data transmission, and facilitating the normal and high-quality operation of related subsequent operations such as display.

[0029] like Figure 5 As shown, this fourth embodiment of the present application is a further improvement and refinement of the first embodiment described above. The data line group 110 includes two data lines, namely a first data line S1 and a second data line S2. The first data line S1 and the second data line S2 are respectively connected to different pins of the data driver chip 220. The data driver chip 220 includes a digital-to-analog conversion module 221 and a data copying module 222. Step S2 includes: S251: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled. Different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled. Digital voltages are output to the data driver chip and stored in the register area. When all the digital voltages of the current row are output to the data driver chip, the data driver chip generates a data latch signal TP. During the rising edge of the data latch signal TP, the data copying module copies the digital voltages stored in the register area to store them in the temporary storage area of ​​the data driver chip. During the falling edge of the data latch signal TP, the digital-to-analog converter converts the digital voltages into analog voltages and outputs them to the first data line S1 and the second data line S2.

[0030] The pixel voltage value is mainly transmitted as a digital voltage by the front-end timing control chip 300 to the data driver chip 220 (source driver IC). Then, the digital-to-analog converter module 221 of the data driver chip 220 converts it into an analog voltage and outputs it to the pixel electrode. By copying the data, the refresh rate is doubled.

[0031] refer to Figure 6 As shown, in DLS mode, DA1 is the first data transmitted from the timing control chip 300 to the data driver chip 220, and DA2 is the data received by the data driver chip 220 and stored in the input register. Once all the data in this row has been transmitted to the data driver chip 220, as shown... Figure 7As shown, a rising edge of the TP (latch signal) signal will be generated. At this time, the data driver chip 220 will push the data in the input register to the temporary storage area (data latch). During this process, the data of DA2 can be copied to DA3 and synchronously stored in the data latch. After the data is converted and processed by the digital-to-analog converter module 221, the converted analog voltage is transmitted to the pixel electrodes of the in-plane sub-pixels for charging on the falling edge of TP. DA2 charges the first column of sub-pixels, and DA3 charges the second column of sub-pixels.

[0032] Similar to the second embodiment, since the data in the two adjacent columns is copied, the actual data transmitted from the timing control chip 300 to the data driver chip 220 within a frame is only half of that in normal mode. If the data transmission rate remains unchanged, the refresh rate can be doubled.

[0033] like Figure 8 As shown, the fifth embodiment of this application is a further refinement and improvement of any of the above embodiments. (Refer to...) Figure 8 and Figure 9 As shown, the data cable group 110 includes a first data cable group 111, a second data cable group 112, and a third data cable group 113. The second data cable group 112 is disposed between the first data cable group 111 and the third data cable group 113. The number of second data cable groups 112 is greater than the number of first data cable groups 111 and third data cable groups 113. The number of data cables in all second data cable groups 112 is greater than the sum of the number of data cables in all first data cable groups 111 and the number of data cables in all second data cable groups 112. The area where the first data cable group 111 is disposed is the first area 121 of the display area 120 of the display panel 100. The area where the second data cable group 112 is disposed is the second area 122 of the display area 120 of the display panel 100. The area where the third data cable group 113 is disposed is the third area 123 of the display area 120 of the display panel 100. Step S1 includes: S181: Detect the refresh rate of the next frame of the second area of ​​the display panel, and determine whether the refresh rate of the next frame of the second area is greater than the preset refresh rate; Step S2 includes: S281: If the refresh rate of the next frame in the second region is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, and different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel; if the refresh rate of the next frame in the second region is greater than the preset refresh rate, the dual data line input mode is enabled, and the same analog voltage is input to all data lines in the data line group to output to the pixel electrode of the corresponding pixel. S282: The first and third regions do not enable the dual data line input mode, and input different analog voltages to the data lines in the data line group respectively, so as to output to the pixel electrode of the corresponding pixel.

[0034] This embodiment mainly takes into account the different display requirements of different areas of the display area 120 of the display panel 100. The middle area is generally used to display dynamic images and is also a more sensitive area for the human eye. Therefore, the display area 120 is divided into three areas. In each area, the data cable is divided into multiple data cable groups 110. However, when the refresh rate is changed, only the middle area starts the dual data cable input mode to improve the refresh rate of the middle area and improve the display effect of the middle area.

[0035] like Figure 10 As shown, the sixth embodiment of this application is a further refinement and improvement of the first embodiment described above. The S1 step includes: S11: Monitor the blank duration of the blank area of ​​the next frame based on the acquired frame rate signal, determine the refresh rate of the next frame based on the blank duration, and determine whether the refresh rate of the next frame is greater than the preset refresh rate. The driving method further includes the following steps: S3: Determine the refresh rate range where the next frame refresh rate is located, and set different compensation ranges based on different refresh rate ranges; The refresh rate ranges below the preset refresh rate are divided into the first refresh rate range and the second refresh rate range, while the refresh rate ranges above the preset refresh rate are divided into the third refresh rate range and the fourth refresh rate range. The compensation value corresponding to the refresh rate value in the first refresh rate range and the second refresh rate range is less than the compensation value corresponding to the refresh rate value in the third refresh rate range and the fourth refresh rate range. The difference in compensation values ​​corresponding to adjacent refresh rate values ​​in the third refresh rate range is less than the difference in compensation values ​​corresponding to adjacent refresh rate values ​​in the fourth refresh rate range.

[0036] The entire driving method also includes a step (S3) to determine the refresh rate range of the next frame, and to set different compensation ranges based on different refresh rate ranges. By using the frame rate signal to monitor the duration of the blank area to determine the refresh rate, the actual refresh rate of each frame can be obtained relatively accurately, providing a precise data foundation for subsequent collaborative work with other systems or for optimizing and adjusting the display effect. For example, the brightness, sharpness, and other parameters of the display can be adjusted in real time according to different refresh rates to achieve a better visual experience.

[0037] Setting different compensation intervals for different refresh rate ranges allows for more precise display compensation for varying refresh rates. For refresh rates lower than the preset range, the impact on display quality is relatively small due to the lower refresh rate, so a smaller compensation value is set. Conversely, for refresh rates higher than the preset range, the potential impact on display quality is relatively large due to the higher refresh rate, so a larger compensation value is set. This allows for the rational allocation of system resources while ensuring display quality, avoiding resource waste caused by over-compensation. Differentiating the compensation value differences between adjacent refresh rate values ​​in the third and fourth refresh rate ranges further optimizes the transition of display effects. This results in smoother and more natural changes in display effects across different refresh rate ranges, reducing flickering and stuttering caused by refresh rate changes, and improving overall visual comfort and image smoothness.

[0038] like Figure 11 As shown, as the seventh embodiment of this application, a driving circuit 200 is disclosed to drive a display panel 100 using the driving method described in any of the above embodiments. The driving circuit 200 includes a timing control chip 300 and a data driving chip 220. The timing control chip 300 outputs a digital voltage to the data driving chip 220. The display panel 100 includes multiple scan lines and data lines, as well as multiple pixels connected to the scan lines and data lines. The multiple data lines are divided into multiple data line groups 110, each including at least two data lines. The data driver chip 220 detects the refresh rate of the next frame and determines whether the refresh rate of the next frame is greater than the preset refresh rate. If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, and different analog voltages are input to the data lines in the data line group 110 to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled, and the digital voltage is converted into an analog circuit. The same analog voltage is input to all the data lines in the data line group 110 to output to the pixel electrode of the corresponding pixel.

[0039] In this embodiment, the data driver chip 220 detects the refresh rate of the next frame and compares it with a preset refresh rate. Specifically, if the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not activated. Instead, different analog voltages are input to each data line in the data line group 110, and these input analog voltages are transmitted to the pixel electrodes of the corresponding pixels. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is activated. The digital signal is converted into an analog signal, and the same analog voltage is input to all data lines in the data line group 110. These voltages are also output to the pixel electrodes of the corresponding pixels.

[0040] Based on the comparison between the next frame refresh rate and the preset refresh rate, the system can flexibly choose whether to enable the dual data line input mode and different voltage input methods, effectively adapting to the display needs of different frame rate scenarios. For example, in low refresh rate scenarios, inputting different analog voltages to different data lines can ensure basic display effects and allow the image to be displayed normally; in high refresh rate scenarios, enabling the dual data line input mode and inputting the same analog voltage helps to quickly complete the image update, reduce display anomalies caused by refresh rate changes, and improve the overall smoothness and stability of the display.

[0041] Disabling dual data line input mode at low refresh rates avoids unnecessary energy waste, as it eliminates the need for uniform high-frequency operation on all data lines. Conversely, using a uniform analog voltage input and dual data line input mode at high refresh rates simplifies circuit operation, improves data processing and transmission efficiency, and makes the entire display driving process more efficient. This not only ensures display quality but also reduces power consumption and extends device battery life to some extent.

[0042] like Figure 12As shown, the eighth embodiment of this application is a further improvement and refinement of the seventh embodiment described above. The data driver chip 220 includes a judgment module 223. The data line group 110 includes two data lines, namely a first data line S1 and a second data line S2. A switch control circuit 210 is provided between the first data line S1 and the second data line S2 in each data line group 110. The switch control circuit 210 includes a first transistor 211 and a second transistor 212. The input terminal of the first transistor 211 is connected to the first data line S1 and the pin connected to the first data line S1, the output terminal is connected to the second data line S2, and the control terminal is connected to the judgment module 223. The second transistor 212 is disposed between the second data line S2 and the pin of the data driver chip 220 corresponding to the second data line S2. When the dual data line input mode is enabled, the judgment module 223 generates a corresponding control signal to control the first transistor 211 to turn on and the judgment module 223 generates a corresponding control signal to control the second transistor 212 to turn off.

[0043] In this embodiment, the data driver chip 220 includes a judgment module 223. The entire data line group 110 consists of a first data line S1 and a second data line S2. Within each data line group 110, a switch control circuit 210 is configured between the first data line S1 and the second data line S2. This circuit includes a first transistor 211 and a second transistor 212. The input terminal of the first transistor 211 is connected to the first data line S1 and its corresponding pin, while its output terminal is connected to the second data line S2. Its control terminal is connected to the judgment module 223. The second transistor 212 is located between the second data line S2 and its corresponding pin of the data driver chip 220. When the dual data line input mode is enabled, the judgment module 223 generates a corresponding control signal, turning on the first transistor 211 and simultaneously turning off the second transistor 212. By using the judgment module 223 to accurately generate control signals based on whether the dual data line input mode is enabled, the circuit can control the conduction and shutdown of the first transistor 211 and the second transistor 212, efficiently switching between single data line input mode and dual data line input mode. This switching function allows the circuit to flexibly adjust its operating state according to actual needs, adapting to different data transmission and display scenarios, thus enhancing the operability and compatibility of the entire circuit system.

[0044] By properly controlling the states of the two transistors, the first transistor 211 is turned on and the second transistor 212 is turned off in the dual data line input mode. This ensures that data is accurately transmitted in the corresponding lines and avoids signal interference, short circuits, and other problems caused by incorrect transistor states. It effectively guarantees the accuracy and stability of data transmission and provides strong support for the subsequent pixel electrodes to receive correct and stable analog voltage signals, thereby helping to improve display quality and enabling the display to be presented clearly and stably.

[0045] It should be noted that the limitations on the steps involved in this solution, without affecting the implementation of the specific solution, are not considered as limiting the order of the steps. That is, the steps listed first can be performed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the protection scope of this application. The inventive concept of this application can form many embodiments, but due to space limitations in the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. The combination of embodiments or technical features will enhance the original technical effect.

[0046] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A driving method for driving a display panel, the display panel comprising a plurality of scan lines and data lines, and a plurality of pixels connected to the scan lines and data lines, characterized in that, All pixels in the same row have the same color. Multiple data lines are divided into multiple data line groups. Each data line group includes two data lines. The pixels connected by the data lines in each data line group have the same polarity and color in the same row. Adjacent rows of pixels have different colors and different polarities. The driving method includes the following steps: S1: Detect the refresh rate of the next frame and determine whether the refresh rate of the next frame is greater than the preset refresh rate; Step S1 includes: Based on the acquired frame rate signal, monitor the blank duration of the blank area in the next frame, determine the refresh rate of the next frame based on the blank duration, and determine whether the refresh rate of the next frame is greater than the preset refresh rate. S2: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled. Different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled. The same analog voltage is input to all data lines in the data line group to output to the pixel electrode of the corresponding pixel. In the dual data line input mode, when the data lines in each data line group are connected to the pixels, the two adjacent data lines connected to adjacent pixels of the same color receive the same analog voltage. The data line group includes two data lines, namely a first data line and a second data line. A switch control circuit is provided between the first data line and the second data line in each data line group. The switch control circuit is located at one end close to the data driver chip. Each data line in the data line group is connected to a different pin of the data driver chip. Step S2 includes: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled, a first control signal is generated, and the switch control circuit is deactivated. Different pins of the data driver chip input different analog voltages to the data lines in the data line group, so as to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled, the switch control circuit is activated, and the pins of the data driver chip connected to the first data line output analog voltages to the first data line and output to the second data line through the switch control circuit, so as to output to the pixel electrode of the corresponding pixel. The data driving chip includes a judgment module, which detects whether the refresh rate of the next frame is greater than a preset refresh rate and generates a corresponding control signal to output to the switch control circuit to control the switch control circuit to connect the first data line and the second data line. The switch control circuit includes a first transistor, the input terminal of the first transistor is connected to the first data line and the pin connected to the first data line, the output terminal is connected to the second data line, and the control terminal is connected to the judgment module. Along the scan line direction, the threshold of the first transistor in the middle of the display area of ​​the display panel is greater than the threshold of the first transistors on both sides. The data cable group includes a first data cable group, a second data cable group, and a third data cable group. The second data cable group is disposed between the first data cable group and the third data cable group. The number of second data cable groups is greater than the number of the first and third data cable groups. The number of data cables in all second data cable groups is greater than the sum of the number of data cables in all first data cable groups and the number of data cables in all third data cable groups. The area where the first data cable group is disposed is the first area of ​​the display area of ​​the display panel. The area where the second data cable group is disposed is the second area of ​​the display area of ​​the display panel. The area where the third data cable group is disposed is the third area of ​​the display area of ​​the display panel. The second area is between the first area and the third area, and the second area is an intermediate area. Step S1 includes: Detect the refresh rate of the next frame in the second area of ​​the display panel and determine whether the refresh rate of the next frame in the second area is greater than the preset refresh rate; Step S2 includes: If the refresh rate of the next frame in the second region is less than or equal to the preset refresh rate, the dual data line input mode is not enabled. Instead, different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame in the second region is greater than the preset refresh rate, the dual data line input mode is enabled. Instead, the same analog voltage is input to all the data lines in the data line group to output to the pixel electrode of the corresponding pixel. The first and third regions do not enable the dual data line input mode. Different analog voltages are input to the data lines in the data line group respectively, so as to output to the pixel electrode of the corresponding pixel. The driving method further includes the following steps: S3: Determine the refresh rate range where the next frame refresh rate is located, and set different compensation ranges based on different refresh rate ranges; The refresh rate ranges below the preset refresh rate are divided into the first refresh rate range and the second refresh rate range, while the refresh rate ranges above the preset refresh rate are divided into the third refresh rate range and the fourth refresh rate range. The compensation value corresponding to the refresh rate value in the first refresh rate range and the second refresh rate range is less than the compensation value corresponding to the refresh rate value in the third refresh rate range and the fourth refresh rate range. The difference in compensation values ​​corresponding to adjacent refresh rate values ​​in the third refresh rate range is less than the difference in compensation values ​​corresponding to adjacent refresh rate values ​​in the fourth refresh rate range.

2. A driving method for driving a display panel, the display panel comprising a plurality of scan lines and data lines, and a plurality of pixels connected to the scan lines and data lines, characterized in that, All pixels in the same row have the same color. Multiple data lines are divided into multiple data line groups. Each data line group includes two data lines. The pixels connected by the data lines in each data line group have the same polarity and color in the same row. Adjacent rows of pixels have different colors and different polarities. The driving method includes the following steps: S1: Detect the refresh rate of the next frame and determine whether the refresh rate of the next frame is greater than the preset refresh rate; Step S1 includes: Based on the acquired frame rate signal, monitor the blank duration of the blank area in the next frame, determine the refresh rate of the next frame based on the blank duration, and determine whether the refresh rate of the next frame is greater than the preset refresh rate. S2: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled. Different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled. The same analog voltage is input to all data lines in the data line group to output to the pixel electrode of the corresponding pixel. The data line group includes two data lines, namely a first data line and a second data line. The first data line and the second data line are respectively connected to different pins of the data driver chip. The data driver chip includes a digital-to-analog conversion module and a data copying module. Step S2 includes: If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode is not enabled. Different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled. Digital voltages are output to the data driver chip and stored in the register area. When all the digital voltages of the current row are output to the data driver chip, the data driver chip generates a data latch signal. During the rising edge of the data latch signal, the data copying module copies the digital voltages stored in the register area to store them in the temporary storage area of ​​the data driver chip. During the falling edge of the data latch signal, the digital-to-analog converter converts the digital voltages into analog voltages and outputs them to the first data line and the second data line. The data driving chip includes a judgment module, which detects whether the refresh rate of the next frame is greater than a preset refresh rate and generates a corresponding control signal to output to the switch control circuit to control the switch control circuit to connect the first data line and the second data line. The switch control circuit includes a first transistor, the input terminal of the first transistor is connected to the first data line and the pin connected to the first data line, the output terminal is connected to the second data line, and the control terminal is connected to the judgment module. Along the scan line direction, the threshold of the first transistor in the middle of the display area of ​​the display panel is greater than the threshold of the first transistors on both sides. The switch control circuit further includes a second transistor, which is disposed between the second data line and the pin of the data driver chip corresponding to the second data line. When the dual data line input mode is enabled, the judgment module generates a corresponding control signal to control the first transistor to turn on, and the judgment module generates a corresponding control signal to control the second transistor to turn off. The data cable group includes a first data cable group, a second data cable group, and a third data cable group. The second data cable group is disposed between the first data cable group and the third data cable group. The number of second data cable groups is greater than the number of the first and third data cable groups. The number of data cables in all second data cable groups is greater than the sum of the number of data cables in all first data cable groups and the number of data cables in all third data cable groups. The area where the first data cable group is disposed is the first area of ​​the display area of ​​the display panel. The area where the second data cable group is disposed is the second area of ​​the display area of ​​the display panel. The area where the third data cable group is disposed is the third area of ​​the display area of ​​the display panel. The second area is between the first area and the third area, and the second area is an intermediate area. Step S1 includes: Detect the refresh rate of the next frame in the second area of ​​the display panel and determine whether the refresh rate of the next frame in the second area is greater than the preset refresh rate; Step S2 includes: If the refresh rate of the next frame in the second region is less than or equal to the preset refresh rate, the dual data line input mode is not enabled. Instead, different analog voltages are input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame in the second region is greater than the preset refresh rate, the dual data line input mode is enabled. Instead, the same analog voltage is input to all the data lines in the data line group to output to the pixel electrode of the corresponding pixel. The first and third regions do not enable the dual data line input mode. Different analog voltages are input to the data lines in the data line group respectively, so as to output to the pixel electrode of the corresponding pixel. The driving method further includes the following steps: Determine the refresh rate range in which the next frame's refresh rate falls, and set different compensation ranges based on different refresh rate ranges; The refresh rate ranges below the preset refresh rate are divided into the first refresh rate range and the second refresh rate range, while the refresh rate ranges above the preset refresh rate are divided into the third refresh rate range and the fourth refresh rate range. The compensation value corresponding to the refresh rate value in the first refresh rate range and the second refresh rate range is less than the compensation value corresponding to the refresh rate value in the third refresh rate range and the fourth refresh rate range. The difference in compensation values ​​corresponding to adjacent refresh rate values ​​in the third refresh rate range is less than the difference in compensation values ​​corresponding to adjacent refresh rate values ​​in the fourth refresh rate range.

3. The driving method as described in claim 1 or 2, characterized in that, Both columns of data on the first and second data lines are copied, and the data transmitted from the timing control chip to the data driver chip within one frame is half of the original.

4. The driving method as described in claim 3, characterized in that, The transmission rate of the two columns of data on the first data line and the second data line remains unchanged.

5. A driving circuit that drives a display panel using the driving method as described in any one of claims 1-4, characterized in that, The driving circuit includes a timing control chip and a data driving chip. The timing control chip outputs a digital voltage to the data driving chip. The display panel includes multiple scan lines and data lines, as well as multiple pixels connected to the scan lines and data lines. The multiple data lines are divided into multiple data line groups, each including two data lines. The data driver chip detects the refresh rate of the next frame and determines whether the refresh rate of the next frame is greater than the preset refresh rate. If the refresh rate of the next frame is less than or equal to the preset refresh rate, the dual data line input mode will not be enabled. Instead, different analog voltages will be input to the data lines in the data line group to output to the pixel electrode of the corresponding pixel. If the refresh rate of the next frame is greater than the preset refresh rate, the dual data line input mode is enabled, and the digital voltage is converted into an analog voltage. The same analog voltage is then input to all data lines in the data line group to output to the pixel electrode of the corresponding pixel.

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