Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure. The preparation method comprises the following steps: providing a substrate; forming an isolation layer on the substrate; forming a first metal structure layer with a specific structure on the isolation layer; forming a natural oxide layer on the first metal structure layer; forming a protective layer on the natural oxide layer; a mask layer is formed on the protective layer, the protective layer and the natural oxide layer are etched downwards with the mask layer as a mask, and a reserved overlapping structure position is formed; forming a subsequent oxide layer on the first metal structure layer corresponding to the reserved overlapping structure position under a preset condition; and forming a second metal layer on the subsequent oxide layer, etching the second metal layer to form an overlapping structure, and taking the protection layer as an etching stop layer to protect the first metal structure layer when the second metal layer is etched. According to the invention, the first metal structure layer at the non-overlapping structure can be effectively prevented from being damaged when the second metal layer is etched, and the reliability problem is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] Some existing special chip manufacturing processes are to stack two layers of metal, and form a cross-stacked overlapping structure in specific places, such as Figure 1 In the manufacturing process of this special chip, except for the overlapping structure (generally composed of two superconductors sandwiched by a very thin barrier layer, superconducting electrons can tunnel from one side through the semiconductor or insulator film to the other side), the rest of the metal layers do not overlap (such as Figure 1 Therefore, when etching the second metal layer, the first metal layer at the non-overlapping structure will be damaged, causing some first metal layers with narrow line widths to have high resistance or even break, or even to fuse due to being unable to withstand the normal operating voltage, leading to reliability problems.

[0003] Based on this, the actual mass production process needs to be optimized and adjusted to ensure that the actual chip functions and design requirements are met. Summary of the invention

[0004] The main purpose of the present invention is to provide a method for preparing a semiconductor structure and a semiconductor structure, which can effectively prevent the first layer of metal at the non-overlapping structure from being damaged when etching the second layer of metal, thereby avoiding reliability problems.

[0005] The technical solution adopted by the present invention is: A method for preparing a semiconductor stacked structure is provided, comprising the following steps: providing a substrate; forming an isolation layer on a substrate; forming a first metal structure layer with a specific structure on the isolation layer; forming a natural oxide layer on the first metal structure layer; Forming a protective layer on the natural oxide layer; Forming a mask layer on the protective layer, and using the mask layer as a mask to etch downward the protective layer and the natural oxide layer to form a reserved overlapping structure position; Under a preset condition, forming a subsequent oxide layer on the first metal structure layer corresponding to the reserved overlapping structure position; A second metal layer is formed on the subsequent oxide layer, and the second metal layer is etched to form an overlapping structure. When etching the second metal layer, the protective layer is used as an etching stop layer to protect the first metal structure layer.

[0006] Following the above technical solution, the formation of the first metal structure layer includes the steps of: covering a metal layer on the isolation layer, forming an anti-reflection layer and a mask layer on the metal layer, and etching the metal layer using the mask layer as a mask to form the first metal structure layer.

[0007] According to the above technical solution, the material of the protective layer is SiON, SiN or SiO 2 .

[0008] According to the above technical solution, the protective layer is formed by chemical vapor deposition.

[0009] Following the above technical solution, the mask layer formed on the protection layer also defines the routing area.

[0010] Continuing with the above technical solution, the formation of the overlapping structure includes the steps of: covering a metal layer on the exposed protective layer and the subsequent oxide layer, forming an anti-reflection layer and a mask layer on the metal layer, etching the metal layer using the mask layer as a mask and the protective layer as an etching stop layer to form an overlapping structure.

[0011] The above technical solution further includes the step of: after the overlapping structure is formed, removing the protective layer at the non-overlapping structure.

[0012] Following the above technical solution, after forming the first metal structure layer or the overlapping structure, the method further includes the step of removing the anti-reflection layer and the mask layer.

[0013] Following the above technical solution, after forming the isolation layer on the substrate, a zero-layer marking layer is formed as a subsequent alignment layer.

[0014] According to the above technical solution, the material of the first metal structure layer includes titanium, tantalum, aluminum, iron, copper-based materials or a combination thereof; and / or the material of the second metal layer includes titanium, tantalum, aluminum, iron, copper-based materials or a combination thereof.

[0015] The present invention also provides a semiconductor structure, which is prepared by the method for preparing the semiconductor stacked structure described in the above technical solution.

[0016] The unexpected beneficial effect produced by the present invention is: the present invention forms a protective layer on the natural oxide layer of the first metal structure layer, and uses the protective layer as an etching stop layer when etching the second metal layer to form an overlapping structure. The unexpected effect is that in the specific process implementation process, there is no need to strictly control the etching stop signal capture interval, thereby greatly improving the mass production operation space; and the protective layer can protect the metal at the non-overlapping structure of the first metal structure layer from being damaged by secondary etching; in addition, the protective layer serves as an intermediate sacrificial layer, which can not only protect the first metal structure layer during the process, but also can be finally selected to be removed according to specific needs.

[0017] Furthermore, by regrowing the oxide layer of the overlapping structure for the second time, the overall quality of the formed overlapping structure can be better, the electrical property difference can be less varied, and the consistency can be better.

[0018] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 It is a schematic diagram of damaging the first metal layer when forming an overlapping structure in the prior art; Figure 2 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present invention; Figure 3 It is a cross-sectional schematic diagram of manufacturing a substrate and an isolation layer in a method for manufacturing a semiconductor structure according to an embodiment of the present invention; Figure 4 is a cross-sectional schematic diagram of manufacturing a mask for a first metal structure layer in a method for manufacturing a semiconductor structure according to an embodiment of the present invention; Figure 5A is a schematic top view of manufacturing a first metal structure layer in a method for manufacturing a semiconductor structure according to an embodiment of the present invention; Figure 5B For along Figure 5A Schematic cross-sectional view along the AA direction; Figure 6 is a cross-sectional schematic diagram of forming a protective layer in a method for preparing a semiconductor structure according to an embodiment of the present invention; Fig. 7A is a top view schematic diagram of forming a mask on a protective layer in a method for preparing a semiconductor structure according to an embodiment of the present invention; Figure 7B For along Fig. 7A Schematic cross-sectional view in the middle BB direction; Figure 8 is a cross-sectional schematic diagram after etching the protective layer in the method for preparing the semiconductor structure according to the embodiment of the present invention; Fig. 9 is a cross-sectional schematic diagram of forming a subsequent oxide layer in a method for preparing a semiconductor structure according to an embodiment of the present invention; Fig.10 is a cross-sectional schematic diagram after the second metal layer is formed in the method for preparing the semiconductor structure according to the embodiment of the present invention; Fig.11Ais a cross-sectional schematic diagram of forming a reflective layer and a mask layer on a second metal layer in a method for preparing a semiconductor structure according to an embodiment of the present invention; Fig. 11B For along Fig.11A Schematic cross-sectional view in the CC direction; Fig. 12A is a cross-sectional schematic diagram of forming an overlapping structure in a method for preparing a semiconductor structure according to an embodiment of the present invention; Fig. 12B is a schematic top view after an overlapping structure is formed in the method for preparing a semiconductor structure according to an embodiment of the present invention; Fig.13 It is a cross-sectional schematic diagram of removing the protective layer at the non-overlapping structure after forming the overlapping structure 112 in the method for preparing the semiconductor structure according to the embodiment of the present invention.

[0021] In the figure: 101, substrate; 102, isolation layer; 103, zero layer marking layer; 104, first metal layer; 105, anti-reflection layer; 106, mask layer; 107, first metal structure layer; 108, natural oxide layer; 109, protective layer; 110, subsequent oxide layer; 111, second metal layer; 112, overlapping structure. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0023] It should be noted that the illustrations provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout type may also be more complicated.

[0024] In the present invention, it is also necessary to explain that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0025] In addition, it should be noted that the features of the various embodiments of the present invention may be combined or combined in part or in whole, and may interact and operate in different ways as will be appreciated by those skilled in the art. Each embodiment may be implemented independently of one another, or in an associated relationship.

[0026] like Figure 2 As shown, the method for preparing a semiconductor structure according to an embodiment of the present invention mainly includes the following steps: S1. providing a substrate; S2, forming an isolation layer on the substrate; S3, forming a first metal structure layer with a specific structure on the isolation layer; S4, forming a natural oxide layer on the first metal structure layer; S5, forming a protective layer on the natural oxide layer; S6, forming a mask layer on the protective layer, and etching the protective layer and the natural oxide layer downward using the mask layer as a mask to form a reserved overlapping structure position; S7, under preset conditions, forming a subsequent oxide layer on the first metal structure layer corresponding to the reserved overlapping structure position; S8. Form a second metal layer on the subsequent oxide layer, etch the second metal layer to form an overlapping structure, and use the protective layer as an etching stop layer to protect the first metal structure layer when etching the second metal layer.

[0027] Among them, Figure 3 As shown, in step S1, the material of substrate 101 is a semiconductor material, an insulating material, a conductor material or any combination thereof. And the substrate 101 can be a single-layer structure or a multi-layer structure. It can be selected according to the needs. Optionally, the substrate 101 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. It can also be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. The embodiment of the present invention preferably uses an Al / Si substrate 101.

[0028] In step S2, Figure 3 As shown, a layer of isolation layer 102 can be grown by a furnace tube method. The isolation layer 102 can be an oxide layer, such as silicon dioxide (SiO 2 ), after forming the isolation layer 102, a zero mark layer 103 (Zero Mark) can also be formed in the isolation layer 102 as a subsequent alignment layer for alignment in the subsequent photolithography process to improve the overlay accuracy of the photolithography process.

[0029] like Figure 4-5B As shown, in step S3, a first metal layer 104 and a first metal structure layer 107 of a specific structure are formed on the isolation layer 102. The specific formation process is: a first metal layer 104 is covered on the isolation layer 102, an anti-reflection layer 105 and a mask layer 106 are formed on the first metal layer 104, and the first metal layer 104 is etched using the mask layer 106 as a mask to form the first metal structure layer 107. The anti-reflection layer 105 can be made of silicon oxynitride (SiON) as a bottom anti-reflection coating BARC, which can prevent the standing wave effect from being generated during the subsequent photoresist exposure, thereby affecting the dissolution effect of the exposed part of the photoresist. The mask layer 106 may be a photoresist layer, and a positive photoresist or a negative photoresist is coated thereon, and a specific pattern of the first metal structure layer 107 is defined by a photomask, and then the pattern on the photomask is transferred to the photoresist layer by exposure to form a mask layer 106; the first metal layer 104 is etched according to the mask layer 106 to form a first metal structure layer 107 of a specific structure, and finally the photoresist and the anti-reflection layer 105 are removed. The material of the first metal layer 104 includes titanium, tantalum, aluminum, iron, copper-based materials or a combination thereof. In this embodiment, the first metal layer 104 is aluminum (Al).

[0030] like Figure 6 As shown, step S4 mainly forms a natural oxide layer 108 under a natural environment. The natural state is mainly a normal temperature and pressure state, such as 25°C and 1.01325Pa. After staying at normal temperature and pressure for a period of time, a natural oxide layer 108 is formed on the exposed surface of the first metal structure layer 107. Since the natural oxide layer 108 cannot be converted from an insulating state to a conductive state under a specific state, it cannot be used as an insulating material in the overlapping structure. Therefore, it is necessary to remove the natural oxide layer 108 at the overlapping structure in the subsequent process.

[0031] For example Figure 6 As shown, after the natural oxide layer 108 is formed, a protective layer 109 is formed thereon. The protective layer 109 serves as an etching stop layer when the second metal layer 111 is subsequently formed. Therefore, there is no need to strictly control the etching stop signal capture interval of the second metal layer 111, thereby greatly improving the mass production operation space. And the protective layer 109 can prevent the metal at the non-overlapping structure on the first metal structure layer 107 from being damaged by secondary etching. Specifically, a protective layer 109 can be directly deposited by a chemical vapor deposition process (Chemical Vapor Deposition, CVD) with a thickness of several tens of angstroms (such as 40 angstroms-80 angstroms), and it is not necessary to fill the grooves formed when etching the first metal layer 104. The material of the protective layer 109 can be selected from SiON, SiN or SiO 2In addition, the protection layer 109 serves as an intermediate sacrificial layer, which can protect the first metal structure layer 107 during the process and can be removed or not according to specific needs.

[0032] like Fig. 7A , 7B As shown, step S6 specifically includes: forming a mask on the protective layer 109, such as a photoresist, and forming a corresponding mask layer 106 by exposure and development, wherein a certain area is exposed at the position where the overlapping structure 112 is to be formed (the wiring area of ​​the second metal layer 111 to be formed later can also be exposed), and other areas are all covered with photoresist; then the protective layer 109 and the natural oxide layer 108 are etched downward using the mask layer 106 as a mask to form a reserved overlapping structure position, and specifically, the protective layer 109 at the reserved overlapping structure can be etched away by dry-wet method (Dry+Wet) or wet method (Wet) only, and the natural oxide layer 108 is removed to avoid quality problems when the overlapping structure is formed later; finally, the photoresist layer is removed. When forming the overlapping structure, dry etching followed by wet etching or only wet etching is adopted. First, it ensures that the protective oxide layer (i.e., the natural oxide layer 108) on the side wall of the first metal structure layer 107 can be removed completely; second, the wet etching method increases the metal selectivity and will not cause damage to the first metal structure layer 107; third, wet etching is a naturally isotropic etching, which will etch a part laterally, which can ensure that the old oxide layer in the effective junction area when the overlapping structure is formed is completely removed, does not affect the formation of the subsequent oxide layer, and ensures the quality of the reformation of the upper and lower metal intermediate isolation layers in the effective junction area of ​​the overlapping structure, thereby ensuring the quality of the final product.

[0033] In the prior art, there is also a method of first forming a first metal structure on a substrate, then filling an isolation structure on the first metal structure, then digging a groove on the isolation structure, and flattening (grinding) a portion of the isolation structure and the sacrificial oxide layer, thereby reducing the height difference between the second metal layer and the first metal layer when the second metal layer is formed, and in this way, avoiding damage to the first metal structure when etching the second metal layer. However, in this method of reserving the position of the overlapping structure by digging a groove in the first metal layer, there will be problems with development and etching during the process of digging the groove by photolithography, especially etching will have a foot shrinkage effect, and it is easy for the oxide layer to remain at the bottom, resulting in part of the oxide layer being eaten or severely damaged, which will affect the formation of the oxide layer and the subsequent product yield and functional use. And when digging the groove, the side will retain the foot height. The deeper the digging, the more etching residues, and the deeper the groove, the more difficult it is to fill the second metal layer, which is easy to cause void defects, thereby further affecting product performance. However, the present invention does not have the process of digging and filling the groove, so these defects can be avoided.

[0034] like Figure 8-9As shown, in step S7, since the protective layer 109 and the natural oxide layer 108 are etched to form a reserved overlapping structure, the first metal structure layer 107 is exposed here, and a subsequent oxide layer 110 is formed on the exposed first metal structure layer 107 under preset conditions. In this embodiment, a new aluminum oxide (Al2O3) is formed under preset conditions. 2 O 3 ), the preset condition is a constant temperature and humidity environment, and the contents of oxygen, nitrogen, and carbon dioxide are all preset special values, and the thickness of the subsequent oxide layer 110 is uniform, about 10 angstroms to 20 angstroms. The subsequent oxide layer 110 serves as an intermediate isolation layer of the overlapping structure 112. Its first state is an insulating state under normal conditions, the second state is a superconducting state at ultra-low temperatures, and the third state is a suspended state (intermediate state) between insulation and superconductivity. When the conditions change, it can be switched to an insulating state or a superconducting state at any time.

[0035] like Figure 10-12B As shown, in step S8, the formation of the overlapping structure 112 includes the steps of: covering the exposed protection layer 109 and the subsequent oxide layer 110 with a second metal layer 111, forming an anti-reflection layer 105 and a mask layer 106 on the second metal layer 111, and etching the second metal layer 111 with the mask layer 106 as a mask and the protection layer 109 as an etching stop layer to form the overlapping structure 112. The anti-reflection layer 105 can be selected from silicon oxynitride (SiON) as a bottom anti-reflection coating BARC, which can prevent the standing wave effect from being generated during the subsequent photoresist exposure, thereby affecting the dissolution effect of the exposed part of the photoresist. The mask layer 106 may be a photoresist layer, and a positive photoresist or a negative photoresist is coated thereon, and the specific pattern of the Josephson junction 112 is defined by the mask, and then the pattern on the mask is transferred to the photoresist layer by exposure to form the mask layer 106; the second metal layer 111 is etched according to the mask layer 106 to form an overlapping structure 112, and finally the photoresist and the anti-reflection layer 105 are removed. Among them, the material of the second metal layer 111 includes titanium, tantalum, aluminum, iron, copper-based materials or a combination thereof. In this embodiment, the second metal layer 111 selects aluminum (Al).

[0036] Furthermore, if Fig.13 As shown, the step of removing the protective layer 109 at the non-overlapping structure after forming the overlapping structure 112 is also included. Whether it is necessary to remove the protective layer 109 at the non-overlapping structure can be determined according to the specification and performance requirements of the specific device. Generally, the noise tolerance of the performance is large and has no impact. For high performance, the protective layer 109 needs to be removed as much as possible to avoid introducing noise interference.

[0037] The semiconductor structure of the embodiment of the present invention can be prepared by the method for preparing the semiconductor overlapping structure 112 of the above method embodiment, and the semiconductor structure specifically includes a substrate 101, an isolation layer 102, a first metal structure layer 107, and an overlapping structure 112 formed on the first metal structure layer 107. The formation process of the overlapping structure 112 is mainly to form a protective layer 109 on the first metal structure layer 107 as an etching stop layer for the secondary etching of the second metal layer 111 to protect the first metal structure layer 107 from being damaged. The overlapping structure 112 includes two layers of metal, and an insulating layer is also provided between the two metal layers. The insulating layer is an oxide layer containing specific components formed on the first metal structure layer 107 under preset conditions. The insulating layer can exhibit an insulating state, an intermediate suspended state, and a superconducting state under different conditions.

[0038] In some implementations, when the overlapping structure 112 is formed, a protective layer 109 is also formed on the first metal structure layer 107 at the non-overlapping structure, and whether to retain the protective layer 109 can be determined based on actual needs.

[0039] In summary, the present invention forms a protective layer on the natural oxide layer of the first metal structure layer, and uses the protective layer as an etching stop layer when etching the second metal layer to form an overlapping structure. An unexpected effect is that in the process of realizing the overlapping structure, there is no need to strictly control the etching stop signal capture interval, thereby greatly improving the mass production operation space; and the protective layer can protect the first metal structure layer from being damaged by secondary etching; in addition, the protective layer serves as an intermediate sacrificial layer, which can not only protect the first metal structure layer during the process, but also can be finally selected to be removed according to specific needs.

[0040] It should be pointed out that, according to the needs of implementation, the various steps / components described in this application can be split into more steps / components, and two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0041] The order of execution of each step in the above embodiment does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0042] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The following steps are involved: providing a substrate; forming an isolation layer on a substrate; forming a first metal structure layer with a specific structure on the isolation layer; forming a natural oxide layer on the first metal structure layer; Forming a protective layer on the natural oxide layer; Forming a mask layer on the protective layer, and using the mask layer as a mask to etch downward the protective layer and the natural oxide layer to form a reserved overlapping structure position; Under a preset condition, forming a subsequent oxide layer on the first metal structure layer corresponding to the reserved overlapping structure position; A second metal layer is formed on the subsequent oxide layer, and the second metal layer is etched to form an overlapping structure. When etching the second metal layer, the protection layer is used as an etching stop layer to protect the first metal structure layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The formation of the first metal structure layer includes the steps of: covering a metal layer on the isolation layer, forming an anti-reflection layer and a mask layer on the metal layer, and etching the metal layer using the mask layer as a mask to form the first metal structure layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The material of the protection layer is SiON, SiN or SiO2.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The protective layer is formed by chemical vapor deposition.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The formation of the overlapping structure includes the steps of covering a metal layer on the exposed protective layer and the subsequent oxide layer, forming an anti-reflection layer and a mask layer on the metal layer, etching the metal layer using the mask layer as a mask and the protective layer as an etching stop layer to form the overlapping structure.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: After forming an isolation layer on the substrate, a zero-layer marking layer is formed as a subsequent alignment layer.

7. The method for preparing a semiconductor structure according to claim 2 or 5, characterized in that: After forming the first metal structure layer or the overlapping structure, the method further includes a step of removing the anti-reflection layer and the mask layer.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: The material of the first metal structure layer includes titanium, tantalum, aluminum, iron, copper-based materials or a combination thereof; and / or the material of the second metal layer includes titanium, tantalum, aluminum, iron, copper-based materials or a combination thereof.

9. A semiconductor structure, characterized in that: It is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 8.

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