Method for preparing semiconductor structure and semiconductor structure

Abstract

The present invention discloses a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes the following steps: providing a substrate; forming an isolation layer on the substrate; forming a first metal structure layer with a specific structure on the isolation layer; forming a natural oxide layer on the first metal structure layer; forming a protective layer on the natural oxide layer; forming a mask layer on the protective layer, and using the mask layer as a mask to etch the protective layer and the natural oxide layer downward to form a reserved overlapping structure position; under preset conditions, forming a subsequent oxide layer on the first metal structure layer corresponding to the reserved overlapping structure position; forming a second metal layer on the subsequent oxide layer, etching the second metal layer to form an overlapping structure, and using the protective layer as an etching stop layer to protect the first metal structure layer when etching the second metal layer. The present invention can effectively prevent the first metal structure layer at non-overlapping structures from being damaged when etching the second layer of metal, and avoid problems with reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] Some existing manufacturing processes for special chips are in the form of upper and lower metal laminations. An overlapping structure is formed by cross-stacking at specific locations, as shown in the two side boxes of Figure 1 . In the manufacturing process of this special chip, except for the overlapping structure (generally a structure composed of two superconductors sandwiching a very thin barrier layer, and superconducting electrons can pass from one side to the other through the tunneling effect through a semiconductor or insulator film), there is no overlap in the metal layers at other locations (as shown in the middle box of Figure 1 ), and they are in the same plane. Therefore, when etching the second metal layer, the first metal layer at the non-overlapping structure will be damaged, resulting in a high resistance or even possible disconnection of some first metal layers with a narrow line width, and it may also be melted due to the inability to withstand the normal working voltage, etc., leading to reliability problems.

[0003] Based on this, it is necessary to optimize and adjust the actual mass production process to ensure meeting the actual chip functions and design requirements. Summary of the Invention

[0004] The main object of the present invention is to provide a method for manufacturing a semiconductor structure and a semiconductor structure, which can effectively prevent the damage of the first metal layer at the non-overlapping structure when etching the second metal layer and avoid reliability problems.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A method for manufacturing a semiconductor stacked structure is provided, including the following steps:

[0007] Provide a substrate;

[0008] Form an isolation layer on the substrate;

[0009] Form a first metal structure layer with a specific structure on the isolation layer;

[0010] Form a natural oxide layer on the first metal structure layer;

[0011] Form a protective layer on the natural oxide layer;

[0012] Form a mask layer on the protective layer, and use this mask layer as a mask to etch the protective layer and the natural oxide layer downward to form a reserved overlapping structure position;

[0013] Under preset conditions, form a subsequent oxide layer on the first metal structure layer corresponding to the reserved overlapping structure position;

[0014] A second metal layer is formed on the subsequent oxide layer, and the second metal layer is etched to form an overlapping structure, and the protective layer is used as an etching stop layer to protect the first metal structure layer when etching the second metal layer.

[0015] Continuing with the above technical solution, the formation of the first metal structure layer includes the steps of: covering a metal layer on the isolation layer, forming an anti-reflection layer and a mask layer on the metal layer, and etching the metal layer using the mask layer as a mask to form the first metal structure layer.

[0016] Continuing with the above technical solution, the material of the protective layer is SiON, SiN or SiO2.

[0017] Continuing with the above technical solution, the protective layer is specifically formed by chemical vapor deposition.

[0018] Continuing with the above technical solution, the mask layer formed on the protective layer also defines a wiring area.

[0019] Continuing with the above technical solution, the formation of the overlapping structure includes the steps of: covering a metal layer on the exposed protective layer and the subsequent oxide layer, forming an anti-reflection layer and a mask layer on the metal layer, and etching the metal layer using the mask layer as a mask and the protective layer as an etching stop layer to form the overlapping structure.

[0020] Continuing with the above technical solution, it further includes the step of removing the protective layer at non-overlapping structures after forming the overlapping structure.

[0021] Continuing with the above technical solution, after forming the first metal structure layer or the overlapping structure, it further includes the step of removing the anti-reflection layer and the mask layer.

[0022] Continuing with the above technical solution, after forming the isolation layer on the substrate, a zero-layer marking layer is formed as a subsequent alignment layer.

[0023] Continuing with the above technical solution, the material of the first metal structure layer includes titanium, tantalum, aluminum, iron, copper-based materials or a combination thereof; and / or the material of the second metal layer includes titanium, tantalum, aluminum, iron, copper-based materials or a combination thereof.

[0024] The present invention also provides a semiconductor structure, which is prepared by using the preparation method of the semiconductor stack structure described in the above technical solution.

[0025] The unexpected beneficial effects of the present invention are as follows: By forming a protective layer on the natural oxide layer of the first metal structure layer, when etching the second metal layer to form an overlapping structure, this protective layer is used as an etch stop layer. The unexpected effect is that in the specific process implementation, there is no need to extremely strictly control the etch stop signal capture interval, thus greatly improving the mass production operation space. Moreover, the metal at the non-overlapping structure of the first metal structure layer can be protected by this protective layer from being damaged by secondary etching. In addition, as an intermediate sacrificial layer, this protective layer can not only protect the first metal structure layer during the process, but also can be finally selected to be removed or not according to specific requirements.

[0026] Furthermore, by re-growing the oxide layer of the overlapping structure twice, the overall quality of the formed overlapping structure can be better, the electrical property difference change is smaller, and the consistency is better.

[0027] Of course, any product implementing the present invention does not necessarily need to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0029] Figure 1 It is a schematic diagram of damaging the first layer of metal when forming an overlapping structure in the prior art;

[0030] Figure 2 It is a flowchart of the preparation method of the semiconductor structure in the embodiment of the present invention;

[0031] Figure 3 It is a cross-sectional schematic diagram when manufacturing a substrate and an isolation layer in the preparation method of the semiconductor structure in the embodiment of the present invention;

[0032] Figure 4 It is a cross-sectional schematic diagram when manufacturing a mask of the first metal structure layer in the preparation method of the semiconductor structure in the embodiment of the present invention;

[0033] Figure 5A It is a top view schematic diagram when manufacturing the first metal structure layer in the preparation method of the semiconductor structure in the embodiment of the present invention;

[0034] Figure 5B For the cross-sectional schematic diagram along Figure 5A the A-A direction in

[0035] Figure 6It is a cross-sectional schematic view when forming a protective layer in the method for preparing a semiconductor structure according to an embodiment of the present invention;

[0036] Figure 7A It is a top-down schematic view when forming a mask on the protective layer in the method for preparing a semiconductor structure according to an embodiment of the present invention;

[0037] Figure 7B For along Figure 7A The cross-sectional schematic view in the B-B direction in

[0038] Figure 8 It is a cross-sectional schematic view after etching the protective layer in the method for preparing a semiconductor structure according to an embodiment of the present invention;

[0039] Figure 9 It is a cross-sectional schematic view when forming a subsequent oxide layer in the method for preparing a semiconductor structure according to an embodiment of the present invention;

[0040] Figure 10 It is a cross-sectional schematic view when forming a second metal layer in the method for preparing a semiconductor structure according to an embodiment of the present invention;

[0041] Figure 11A It is a cross-sectional schematic view when forming a reflective layer and a mask layer on the second metal layer in the method for preparing a semiconductor structure according to an embodiment of the present invention;

[0042] Figure 11B For along Figure 11A The cross-sectional schematic view in the C-C direction in

[0043] Figure 12A It is a cross-sectional schematic view when forming an overlapping structure in the method for preparing a semiconductor structure according to an embodiment of the present invention;

[0044] Figure 12B It is a top-down schematic view after forming the overlapping structure in the method for preparing a semiconductor structure according to an embodiment of the present invention;

[0045] Figure 13 It is a cross-sectional schematic view when removing the protective layer at the non-overlapping structure after forming the overlapping structure 112 in the method for preparing a semiconductor structure according to an embodiment of the present invention.

[0046] In the figure: 101, substrate; 102, isolation layer; 103, zero-layer marking layer; 104, first metal layer; 105, anti-reflection layer; 106, mask layer; 107, first metal structure layer; 108, natural oxide layer; 109, protective layer; 110, subsequent oxide layer; 111, second metal layer; 112, overlapping structure. Detailed implementation manners

[0047] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0048] It should be noted that the illustrations provided in the embodiments of the present invention only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation. The types, numbers and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0049] In the present invention, it should also be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes and cannot be construed as indicating or implying relative importance.

[0050] In addition, it should also be noted that the features of various embodiments of the present invention can be partially or wholly combined or integrated, and as can be understood by those skilled in the art, they can interact and operate in different ways. Each embodiment can be implemented independently of each other or in an associated relationship.

[0051] As Figure 2 shown, the method for preparing a semiconductor structure according to an embodiment of the present invention mainly includes the following steps:

[0052] S1. Provide a substrate;

[0053] S2. Form an isolation layer on the substrate;

[0054] S3. Form a first metal structure layer with a specific structure on the isolation layer;

[0055] S4. Form a natural oxide layer on the first metal structure layer;

[0056] S5. Form a protective layer on the natural oxide layer;

[0057] S6. Form a mask layer on the protective layer, and use the mask layer as a mask to etch the protective layer and the natural oxide layer downward to form a reserved overlapping structure position;

[0058] S7. Under preset conditions, form a subsequent oxide layer on the first metal structure layer corresponding to the reserved overlapping structure position;

[0059] S8. Form a second metal layer on the subsequent oxide layer, etch the second metal layer to form an overlapping structure, and use the protective layer as an etch stop layer to protect the first metal structure layer when etching the second metal layer.

[0060] Among them, as Figure 3 shown, in step S1, the material of the substrate 101 is a semiconductor material, an insulating material, a conductive material, or any combination thereof. And the substrate 101 can be a single-layer structure or a multi-layer structure. Specifically, it can be selected according to requirements. Optionally, the substrate 101 can be, for example, a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. It can also be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. In the embodiment of the present invention, an Al / Si substrate 101 is preferably used.

[0061] In step S2, again as Figure 3 shown, an isolation layer 102 can be grown by a furnace tube method. The isolation layer 102 can be an oxide layer, such as silicon dioxide (SiO2). After forming the isolation layer 102, a zero-layer mark layer 103 (Zero Mark) can also be formed in the isolation layer 102 as a subsequent alignment layer for alignment in the subsequent lithography process to improve the overlay accuracy of the lithography process.

[0062] As Figures 4 - 5BAs shown in the figure, in step S3, a first metal layer 104 with a specific structure, i.e., a first metal structure layer 107, is formed on the isolation layer 102. The specific formation process is as follows: A layer of the first metal layer 104 is covered on the isolation layer 102, and an anti-reflection layer 105 and a mask layer 106 are formed on the first metal layer 104. Using the mask layer 106 as a mask, the first metal layer 104 is etched to form the first metal structure layer 107. The anti-reflection layer 105 can be silicon oxynitride (SiON), which serves as a bottom anti-reflection coating (BARC) and can prevent the generation of standing wave effects during subsequent photoresist exposure, affecting the dissolution effect of the exposed part of the photoresist. The mask layer 106 can be a photoresist layer, and a positive photoresist or a negative photoresist is coated on it. The specific pattern of the first metal structure layer 107 is defined through a photomask, and then the pattern on the photomask is transferred to the photoresist layer through exposure to form the mask layer 106. According to the mask layer 106, the first metal layer 104 is etched to form the first metal structure layer 107 with a specific structure. Finally, the photoresist and the anti-reflection layer 105 are removed. Among them, the material of the first metal layer 104 includes titanium, tantalum, aluminum, iron, copper-based materials, or a combination thereof. In this embodiment, the first metal layer 104 is selected as aluminum (Al).

[0063] As Figure 6 shown, in step S4, a natural oxide layer 108 is mainly formed in a natural environment. This natural state is mainly at normal temperature and pressure, such as 25°C and 1.01325 Pa. After staying at normal temperature and pressure for a period of time, a natural oxide layer 108 is formed on the exposed surface of the first metal structure layer 107. Since the natural oxide layer 108 cannot be converted from an insulating state to a conducting state under specific conditions and cannot be used as an insulating material in the overlapping structure, it is necessary to remove the natural oxide layer 108 at the overlapping structure in subsequent processes.

[0064] Again Figure 6 as shown, after the natural oxide layer 108 is formed, a protective layer 109 is formed on it. The protective layer 109 serves as an etch stop layer when the second metal layer 111 is formed subsequently. Therefore, it is not necessary to strictly control the etching stop signal capture range of the second metal layer 111, thereby greatly improving the mass production operation space. And through the protective layer 109, the metal at the non-overlapping structure on the first metal structure layer 107 can be prevented from being damaged by secondary etching. Specifically, a protective layer 109 can be directly deposited through a chemical vapor deposition (CVD) process, with a thickness of dozens of angstroms (such as 40 Å - 80 Å), and it is not necessary to fill the grooves formed when etching the first metal layer 104. The material of the protective layer 109 can be selected from SiON, SiN, or SiO2. In addition, the protective layer 109 serves as an intermediate sacrificial layer, which can protect the first metal structure layer 107 during the process and can finally be selected to be removed or not according to specific requirements.

[0065] As Figure 7A , 7B shown, step S6 specifically includes: forming a mask on the protective layer 109, which can be a photoresist, and forming a corresponding mask layer 106 by exposure and development. At the position where the overlapping structure 112 is to be formed, a certain area is exposed (the wiring area for the subsequent formation of the second metal layer 111 can also be exposed), and the other areas are all covered with photoresist; then, using this mask layer 106 as a mask, the protective layer 109 and the native oxide layer 108 are etched downward to form a reserved position for the overlapping structure. Specifically, the protective layer 109 at the reserved overlapping structure position can be etched away by dry+wet method or only wet method, and the native oxide layer 108 is removed to avoid quality problems when the overlapping structure is formed subsequently; finally, the photoresist layer is removed. When forming the overlapping structure, dry-first and then wet etching or only wet etching is used. First, it ensures that the protective oxide layer (i.e., the native oxide layer 108) on the sidewall of the first metal structure layer 107 can be removed completely; second, the wet etching method increases the selectivity of the metal, and will not damage the first metal structure layer 107; third, the wet etching is a natural isotropic etching property, which will etch laterally by a certain amount, and can ensure that all the old oxide layers within the effective junction area when forming the overlapping structure are removed completely, without affecting the formation of the subsequent oxide layer and ensuring the quality of the re-formation of the intermediate isolation layer between the upper and lower layer metals within the effective junction area of the overlapping structure, thus ensuring the quality of the final product.

[0066] In the prior art, there is also a method of first forming a first metal structure on a substrate, then filling an isolation structure on the first metal structure, then grooving on the isolation structure, and performing planarization (grinding) on part of the isolation structure and the sacrificial oxide layer, so as to reduce the height difference between the formation of the second metal layer and the existing first metal layer, and avoid damaging the first metal structure when etching the second metal layer in this way. However, when reserving the position of the overlapping structure by grooving in the first metal layer, there will be problems in development and etching during the photolithography grooving process. Especially in etching, there will be a foot shrinking effect, and it is easy to have residual oxide layers at the bottom feet, resulting in partial side etching or serious damage to the oxide layer, which will affect the formation of the oxide layer and the subsequent product yield and functional use. And when grooving, a foot height will be reserved on the side. The deeper the groove is dug, the more etching residues there will be, and the deeper the groove is dug, the more difficult it is to fill the second metal layer, which is likely to cause void defects, thus further affecting the product performance. And the present invention does not have the process of groove filling, so these defects can be avoided.

[0067] As Figures 8 - 9As shown, in step S7, since the positions of the reserved overlapping structures are formed by etching the protective layer 109 and the native oxide layer 108, the first metal structure layer 107 will be exposed here. Under preset conditions, a subsequent oxide layer 110 needs to be formed on the exposed first metal structure layer 107. In this embodiment, a new aluminum oxide (Al2O3) is formed under the preset conditions. The preset conditions are a constant temperature and humidity environment, and the contents of oxygen, nitrogen, and carbon dioxide are all preset special values. Moreover, the thickness of the subsequent oxide layer 110 is uniform, approximately 10 angstroms - 20 angstroms. The subsequent oxide layer 110 serves as the intermediate isolation layer of the overlapping structure 112. Its first state is the insulating state under normal conditions, the second state is the superconducting state at ultra-low temperature, and the third state is the suspended state (intermediate state) between insulation and superconductivity. It can be switched to the insulating state or the superconducting state at any time when the conditions are changed.

[0068] As Figures 10 - 12B shown, in step S8, the formation of the overlapping structure 112 includes the steps of: covering a second metal layer 111 on the exposed protective layer 109 and the subsequent oxide layer 110, forming an anti-reflection layer 105 and a mask layer 106 on the second metal layer 111, etching the second metal layer 111 with the mask layer 106 as the mask and the protective layer 109 as the etching stop layer to form the overlapping structure 112. The anti-reflection layer 105 can be silicon oxynitride (SiON), which serves as the bottom anti-reflection coating BARC and can prevent the standing wave effect from occurring during the subsequent exposure of the photoresist, affecting the dissolution effect of the exposed part of the photoresist. The mask layer 106 can be a photoresist layer, and a positive photoresist or a negative photoresist is coated on it. The specific pattern of the Josephson junction 112 is defined by a photomask, and then the pattern on the photomask is transferred to the photoresist layer through exposure to form the mask layer 106; the second metal layer 111 is etched according to the mask layer 106 to form the overlapping structure 112, and finally the photoresist and the anti-reflection layer 105 are removed. Among them, the material of the second metal layer 111 includes titanium, tantalum, aluminum, iron, copper-based materials or combinations thereof. In this embodiment, the second metal layer 111 is selected as aluminum (Al).

[0069] Further, as Figure 13 shown, it further includes the step of: after forming the overlapping structure 112, removing the protective layer 109 at the non-overlapping structure. Whether it is necessary to remove the protective layer 109 at the non-overlapping structure can be determined according to the specifications and performance requirements of the specific device. For general performance, the noise tolerance is large and it does not affect. For high performance, it is necessary to remove the protective layer 109 as much as possible to avoid introducing noise interference.

[0070] The semiconductor structure of the embodiment of the present invention can be prepared by using the preparation method of the semiconductor overlapping structure 112 in the above method embodiment. Specifically, the semiconductor structure includes a substrate 101, an isolation layer 102, a first metal structure layer 107, and an overlapping structure 112 formed on the first metal structure layer 107. The formation process of the overlapping structure 112 is mainly to form a protection layer 109 on the first metal structure layer 107 as an etching stop layer for second etching the second metal layer 111 to protect the first metal structure layer 107 from being damaged. The overlapping structure 112 includes two layers of metal, and an insulating layer is further provided between the two metal layers. The insulating layer is an oxide layer containing specific components formed on the first metal structure layer 107 under preset conditions. The insulating layer can exhibit an insulating state, an intermediate suspended state, and a superconducting state under different circumstances.

[0071] In some embodiments, when forming the overlapping structure 112, a protection layer 109 is also formed on the first metal structure layer 107 at the non-overlapping structure, and whether to retain the protection layer 109 can be determined according to actual needs.

[0072] In summary, the present invention forms a protection layer on the natural oxide layer of the first metal structure layer. When etching the second metal layer to form the overlapping structure, the protection layer is used as the etching stop layer. Unexpectedly, during the implementation of the overlapping structure, there is no need to extremely strictly control the etching stop signal capture interval, thus greatly improving the mass production operation space; and the first metal structure layer can be protected by the protection layer from being damaged by the second etching; in addition, the protection layer, as an intermediate sacrificial layer, can protect the first metal structure layer during the process and can ultimately be selected to be removed or not according to specific needs.

[0073] It should be noted that according to the needs of implementation, each step / component described in the present application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0074] In the above embodiments, the magnitudes of the sequence numbers of the steps do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0075] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that, It includes the following steps: Provide a substrate; Form an isolation layer on the substrate; Form a first metal structure layer with a specific structure on the isolation layer; Form a natural oxide layer on the first metal structure layer; Form a protective layer on the natural oxide layer; Form a mask layer on the protective layer, and use this mask layer as a mask to etch the protective layer and the natural oxide layer downward to form a reserved overlapping structure position; Under preset conditions, form a subsequent oxide layer on the first metal structure layer corresponding to the reserved overlapping structure position; Form a second metal layer on the subsequent oxide layer, and etch the second metal layer to form an overlapping structure, which is composed of two superconductors sandwiching a barrier layer; and when etching the second metal layer, use the protective layer as an etch stop layer to protect the first metal structure layer at non-overlapping structure positions.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The formation of the first metal structure layer includes the steps of: covering a metal layer on the isolation layer, forming an anti-reflection layer and a mask layer on the metal layer, and etching the metal layer with this mask layer as a mask to form the first metal structure layer.

3. The method for preparing a semiconductor structure according to claim 1, wherein, The material of the protective layer is SiON, SiN or SiO2.

4. The method for preparing a semiconductor structure according to claim 1, wherein, The protective layer is specifically formed by chemical vapor deposition.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The formation of the overlapping structure includes the steps of: covering a metal layer on the exposed protective layer and the subsequent oxide layer, forming an anti-reflection layer and a mask layer on the metal layer, and etching the metal layer with this mask layer as a mask and using the protective layer as an etch stop layer to form the overlapping structure.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein After forming the isolation layer on the substrate, form a zero-layer marking layer as a subsequent alignment layer.

7. The method for preparing a semiconductor structure according to claim 2 or 5, characterized in that, After forming the first metal structure layer or the overlapping structure, it also includes the step of removing the anti-reflection layer and the mask layer.

8. The manufacturing method of the semiconductor structure according to any one of claims 1-6, characterized in that, The material of the first metal structure layer includes titanium, tantalum, aluminum, iron, copper-based materials or a combination thereof; and / or the material of the second metal layer includes titanium, tantalum, aluminum, iron, copper-based materials or a combination thereof.

9. A semiconductor structure, characterized in that, It is prepared by using the preparation method of the semiconductor structure described in any one of claims 1-8.

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