Semiconductor wafer including test structure

Abstract

Disclosed is a semiconductor wafer including a test structure.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor wafers including test structures. Background Art

[0002] Forming semiconductor devices such as transistor devices, diodes, etc. may include forming multiple semiconductor devices on a wafer using the same manufacturing process. The wafer includes multiple semiconductor bodies and kerf regions arranged between the semiconductor bodies, the multiple semiconductor bodies being regions of the wafer including active device regions of the semiconductor devices. At the end of the manufacturing process, the wafer is separated to obtain multiple individual semiconductor bodies (bare die, chips) that can ultimately be packaged.

[0003] Forming a semiconductor device may include multiple process sequences. These process sequences may include an implantation process in which dopant atoms are implanted into a semiconductor body included in a wafer. In order to be able to monitor the quality of the manufacturing process, test structures may be formed in the cutout region. These test structures, which may also be referred to as PCM (process control monitoring) structures, are formed by the same manufacturing process that is used to form the semiconductor device. The quality of the manufacturing process can be evaluated, for example, by measuring the electrical properties of the test structures. In order to be able to measure the electrical properties of the test structures, one or more test pads connected to the test structures are formed above the cutout region.

[0004] Measuring the electrical characteristics of the test structure can include contacting a probe of a test device with a test structure electrode. The test structure electrode is very small and may only have a size of several thousand square microns. During the evaluation process, it is necessary that the probe is in correct contact with the test pad. Conventional test pads include a conductive material that is not as hard as the conductive material of the probe, so the probe will leave a mark on the test pad. After the measurement process, the position of the mark on the test pad can be evaluated by optical inspection to evaluate whether the probe is correctly aligned with respect to the test pad and has contacted the test pad.

[0005] This type of optical inspection is not possible when the test pads contain a material as hard as the material of the probe needle, such as tungsten (W). In this case, the probe needle will hardly leave a mark on the test pads. Summary of the invention

[0006] An improved test structure is needed.

[0007] One example relates to a test structure. The test structure includes a pad arrangement arranged above a kerf region of a semiconductor wafer. The pad arrangement includes: a contact pad arranged side by side along a first direction; and two alignment pads arranged side by side with the contact pad along the first direction, such that the contact pad is arranged between the two alignment pads. Each contact pad comprises a metal, and each of the alignment pads is different from each of the contact pads and is configured to be irreversibly deformed when contacted by a probe needle. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following examples are explained with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles, and therefore only the aspects necessary for understanding these principles are described. These drawings are not drawn to scale. In the accompanying drawings, the same reference numerals represent the same features.

[0009] Figure 1 schematically shows a top view of a pad arrangement of a test structure, the pad arrangement comprising a number of contact pads arranged side by side and between two alignment pads;

[0010] Figure 2 schematically shows a top view of a wafer, the wafer comprising a plurality of semiconductor bodies and kerf regions arranged between the semiconductor bodies;

[0011] Figure 3A-3B each showing a detailed view of a portion of a cutout area;

[0012] Figure 4A-4B shows a vertical cross-sectional view and a top view of an alignment pad according to an example;

[0013] Figure 5 shows a vertical cross-sectional view of a contact pad according to an example;

[0014] Figure 6 A detection needle of a detection device is schematically shown;

[0015] Figures 7A-7C shows different scenarios that may occur when a probe needle is brought into contact with a contact pad and an alignment pad;

[0016] Figures 8A-8B shows a top view of the alignment pad before and after contacting the probe needle with the alignment pad;

[0017] Figure 9-10 shows a more detailed view of an alignment pad according to various examples;

[0018] Fig.11 shows a more detailed view of a contact pad according to one example;

[0019] Fig.12 shows a vertical cross-sectional view of a portion of a semiconductor body in which an active region of a transistor device is integrated;

[0020] Fig.13 shows a top view of a transistor device according to an example;

[0021] Fig.14 shows a vertical cross-sectional view of a portion of a cutout region including a test structure according to one example;

[0022] Fig.15 Shows Fig.14 A vertical cross-sectional view of a portion of the test structure shown in;

[0023] Figures 16A-16B Shown according to Fig.14 and 15 Modification of the test structure;

[0024] Fig.17 Shown according to Fig.14 and 15 Further modifications of the test structure; and

[0025] Fig.18 Shown according to Fig.17 Modification of the test structure. DETAILED DESCRIPTION

[0026] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings form part of the specification and, for illustrative purposes, show examples of how the invention may be used and implemented. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically noted.

[0027] Figure 1 A top view of a pad arrangement 6 of a test structure is schematically shown. The pad arrangement 6 comprises a plurality of contact pads 61-64, which are arranged side by side and spaced apart from each other along a first lateral direction x1. The pad arrangement 6 further comprises two alignment pads 71, 72. The alignment pads 71, 72 are arranged side by side with the contact pads 61-64 along the first lateral direction x1, so that the contact pads 61-64 are arranged between the two alignment pads 72, 71. Each of the two alignment pads 71, 72 is spaced apart from the contact pads 61-64.

[0028] The size of each pad 71, 72, 61-64 is, for example, several thousand square micrometers. According to one example, the pads 71, 72, 61-64 have a rectangular, in particular square, shape with a side length between 50 micrometers and 120 micrometers.

[0029] Regarding the first lateral direction x1, it should be noted that, unless otherwise specified, the “first lateral direction” includes Figure 1 The direction indicated by the arrow marked x1 and the opposite direction.

[0030] Each of the contact pads 61-64 includes a metal, such as tungsten (W) or titanium (Ti).

[0031] The alignment pads 71, 72 are different from the contact pads 61-64. That is, the alignment pads 71, 72 are implemented in a different way than the contact pads 61-64. Each of the alignment pads 71, 72 is configured to be irreversibly deformed when in contact with a probe needle. This will be explained in detail below.

[0032] Figure 1 The pad arrangement shown in FIG. 2 is arranged, for example, above a kerf region 200 of a semiconductor wafer.

[0033] Figure 2 Schematically shown is a top view of a semiconductor wafer 1. The semiconductor wafer 1 comprises a plurality of semiconductor bodies 100 and a kerf region 200 which is arranged between the semiconductor bodies 100 and separates the semiconductor bodies 100 from each other. The kerf region 200 may also be referred to as a kerf portion 200 of the wafer 1.

[0034] The wafer is, for example, a continuous single-crystal semiconductor wafer, which is separated at the end of the manufacturing process to obtain a plurality of individual semiconductor bodies (bare dies) 100. The single-crystal semiconductor material is a conventional single-crystal semiconductor material, such as, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc. Since the wafer is a single-crystal wafer, there is no visible boundary between the semiconductor body 100 on the wafer 1 and the cutout area 200.

[0035] In the manufacturing process, a device region of the semiconductor device is formed in the semiconductor body 100. The manufacturing process may include an implantation process, wherein in each implantation process, dopant atoms are implanted into a predetermined region of the semiconductor body 100. The manufacturing process may also include forming an insulating layer and an electrode layer over the wafer 1 before separating the wafers.

[0036] The number of semiconductor bodies 100 in the wafer 1 depends on the size of the individual semiconductor bodies 100 and the size of the wafer 1. The total number is, for example, between several tens and several hundred. The wafer 1 is separated, for example, by sawing along the kerf area 200. In this way, at least part of the kerf area 200 is removed.

[0037] Referring to the above, the pad device 6 may be arranged above the kerf region 200 of the wafer. More specifically, the pad device 6 may be arranged in or above the insulating layer 5 formed on top of the semiconductor body 100 and the kerf region 200 of the wafer. However, the insulating layer 5 is not formed on the top of the semiconductor body 100 and the kerf region 200 of the wafer. Figure 2 is shown in .

[0038] Figure 3A and 3B Each shows an enlarged view of a portion D of a wafer 1, wherein Figure 3A and Figure 3B The portion D shown in FIG. 1 comprises a portion of the cutout region 202 and portions of two semiconductor bodies 100 arranged adjacent to the cutout region 200 shown on opposite sides. Figure 3A and 3B Two different examples for arranging a gate pad arrangement over the cutout region 200 are shown.

[0039] according to Figure 3A , the lateral direction x1 along which the contact pads and the alignment pads are arranged side by side corresponds to the direction along which two semiconductor bodies 100 adjacent to the kerf region 200 are spaced apart from each other. In this case, the lateral direction x1 may be substantially perpendicular to the line along which the wafer 1 is finally separated.

[0040] according to Figure 3B , the lateral direction x1 along which the contact pads and the alignment pads are arranged side by side corresponds to a direction substantially perpendicular to the direction along which two semiconductor bodies 100 adjoining the kerf region 200 are spaced apart from each other. In this case, the lateral direction x1 may be substantially parallel to the line along which the wafer 1 is ultimately separated.

[0041] Figure 4A and 4B An alignment pad 70 is shown according to one example. Figure 4A and 4B Reference numeral 70 in FIG. 1 denotes either one of the two alignment pads 71 ​​, 72 explained above. Figure 4A A vertical cross-sectional view of the alignment pad 70 is shown, Figure 4B More specifically, Figure 4A A vertical cross-sectional view of a portion of the insulating layer 5 in which the alignment pad 70 is formed is shown.

[0042] refer to Figure 4A and 4B, the alignment pad 70 includes a plurality of elements 701 that are spaced apart from each other and separated from each other by grooves 702 and are configured to be broken when in contact with a probe needle. The cross-sectional area of ​​each of these elements 701 is, for example, less than 1 square micrometer. The grooves 702 extend from the first surface 501 of the insulating layer 5 into the insulating layer 5 and define the elements 701. The insulating layer 5 is, for example, an oxide layer. Figure 4A and 4B In FIG. 7 , only element 701 is schematically shown. The total number of pins aligned to pad 70 may range between several hundred and several thousand.

[0043] With reference to Fig. 4, each element may each have a needle shape. Element 701 is therefore also referred to as a needle hereinafter. However, the shape of each element is not limited to a needle shape. On the contrary, each element 701 may be implemented with any other shape that enables each element 701 to break when in contact with a probe needle. Each element 701 may have the same shape. However, one alignment pad may also be implemented as an element 701 having different shapes.

[0044] Figure 5 A vertical cross-sectional view of one contact pad 60 according to one example is schematically shown. Figure 5 Reference numeral 60 in FIG. 6 represents any one of the contact pads 61 - 64 explained previously. Figure 5 In the example shown in , the contact pad 60 is formed on top of the surface 501 of the insulating layer 5 . Figure 5 There is shown a vertical cross-sectional view of the insulating layer 5 and the contact pad 60. Referring to above, the contact pad 60 comprises a metal such as tungsten or titanium.

[0045] According to an example, the pad arrangement 6 is used to make contact between the doping test area arranged in the cutout area 200 and a test device. The test device may include a plurality of probe pins. An example of the probe pin arrangement is Figure 6 , the probe needle device is configured to be able to contact with a pad device 6 of the type explained before. In this example, the probe needle device comprises a plurality of needles arranged side by side along the second lateral direction x2. The needles may include contact needles 301-304 and alignment needles 401, 402.

[0046] The alignment pins 401, 402 are arranged side by side with the contact pins 301-304, so that the contact pins 301 to 304 are arranged between the alignment pins 401 and 402. The contact pins 301-304 on the one hand and the alignment pins 401-402 on the other hand can be implemented in the same way. However, the contact pins 301-304 and the alignment pins 401, 402 have different functions.

[0047] For example, each of the contact pins 301-304 is configured to be able to make electrical contact with a corresponding one of the contact pads 61-64 so as to drive a current into the corresponding contact pad 61-64 or measure a voltage between two contact pads 61-64. Each of the alignment pins 401-402 is configured to be able to make physical contact with a corresponding one of the alignment pads 71, 72, and to be able to irreversibly deform the corresponding alignment pad 71, 72 when in contact with the corresponding one of the alignment pads 71, 72.

[0048] During the measurement process, alignment pins 401, 402 are brought into contact with alignment pads 71, 72, while contact pins 301-304 are brought into contact with contact pads 61-64. After the measurement process, by optical inspection of alignment pads 71, 72, information can be obtained on how well the pin arrangement and pad arrangement were aligned during the measurement process.

[0049] Different scenarios for aligning the probe needle device relative to the pad device 6 are Figures 7A-7C Each of these figures schematically shows a top view of the alignment pads 71, 72 and the contact pads 61-64 of the pad arrangement 6 and a top view of the alignment pins 401, 402 and the contact pins 301-304 during one measurement process.

[0050] Fig. 7A An example is shown, in which the probe pin arrangement is fully aligned relative to the pad arrangement 6. That is, each of the alignment pins 401, 402 contacts the corresponding alignment pad 71, 72 substantially at the center of the corresponding alignment pad 71, 72, and each of the contact pins 301-304 contacts the corresponding contact pad 61-64 substantially at the center of the corresponding contact pad 61-64.

[0051] Figure 7B A scenario is shown wherein the direction x2 along which the needles 401 , 402 , 301 - 304 are arranged side by side is substantially parallel to the first direction x1 , but the probe needle arrangement is offset relative to the pad arrangement 6 in a lateral direction y1 substantially perpendicular to the first direction x1 . Figure 7B A worst case scenario is shown, where each of the pins 401, 402, 301-304 does not make contact with the corresponding pad 71, 72, 61-64.

[0052] Figure 7CA scenario is shown in which the probe needle arrangement is tilted relative to the pad arrangement 6 so that the direction x2 along which the needles 401, 402 are arranged side by side is not parallel to the first direction x1. In this scenario, some of the probe needles (302, 303, 304) may contact the corresponding pads, while other probe needles (401, 301, 402) may not contact the corresponding pads.

[0053] Fig. 8A A top view of one alignment pad 70 is shown before the measurement process, ie, before the corresponding alignment pin is brought into physical contact with the alignment pad 70 . Figure 8B A top view of the alignment pad 70 is shown after the measurement process, i.e. after the corresponding alignment pins are in contact with the alignment pad. Referring to the above, the alignment pins cause the alignment pad to be irreversibly deformed. That is, the alignment pins cause some of the pins to break, leaving an imprint 730 including the broken pins.

[0054] Based on the position of the markings 730 on each of the alignment pads 71, 72, the alignment of the probe needle arrangement relative to the pad arrangement 6 during the measurement process can be assessed. Based on this assessment, the needle arrangement can be appropriately readjusted if necessary.

[0055] According to an example, the contact pins 301-304 comprise a metal that is as hard as the metal of the contact pads 61-64, so that the contact pins 301-304 do not leave noticeable marks on the contact pads 61-64. Therefore, the alignment of the pin arrangement relative to the pad arrangement 6 can be assessed based on the alignment pads 71, 72 being irreversibly deformed by the alignment pins 401, 402. It should be noted that the alignment pins 401, 402 do not necessarily comprise the same material as the contact pins 301-304 and that the alignment pins 401 and 402 are not necessarily electrically conductive.

[0056] Fig. 9 A vertical cross-sectional view of an alignment pad 70 according to an example is shown in more detail. Fig. 9 In the example shown in , the groove 702 defining the needle 701 in the insulating layer 5 extends through the insulating layer 5 down to the surface 201 of the wafer located in the kerf region 200. In some cases, the manufacturing process of the semiconductor device formed based on the wafer may include a process performed after forming the alignment pad 70, and the process may involve a substance that etches the semiconductor material of the wafer 1 relative to the material of the insulating layer 5. In this case, the portion of the wafer below the needle 701 may be removed, so that some of the needles may have fallen off during the manufacturing process. This can be avoided by providing a thicker insulating layer 5 on top of the surface 201 so that the groove 702 does not extend completely through the insulating layer 5 to the wafer surface 21. However, in some cases, such a thick insulating layer 5 is not ideal.

[0057] Fig.10 Shows Fig.10 A modification of the alignment pad 70 shown in FIG. Fig.10 In the example shown in , the alignment pad 70 is formed above the insulating trench 51, which extends from the surface 201 into the kerf region 200 of the wafer, and the insulating trench 51 is filled with an insulating layer 52. The alignment pad 70 is formed so that the bottom of the trench 702 defining the needle 701 is spaced apart from the bottom of the insulating trench 51. The insulating layer 52 filling the insulating trench 51 may include the same material as that of the insulating layer 5, and is, for example, an oxide. Fig.10 In the example shown in , the bottom of the trench 702 defining the needle 701 abuts the insulating layer 52 filling the trench 51 , so that no semiconductor region is exposed at the bottom of the trench 702 defining the needle 701 .

[0058] With reference to the above, various types of semiconductor devices may be implemented based on the semiconductor body 100 of the wafer 1. According to one example, the semiconductor device implemented based on the semiconductor body 100 is a transistor device. Fig.12 A vertical cross-sectional view of a portion of a semiconductor body 100 is shown, in which portion an active region of a transistor device is integrated.

[0059] refer to Fig.12 , the semiconductor body 100 comprises an inner region 130 in which the transistor cells 10 of the transistor device are implemented and an edge region 140 surrounding the inner region in a lateral direction. In the finished transistor device, i.e. after the wafer 1 is separated, the edge region 140 is located between the sidewalls of the semiconductor body 100 and the inner region 130. The sidewalls are caused by separating the wafer 1 and terminate the semiconductor body 100 in a lateral direction. The lateral direction is a direction substantially parallel to the first surface 101 and the second surface 102 of the semiconductor body 100.

[0060] refer to Fig.12 Each transistor cell 10 comprises a source region 11 of a first doping type, a body region 12 of a second doping type complementary to the first doping type, and a gate electrode 21. The gate electrode 21 is adjacent to the body region 12 and is dielectrically insulated from the body region 12 by a gate dielectric 22, and is arranged in a gate trench 120 extending from a first surface 101 of the semiconductor body 100 into the semiconductor body 100.

[0061] refer to Fig.12, the source region 11 and the body region 12 of two adjacent transistor cells 10 can be arranged in the mesa region between adjacent gate trenches 120. In this example, the body region 12 of the two adjacent transistor cells 10 can be formed by a continuous doping region of the second doping type. In addition, the two (other) adjacent transistor cells can share the gate electrode 21. That is, the gate electrode 21 of the two adjacent transistor cells can be formed by a continuous electrode arranged in one gate trench 120.

[0062] The gate electrode 21 includes a conductive material. Examples of the conductive material include doped polysilicon, or metal. The gate dielectric 22 includes, for example, an oxide. According to one example, the oxide is silicon oxide (SiO 2 ).

[0063] refer to Fig.12 The transistor device further comprises a source electrode 41 which is arranged above the first surface 101 and is separated from the semiconductor body 100 and the gate electrode 21 by an insulating layer. The insulating layer 5 separating the source electrode 41 from the semiconductor body 100 may be the same insulating layer as follows: On top of the same insulating layer, the pad arrangement 6 (on Fig.12 Contact pads 61-64 (not shown) are arranged above the kerf region 200 of the wafer 1. The source electrode 41 forms a source node S or is connected to a source node S of a transistor device.

[0064] The source electrode 41 is electrically connected to the source region 11 and the body region 12 of the transistor cell 10. Fig.12 In the example shown in , the source electrode 41 is connected to the source region 11 and the body region 12 by means of a conductive via 45 which extends from the source electrode 41 through the insulating layer 5 down to the source region 11 and the body region 12 .

[0065] Optionally, a body contact region 17 of the second doping type is arranged between the via 45 and the body region 12 . The body contact region 17 has a higher doping concentration than the rest of the body region 12 and is used to provide an ohmic contact between the via 45 and the body region 12 .

[0066] refer to Fig.12 , the transistor device further includes a drift region 14 of the first doping type. The drift region 14 is adjacent to the body region 12 of the transistor cell 10, so that a PN junction is formed between the body region 12 of the second doping type and the drift region 14 of the first doping type. In addition, in the vertical direction z of the semiconductor body 100, the drift region 14 is arranged between the body region 12 and the drain region 13 of the first doping type. The drain region 13 may be adjacent to a second surface 102 opposite to the first surface 101. The vertical direction z is a direction substantially perpendicular to the first surface 101 and the second surface 102.

[0067] Optionally, a buffer region 16 of the first doping type and having a doping concentration that is higher than the doping concentration of the drift region 14 and lower than the doping concentration of the drain region 13 is arranged between the drift region 14 and the drain region 13 .

[0068] refer to Fig.12 And as explained above, the gate trenches with the gate electrode 21 can be spaced apart from each other in the first lateral direction x of the semiconductor body 100. According to one example, the gate electrode 21 is implemented as a strip electrode (strip electrode). In this example, the longitudinal direction of the gate electrode 21 corresponds to a second lateral direction y perpendicular to the first lateral direction x.

[0069] According to one example, the transistor device is implemented as a super junction transistor device. In this example, the transistor device includes a plurality of compensation regions 15 (shown in dashed lines) spaced apart from each other in a lateral direction of the semiconductor body 100. Each of the compensation regions 15 is adjacent to a corresponding portion of the drift region 14.

[0070] For illustrative purposes only, Fig.12 In the example shown in , the compensation regions 15 are spaced apart from one another in a first lateral direction x of the semiconductor body 100 . According to another example (not shown), the compensation regions 15 are spaced apart from one another in a second lateral direction y of the semiconductor body 100 .

[0071] The transistor device can be operated in an on state or an off state. In the on state, a conductive path exists between the source region 11 and the drift region 14 along the gate dielectric 22 in the body region 12. To this end, the drift region 14 adjoins the gate dielectric 22 and the body region 12 of at least one of the transistor cells 10.

[0072] Furthermore, each of the optional compensation regions 15 is adjacent to at least one of the portions of the drift region 14 and is connected to the source electrode 41 . Fig.12 In the example shown in , each of the compensation regions 15 adjoins the body region 12 of at least one transistor cell and is connected to the source electrode 41 via the corresponding body region 12 .

[0073] The transistor device can be operated in a conventional manner by applying a driving voltage (gate-source voltage) between the gate electrode 21 and the source electrode 41. When the driving voltage causes a conductive channel to be generated in the body region 12 between the source region 11 and the drift region 14 along the gate dielectric 22, the transistor device is in an on state (conductive state). When the conductive channel is interrupted, the transistor device is in an off state (blocking state).

[0074] The transistor device can be implemented as an N-type transistor device or a P-type transistor device. When the driving voltage is higher than a predefined positive threshold voltage, the N-type transistor device is, for example, in an on state, and when the driving voltage is lower than the threshold voltage, the N-type transistor device is in an off state.

[0075] In an N-type transistor device, the doped region of the first doping type is an N-type region and the doped region of the second doping type is a P-type region. In a P-type transistor device, the doped region of the first doping type is a P-type region and the doped region of the second doping type is an N-type region.

[0076] The source region 11 , the body region 12 , the drift region 14 and the compensation region 15 , the buffer region 16 , and the drain region 13 may also be referred to as (active) device regions of the transistor device.

[0077] Fig.12 A portion of an edge termination structure of a transistor device is further shown. The edge termination structure is arranged in and above an edge region 140 of the semiconductor body 100. According to an example, the edge termination structure comprises an edge trench 53 extending from the first surface 101 into the edge region 140 of the semiconductor body 100 and filled with an electrically insulating layer 54. The edge trench 53 with the insulating layer 51 may surround the inner region 130 in a lateral direction.

[0078] According to an example, Fig.10 The insulating trench 51 below the alignment pad 70 and the insulating layer 52 filling the insulating trench 51 shown in FIG. 5 are formed by the same process as that for forming the edge trench 53 of the edge termination structure of the transistor device and the insulating layer 54 filling the edge trench 53 .

[0079] refer to Fig.12 The edge termination structure may further include a field electrode 31 arranged over the edge trench 53 and electrically connected to the gate runner 42. The gate runner is formed over the insulating layer 42 and connected to the field electrode 31 through a conductive via 46. The field electrode 31 includes, for example, doped polysilicon.

[0080] The gate runner 42 is connected to a gate pad 43 which forms the gate node of the transistor device. Fig.13 is shown in Fig.13 FIG. 1 shows a top view of a transistor device (after separation of the wafer) according to one example. Fig.13 In FIG. 1 , reference numerals 103 to 106 denote sidewalls of the semiconductor body 100. The transistor unit is Fig.13 For illustration purposes only, the strip-shaped gate electrodes 21 arranged below the source electrodes 41 of some transistor cells 21 are not visible in FIG. Fig.13Each of the gate electrodes 21 is connected to the gate flow channel 42 at at least one of its longitudinal ends. However, the connection between the gate electrode 21 and the gate flow channel 42 is not Fig.13 is shown in .

[0081] The edge termination structure may further include a drain runner 44 (shown in dotted lines) arranged above the insulating layer 5. The drain runner may be connected to the drain region 13 or the buffer region 16 through a field stop region (not shown) of a first doping type that is arranged close to the sidewalls 103-106 and extends from the drain region 13 or the buffer region 16 to the first surface 101.

[0082] Fig.12 The vertical cross-section shown in corresponds to e.g. Fig.13 Vertical cross-sectional view in the cross-sectional plane AA shown in .

[0083] The drift region and the compensation region may also be formed in the edge region 140 , wherein reference numeral 14 ′ denotes a drift region arranged in the edge region 140 , and reference numeral 15 ′ denotes a compensation region arranged in the edge region 140 .

[0084] refer to Fig.12 , source electrode 41 and gate flow channel 42 (and equivalently Fig.12 Each of the gate pads 43 (not shown in the figure) may include a first conductive layer 411, 421 and a second conductive layer 412, 422. According to an example, the first conductive layers 411, 421 of the source electrode 41 and the gate runner 42 are formed by the same process as the contact pads 61-64 of the gate pad device 6, and therefore include the same material. According to an example, the first conductive layers 411, 421 also form conductive vias 45, 46. That is, the first conductive layers 411, 421 at least partially fill the via trenches in which the vias 45, 46 are formed.

[0085] The second conductive layers 412 , 422 may be thicker than the first conductive layers 411 , 412 , and may include, for example, aluminum (Al), copper (Cu), or an aluminum-copper alloy.

[0086] Fig.14 An example of a test structure is shown in more detail. More specifically, Fig.14 A vertical cross-sectional view of a portion of a wafer located in a kerf region 200, an insulating layer 5 formed on top of the kerf region 200, and a test structure is shown. In this example, a pad arrangement is formed on top of the insulating layer 5 and includes contact electrodes 61-66. The alignment pads are Fig.14 Not shown.

[0087] The wafer may include multiple epitaxial layers formed on top of a semiconductor substrate. Fig.14 1, reference numeral 210 denotes a portion of a substrate and reference numeral 220 denotes a portion of an epitaxial layer arranged in an edge region (edge ​​portion) 200 of the wafer 1. In the semiconductor body 100, the substrate may form the respective drain regions 13 explained above. In the super junction transistor device, the drift region 14 and the compensation region 15 may be formed by implanting dopant atoms into the epitaxial layer and by activating the implanted dopant atoms in one or more annealing processes.

[0088] Figure 1 The test structure shown in FIG. 1 includes a doped test region 8 in one of the epitaxial layers 221 and can be used to evaluate (monitor) the implantation and annealing processes in the corresponding epitaxial layer 221. The doped test region 8 is formed by the same process as the underlying one, in which dopant atoms are implanted into the respective epitaxial layers in the semiconductor body 100 and the implanted dopant atoms are activated.

[0089] The doped test region 8 is connected to the contact pads 61-66 through doped contact regions 91-96, which extend from the doped test region 8 to the first surface 201 of the wafer 1 in the edge region 200, and each doped contact region is connected to the corresponding contact pad 61-66 through a corresponding conductive via 611-661 formed in the insulating layer 5. The doped contact regions 91-96 may extend through additional epitaxial layers and may be formed by implanting dopant atoms into the other epitaxial layers at corresponding locations to form the doped contact regions 91-96.

[0090] Fig.15 A horizontal cross-sectional view of a doped test region according to an example is shown. That is, Fig.15 2 shows a horizontal cross-sectional view of a portion of the epitaxial layer 221 in which the doping test region 8 is arranged. The contact regions 91-96 formed between the dopant test region 8 and the surface 201 are located at Fig.15 It is shown in dashed lines.

[0091] The doping test area 8 includes at least one of three different areas: a first test area 81, a second test area 82, and a third test area 83. For illustration purposes only, Fig.15 The doping test region 8 shown in FIG. 8 includes each of a first test region 81 , a second test region 82 , and a third test region 83 .

[0092] refer to Fig.15 , the first test region 81 is a substantially uniformly doped region 811 of a first doping type, which may be the same doping type as the drift region 14 , 14 ′ in the transistor device explained before.

[0093] refer to Fig.15 , the second test region 81 may include a plurality of strip-shaped doping regions 821 of the first doping type. The longitudinal direction of these strip-shaped doping regions 821 may correspond to the first direction x1 along which the contact pads 61-66 are arranged side by side. In addition, the strip-shaped doping regions 821 are spaced apart from each other in a direction y1 perpendicular to the longitudinal direction.

[0094] The length of the strip-shaped doped regions 821 (which is the dimension of these regions in the first direction x1) is, for example, between 50 μm and 250 μm. The width of the strip-shaped doped regions 821 as the dimension of these regions in the second direction y1 and the mutual spacing are, for example, in the range of between 1.5 μm and 5 μm.

[0095] Before dopant atoms are implanted, the epitaxial layer 221 in which the doped test region 8 is formed may have a (low) basic doping. Regions 822 of the second test region arranged between the strip-shaped doped regions 821 may have the basic doping of the epitaxial layer 221 .

[0096] refer to Fig.15 , the third test region 83 may include a plurality of first doping regions 831 of a first doping type and a plurality of second doping regions 832 of a second doping type complementary to the first doping type. The longitudinal directions of the first doping regions 831 and the second doping regions 832 may correspond to the first direction x1. The first doping regions 831 and the second doping regions 832 are alternately arranged in a direction y1 perpendicular to the longitudinal directions of the first doping regions 831 and the second doping regions 832.

[0097] The length of the strip-shaped first and second doped regions 821 (which is the dimension of these regions in the first direction x1) is, for example, between 50 μm and 250 μm. The width of these regions in the second direction y1 is, for example, in the range of between 1.5 μm and 5 μm.

[0098] exist Fig.15 In the example shown in , the first test area 81 , the second test area 82 , and the third test area 83 are arranged side by side in the first direction x1 .

[0099] Based on the electrical characteristics of the first test area 81, the second test area 82, and the third test area 83, the implantation and annealing processes can be evaluated. According to one example, the resistance of the first test area 81, the second test area 82, and the third test area 83 can be measured. Measuring the resistance can include driving a current through the three test areas 81, 82, and 83 via the contact pads 61, 66 and the corresponding contact areas 91, 96. Between the locations where the contact areas 91, 96 are connected to the doped test area 8, the first test area 81, the second test area 82, and the third test area 83 are arranged side by side.

[0100] Measuring the resistance of the first test area 81 may include measuring the voltage between the contact pads 62, 63, which are connected to the first test area 82 at positions spaced apart from each other along the first direction x1 through corresponding contact areas 92, 93. Measuring the resistance of the second test area 82 may include measuring the voltage between the contact pads 63, 64, which are connected to the second test area 82 at positions spaced apart from each other along the first direction x1 through corresponding contact areas 93, 94. Measuring the resistance of the third test area 83 may include measuring the voltage between the contact pads 64, 65, which are connected to the third test area 82 at positions spaced apart from each other along the first direction x1 through corresponding contact areas 94, 95. The resistance of each test area 81, 82, 83 is given by the voltage measured across each test area divided by the current driven through each of the test areas 81, 82, 83.

[0101] The same contact pad can be used to measure the voltage across two of the test areas 81, 82, 83. Fig.15 In the example shown in FIG. 8 , for example, contact pad 63 is used to measure a voltage across first test region 81 and to measure a voltage across second test region 82. Likewise, contact pad 64 is used to measure a voltage across first test region 82 and to measure a voltage across third test region 83.

[0102] according to Fig.16A and 16B In one example shown in FIG. 8 , the doped test region 8 is surrounded by a shielding region 80 of the second doping type. Fig.16A A vertical cross-sectional view of the edge region 200 is shown in section, the section including the Fig.14 and 15 The doped test region 8 and the corresponding contact regions 91 - 96 are of one of the types. Fig. 16B A top view of the edge portion 20 is shown. The insulating layer and the gate pad are not shown in these figures.

[0103] refer to Fig.16A , the shielding region includes a bottom portion 801 arranged between the doped test region 8 and the substrate 210 and a sidewall portion 802 adjacent to the bottom portion 801 and surrounding the doped test region 8 in a lateral direction. The shielding region 80 may be formed by implanting second type dopant atoms into an epitaxial layer that is formed on the substrate 210 in a stacked form.

[0104] Fig.17 A test structure according to another example is shown. Fig.17In the example shown in FIG. 1 , two doped test areas, a first doped test area 8a and a second doped test area 8b, are arranged in the same shielding area 18. Each of the test areas 8a, 8b is, for example, arranged according to reference Fig.15 The example explained. Each of the doped test regions 8a, 8b is connected to a corresponding contact pad 61a-66a, 61b-66b. The contact pads 61a-66a, 61b-66b are arranged side by side along the first direction x1 and arranged between two alignment pads 71, 72. The doped test regions 8a, 8b are arranged in different epitaxial layers 221a, 221b.

[0105] exist Fig.17 In the example shown in , contact pads 61a, 66a may be used to drive current through the first doped test region 8a, and contact pads 61b, 66b may be used to drive current through the second doped test region 8b.

[0106] Fig.18 Shows Fig.17 A modification of the test structure shown in . Fig.18 In the example shown in , contact pad 61ab is connected to both test areas 8a, 8b through corresponding contact area 91ab. Contact pad 61ab together with contact pad 61a can be used to drive current through first test area 8a in a first measurement sequence, and contact pad 61ab together with contact pad 66b can be used to drive current through second test area 8b in a second measurement sequence.

Claims

1. A test structure, comprising: A pad device (6) is arranged above a kerf area (200) of a semiconductor wafer (1) and comprises: contact pads (60; 61-66), the contact pads (60; 61-66) being arranged side by side along a first direction (x1); and two alignment pads (70; 71, 72), the two alignment pads (70; 71, 72) being arranged side by side with the contact pads (61-66) along a first direction (x1), so that the contact pads (61-66) are arranged between the two alignment pads (71, 72), wherein each of the contact pads (60; 61-66) comprises metal, and Each of the alignment pads is different from each of the contact pads (61-66) and is configured to be irreversibly deformed when in contact with a probe (401, 402).

2. The test structure according to claim 1, in, The metal includes one of tungsten and titanium.

3. The test structure according to claim 1 or 2, in, Each of the alignment pads (70; 71, 72) includes a plurality of elements (701) which are spaced apart from each other and are configured to be broken upon contact with a probe needle (401, 402).

4. The test structure according to claim 3, in, The element (701) comprises an oxide.

5. The test structure according to claim 3 or 4, in, The elements (701) are separated from each other by grooves (702) extending from a surface (501) of the insulating layer (5) into the insulating layer (5).

6. The structure according to any one of claims 3 to 5, wherein: The element has the shape of a needle.

7. The test structure according to claim 5 or 6, in, The contact pads (60; 61-66) are formed above the surface (501) of the insulating layer (5).

8. The test structure according to claim 6 or 7, in, The groove (702) extends to the surface (201) of the cutout region (200).

9. The test structure according to claim 6 or 7, wherein: Each of the alignment pads (70; 71, 72) is formed above an insulating trench (51), the insulating trench (51) extending from a surface (201) of the cutout region (200) into the cutout region (200) and filled with an insulating layer (52), The bottom of the groove (702) separating the needles (701) is spaced apart from the bottom of the insulating groove (51).

10. A test structure according to any one of the preceding claims, wherein: The test structure also includes: A doped test region (8) is in the kerf region (200) of the wafer (1) and is connected to the contact pads (61-62).

11. The test structure according to claim 10, in, The doped test region (8) is connected to the contact pad through a doped contact region (91-96) arranged in the cutout region (200) and a conductive via (611-661) arranged in the insulating layer (5).

12. The test structure according to claim 10 or 11, wherein: The doping test area (8) includes at least one of the following: a first region (81) of a first doping type; a second region (82), the second region (82) comprising a plurality of strip-shaped doping regions (821) of the first doping type, the plurality of strip-shaped doping regions (821) being spaced apart from each other in a direction perpendicular to a longitudinal direction of the doping regions (821); as well as A third region (83), the third region (83) comprising a plurality of strip-shaped first doping regions (831) of the first doping type and a plurality of strip-shaped second doping regions (832) of a second doping type complementary to the first doping type, wherein the first doping regions (831) and the second doping regions (832) are alternately arranged in a direction perpendicular to a longitudinal direction of the first doping regions (831) and the second doping regions (832).

13. The test structure according to claim 12, wherein: The doping test area (8) includes each of the first area (81), the second area (82) and the third area (83), The first region, the second region and the third region are arranged adjacent to each other in a direction corresponding to a longitudinal direction of the doping region (821) of the second region (82) and the first doping region (831) and the second doping region (832) of the third region (83).

14. A test structure according to claim 12 or 13, in, The doping test region (8) is arranged in the epitaxial layer (221) of the wafer (1).

15. The test structure according to claim 14, wherein: The doped test region is a first doped test region (8a), the epitaxial layer is a first epitaxial layer (221a), and The test structure further includes at least one second doped test region (8b) arranged in a second epitaxial layer (221b) different from the first epitaxial layer (221a).

16. The test structure according to claim 15, wherein: Contact pads connected to the first doped test region (8a) and the second doped test region (8b) are arranged side by side along the first direction (x1) and between the two alignment pads (71, 72).

17. The test structure according to any one of claims 12 to 16, wherein: The test structure further comprises a doping shielding region (80) of the second doping type, the doping shielding region (80) surrounding the doping test region (8) in the kerf region (200) of the wafer (1).

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