Placement method, device and equipment of semiconductor test structure and medium

Abstract

The invention provides a semiconductor test structure placing method, device and equipment and a medium, and the method comprises the steps: obtaining a to-be-tested target region on a wafer; the positions of a plurality of main chip areas and a plurality of cutting channel areas are counted on the target area, and the cutting channel areas are located on the peripheral sides of the main chip areas; photoetching marks are placed in part of the cutting channel areas, and other cutting channel areas are marked as placing areas of the test structure; based on preset position information of the to-be-placed test structure, comparing the to-be-placed test structure with a placement rule in a placement rule base, and obtaining a current placement rule corresponding to the to-be-placed test structure; according to the priority order of the current placement rule, grid division is carried out on the target area in sequence, and different grid areas and corresponding grid coordinates are obtained; and according to the priority order of the current placement rule, placing the corresponding to-be-placed test structure in the grid area of the placement area. According to the invention, the placement efficiency of the test structure can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method, device, equipment and medium for placing a semiconductor test structure. Background Art

[0002] In the field of semiconductor manufacturing, for example, in a standard area (Frame) for testing on a wafer, test structures (Testkey) are placed at different positions in the standard area for testing, which can test performance deviations caused by slight deviations in the manufacturing process. Currently, for test structures that require placement at different positions, it is impossible to implement an automatic placement process in the standard area. Manual selection and placement of the coordinate position of the test structure is inefficient and prone to errors. Therefore, there is room for improvement. Summary of the invention

[0003] The present invention provides a method, device, equipment and medium for placing a semiconductor test structure, so as to solve the technical problems in the prior art of manually selecting and placing the coordinate position of the test structure, which is inefficient and prone to errors.

[0004] The present invention provides a method for placing a semiconductor test structure, comprising: On the wafer, obtaining a target area to be tested; On the target area, counting the positions of a plurality of main chip areas and a plurality of cutting lane areas, wherein the cutting lane areas are located at the periphery of the main chip area; Placing photolithography marks in some of the scribe line areas, and marking other scribe line areas as test structure placement areas; Based on the preset position information of the test structure to be placed, the placement rules in the placement rule library are compared to obtain the current placement rule corresponding to the test structure to be placed, wherein the placement rule in the placement rule library is characterized by placing different test structures according to the corresponding position information on the placement area; According to the priority order of the current placement rules, the target area is grid-divided in sequence to obtain different grid areas and corresponding grid coordinates, wherein the correlation between the grid area and the grid coordinates of the test structure to be placed is related to the priority order of the current placement rules; According to the priority order of the current placement rule, the corresponding test structure to be placed is placed in the grid area of ​​the placement area.

[0005] In one embodiment of the present invention, the step of comparing the preset position information of the test structure to be placed with the placement rules in the placement rule library to obtain the current placement rule corresponding to the test structure to be placed includes: Based on the position information of the test structure to be placed, obtaining the grid area and corresponding grid coordinates of the test structure to be placed on the target area; According to the priority order of the placement rules in the placement rule library, the correlation between the grid area of ​​the test structure to be placed and the corresponding grid coordinates is analyzed in turn to obtain the current placement rule corresponding to the test structure to be placed, wherein the priority order of the placement rules in the placement rule library is related to the correlation between the grid area and the grid coordinates of different test structures on the target area.

[0006] In one embodiment of the present invention, the step of analyzing the correlation between the grid areas of the test structures to be placed and the corresponding grid coordinates in sequence according to the priority order of the placement rules in the placement rule library comprises: Placement rules with grid area association and grid coordinate association between different test structures are recorded as high-priority placement rules; Placement rules that have grid area association or grid coordinate association between different test structures are recorded as medium priority placement rules; Placement rules that have no grid area association or grid coordinate association between different test structures are recorded as low-priority placement rules; According to the order of high priority, medium priority and low priority of the placement rules, the correlation between the grid areas of the test structure to be placed and the corresponding grid coordinates is analyzed in turn.

[0007] In one embodiment of the present invention, in placement rules of the same priority, the correlation between the grid areas and the corresponding grid coordinates of the test structures to be placed is analyzed in the order from most to least according to the number of grid areas and / or grid coordinates corresponding to the test structures in the placement rules.

[0008] In one embodiment of the present invention, the step of dividing the target area into grids in sequence according to the priority order of the current placement rule to obtain different grid areas and corresponding grid coordinates includes: According to the placement rule with a high priority in the current placement rule, the target area is grid-divided to obtain a corresponding grid area and corresponding grid coordinates; According to the placement rule with a medium priority in the current placement rule, the target area is grid-divided to obtain a corresponding grid area and corresponding grid coordinates; According to the placement rules with low priority in the current placement rules, the target area is grid-divided to obtain corresponding grid areas and corresponding grid coordinates.

[0009] In one embodiment of the present invention, after the step of dividing the target area into grids according to the placement rule with a high priority in the current placement rule to obtain the corresponding grid area and the corresponding grid coordinates, the method further comprises: Placing a first test structure to be placed in a grid area at a corner position of the target area, and recording the grid coordinates of the first test structure; Placing a second test structure to be placed in a grid area at an edge position of the target area, and associating the grid coordinates of the second test structure with the grid coordinates of the first test structure; The third test structure to be placed is placed in the grid area at the center of the target area, and the grid coordinates of the third test structure are associated with the grid coordinates of the second test structure.

[0010] In one embodiment of the present invention, after the step of dividing the target area into grids according to the placement rule with a medium priority in the current placement rule to obtain the corresponding grid area and the corresponding grid coordinates, the method further comprises: Placing a first test structure to be placed in a grid area at an edge position or a corner position of the target area, and recording the grid coordinates of the first test structure; Placing other test structures to be placed on the placement area along the direction of the straight line where the grid coordinates of the first test structure are located; or Placing a second test structure to be placed in a grid area at the center of the target area, and placing another test structure to be placed in a grid area at a corner of the target area, wherein the second test structure and the other test structure form a group of test structures; Another second test structure to be placed is placed in the grid area at the center of the target area, and another other test structure to be placed is placed in the grid area at the corner of the target area. The second test structure and the other test structure form another group of test structures, so that multiple groups of test structures are formed in the placement area.

[0011] The present invention also provides a semiconductor test structure placement device, comprising: A first acquisition unit is used to acquire a target area to be tested on a wafer; A statistical unit, for statistically calculating the positions of a plurality of main chip regions and a plurality of cutting lane regions on the target area, wherein the cutting lane regions are located at the periphery of the main chip region; A recording unit, used to place photolithography marks in part of the scribe line area, and record other scribe line areas as test structure placement areas; A second acquisition unit is used to compare the preset position information of the test structure to be placed with the placement rules in the placement rule library to obtain the current placement rule corresponding to the test structure to be placed, wherein the placement rule in the placement rule library is characterized by placing different test structures according to the corresponding position information on the placement area; a dividing unit, for successively dividing the target area into grids according to the priority order of the current placement rules to obtain different grid areas and corresponding grid coordinates, wherein the correlation between the grid areas and grid coordinates of the test structure to be placed is related to the priority order of the current placement rules; and The placement unit is used to place the corresponding test structure to be placed in the grid area of ​​the placement area according to the priority order of the current placement rule.

[0012] The present invention also proposes an electronic device, comprising a processor, a memory and a communication bus; the communication bus is used to connect the processor and the memory; the processor is used to execute a computer program stored in the memory to implement a semiconductor test structure placement method as described in any one of the above items.

[0013] The present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is used to enable a computer to execute the semiconductor test structure placement method as described in any one of the above items.

[0014] Beneficial effects of the present invention: The present invention proposes a method, device, equipment and medium for placing semiconductor test structures. The unexpected technical effect of the present invention is that after clarifying the preset position information of the test structure to be placed, the current placement rules corresponding to the test structure to be placed can be statistically calculated based on the preset position information and the placement rules in the placement database. In the target area, the corresponding grid area and grid coordinates are divided according to the current placement rules corresponding to the test structure to be placed, and based on the placement requirements of the test structure to be placed at different positions, the automatic placement of the test structure to be placed is realized, thereby improving the placement efficiency of the test structure to be placed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A schematic diagram of the steps of a method for placing a semiconductor test structure provided by an embodiment of the present invention.

[0017] Figure 2 A schematic diagram of the position of semiconductor test structures provided by an embodiment of the present invention arranged in a straight line.

[0018] Figure 3 A schematic diagram of the positions of semiconductor test structures provided by an embodiment of the present invention in multiple groups.

[0019] Figure 4 A schematic diagram of a semiconductor test structure provided by an embodiment of the present invention is provided in a plurality of groups.

[0020] Figure 5 A schematic diagram of the position of a semiconductor test structure arranged in a triangle according to an embodiment of the present invention.

[0021] Figure 6 A schematic diagram of a semiconductor test structure arranged in a triangle according to an embodiment of the present invention.

[0022] Figure 7 A schematic diagram of a semiconductor test structure provided by an embodiment of the present invention in a plurality of arrangements.

[0023] Figure 8 An embodiment of the present invention provides Figure 1 Schematic diagram of step S40 in FIG.

[0024] Fig. 9 An embodiment of the present invention provides Figure 8 Schematic diagram of step S420 in FIG.

[0025] Fig.10 An embodiment of the present invention provides Figure 1 Schematic diagram of step S50 in FIG.

[0026] Fig.11 An embodiment of the present invention provides Fig.10 Schematic diagram of step S60 in FIG.

[0027] Fig.12 An embodiment of the present invention provides Fig.10 Schematic diagram of step S60 in FIG.

[0028] Fig.13 Another embodiment of the present invention provides Fig.10 Schematic diagram of step S60 in FIG.

[0029] Fig.14 A schematic structural diagram of a semiconductor test structure placement device provided by an embodiment of the present invention.

[0030] Fig.15 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0032] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0033] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0034] See also Figures 1 to 15The present invention proposes a method, device, equipment and medium for placing a semiconductor test structure, which can be applied in the field of testing semiconductor devices. For example, in a standard area (Frame) for testing on a wafer, a test structure (Testkey) 50 is placed at different positions in the standard area for testing, and performance deviations caused by slight deviations in the manufacturing process can be tested. The present invention can meet the requirements of placing different test structures 50 at different positions in the standard area by implementing different types of grid area divisions in the standard area. After clarifying the placement positions of multiple test structures 50 to be placed, the present invention can realize the automatic placement of multiple test structures 50 to be placed according to different placement rules corresponding to the test structures 50 to be placed, thereby improving the placement efficiency of the test structures 50 to be placed. The following is a detailed description through specific embodiments.

[0035] See also Figure 1 In one embodiment of the present invention, the present invention provides a method for placing a semiconductor test structure, which may include the following steps.

[0036] Step S10: Acquire a target area to be tested on the wafer.

[0037] Step S20 , counting the positions of a plurality of main chip regions and a plurality of cutting street regions in the target area, wherein the cutting street regions are located at the periphery of the main chip regions.

[0038] Step S30: placing photolithography marks in part of the cutting area, and marking other cutting areas as test structure placement areas.

[0039] Step S40, based on the preset position information of the test structure to be placed, compare with the placement rules in the placement rule library to obtain the current placement rules corresponding to the test structure to be placed, wherein the placement rules in the placement rule library are characterized as placing different test structures according to the corresponding position information on the placement area.

[0040] Step S50, according to the priority order of the current placement rules, the target area is grid-divided in sequence to obtain different grid areas and corresponding grid coordinates, wherein the correlation between the grid area and the grid coordinates of the test structure to be placed is related to the priority order of the current placement rules.

[0041] Step S60: Place the corresponding test structures to be placed in the grid area of ​​the placement area according to the priority order of the current placement rule.

[0042] The following is a detailed description through specific embodiments.

[0043] Step S10: Acquire a target area to be tested on the wafer.

[0044] In one embodiment of the present invention, Figure 2 , Figure 3 and Figure 5 As shown, on the surface of the wafer, a target area 10 that needs to be tested can be found. The target area 10 is a standard area (Frame) on the wafer for testing. By placing a test structure (Testkey) 50 at different positions of the target area 10 for testing, performance deviations caused by slight deviations in the manufacturing process can be tested.

[0045] Step S20 , counting the positions of a plurality of main chip regions and a plurality of cutting street regions in the target area, wherein the cutting street regions are located at the periphery of the main chip regions.

[0046] In one embodiment of the present invention, Figure 4 , Figure 6 and Figure 7 As shown, the target area 10 may include a main die area 20, which refers to the main chip manufactured on the wafer, and is an integrated circuit (IC) that will be cut and packaged into a final product. Each main die area 20 can be manufactured into a completed electronic device, such as a microprocessor, a memory chip, a radio frequency chip, etc.

[0047] Specifically, the number of main chip areas 20 may be tens of thousands, and different main chip areas 20 may be distributed in a rectangular array on the wafer. A cutting path area 30 may be formed around the main chip area 20. After the main chip area 20 has been tested and proved to be qualified, the cutting path area 30 may be cut to cut the main chip area 20 from the wafer. After that, the main chip area 20 may be packaged to form a complete electronic component.

[0048] Specifically, the cutting path area 30 refers to a part of the cutting path. Since it is necessary to place a photolithography mark (Photo Mark) 40 and / or a test structure (Testkey) 50 in the cutting path on the side of the main chip area 20, the cutting paths on the sides of a main chip area 20 or several main chip areas 20 can be recorded as the cutting path area 30.

[0049] Step S30: placing photolithography marks in part of the cutting area, and marking other cutting areas as test structure placement areas.

[0050] In one embodiment of the present invention, Figure 4 , Figure 6 and Figure 7As shown, in the target area 10, after counting the positions of multiple main chip areas 20 and multiple cutting road areas 30, a photolithography mark 40 can be placed in a part of the cutting road area 30. In the target area 10, the photolithography mark 40 can be used to play the role of alignment and positioning mark, and can be used to guide the alignment system of the photolithography machine.

[0051] Specifically, the test structure 50 has a different function from the main chip area 20. The main chip area 20 contains the actual functional circuit and is packaged after completing the test and proving qualified to become a complete electronic component. The test structure 50 is mainly used for process control and testing purposes. The test structure 50 plays the role of electrical parameter testing, function verification and reliability evaluation of the main chip area 20. The test structure 50 will not form a final electronic component.

[0052] Specifically, based on the different functions of the photolithography mark 40 and the test structure 50, the priority of placing the photolithography mark 40 is higher than that of placing the test structure 50, that is, the photolithography mark 40 needs to be placed on the scribe line area 30 of the target area 10 before the test structure 50. After the photolithography mark 40 is placed in a certain scribe line area 30, the test structure 50 cannot be placed in the scribe line area 30. Therefore, after the photolithography mark 40 is placed in some scribe line areas 30, the other scribe line areas 30 can be recorded as the placement area of ​​the test structure 50.

[0053] Step S40, based on the preset position information of the test structure to be placed, compare with the placement rules in the placement rule library to obtain the current placement rules corresponding to the test structure to be placed, wherein the placement rules in the placement rule library are characterized as placing different test structures according to the corresponding position information on the placement area.

[0054] In one embodiment of the present invention, the specific structures of the multiple test structures 50 can be set to be the same, and the test structures 50 can be divided into placed test structures 50 and test structures 50 to be placed according to whether they have been placed in the placement area of ​​the target area 10. Figure 2 , Figure 3 and Figure 5 As shown, for multiple test structures 50, when the preset position information is determined, the multiple test structures 50 may have a specific position association. On the target area 10, different test structures 50 can be placed according to certain position information, which is defined as a placement rule. Different test structures 50 may correspond to different placement rules, and multiple different placement rules may be established into a placement rule library.

[0055] Specifically, Figure 2 As shown, multiple test structures 50 are placed on the target area 10, and the corresponding placement rule is to be distributed in a straight line segment. Figure 3 As shown, multiple test structures 50 are placed on the target area 10, and the corresponding placement rules are distributed in different areas. That is, after placing the test structure 50 in the center area of ​​the target area 10, it is necessary to place the test structure 50 in the corner area of ​​the target area 10 accordingly, so as to form multiple groups of test structures 50 in the center area and corner area of ​​the target area 10. Figure 5 As shown, a plurality of test structures 50 are placed on the target area 10 , and the corresponding placement rule is a triangular distribution.

[0056] Specifically, Figure 7 As shown, when multiple test structures 50 to be placed need to be placed at different positions on the target area 10, the multiple test structures 50 to be placed may correspond to different placement rules. For example, some test structures 50 to be placed may correspond to the placement rule of triangular distribution, and other test structures 50 to be placed may correspond to the placement rules of different area distributions.

[0057] Of course, different placement rules of the test structures 50 also mean different test purposes for the target area 10. For example, the placement rule of the triangle distribution means that the corner area, the center area, and the edge area of ​​the target area 10 need to be tested separately. The placement rule of the straight line segment distribution means that the center area and the edge area of ​​the target area 10, or the corner area and the edge area of ​​the target area 10 need to be tested.

[0058] In one embodiment of the present invention, Figure 7 As shown, when multiple test structures 50 to be placed need to be placed at different positions on the target area 10, the preset position information of the test structures 50 to be placed can be compared with the placement rules of the placement database, so as to obtain the current placement rules corresponding to the multiple test structures 50 to be placed. How to accurately and quickly count the current placement rules corresponding to the multiple test structures 50 to be placed will be further described below.

[0059] Step S50, according to the priority order of the current placement rules, the target area is grid-divided in sequence to obtain different grid areas and corresponding grid coordinates, wherein the correlation between the grid area and the grid coordinates of the test structure to be placed is related to the priority order of the current placement rules.

[0060] In one embodiment of the present invention, Figure 7As shown, after confirming the current placement rules corresponding to multiple test structures 50 to be placed, the target area 10 can be gridded in sequence according to the priority order of the current placement rules to obtain different grid areas and corresponding grid coordinates. The priority order of the current placement rules is related to the correlation between the grid area and the grid coordinates of the test structure 50 to be placed. For example, if the test structure 50 to be placed is on the target area 10 and has the correlation between the grid area and the grid coordinates, the corresponding placement rule has a high priority. If the test structure 50 to be placed is on the target area 10 and only has the correlation of the grid area or only has the correlation of the grid coordinates, the corresponding placement rule has a medium priority. If the test structure 50 to be placed is on the target area 10 and does not have the correlation of the grid area or does not have the correlation of the grid coordinates, the corresponding placement rule has a low priority.

[0061] Specific, for example Figure 6 The placement rules corresponding to the triangle distribution have high priority. Figure 4 The placement rules corresponding to different area distributions are of medium priority. Figure 2 The placement rule corresponding to the distribution of straight line segments is of low priority. First, the target area 10 can be gridded according to the high-priority placement rule to obtain the grid area corresponding to the high priority and the corresponding grid coordinates. Secondly, the target area 10 can be gridded according to the medium-priority placement rule to obtain the grid area corresponding to the medium priority and the corresponding grid coordinates. Then, the target area 10 can be gridded according to the low-priority placement rule to obtain the grid area corresponding to the low priority and the corresponding grid coordinates.

[0062] It is worth mentioning that Figure 6 The test structure 50 in Figure 4 The test structure 50 in is the same structure, Figure 4 In the example, a straight line segment is used to represent the test structure 50, and Figure 6 The dotted line fill diagram is used to represent the test structure 50, which is only used to make a certain appearance distinction for the convenience of description. Figure 4 The test structures 50 are distributed in different regions, and Figure 6 The test structures 50 are distributed in a triangular shape.

[0063] Specifically, the grid area refers to the grid position on the target area 10, and the grid coordinates refer to the grid coordinates on the target area 10. Figure 4 As shown, the target area 10 can be divided into three rows and three columns, so the target area 10 has nine grid areas. The grid coordinates can be set differently based on different placement rules. For example, Figure 4 In the example, the target area 10 can be established as a 3×3 plane coordinate system, thereby specifically setting the grid coordinates.

[0064] Step S60: Place the corresponding test structures to be placed in the grid area of ​​the placement area according to the priority order of the current placement rule.

[0065] In one embodiment of the present invention, Figure 7 As shown, when multiple test structures 50 to be placed need to be placed at different positions on the target area 10, the target area 10 can be first gridded according to the high-priority placement rules to obtain the grid area and corresponding grid coordinates corresponding to the high priority. Then, the test structure 50 to be placed corresponding to the high-priority placement rules is placed in the placement area according to the position information of the test structure 50 in the corresponding network area and / or grid coordinates. Afterwards, the target area 10 can be gridded according to the medium-priority and low-priority placement rules to obtain the grid areas and corresponding grid coordinates corresponding to the medium-priority and low-priority. Then, the test structure 50 to be placed corresponding to the medium-priority and low-priority placement rules is placed in the placement area according to the position information of the test structure 50 in the corresponding network area and / or grid coordinates.

[0066] See also Figure 8 In one embodiment of the present invention, step S40 may include step S410 and step S420. Step S410 may be represented as obtaining a grid area and corresponding grid coordinates of the test structure 50 to be placed on the target area 10 based on the position information of the test structure 50 to be placed.

[0067] Step S420 can be expressed as analyzing the correlation between the grid area and the corresponding grid coordinates of the test structure 50 to be placed in turn according to the priority order of the placement rules in the placement rule library, and obtaining the current placement rule corresponding to the test structure 50 to be placed, wherein the priority order of the placement rules in the placement rule library is related to the correlation between the grid area and the grid coordinates of different test structures 50 on the target area 10.

[0068] In step S410, for the preset position information of the multiple test structures 50 to be placed, when the number and placement positions of the test structures 50 to be placed are determined, the grid areas and corresponding grid coordinates of the multiple test structures 50 to be placed on the target area 10 are relatively fixed, so the grid areas and corresponding grid coordinates of the multiple test structures 50 to be placed can be counted.

[0069] In step S420, if Figure 7As shown, when multiple test structures 50 to be placed need to be placed at different positions on the target area 10, and after the grid areas and corresponding grid coordinates of the multiple test structures 50 to be placed are counted, it is necessary to confirm the placement rules corresponding to the multiple test structures 50 to be placed, so as to quickly and efficiently place the multiple test structures 50 to be placed according to different placement rules.

[0070] Specifically, since different test structures 50 to be placed correspond to placement rules of different priorities, the test structures 50 corresponding to different placement rules have obvious differences in the grid areas and corresponding grid coordinates on the target area 10. Therefore, the grid areas and corresponding grid coordinates of the multiple test structures 50 to be placed can be analyzed in turn according to the priority order of the placement rules, and the placement rules corresponding to the multiple test structures 50 to be placed can be counted. Specifically, see the analysis at step S421, step S422, step S423 and step S424.

[0071] See also Fig. 9 In one embodiment of the present invention, step S420 may include step S421, step S422, step S423 and step S424. Step S421 may be represented as recording the placement rules with grid area association and grid coordinate association between different test structures 50 as high priority placement rules. Step S422 may be represented as recording the placement rules with grid area association or grid coordinate association between different test structures 50 as medium priority placement rules. Step S423 may be represented as recording the placement rules with no grid area association or grid coordinate association between different test structures 50 as low priority placement rules. Step S424 may be represented as analyzing the correlation between the grid areas and the corresponding grid coordinates of the test structures 50 to be placed in the order of high priority, medium priority and low priority of the placement rules. Afterwards, the placement rules corresponding to multiple test structures 50 to be placed may be counted.

[0072] Specifically, Figure 7 As shown, it includes both the test structures 50 distributed in a triangle and the test structures 50 distributed in different areas. When analyzing the priority of the placement rules, the position information of the grid areas and the corresponding grid coordinates of the multiple test structures 50 to be placed should be considered at the same time.

[0073] For example, the test structures 50 distributed in a triangle not only require that multiple test structures 50 to be placed are located in the central area, edge area and corner area of ​​the target area 10, but also require that a triangle be formed between the test structures 50 in the central area, edge area and corner area, that is, the test structures 50 distributed in a triangle have more limiting conditions.

[0074] For another example, the test structures 50 distributed in different areas only require multiple test structures 50, which are respectively located in the central area and the corner area of ​​the target area 10, and the test structures 50 in the central area and the test structures in the corner area are distributed in multiple groups, and there is no requirement for the test structures 50 in the central area and the test structures in the corner area to have a relationship in grid coordinates, that is, the test structures 50 distributed in different areas have fewer limiting conditions.

[0075] It can be seen that in Figure 7 Among the multiple test structures 50 shown, when the test structure 50 to be placed in the dot-line filling diagram is confirmed, the grid area and grid coordinates between the test structures 50 in the dot-line filling diagram are fixed, and are distributed in a triangular shape. In addition, due to the large number of limiting conditions, the test structure 50 to be placed in the dot-line filling diagram cannot form a different regional distribution with other test structures 50 to be placed. Therefore, in order to improve the placement efficiency of the multiple test structures 50 to be placed, the grid areas and corresponding grid coordinates of the multiple test structures 50 to be placed can be analyzed in turn according to the order of placement rules of high priority, medium priority, and low priority, and the placement rules corresponding to the multiple test structures 50 to be placed can be counted.

[0076] See also Figure 7 In one embodiment of the present invention, in placement rules of the same priority, the correlation between the grid areas and the corresponding grid coordinates of the test structures 50 to be placed is analyzed in the order from most to least according to the number of grid areas and / or grid coordinates corresponding to the test structures 50 in the placement rules.

[0077] Specifically, for high-priority placement rules, different test structures 50 have grid area associations and grid coordinate associations. For example, four test structures 50 to be placed are distributed in a rectangular shape, and another example is that three test structures 50 to be placed are distributed in a triangular shape. Setting different priorities for different placement rules is to improve the placement efficiency of multiple test structures 50 to be placed. Similarly, placement rules of the same priority may correspond to placement rules of different shapes or types. Therefore, in order to improve the placement efficiency of multiple test structures 50 to be placed, placement rules of different shapes or types should also be distinguished.

[0078] To this end, in placement rules of the same priority, the correlation between the grid areas and the corresponding grid coordinates of the test structures 50 to be placed is analyzed in the order from most to least according to the number of grid areas and / or grid coordinates corresponding to the test structures 50 in the placement rules, so as to improve the placement efficiency of multiple test structures 50 to be placed.

[0079] See also Fig.10In one embodiment of the present invention, step S50 may include step S510, step S520 and step S530. Step S510 may be represented as gridding the target area 10 according to the placement rule with high priority in the current placement rule to obtain the corresponding grid area and the corresponding grid coordinates. Step S520 may be represented as gridding the target area 10 according to the placement rule with medium priority in the current placement rule to obtain the corresponding grid area and the corresponding grid coordinates. Step S530 may be represented as gridding the target area 10 according to the placement rule with low priority in the current placement rule to obtain the corresponding grid area and the corresponding grid coordinates.

[0080] Specifically, since the placement rules with high priority correspond to more limiting conditions of the test structure 50, the grid area and the corresponding grid coordinates of this part of the test structure 50 are relatively fixed, so the placement rules with high priority correspond to the test structure 50 and place them in the placement area. Then, the placement rules with medium priority correspond to the test structure 50 and place them in the placement area, and finally the placement rules with low priority correspond to the test structure 50 and place them in the placement area.

[0081] See also Fig.11 In one embodiment of the present invention, step S60 may include step S611, step S612, and step S613. Step S611 may be represented as placing the first test structure 50 to be placed in the grid area at the corner position of the target area 10, and recording the grid coordinates of the first test structure 50. Step S612 may be represented as placing the second test structure 50 to be placed in the grid area at the edge position of the target area 10, and associating the grid coordinates of the second test structure 50 with the grid coordinates of the first test structure 50. Step S613 may be represented as placing the third test structure 50 to be placed in the grid area at the center position of the target area 10, and associating the grid coordinates of the third test structure 50 with the grid coordinates of the second test structure 50.

[0082] Specifically, Figure 6 As shown, for high-priority placement rules, the target area 10 may be divided into corresponding grid areas and grid coordinates, for example, the target area 10 may be divided into 18 parts on the horizontal coordinate and the target area 10 may be divided into 3 parts on the vertical coordinate.

[0083] First, place the first test structure 50 to be placed in the grid area at the corner position, and record the grid coordinates of the first test structure 50, for example, (18, 3, 3, 1), (18, 3, 3, 1) can respectively indicate that the target area 10 is divided into 18 parts in the horizontal coordinate, the target area 10 is divided into 3 parts in the vertical coordinate, the first test structure 50 is in the third part of the horizontal coordinate of the target area 10, and the first test structure 50 is in the first part of the vertical coordinate of the target area 10.

[0084] Next, the second test structure 50 to be placed is placed in the grid area at the edge position, and the grid coordinates of the second test structure 50 are associated with the grid coordinates of the first test structure 50, for example, the grid coordinates of the second test structure 50 are set to (18, 3, 11, 1). (18, 3, 11, 1) can respectively refer to the target area 10 being divided into 18 parts in the horizontal coordinate, the target area 10 being divided into 3 parts in the vertical coordinate, the second test structure 50 being in the 11th part of the horizontal coordinate of the target area 10, and the second test structure 50 being in the 1st part of the vertical coordinate of the target area 10.

[0085] Then, the third test structure 50 to be placed is placed in the grid area at the center position, and the grid coordinates of the third test structure 50 are associated with the grid coordinates of the second test structure 50, for example, the grid coordinates of the third test structure 50 are set to (18, 3, 11, 2). (18, 3, 11, 2) can respectively refer to the target area 10 being divided into 18 parts in the horizontal coordinate, the target area 10 being divided into 3 parts in the vertical coordinate, the third test structure 50 being in the 11th part of the horizontal coordinate of the target area 10, and the third test structure 50 being in the 2nd part of the vertical coordinate of the target area 10.

[0086] See also Fig.12 In one embodiment of the present invention, step S60 may further include step S621 and step S622. Step S621 may be represented as placing the first test structure 50 to be placed in the grid area at the edge or corner of the target area 10, and recording the grid coordinates of the first test structure 50. Step S622 may be represented as placing the other test structures 50 to be placed in the placement area along the direction of the straight line where the grid coordinates of the first test structure 50 are located.

[0087] Specifically, Figure 2As shown, for a plurality of test structures 50 to be placed distributed in a straight line segment, first, the first test structure 50 to be placed can be placed in a grid area at an edge position or a corner position of the target area 10, and the grid coordinates of the first test structure 50 can be recorded. Secondly, along the direction of the straight line where the grid coordinates of the first test structure 50 are located, for example, along the direction of the straight line where the horizontal coordinates or the vertical coordinates of the first test structure 50 are located, the other test structures 50 to be placed can be placed in sequence on the placement area.

[0088] See also Fig.13 In one embodiment of the present invention, step S60 may further include step S6210 and step S6211. Step S6210 may be represented as placing a second test structure 50 to be placed in the grid area at the center of the target area 10, placing another test structure 50 to be placed in the grid area at the corner of the target area 10, and the second test structure 50 and the other test structure 50 form a group of test structures 50. Step S6211 may be represented as placing another second test structure 50 to be placed in the grid area at the center of the target area 10, placing another other test structure 50 to be placed in the grid area at the corner of the target area 10, and the second test structure 50 and the other test structure 50 form another group of test structures 50, so that multiple groups of test structures 50 are formed in the placement area.

[0089] Specifically, Figure 4 As shown, for the placement rule of medium priority, the target area 10 can be divided into corresponding grid areas and grid coordinates, for example, the target area 10 is divided into three parts on the horizontal coordinate, and the target area 10 is divided into three parts on the vertical coordinate.

[0090] First, place the second test structure 50 to be placed in the grid area at the center of the target area 10, and record the grid coordinates of the second test structure 50 to be placed, for example, (3, 3, 2, 2). (3, 3, 2, 2) can respectively indicate that the target area 10 is divided into 3 parts in the horizontal coordinate, the target area 10 is divided into 3 parts in the vertical coordinate, the second test structure 50 is in the second part of the horizontal coordinate of the target area 10, and the second test structure 50 is in the second part of the vertical coordinate of the target area 10.

[0091] Next, the other test structures 50 to be placed are placed in the grid area at the edge of the target area 10, for example, the grid coordinates of the other test structures 50 are set to (3, 3, 3, 3). (3, 3, 3, 3) may respectively refer to the target area 10 being divided into 3 parts in the horizontal coordinate, the target area 10 being divided into 3 parts in the vertical coordinate, the other test structures 50 being in the third part of the horizontal coordinate of the target area 10, and the other test structures 50 being in the third part of the vertical coordinate of the target area 10. The second test structure 50 and the other test structure 50 form a group of test structures 50.

[0092] Then, another second test structure 50 to be placed is placed in the grid area at the center of the target area 10, and the coordinates of the second test structure 50 are (3, 3, 2, 2). Another other test structure 50 to be placed is placed in the grid area at the corner of the target area 10, and the coordinates of the other test structure 50 are (3, 3, 3, 3). The second test structure 50 and the other test structure 50 form another group of test structures 50, so that the placement area forms multiple groups of test structures 50.

[0093] See also Figure 4 , Figure 6 and Figure 7 In one embodiment of the present invention, the position information of the test structure 50 includes information of the grid area and the grid coordinates, and the placement position of the test structure 50 is recorded as (M, N, P, Q). Among them, M represents the target area 10 is divided into M parts in the horizontal coordinate, N represents the target area 10 is divided into N parts in the vertical coordinate, P represents the horizontal coordinate of the test structure 50 on the target area 10, and Q represents the vertical coordinate of the test structure 50 on the target area 10.

[0094] See also Fig.14 In one embodiment of the present invention, a placement device for a semiconductor test structure is provided, which may include a first acquisition unit 110, a statistical unit 120, a recording unit 130, a second acquisition unit 140, a division unit 150 and a placement unit 160.

[0095] Among them, the first acquisition unit 110 is used to acquire the target area 10 to be tested on the wafer; the statistical unit 120 is used to count the positions of multiple main chip areas 20 and multiple cutting road areas 30 on the target area 10, wherein the cutting road area 30 is located on the peripheral side of the main chip area 20; the recording unit 130 is used to place the lithography mark 40 in part of the cutting road area 30, and record the other cutting road areas 30 as the placement area of ​​the test structure 50; the second acquisition unit 140 is used to compare the preset position information of the test structure 50 to be placed with the placement rules in the placement rule library to obtain the test structure 50 to be placed. The current placement rules corresponding to the placement rules are characterized in that the different test structures 50 are placed in the placement area according to the corresponding position information; a division unit 150 is used to divide the target area 10 into grids in sequence according to the priority order of the current placement rules to obtain different grid areas and corresponding grid coordinates, wherein the correlation between the grid area and the grid coordinates of the test structure 50 to be placed is related to the priority order of the current placement rules; and a placement unit 160 is used to place the corresponding test structure 50 to be placed into the grid area of ​​the placement area according to the priority order of the current placement rules.

[0096] See also Fig.15 As shown, a structural schematic diagram of a computer device in one embodiment of the present invention. In one embodiment, a computer device is provided, and the computer device 200 can be a server. The computer device 200 includes a processor 201, a memory 202, a network interface 204 and a database connected via a system bus. Among them, the processor 201 of the computer device 200 is used to provide computing and control capabilities. The memory 202 of the computer device 200 includes a non-volatile and / or volatile storage medium, and an internal memory 203. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device 200 is used to communicate with an external client through a network connection. When the computer program is executed by the processor, it implements the functions or steps of a server-side method for placing a semiconductor test structure.

[0097] In one embodiment, a computer device 200 is provided, including a memory 202, a processor 201, and a computer program stored in the memory and executable on the processor. When the processor 201 executes the computer program, the following steps are implemented: On a wafer, a target area 10 to be tested is obtained; on the target area 10, the positions of multiple main chip areas 20 and multiple cutting road areas 30 are counted, wherein the cutting road area 30 is located on the peripheral side of the main chip area 20; in part of the cutting road area 30, a photolithography mark 40 is placed, and other cutting road areas 30 are recorded as placement areas for test structures 50; based on the preset position information of the test structure 50 to be placed, the placement rules in the placement rule library are compared to obtain the current placement rules corresponding to the test structure 50 to be placed, wherein the placement rules in the placement rule library are characterized as placing different test structures 50 according to the corresponding position information on the placement area; according to the priority order of the current placement rules, the target area 10 is grid-divided in turn to obtain different grid areas and corresponding grid coordinates, wherein the correlation between the grid area and the grid coordinates of the test structure 50 to be placed is related to the priority order of the current placement rules; according to the priority order of the current placement rules, the corresponding test structure 50 to be placed is placed in the grid area of ​​the placement area.

[0098] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented: On a wafer, a target area 10 to be tested is obtained; on the target area 10, the positions of multiple main chip areas 20 and multiple cutting road areas 30 are counted, wherein the cutting road area 30 is located on the peripheral side of the main chip area 20; in part of the cutting road area 30, a photolithography mark 40 is placed, and other cutting road areas 30 are recorded as placement areas for test structures 50; based on the preset position information of the test structure 50 to be placed, the placement rules in the placement rule library are compared to obtain the current placement rules corresponding to the test structure 50 to be placed, wherein the placement rules in the placement rule library are characterized as placing different test structures 50 according to the corresponding position information on the placement area; according to the priority order of the current placement rules, the target area 10 is grid-divided in turn to obtain different grid areas and corresponding grid coordinates, wherein the correlation between the grid area and the grid coordinates of the test structure 50 to be placed is related to the priority order of the current placement rules; according to the priority order of the current placement rules, the corresponding test structure 50 to be placed is placed in the grid area of ​​the placement area.

[0099] It should be noted that the above functions or steps that can be implemented by the computer-readable storage medium or computer device can refer to the relevant descriptions on the server side and the client side in the aforementioned method embodiment. To avoid repetition, they will not be described one by one here.

[0100] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0101] In summary, the present invention proposes a method, device, equipment and medium for placing semiconductor test structures. The unexpected technical effect of the present invention is: after clarifying the preset position information of the test structure to be placed, the current placement rules corresponding to the test structure to be placed can be statistically calculated based on the position information and the placement rules in the placement database. In the target area, according to the current placement rules corresponding to the test structure to be placed, the corresponding grid area and grid coordinates are divided, and based on the placement requirements of the test structure to be placed at different positions, the automatic placement of the test structure to be placed is realized, thereby improving the placement efficiency of the test structure to be placed.

[0102] The flow chart and block diagram in the accompanying drawings illustrate the possible implementation architecture, function and operation of the method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

Claims

1. A method for placing a semiconductor test structure, characterized in that: include: On the wafer, obtaining a target area to be tested; On the target area, counting the positions of a plurality of main chip areas and a plurality of cutting lane areas, wherein the cutting lane areas are located at the periphery of the main chip area; Placing photolithography marks in some of the scribe line areas, and marking other scribe line areas as test structure placement areas; Based on the preset position information of the test structure to be placed, the placement rules in the placement rule library are compared to obtain the current placement rule corresponding to the test structure to be placed, wherein the placement rule in the placement rule library is characterized by placing different test structures according to the corresponding position information on the placement area; According to the priority order of the current placement rules, the target area is grid-divided in sequence to obtain different grid areas and corresponding grid coordinates, wherein the correlation between the grid area and the grid coordinates of the test structure to be placed is related to the priority order of the current placement rules; According to the priority order of the current placement rule, the corresponding test structure to be placed is placed in the grid area of ​​the placement area.

2. The method for placing a semiconductor test structure according to claim 1, characterized in that: The step of comparing the preset position information of the test structure to be placed with the placement rules in the placement rule library to obtain the current placement rule corresponding to the test structure to be placed includes: Based on the position information of the test structure to be placed, obtaining the grid area and corresponding grid coordinates of the test structure to be placed on the target area; According to the priority order of the placement rules in the placement rule library, the correlation between the grid area of ​​the test structure to be placed and the corresponding grid coordinates is analyzed in turn to obtain the current placement rule corresponding to the test structure to be placed, wherein the priority order of the placement rules in the placement rule library is related to the correlation between the grid area and the grid coordinates of different test structures on the target area.

3. The method for placing a semiconductor test structure according to claim 2, characterized in that: The step of analyzing the correlation between the grid areas of the test structures to be placed and the corresponding grid coordinates in sequence according to the priority order of the placement rules in the placement rule library comprises: Placement rules with grid area association and grid coordinate association between different test structures are recorded as high-priority placement rules; Placement rules that have grid area association or grid coordinate association between different test structures are recorded as medium priority placement rules; Placement rules that have no grid area association or grid coordinate association between different test structures are recorded as low-priority placement rules; According to the order of high priority, medium priority and low priority of the placement rules, the correlation between the grid areas of the test structure to be placed and the corresponding grid coordinates is analyzed in turn.

4. The method for placing a semiconductor test structure according to claim 3, characterized in that: In placement rules of the same priority, the correlation between the grid areas and corresponding grid coordinates of the test structures to be placed is analyzed in the order of the number of grid areas and / or grid coordinates corresponding to the test structures in the placement rules from large to small.

5. The method for placing a semiconductor test structure according to claim 1, characterized in that: The step of dividing the target area into grids in sequence according to the priority order of the current placement rules to obtain different grid areas and corresponding grid coordinates includes: According to the placement rule with a high priority in the current placement rule, the target area is grid-divided to obtain a corresponding grid area and corresponding grid coordinates; According to the placement rule with a medium priority in the current placement rule, the target area is grid-divided to obtain a corresponding grid area and corresponding grid coordinates; According to the placement rules with low priority in the current placement rules, the target area is grid-divided to obtain corresponding grid areas and corresponding grid coordinates.

6. The method for placing a semiconductor test structure according to claim 5, characterized in that: After the step of dividing the target area into grids according to the placement rule with a high priority in the current placement rule to obtain the corresponding grid area and the corresponding grid coordinates, the method further comprises: Placing a first test structure to be placed in a grid area at a corner position of the target area, and recording the grid coordinates of the first test structure; Placing a second test structure to be placed in a grid area at an edge position of the target area, and associating the grid coordinates of the second test structure with the grid coordinates of the first test structure; The third test structure to be placed is placed in the grid area at the center of the target area, and the grid coordinates of the third test structure are associated with the grid coordinates of the second test structure.

7. The method for placing a semiconductor test structure according to claim 5, characterized in that: After the step of dividing the target area into grids according to the placement rule with a medium priority in the current placement rule to obtain the corresponding grid area and the corresponding grid coordinates, the method further comprises: Placing a first test structure to be placed in a grid area at an edge position or a corner position of the target area, and recording the grid coordinates of the first test structure; Placing other test structures to be placed on the placement area along the direction of the straight line where the grid coordinates of the first test structure are located; or Placing a second test structure to be placed in a grid area at the center of the target area, and placing another test structure to be placed in a grid area at a corner of the target area, wherein the second test structure and the other test structure form a group of test structures; Another second test structure to be placed is placed in the grid area at the center of the target area, and another other test structure to be placed is placed in the grid area at the corner of the target area. The second test structure and the other test structure form another group of test structures, so that multiple groups of test structures are formed in the placement area.

8. A placement device for a semiconductor test structure, characterized in that: include: A first acquisition unit is used to acquire a target area to be tested on a wafer; A statistical unit, for statistically calculating the positions of a plurality of main chip regions and a plurality of cutting lane regions on the target area, wherein the cutting lane regions are located at the periphery of the main chip region; A recording unit, used to place photolithography marks in part of the scribe line area, and record other scribe line areas as test structure placement areas; A second acquisition unit is used to compare the preset position information of the test structure to be placed with the placement rules in the placement rule library to obtain the current placement rule corresponding to the test structure to be placed, wherein the placement rule in the placement rule library is characterized by placing different test structures according to the corresponding position information on the placement area; a dividing unit, for successively dividing the target area into grids according to the priority order of the current placement rules to obtain different grid areas and corresponding grid coordinates, wherein the correlation between the grid areas and grid coordinates of the test structure to be placed is related to the priority order of the current placement rules; and The placement unit is used to place the corresponding test structure to be placed in the grid area of ​​the placement area according to the priority order of the current placement rule.

9. An electronic device, characterized in that: It comprises a processor, a memory and a communication bus; the communication bus is used to connect the processor and the memory; the processor is used to execute a computer program stored in the memory to implement the semiconductor test structure placement method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program is used to enable a computer to execute the semiconductor test structure placement method as described in any one of claims 1-7.

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