A clock synchronization method for time-sensitive networks

Abstract

The present invention provides a clock synchronization method for a time-sensitive network, wherein the method includes the following steps: calculating the link delay between a master clock server and a clock client, and obtaining a clock frequency ratio between the clock client and the master clock server based on the link delay; calculating a time phase error between the clock client and the master clock server based on the link delay and the clock frequency ratio; calculating a second adjustment direction and a nanosecond adjustment direction based on the time phase error, and adjusting the time phase error of the clock client's local clock based on the second adjustment direction and the nanosecond adjustment direction; calculating the time and frequency adjustment direction required for each nanosecond frequency error based on the clock frequency ratio, and adjusting the frequency error of the clock client's local clock based on the time and frequency adjustment direction required for each nanosecond frequency error. This time synchronization method improves the time synchronization accuracy of the time-sensitive network.

Description

Technical Field

[0001] The present invention relates to the technical field of network communications, and in particular to a clock synchronization method for a time-sensitive network. Background Art

[0002] Time-Sensitive Ethernet (TSE) is a standardized network technology based on standard Ethernet, providing deterministic data transmission services at the data link layer. With the increasing integration of aircraft, the real-time transmission of critical data is required to be even more precise. Aircraft networks involve safety-critical systems such as electromechanical systems and flight control systems. Compatible with communication transmissions of different safety criticality levels on a unified airborne network platform, this requires even higher synchronization accuracy to meet the high real-time, deterministic transmission requirements of these safety criticality levels.

[0003] For some safety-critical application data, network transmission needs to improve the determinism and real-time performance of its data to meet the determinism and real-time indicators of the application system. Currently, there is no simple and convenient method to achieve high-precision time synchronization. Summary of the Invention

[0004] In view of this, embodiments of this specification provide a clock synchronization method for a time-sensitive network, so as to achieve the purpose of improving the time synchronization accuracy of the time-sensitive network based on the IEEE802.1AS time synchronization mechanism.

[0005] The embodiments of this specification provide the following technical solutions:

[0006] A clock synchronization method for a time-sensitive network, comprising:

[0007] Calculate the link delay D between the master clock server and the clock client, and use the link delay D to calculate the clock frequency ratio r between the clock client and the master clock server.

[0008] The time phase error offset between the clock client and the master clock server is calculated using the link delay D and the clock frequency ratio r.

[0009] The time phase error offset is used to calculate the second adjustment direction sign_s and the nanosecond adjustment direction sign_ns. The time phase error of the local clock of the clock client is adjusted using the second adjustment direction sign_s and the nanosecond adjustment direction sign_ns.

[0010] The time offsetPerNsec and the frequency adjustment direction fre_sign required for each nanosecond frequency error are calculated based on the clock frequency ratio r. The frequency error of the local clock of the clock client is adjusted based on the time offsetPerNsec and the frequency adjustment direction fre_sign required for each nanosecond frequency error.

[0011] Furthermore, the link delay D between the master clock server and the clock client is calculated, including:

[0012] The clock client initiates a time synchronization request, and the master clock server responds to the time synchronization request;

[0013] The clock client obtains the first time T1, the second time T2, the third time T3, and the fourth time T4 through the interaction process of the Pdelay_Req message, the Pdelay_Resp message, and the Pdelay_Resp_Follow_Up message in the link delay measurement phase;

[0014] The link delay D between the clock client and the master clock server is calculated based on the first time T1, the second time T2, the third time T3 and the fourth time T4, where the link delay D is

[0015]

[0016] Furthermore, the clock frequency ratio r between the clock client and the master clock server is calculated using the link delay D, including:

[0017] The clock server sends a continuous first synchronization message SYNC_i-1 and a second synchronization message SYNC_i to the clock client, and records the first sending timestamp t1_i-1 and the second sending timestamp t1_i;

[0018] The recording clock client records a first receiving time t2_i-1 of receiving the first synchronization message SYNC_i-1 and a second receiving time t2_i of the second synchronization message SYNC_i;

[0019] The clock frequency ratio r is calculated based on the first sending timestamp t1_i-1, the second sending timestamp t1_i, the first receiving time t2_i-1 and the second receiving time t2_i, wherein the clock frequency ratio r is

[0020] Furthermore, the time phase error offset between the clock client and the master clock server is calculated using the link delay D and the clock frequency ratio r, including:

[0021] The master clock server periodically sends SYNC messages and records the sending time T5, fills the sending time T5 into the Follow_up message, and sends it to the clock client;

[0022] The clock client receives the SYNC message and records the receiving time T6;

[0023] The clock client parses the sending time T5 and calculates the time phase error offset between the clock client and the master clock server based on the clock frequency ratio r, link delay D, sending time T5 and receiving time T6, where offset = T6-(T5+D)*r.

[0024] Furthermore, the second adjustment direction sign_s and the nanosecond adjustment direction sign_ns are obtained by calculating the time phase error offset, including:

[0025] If the time phase error offset is greater than or equal to 0, the second adjustment direction sign_s is 2, and the nanosecond adjustment direction sign_ns is 1;

[0026] If the time phase error offset is less than 0, the second adjustment direction sign_s is 0 and the nanosecond adjustment direction sign_ns is 0.

[0027] Furthermore, adjusting the time phase error of the local clock of the clock client through the second adjustment direction sign_s and the nanosecond adjustment direction sign_ns includes:

[0028] Adjust the nanosecond value of the local clock according to the nanosecond adjustment direction sign_ns and determine whether second carry is required;

[0029] If you need to carry the second, adjust the second value through the second adjustment direction sign_s, and then add 1 second;

[0030] If the second increment is not required, adjust the second value of the local clock using the second adjustment direction sign_s.

[0031] Furthermore, the time offsetPerNsec required for a 1 nanosecond frequency error and the frequency adjustment direction fre_sign are calculated based on the clock frequency ratio r, including:

[0032] Set the second setting value, and calculate the frequency offset fre_offset and correction direction fre_sign generated between the clock client and the master clock server within one second based on the clock frequency ratio r and the second setting value;

[0033] According to the frequency offset fre_offset, the time offsetPerNsec required for a frequency error of 1 nanosecond is calculated. If the frequency offset fre_offset is not equal to the second set value, the time offsetPerNsec required for a frequency error of 1 nanosecond is 10 9 / fre_offset;

[0034] If the frequency offset fre_offset is equal to the second set value, the time offsetPerNsec required for a 1 nanosecond frequency error is equal to the second set value.

[0035] Furthermore, based on the clock frequency ratio r and the second set value, the frequency offset fre_offset and the correction direction fre_sign generated between the clock client and the master clock server within one second are calculated, including:

[0036] If the clock frequency ratio r is less than 1, the frequency offset Correction direction fre_sign = 2;

[0037] If the clock frequency ratio r is greater than 1, the frequency offset Correction direction fre_sign = 1;

[0038] If the clock frequency ratio r is equal to 1, the frequency offset fre_offset=the second set value.

[0039] Furthermore, it also includes:

[0040] A clock synchronization method for a time-sensitive network is periodically executed to achieve synchronization of the time-sensitive network.

[0041] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0042] The frequency error between the master clock server and the clock client due to crystal oscillator offset is calculated by using the transmission of messages during the synchronization process. The frequency error calculated by the software is written into the logic register. The time error introduced by crystal oscillator drift is compensated and corrected within the logic, thereby improving the accuracy of time synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 is a schematic diagram of a clock synchronization method for a time-sensitive network according to an embodiment of the present invention;

[0045] Figure 2 This is a process of clock synchronization using the IEEE802.1AS protocol in an embodiment of the present invention;

[0046] Figure 3 4 is a diagram showing the calculation principle of the clock frequency ratio according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0048] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0049] It is realized through the interaction between the master clock server and the clock client. The frequency ratio between the master clock server and the clock client can be calculated based on the periodic SYNC message. The specific implementation process is as follows: Figure 2 shown.

[0050] The time synchronization algorithm uses the PTP protocol to achieve time synchronization of nodes in the network. The time synchronization process is as follows: Figure 2 shown.

[0051] The clock client calculates the frequency error and time phase error between the clock and the master clock during the synchronization process, and compensates and corrects these two errors through internal logic. Figure 1 shown.

[0052] A method for improving time synchronization accuracy includes the following steps:

[0053] Step 1: If Figure 2 As shown, the link delay and time phase error between the master clock server and the clock client are calculated according to the IEEE802.1AS protocol. The time synchronization algorithm consists of a master clock server and a clock client. Within the protocol cycle, the clock client initiates a time request according to the request-response mechanism, and the master clock server responds. Based on the interaction of the Pdelay_Req message, Pdelay_Resp message, and Pdelay_Resp_Follow_Up message during the link delay measurement phase, the clock client obtains four times, T1-T4, and calculates the link delay D between the clock client and the master clock server according to Formula 1. Here, the first time T1 is the time when the Pdelay_Req message is sent, the second time T2 is the time when the Pdelay_Req message is received, the third time T3 is the time when the Pdelay_Resp_Follow_Up message is sent, and the fourth time T4 is the time when the Pdelay_Resp_Follow_Up message is sent.

[0054] Link delay

[0055] Step 2: The master clock server periodically sends SYNC messages and records the sending time T5. It then adds the sending time T5 to the Follow_up message and sends it to the clock client.

[0056] Step 3: The clock client receives the SYNC message and records the receiving time T6;

[0057] Step 4: If Figure 3 As shown, the clock frequency ratio r between the clock client and the master clock server can be calculated by sending and receiving two consecutive SYNC messages. The specific process is as follows: the clock server sends consecutive synchronization SYNC messages SYNC_i-1 and SYNC_i to the clock client and records the sending timestamps t1_i-1 and t1_i. The clock client records the time t2_i-1 and t2_i of receiving the SYNC_i-1 and SYNC_i messages.

[0058] Step 5. Because the link delay is sufficiently stable, the actual time interval between the last synchronization and the current synchronization, the difference between timestamps t1_i-1 and t1_i recorded by the master clock server, and the difference between timestamps t2_i-1 and t2_i recorded by the slave clock, is the same. However, due to different frequencies, the master and slave clocks' measurements of this actual time interval differ. Therefore, the master-slave frequency ratio is calculated based on the measured values ​​and the clock frequency ratio r with the master clock server is recorded. Calculation formula 2 is as follows:

[0059] t1_off=t1_i-t1_i-1

[0060] t2_off=t2_i-t2_i-1

[0061]

[0062] Step 6: Figure 2 As shown in the figure, after receiving the Follow_up message, the clock client parses the time T5 in the message and calculates the time phase error offset between the clock client and the master clock server according to formula 3 based on the clock frequency ratio r, link delay D, T5 and T6:

[0063] offset=T6-(T5+D)*r (3);

[0064] Step 7: Figure 1 As shown, the clock client assigns the calculated time error offset seconds to offset_s and the nanosecond value to offset_ns. The second and nanosecond values ​​are written to the corresponding second value module and nanosecond value module through the second value read and write interface and the nanosecond value read and write interface respectively. The direction sign_s and nanosecond value adjustment direction sign_ns that need to be adjusted are written according to the positive and negative values ​​of offset_s and offset_ns:

[0065] If offset>=0:

[0066] sign_s=0x2

[0067] sign_ns=0x1

[0068] else

[0069] sign_s=0x0

[0070] sign_ns = 0x0; (4);

[0071] Step 8: After the time phase error calculated by the clock client is written into the logic, the clock client software writes the value of the time adjustment signal register (initialized by the host software) adj_enable to indicate to the logic that the local clock (the client's clock) needs to be adjusted.

[0072] Step 9: When the logic detects the rising edge of the adj_enable signal (i.e., the value is 1), it indicates that the time phase error adjustment is required at this time, and the logic adjustment status register In_adjust is set to 1 to indicate that it is in the correction state. At the same time, the logic adjusts the second value counter slave_counter_second_48 according to the second value offset_s and the second value adjustment direction sign_s, and adjusts the nanosecond value counter slave_count_ns_32 according to the nanosecond value offset_ns and the nanosecond value adjustment direction sign_ns. The specific method is as follows:

[0073] Nanosecond value adjustment: If sign_ns = 0x0, the nanosecond value counter subtracts the nanosecond value offset_ns. If sign_ns = 0x1, the nanosecond value counter adds the nanosecond value offset_ns. The adjusted nanosecond value is AdjValue_ns. When AdjValue_ns>, that is, greater than 1s, AdjValue_ns = AdjValue_ns-, and AddValue_s is set to 1, indicating that the second is carried.

[0074] Second value module adjustment: If sign_s = 0x0, the second value counter subtracts the second value offset_s. If sign_s = 0x2, the second value counter adds the second value offset_s. The adjusted second value is AdjValue_s, and the carry of the nanosecond value is added, that is, AdjValue_s = AdjValue_s + AddValue_s.

[0075] Step 10: After the logic adjustment is completed, the logic adjustment status register In_adjust is set to 0, indicating that the time phase error correction is completed;

[0076] Step 11: The clock client calculates the clock frequency ratio r according to Step 5, and calculates the frequency offset fre_offset and correction direction fre_sign generated between the clock client and the master clock server within one second according to Formula 5.

[0077] If r<1

[0078]

[0079] fre_sign=2;

[0080] else if r>1

[0081]

[0082] fre_sign=1;

[0083] else

[0084] fre_offset = 0x7fffffff (5);

[0085] in, Indicates that the master clock has passed 1s(10 9 ns), the nanosecond time passed by the clock client;

[0086] fre_offset represents the nanosecond difference between the clock client and the clock server within a 1s time interval. When the clock frequency ratio r is equal to 1, the clock frequencies of the clock client and the clock server are consistent and there is no clock frequency error. In this case, the value of fre_offset is 0x7fffffff (the second set value), indicating that no clock frequency adjustment is performed.

[0087] fre_sign indicates the direction of adjustment. fre_sign = 2 means the client clock time is faster than the server clock time and needs to be slowed down, that is, the frequency offset is subtracted. fre_sign = 1 means the client clock time is slower than the server clock time and needs to be accelerated, that is, the frequency offset is increased.

[0088] Step 12: The clock client calculates the time offsetPerNsec required to generate a frequency error of 1 nanosecond based on the fre_offset value and formula 6.

[0089] If fre_offset!=0x7fffffff

[0090] offsetPerNsec= / fre_offset;

[0091] else

[0092] offsetPerNsec = 0x7fffffff; (6);

[0093] Step 13: The clock client software writes the offsetPerNsec value and adjustment direction fre_sign into the logic register through the nanosecond value read / write interface, and indicates that frequency adjustment is required through the AdjFre_Enable signal.

[0094] Step 14: When the clock client logic detects the rising edge of the AdjFre_Enable signal, it indicates that a frequency adjustment is required. Since the logic's internal processing clock is 200 MHz, the minimum unit of the logic adjustment is 5 nanoseconds. The logic increments the frequency adjustment counter Fre_Count by 1 every offsetPerNsec. When Fre_Count reaches 5, it indicates that a 5-nanosecond frequency offset has occurred between the clock client and the master clock server. At this point, the logic adjusts the local clock based on the value of fre_sign. That is, when fre_sign = 2, the nanosecond counter decrements by 5; when fre_sign = 1, the nanosecond counter increments by 5.

[0095] Step 15: After the clock client logic adjusts the clock frequency error, it sets the AdjFre_Enable signal to 0 to indicate that the frequency adjustment is complete.

[0096] Step 16: The master clock server and the clock client periodically execute steps 1-15 to achieve network synchronization.

[0097] The clock synchronization method according to the embodiment of the present invention has the following beneficial effects:

[0098] A method for improving time synchronization accuracy is proposed. Based on the IEEE802.1AS protocol, the time deviation of different nodes in the network is calculated through interactive message transmission. The time deviation is written into a logic register, and the time error is adjusted internally in the logic to achieve time synchronization of the nodes in the network. At the same time, the frequency error between the master clock server and the clock client due to crystal oscillator offset is calculated by using the transmission of messages during the synchronization process. The frequency error calculated by the software is written into the logic register. The time error introduced by crystal oscillator drift is compensated and corrected internally in the logic, thereby improving the accuracy of time synchronization.

[0099] The above description is merely a specific embodiment of the present invention and should not be construed as limiting the scope of the invention. Therefore, substitutions of equivalent components, or equivalent changes and modifications made within the scope of patent protection, should still fall within the scope of this patent. Furthermore, the technical features of the present invention may be freely combined with one another, with other technical solutions, and with other technical solutions.

Claims

1. A clock synchronization method for a time-sensitive network, characterized in that: include: Calculating a link delay D between the master clock server and the clock client, and obtaining a clock frequency ratio r between the clock client and the master clock server based on the link delay D; Calculating a time phase error offset between the clock client and the master clock server using the link delay D and the clock frequency ratio r; Calculating a second adjustment direction sign_s and a nanosecond adjustment direction sign_ns by using the time phase error offset, and adjusting the time phase error of the local clock of the clock client by using the second adjustment direction sign_s and the nanosecond adjustment direction sign_ns; The time offsetPerNsec and the frequency adjustment direction fre_sign required for each 1 nanosecond frequency error are calculated according to the clock frequency ratio r, and the frequency error of the local clock of the clock client is adjusted according to the time offsetPerNsec and the frequency adjustment direction fre_sign required for the 1 nanosecond frequency error.

2. The clock synchronization method for a time-sensitive network according to claim 1, wherein: Calculate the link delay D between the master clock server and the clock client, including: The clock client initiates a time synchronization request, and the master clock server responds to the time synchronization request; The clock client obtains the first time T1, the second time T2, the third time T3 and the fourth time T4 through the interaction process of the Pdelay_Req message, the Pdelay_Resp message and the Pdelay_Resp_Follow_Up message in the link delay measurement phase; The link delay D between the clock client and the master clock server is calculated based on the first time T1, the second time T2, the third time T3 and the fourth time T4, wherein the link delay D= = .

3. The clock synchronization method for a time-sensitive network according to claim 1, wherein: Calculating a clock frequency ratio r between the clock client and the master clock server using the link delay D includes: The clock server sends a continuous first synchronization message SYNC_i-1 and a second synchronization message SYNC_i to the clock client, and records a first sending timestamp t1_i-1 and a second sending timestamp t1_i; Recording a first receiving time t2_i-1 at which the clock client receives the first synchronization message SYNC_i-1 and a second receiving time t2_i at which the second synchronization message SYNC_i is received; The clock frequency ratio r is calculated based on the first sending timestamp t1_i-1, the second sending timestamp t1_i, the first receiving time t2_i-1 and the second receiving time t2_i, wherein the clock frequency ratio r= .

4. The clock synchronization method for a time-sensitive network according to claim 1, wherein: Calculating a time phase error offset between the clock client and the master clock server using the link delay D and the clock frequency ratio r includes: The master clock server periodically sends SYNC messages and records the sending time T5, fills the sending time T5 into the Follow_up message, and sends it to the clock client; The clock client receives the SYNC message and records the receiving time T6; The clock client parses the sending time T5, and calculates the time phase error offset between the clock client and the master clock server based on the clock frequency ratio r, the link delay D, the sending time T5, and the receiving time T6, where: .

5. The clock synchronization method for a time-sensitive network according to claim 1, wherein: The second adjustment direction sign_s and the nanosecond adjustment direction sign_ns are obtained by calculating the time phase error offset, including: If the time phase error offset is greater than or equal to 0, the second adjustment direction sign_s is 2, and the nanosecond adjustment direction sign_ns is 1; If the time phase error offset is less than 0, the second adjustment direction sign_s is 0, and the nanosecond adjustment direction sign_ns is 0.

6. The clock synchronization method for a time-sensitive network according to claim 1, wherein: Adjusting the time phase error of the local clock of the clock client by using the second adjustment direction sign_s and the nanosecond adjustment direction sign_ns includes: Adjust the nanosecond value of the local clock according to the nanosecond adjustment direction sign_ns, and determine whether a second carry is required; If the second increment is required, adjust the second value using the second adjustment direction sign_s and then add 1 second. If the second carry is not required, the second value of the local clock is adjusted using the second adjustment direction sign_s.

7. The clock synchronization method for a time-sensitive network according to claim 1, wherein: The time offsetPerNsec required for a 1 nanosecond frequency error and the frequency adjustment direction fre_sign are calculated according to the clock frequency ratio r, including: Setting a second set value, and calculating the frequency offset fre_offset and the correction direction fre_sign generated between the clock client and the master clock server within one second based on the clock frequency ratio r and the second set value; According to the frequency offset fre_offset, the time offsetPerNsec required for a frequency error of 1 nanosecond is calculated. If the frequency offset fre_offset is not equal to the second set value, the time offsetPerNsec required for a frequency error of 1 nanosecond is equal to / fre_offset; If the frequency offset fre_offset is equal to the second set value, the time offsetPerNsec required for a 1 nanosecond frequency error is equal to the second set value.

8. The clock synchronization method for a time-sensitive network according to claim 7, characterized in that: The frequency offset fre_offset and the correction direction fre_sign generated between the clock client and the master clock server within one second are calculated based on the clock frequency ratio r and the second set value, including: If the clock frequency ratio r is less than 1, the frequency offset fre_offset= - , the correction direction fre_sign=2; If the clock frequency ratio r is greater than 1, the frequency offset fre_offset= - , the correction direction fre_sign=1; If the clock frequency ratio r is equal to 1, the frequency offset fre_offset=the second set value.

9. The clock synchronization method for a time-sensitive network according to any one of claims 1 to 8, characterized in that: Also includes: The clock synchronization method for a time-sensitive network is executed periodically to achieve synchronization of the time-sensitive network.

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