Sampler circuit for high-speed serializer / deserializer

Abstract

The invention relates to a sampler circuit for a high speed serializer / deserializer. In one example, a circuit (400) includes a differential input circuit having a first input (310) at a first capacitor terminal and a second input (312) at a second capacitor terminal. The differential input circuit includes a first transistor (402) having a first transistor control terminal and first and second terminals. The differential input circuit includes a second transistor (404) having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors being coupled together. The circuit (400) includes a first capacitor (314) having a first capacitor terminal and having another terminal coupled to the first transistor control terminal. The circuit (400) also includes a second capacitor (316) having a second capacitor terminal and having another terminal coupled to the second transistor control terminal. The circuit (400) includes a first offset correction input (322) coupled to the first transistor control terminal and a second offset correction input (324) coupled to the second transistor control terminal.

Description

Background Art

[0001] High-speed data links can be used to transmit high-resolution signals, such as video. One high-speed digital video interface is Flat Panel Display Link (FPD-Link). FPD-Link is used in a variety of applications, such as connecting the output from a graphics processing unit (GPU) to a display panel. FPD-Link can also be used in automotive applications such as navigation systems, vehicle entertainment systems, and backup cameras, as well as advanced driver assistance systems and autonomous vehicles. The sensitivity and signal-to-noise ratio (SNR) of the link circuitry are factors that can affect the performance of the data link. Summary of the invention

[0002] In at least one example of the present specification, a circuit includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal. The differential input circuit includes a first transistor having a first transistor control terminal and a first terminal and a second terminal. The differential input circuit also includes a second transistor having a second transistor control terminal and a first terminal and a second terminal, the first terminals of the first transistor and the second transistor being coupled together. The circuit includes a first capacitor having a first capacitor terminal and having another terminal coupled to the first transistor control terminal. The circuit also includes a second capacitor having a second capacitor terminal and having another terminal coupled to the second transistor control terminal. The circuit includes a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal. The circuit includes a differential output circuit having a first output at a first inverter output, having a second output at a second inverter output, having a third transistor control terminal coupled to the second terminal of the first transistor, and having a fourth transistor control terminal coupled to the second terminal of the second transistor.

[0003] In at least one example of the present specification, a circuit includes a differential input circuit having a first transistor having a first transistor control terminal and a first terminal and a second terminal. The differential input circuit also includes a second transistor having a second transistor control terminal and a first terminal and a second terminal, the first terminals of the first transistor and the second transistor being coupled together. The circuit includes a first capacitor coupled to the control terminal of the first transistor and a second capacitor coupled to the control terminal of the second transistor. The circuit includes an offset correction circuit having a first terminal coupled to the control terminal of the first transistor and having a second terminal coupled to the control terminal of the second transistor. The circuit includes a differential output circuit having a third transistor having a third transistor control terminal coupled to the second terminal of the first transistor. The differential output circuit also includes a fourth transistor having a fourth transistor control terminal coupled to the second terminal of the second transistor. The circuit includes a preamplifier circuit having a first terminal coupled to the second terminal of the first transistor and the control terminal of the third transistor and having a second terminal coupled to the second terminal of the second transistor and the control terminal of the fourth transistor.

[0004] In at least one example of the present specification, a system includes an equalizer having an output. The system also includes an amplifier having an input coupled to the output of the equalizer and having an output. The system includes a sampler having a first input coupled to the output of the amplifier, having an offset input and having an output. The sampler includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal, the differential input circuit including a first transistor and a second transistor, the first transistor having a first transistor control terminal and a first terminal and a second terminal, and the second transistor having a second transistor control terminal and a first terminal and a second terminal. The sampler also includes a first capacitor having a first capacitor terminal and having another terminal coupled to the first transistor control terminal. The sampler includes a second capacitor having a second capacitor terminal and having another terminal coupled to the second transistor control terminal. The sampler includes a differential output circuit having a first output at a first inverter output, having a second output at a second inverter output, having a third transistor and having a fourth transistor, the third transistor having a third transistor control terminal coupled to the second terminal of the first transistor, and the fourth transistor having a fourth transistor control terminal coupled to the second terminal of the second transistor. The sampler includes a deserializer having an input coupled to an output of the sampler. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1is a block diagram of SerDes in various examples.

[0006] Figure 2 is a block diagram of the deserializer in various examples.

[0007] Figure 3 is a block diagram of the samplers used in various examples.

[0008] Figure 4 are circuit diagrams of samplers used in various examples.

[0009] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar (functionally and / or structurally) features. DETAILED DESCRIPTION

[0010] High-speed data links can use serializers and deserializers (SerDes) to transmit data over a single wire on the link. The serializer receives parallel data and converts it to serial data for transmission over the link. The deserializer receives serial data from the link and converts it back to parallel data. The deserializer samples the data signal in the received serial data in synchronization with a clock signal using a sampler circuit (such as a sampler circuit system or sampler). The sampler determines whether the data signal is a 1 or a 0, and then the received data is deserialized. The sampler can be a component of a decision feedback equalizer (DFE) circuit for accurately sampling the data signal. The DFE circuit uses a feedback loop with timing requirements so that the sample is determined before the next sample arrives at the link. Therefore, any delay in the sampler is small, helping to avoid errors.

[0011] A sampler circuit uses a strong ARM latch circuit having two differential input pairs: one pair for receiving an input signal and the other pair for providing an offset voltage at the input to set a reference voltage level for the input signal. In a strong ARM latch circuit, the differential input pair providing the offset voltage adds noise to the circuit. The cross-coupled latch in the strong ARM latch circuit also has transistor stacks coupled between a terminal receiving an input signal and a terminal receiving a voltage source, which may reduce the speed of the latch due to the time required for these transistors to turn on.

[0012] In an example of this article, a sampler circuit is described that applies an offset voltage to an input signal without using a second differential input pair. The offset voltage is AC coupled to the input signal differential pair. This structure provides a high impedance input for the offset voltage and eliminates the need for a second differential input pair, which results in lower noise and higher sensitivity than a strong ARM latch circuit. In the sampler circuit described in this article, the latch has fewer transistor stacks than a strong ARM latch circuit, which increases the speed of the sampler circuit. The sampler circuit described in this article includes a preamplifier circuit (also referred to as a preamplifier stage) that increases the sensitivity of the sampler circuit. The latch in the sampler circuit described in this article also has a fast regeneration time.

[0013] Figure 1 1 is a block diagram of a SerDes 100 in various examples herein. The SerDes 100 includes a sensor module 102 and an electronic control unit (ECU) 104 connected via a coaxial cable 106. The sensor module 102 includes a DC-DC regulator 108, an image sensor 110, and a serializer 112. The ECU 104 includes a power source 114, a deserializer 116, a processor system on chip (SOC) 118, and a sampler 120.

[0014] The DC-DC regulator 108 provides voltage to the image sensor 110 and the serializer 112. The image sensor 110 includes an output coupled to an input of the serializer 112. The serializer 112 has an output coupled to the coaxial cable 106. The deserializer 116 has an input coupled to the coaxial cable 106. The power source 114 provides power to the deserializer 116 and the processor SOC 118. The deserializer 116 has an output coupled to an input of the processor SOC 118.

[0015] Examples herein may be used for FPD-Link applications. Serializer 112 may be an FPD-Link serializer that supports high-speed raw data sensors (e.g., image sensor 110). Deserializer 116 may be an FPD-Link deserializer that receives serialized sensor data from a source via an FPD-Link interface. The data is received by deserializer 116 and provided to a processor (e.g., processor SOC 118).

[0016] In one example, the sensor module 102 may be a sensor module in an automobile, and the ECU 104 may be an automobile ECU. The image sensor 110 may receive an image from a camera (e.g., a backup camera). The image sensor 110 sends the image data to the serializer 112, which serializes the data. The serializer 112 transmits the data from the sensor module 102 to the ECU 104 via the coaxial cable 106. Instead of the coaxial cable 106, any other type of link may be used to transmit the data. The deserializer 116 in the ECU 104 receives the serialized data and performs deserialization using the sampler 120. The processor SOC 118 may then perform further processing of the deserialized data.

[0017] In the example herein, the deserializer 116 includes a sampler 120 as described above. The sampler 120 applies an offset voltage to the input signal without using a second differential input pair or a differential input circuit. In the sampler 120, the latch (not shown) has fewer transistor stacks than a strong ARM latch circuit, which increases the speed of the sampler 120. The sampler 120 includes a preamplifier stage (not shown) that increases the sensitivity of the sampler 120. Figure 3 and Figure 4 The sampler 120 is further described.

[0018] Figure 2 is a block diagram of the deserializer 116 in various examples herein. The deserializer 116 includes a continuous time linear equalization filter (CTLE) 202, a variable gain amplifier (VGA) 204, a summing amplifier 206, a DFE tap coefficient 208, and a sampler 120. The deserializer 116 also includes a deserializer circuitry 212, a clock and data recovery (CDR) 214, and a phase interpolator 216. Figure 2 Also shown is a voltage offset (V_offset) 218, an input signal 220, and a clock (CLK) signal 222. In other examples, the deserializer 116 may include other components, or may not include Figure 2 Some components are shown. The components in deserializer 116 may be located on one chip or on multiple chips.

[0019] In one example, the CTLE 202 has a Figure 2204). CTLE 202 has an output coupled to an input of VGA 204. Summing amplifier 206 has a first input coupled to the output of VGA 204 and a second input coupled to the output of DFE tap coefficients 208. Summing amplifier 206 has an output coupled to a first input of sampler 120. A second input of sampler 120 is coupled to a terminal that provides voltage offset 218. Sampler 120 has an output coupled to an input of deserializer circuitry 212. The output of sampler 120 is also coupled to an input of DFE tap coefficients 208. The output of deserializer circuitry 212 is coupled to an input of CDR 214. The output of deserializer circuitry 212 is also coupled to processor SOC 118 ( Figure 2 2. CDR 214 has an output coupled to an input of phase interpolator 216. Phase interpolator 216 has an output coupled to a clock input of sampler 120.

[0020] In operation, the deserializer 116 receives a serialized input signal 220 (eg, from the coaxial cable 106). The CTLE 202 equalizes the incoming input signal 220, and the VGA 204 amplifies the input signal 220. In one example, the summing amplifier 206, the DFE tap coefficients 208, and the sampler 120 are a DFE circuit.

[0021] The sampler 120 samples the incoming signal in synchronization with the CLK signal 222. The sampler 120 determines whether the incoming signal is a 1 or a 0 and then feeds the signal along with the DFE tap coefficients 208 back to the summing amplifier 206.

[0022] The feedback loop of the DFE circuit includes timing requirements. The decision from the sampler 120 must be fed back within one unit interval (1 UI) of the data signal. Therefore, a smaller delay from the sampler 120 provides better results. In the example sampler 120, the input from the summing amplifier 206 to the sampler 120 is AC coupled, and V_offset218 is applied directly to the same input using a resistor. Therefore, V_offset 218 is added at the input node of the sampler 120 along with the incoming signal. As described above, this structure eliminates the need for another differential input pair, which improves noise and sensitivity. In some examples, the deserializer 116 can have more than one DFE tap. In other examples, a loop-unrolled DFE is implemented instead of direct feedback to avoid the critical timing requirements of the first DFE tap.

[0023] Deserializer circuitry 212 receives serial input bits from sampler 120 and deserializes them, for example, deserializing the input bits 1:16 to create 16 parallel bits. The 16 parallel bits are provided to SOC 118 and CDR 214. CDR 214 determines whether the clock signal is centered on the data and then adjusts the phase of the clock using phase interpolator 216.

[0024] Figure 3 1 is a block diagram of a sampler 120 in various examples herein. The sampler 120 includes a differential input circuit 302 (also referred to as a differential input stage 302), a preamplifier circuit 304 (also referred to as a preamplifier stage 304), a differential output circuit 306 (also referred to as a differential output stage 306), an offset correction circuit 308, and capacitors 314 and 316. The sampler 120 also has a first input voltage terminal 310, a second input voltage terminal 312, offset voltage terminals 322 and 324, a first output voltage terminal 326 (V OUTP ) and the second output voltage terminal 328 (V OUTN ).

[0025] The offset correction circuit 308 includes resistors 318 and 320 and offset voltage terminals 322 and 324. The offset correction circuit 308 may also include circuitry 330 that provides one or more offset voltages to the offset voltage terminals 322 and 324. In the illustrated example, the circuitry 330 is implemented as a capacitor digital-to-analog (DAC) converter. The capacitor DAC 330 may be coupled to a processor (not shown) that provides a digital code to the capacitor DAC 330. However, any suitable circuitry may be used to provide one or more offset voltages to the offset voltage terminals 322 and 324.

[0026] The differential input stage 302 has an output coupled to an input of the preamplification stage 304 and an input of the differential output stage 306. The capacitor 314 has a first capacitor terminal coupled to the first input voltage terminal 310 and a second capacitor terminal coupled to the differential input stage 302 and the resistor 318. The capacitor 316 has a first capacitor terminal coupled to the second input voltage terminal 312 and a second capacitor terminal coupled to the differential input stage 302 and the resistor 320. The resistor 318 has a first terminal coupled to the differential input stage 302 and a second terminal coupled to the offset voltage terminal 322. The resistor 320 has a first terminal coupled to the differential input stage 302 and a second terminal coupled to the offset voltage terminal 324. The offset correction circuit 308 has a first terminal coupled to the differential stage 302 and the capacitor 314, and has a second terminal coupled to the differential stage 302 and the capacitor 316.

[0027] In one example, a differential input signal is received at the first input voltage terminal 310 and the second input voltage terminal 312. For example, a voltage V is received at the first input voltage terminal 310. INP (positive input voltage), and receives a voltage V at the second input voltage terminal 312 INN (negative input voltage). The differential input stage 302 receives a differential input signal. Figure 4 An example differential input stage 302 is depicted.

[0028] In this example, a differential output signal is provided at the first output voltage terminal 326 and the second output voltage terminal 328. For example, a voltage V is provided at the first output voltage terminal 326. OUTP (positive output voltage), and provides a voltage V at the second output voltage terminal 328 OUTN (negative output voltage). The differential output stage 306 provides a differential output signal. Figure 4 An example differential output stage 306 is depicted.

[0029] In an example operation, an offset voltage is applied between offset voltage terminals 322 and 324. Here, voltage VOSN is received at offset voltage terminal 322, and voltage VOSP is received at offset voltage terminal 324. In this example, no differential input pair is used to provide the offset voltage to sampler 120, which reduces noise in sampler 120. The offset voltage allows the differential input signal to be sliced ​​at a certain reference voltage. Resistors 318 and 320 provide a high impedance input for the offset voltage, so the offset voltage is defined as any suitable value. Capacitors 314 and 316 are AC coupled to the differential input signal provided to differential input stage 302. In one example, the values ​​of resistors 318 and 320 and capacitors 314 and 316 are set to produce a resistor-capacitor (RC) value of approximately 10 megahertz (MHz). In one example, capacitors 314 and 316 are approximately 150 femtofarads, while resistors 318 and 320 are approximately 100 kilo-ohms. In some examples, the offset voltage is set between 0V and 800mV.

[0030] The preamplifier stage 304 amplifies the differential input signal, thereby providing the amplified signal to the differential output stage 306. The preamplifier stage 304 includes any suitable circuit system for amplifying the differential input signal. Figure 4 An example preamplification stage 304 is depicted.

[0031] When implemented as a cross-coupled latch, the differential output stage 306 receives the amplified differential input signal from the differential input stage 302 and latches or captures a data sample in response to the clock signal. The differential output stage 306 generates a high value or a low value (e.g., a data sample) at the differential output based on the differential input signal. The sampler 120 provides a clock signal to the differential output stage 306. Figure 2 The deserializer circuitry 212 shown in provides data sampling. An example cross-coupled latch that is faster than the strong ARM latch circuit is described below.

[0032] Figure 4 4 is a circuit diagram of a sampler 400 in various examples herein. In some examples, the sampler 400 is an example of the sampler 120. The sampler 400 includes a differential input stage 302, a preamplification stage 304, and a differential output stage 306. As described above with reference to Figure 3 As described, the sampler 400 includes a first input voltage terminal 310 , a second input voltage terminal 312 , capacitors 314 and 316 , resistors 318 and 320 , offset voltage terminals 322 and 324 , a first output voltage terminal 326 , and a second output voltage terminal 328 .

[0033] Differential input stage 302 includes transistors 402 and 404. Preamplifier stage 304 includes transistors 406, 408, and 410. Node 412 (V 1N ) and 414 (V 1P ) is also shown in the preamplifier stage 304. The differential output stage 306 includes transistors 416, 418, 420, 422, 424, 426, 428, and 430. The differential output stage 306 includes inverters 432 and 434 and a node 436 (R ON ) and 438 (R OP ).

[0034] The sampler 400 further includes transistors 440 and 442. The first voltage terminal 444 provides a voltage V to the sampler 400. DD The second voltage terminal 446 provides a second voltage to the sampler 400 , which in one example is ground (GND). The sampler 400 also receives a clock (CLK) signal provided by a clock source (not shown) via a clock terminal 448 .

[0035] In this example, the transistors in sampler 400 are field effect transistors (FETs). However, other types of transistors may be used in other examples. As shown, transistors 402, 404, 416, 418, 420, 422, 440, and 442 are n-channel FETs, while transistors 406, 408, 410, 424, 426, 428, and 430 are p-channel FETs. In one example, the transistors described herein each include a gate or control terminal. In one example, each transistor described herein also includes a source terminal and a drain terminal, which are referred to herein as a first terminal and a second terminal, and vice versa.

[0036] As shown, transistor 402 includes a gate or control terminal coupled to capacitor 314 and resistor 318. First input voltage terminal 310 provides the positive portion of the differential input signal (eg, V INP ). The drain of transistor 402 is coupled to node 412 and transistor 406, and the source of transistor 402 is coupled to transistor 404 and transistor 440. Transistor 404 includes a gate or control terminal coupled to capacitor 316 and resistor 320. Second input voltage terminal 312 provides the negative portion of the differential input signal (e.g., V INN ). The drain of transistor 404 is coupled to node 414 and transistor 408, and the source of transistor 404 is coupled to transistor 402 and transistor 440. The differential input stage 302 receives a differential input signal across the first input voltage terminal 310 and the second input voltage terminal 312. The differential input signal is offset by an offset voltage provided by offset voltage terminals 322 and 324. The differential input signal is amplified by the preamplification stage 304 and then provided to the differential output stage 306 for sampling.

[0037] Preamplifier stage 304 includes transistors 406, 408, and 410. Transistor 406 has a gate or control terminal coupled to clock terminal 448. Transistor 406 has a source coupled to first voltage terminal 444 and a drain coupled to node 412 and transistor 402. Transistor 408 has a gate or control terminal coupled to clock terminal 448 and the gate of transistor 406. Transistor 408 has a source coupled to first voltage terminal 444 and a drain coupled to node 414 and transistor 404. Transistor 410 has a gate coupled to clock terminal 448, a drain coupled to node 412, and a source coupled to node 414. Transistors 406, 408, and 410 are clock-gated transistors. Clock-gated transistors receive a clock signal at their gates or control terminals, and these transistors are turned on or off based on the clock signal.

[0038] Differential output stage 306 includes transistors 416, 418, 420, 422, 424, 426, 428, and 430, inverters 432 and 434, and node 436 (R ON ) and 438 (R OP ). Transistor 416 has a gate coupled to node 414, a drain coupled to the drain of transistor 418 and node 436, and a source coupled to the sources of transistors 418, 420, and 422. Transistor 418 has a gate coupled to the gate of transistor 426 and a gate coupled to node 438. Transistor 418 has a drain coupled to the drain of transistor 416 and a source coupled to the sources of transistors 416, 420, and 422. Transistor 420 has a gate coupled to the gate of transistor 428 and node 436, a drain coupled to the drain of transistor 422, and a source coupled to the sources of transistors 416, 418, and 422. Transistor 422 has a gate coupled to node 412, a drain coupled to the drain of transistor 420, and a source coupled to the sources of transistors 416, 418, and 420. As Figure 4 As shown, transistors 416 and 422 are coupled to the differential input stage 302 and the preamplification stage 304 via their respective gates or control terminals. Thus, transistors 416 and 422 are components of the differential output stage 306 that receives the differential input signal from the differential input stage 302.

[0039] Transistor 424 in differential output stage 306 has a gate coupled to clock terminal 448, a drain coupled to node 436 and the drain of transistor 426, and a source coupled to first voltage terminal 444. Transistor 426 has a gate coupled to the gate of transistor 418 and node 438, a drain coupled to node 436 and the drain of transistor 424, and a source coupled to first voltage terminal 444. Transistor 428 has a gate coupled to the gate of transistor 420 and node 436, a drain coupled to node 438 and the drain of transistor 430, and a source coupled to first voltage terminal 444. Transistor 430 has a gate coupled to clock terminal 448, a drain coupled to node 438 and the drain of transistor 428, and a source coupled to first voltage terminal 444. Transistors 424 and 430 are clock gating transistors.

[0040] The differential output stage 306 also includes inverters 432 and 434. Inverter 432 has an inverter input coupled to node 436 and an inverter output (V OUTP Inverter 434 has an inverter input coupled to node 438 and an inverter output (V OUTN ). A differential output signal is provided across output voltage terminals 326 and 328.

[0041] Sampler 400 also includes transistors 440 and 442. Transistor 440 has a gate coupled to clock terminal 448, a drain coupled to the sources of transistors 402 and 404, and a source coupled to a second voltage terminal 446 (e.g., ground). Transistor 442 has a gate coupled to the gate of transistor 440 and clock terminal 448, a drain coupled to the sources of transistors 416, 418, 420, and 422, and a source coupled to a second voltage terminal 446 (e.g., ground). Transistors 440 and 442 are clock-gated transistors.

[0042] In operation, the sampler 400 receives a differential input signal at the differential input stage 302. The preamplifier stage 304 amplifies the differential input signal and provides the differential input signal to the differential output stage 306 when the clock signal is high. When the clock signal changes from low to high, the differential output stage 306 exits reset and makes a decision (0 or 1) based on the differential input signal and provides a differential output signal between the output voltage terminals 326 and 328.

[0043] Sampler 400 latches a differential input signal to generate an output signal in response to a clock signal from a clock source provided to clock terminal 448. The differential input signal is received at first input voltage terminal 310 and second input voltage terminal 312. The input signal is not latched until the clock signal goes high. First, when the input signal is received, the clock signal is low. Therefore, a low value is provided at clock terminal 448. If the voltage at clock terminal 448 is low, transistors 406 and 408 are turned on due to the low voltage at their respective gates. Therefore, nodes 412 and 414 are pulled high to V DD Transistor 410 is also turned on due to the low clock signal at its gate. Transistors 424, 426, 428, and 430 are also turned on in response to the low clock signal at clock terminal 448, and nodes 436 and 438 are pulled high to V DD The low clock signal also turns off transistors 440 and 442. If transistor 440 is off, transistors 402 and 404 of the differential input stage are also off. If transistor 442 is off, transistors 416, 418, 420, and 422 are also off.

[0044] Because the low clock signal pulls nodes 412, 414, 436, and 438 high, the sampler 400 can quickly latch and provide a differential output signal that meets the timing requirements of the SerDes when the clock transitions. In response to the transition of the clock signal from low to high, the sampler 400 will latch the value of the differential input signal and generate a differential output signal. As described above, the differential input signal is received between the first input voltage terminal 310 and the second input voltage terminal 312. The offset voltage terminals 322 and 324 can increase the level of the differential input signal by providing an offset voltage at the differential input. As described above, by providing an offset voltage directly at the differential input stage 302, rather than using a second differential input pair to provide an offset voltage, noise is reduced.

[0045] A differential input signal is received at the first input voltage terminal 310 and the second input voltage terminal 312, which will produce a small voltage difference between the two voltage terminals. When the clock transitions from low to high, transistors 440 and 442 are turned on due to the high clock signal at their respective gates. Transistor 440 is turned on and pulls the source terminals of transistors 402 and 404 low (e.g., to ground). Transistors 402 and 404 have differential input signals at their respective gates and their sources are pulled low, thereby turning on transistors 402 and 404. When transistors 402 and 404 are turned on, the voltages at nodes 412 and 414 are pulled down. At this time, transistors 406, 408 and 410 have low clock signals at their respective gates, so the voltages at nodes 412 and 414 are pulled down by transistors 402 and 404. These voltages (V 1N and V 1P ) will be pulled to near zero (e.g., ground) by the voltage difference between them, where the voltage difference is based on the differential input voltage.

[0046] The voltage signals at nodes 412 and 414 are provided to the differential output stage 306. Node 414 is coupled to the gate of transistor 416, and node 412 is coupled to the gate of transistor 422. The high clock signal at the gate of transistor 442 turns on transistor 442, which causes transistors 416, 418, 420, and 422 to turn on. The voltage values ​​at nodes 436 and 438 were previously high, but now are pulled down because the clock signal goes high and transistors 416, 418, 420, and 422 are turned on. The voltage values ​​at nodes 436 and 438 are pulled down slightly before latching to their final values. One node (436 or 438) will latch to a high value, while the other node (436 or 438) will latch to a low value. These values ​​are inverted by inverters 432 and 434, and then provide differential output signals at output voltage terminals 326 and 328.

[0047] In one example operation, the differential input signal (V INN ) is higher than the signal at the first input voltage terminal 310 (V INP ). Thus, when the clock transitions from low to high, transistor 404 conducts slightly more current than transistor 402. This causes the voltage at node 414 to discharge faster than the voltage at node 412 (e.g., the voltage at node 414 is pulled below the voltage at node 412). The voltage at node 412 being higher than the voltage at node 414 causes transistor 422 in the differential output stage 306 to turn on faster than transistor 416. Because transistor 422 turns on faster than transistor 416, transistor 426 turns on faster than transistor 428. Transistor 426 has a drain coupled to node 436, and node 436 is pulled high faster than node 438. Thus, the voltage at node 436 latches high, while the voltage at node 438 latches low. Inverters 432 and 434 invert the differential output voltages before providing them to output voltage terminals 326 and 328. V at first output voltage terminal 326 is OUTP becomes low, and V at the second output voltage terminal 328 OUTN In short, the higher the input signal V INN Produces a higher output signal V OUTN In the opposite operation, if the differential input signal (V INP ) is higher than the signal at the second input voltage terminal 312 (V INN ), then V OUTP (first output voltage terminal 326) will provide a high output signal, and V OUTN (The second output voltage terminal 328) will provide a low output signal.

[0048] In the example described herein, the sampler circuit applies an offset voltage to the input signal without using a second differential input pair. The offset voltage is AC coupled to the input signal differential pair. This structure provides a high impedance input for the offset voltage, thereby providing lower noise and higher sensitivity. The latch described herein has fewer transistor stacks than a strong ARM latch circuit, which increases the speed of the sampler circuit. The latch in the sampler circuit described herein also has a fast regeneration time. The sampler circuit described herein also includes a preamplifier stage that increases the sensitivity of the sampler circuit.

[0049] In this specification, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B through a direct connection; or (b) in a second example, if the intervening component C does not substantially change the functional relationship between device A and device B, device A is coupled to device B through an intervening component C, so that device B is controlled by device A via the control signal generated by device A.

[0050] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by the manufacturer at the time of manufacture to perform that function, and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnects, or a combination thereof.

[0051] Circuits or devices described herein as including certain components may instead be adapted to be coupled to these components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and / or inductors), and / or one or more sources (such as voltage sources and / or current sources) may instead include only the semiconductor element within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the structure during or after manufacturing (e.g., by an end user and / or a third party).

[0052] Although certain components may be described herein as belonging to a specific process technology, these components may be replaced with components of other process technologies. The circuits described herein may be reconfigured to include replaceable components to provide functionality that is at least partially similar to the functionality available before the component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the impedance amount represented by the illustrated resistor. For example, a resistor or capacitor shown and described herein as a single component may be replaced with multiple resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may be replaced with multiple resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0053] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used with little or no change to the remaining circuitry. For example, metal oxide silicon field effect transistors ("MOSFETs") (e.g., n-channel MOSFETs (nMOSFETs) or p-channel MOSFETs (pMOSFETs)), bipolar junction transistors (BJTs, such as NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, natural transistors, or other types of device structure transistors. Furthermore, these devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs). Generally, herein, a transistor has a control input / control terminal (e.g., gate, base) and two additional terminals (e.g., source / drain, collector / emitter).

[0054] The phrase "ground" used in the above description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "approximately" or "substantially" preceding a parameter means within + / -10% of the parameter. Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

[0055] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection or an end point thereof between a device element, a circuit element, an integrated circuit, a device or a semiconductor component. In addition, a voltage rail or more simply a "rail" may also be referred to as a voltage terminal and may generally mean a common node or a group of coupled nodes in a circuit that are at the same potential.

Claims

1. A circuit comprising: A differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal, the differential input circuit comprising: a first transistor having a first transistor control terminal and a first terminal and a second terminal; and a second transistor having a second transistor control terminal and a first terminal and a second terminal, the first terminals of the first transistor and the second transistor being coupled together; a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal; a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal; a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal; and A differential output circuit having a first output at a first inverter output, having a second output at a second inverter output, having a third transistor control terminal coupled to the second terminal of the first transistor, and having a fourth transistor control terminal coupled to the second terminal of the second transistor.

2. The circuit according to claim 1, further comprising: a first resistor having a first terminal coupled to the first transistor control terminal and having a second terminal as the first offset correction input; as well as A second resistor has a first terminal coupled to the second transistor control terminal and has a second terminal as the second offset correction input.

3. The circuit of claim 2, further comprising a capacitor digital-to-analog converter coupled to the first resistor and the second terminal of the second resistor.

4. The circuit of claim 1 , further comprising a cross-coupled latch, wherein the cross-coupled latch comprises: a third transistor having a third transistor control terminal coupled to the first transistor and having a first terminal and a second terminal; a fourth transistor having a fourth transistor control terminal coupled to the second transistor and having a first terminal and a second terminal, the first terminals of the third transistor and the fourth transistor being coupled together; a fifth transistor having a fifth transistor control terminal coupled to the third transistor and having a first terminal and a second terminal; as well as A sixth transistor having a sixth transistor control terminal coupled to the fourth transistor and having a first terminal and a second terminal, the first terminals of the fifth transistor and the sixth transistor being coupled together, and wherein the cross-coupled latch includes a differential output.

5. The circuit of claim 4, wherein the differential output circuit comprises: a first inverter having the first inverter output and having an input coupled to the second terminal of the fourth transistor; as well as A second inverter has the second inverter output and has an input coupled to the second terminal of the third transistor.

6. The circuit according to claim 1, further comprising: A preamplifier circuit has a first terminal coupled to the second terminal of the first transistor and the third transistor control terminal, and has a second terminal coupled to the second terminal of the second transistor and the fourth transistor control terminal.

7. The circuit of claim 6, wherein the preamplifier circuit comprises: a third transistor having a control terminal and a first terminal and a second terminal, wherein the first terminal of the third transistor is coupled to the first transistor and the cross-coupled latch; as well as A fourth transistor has a control terminal and a first terminal and a second terminal, wherein the first terminal of the fourth transistor is coupled to the second transistor and the cross-coupled latch.

8. A circuit comprising: A differential input circuit comprising: a first transistor having a first transistor control terminal and a first terminal and a second terminal; and a second transistor having a second transistor control terminal and a first terminal and a second terminal, the first terminals of the first transistor and the second transistor being coupled together; a first capacitor coupled to the control terminal of the first transistor; a second capacitor coupled to the control terminal of the second transistor; an offset correction circuit having a first terminal coupled to the control terminal of the first transistor and having a second terminal coupled to the control terminal of the second transistor; A differential output circuit comprising: a third transistor having a third transistor control terminal coupled to the second terminal of the first transistor; and a fourth transistor having a fourth transistor control terminal coupled to the second terminal of the second transistor; and A preamplifier circuit has a first terminal coupled to the second terminal of the first transistor and the control terminal of the third transistor, and has a second terminal coupled to the second terminal of the second transistor and the control terminal of the fourth transistor.

9. The circuit of claim 8, wherein the offset correction circuit comprises: a first resistor having the first terminal of the offset correction circuit and having a second terminal, the first terminal of the offset correction circuit being coupled to the first transistor control terminal; as well as A second resistor having the second terminal of the offset correction circuit and having a second terminal, the second terminal of the offset correction circuit being coupled to the second transistor control terminal.

10. The circuit of claim 9, wherein the offset correction circuit comprises a capacitor digital-to-analog converter coupled to the first resistor and the second terminal of the second resistor.

11. The circuit of claim 8, further comprising a cross-coupled latch, wherein the cross-coupled latch comprises: a fifth transistor having a fifth transistor control terminal coupled to the third transistor and having a first terminal and a second terminal; as well as A sixth transistor having a sixth transistor control terminal coupled to the fourth transistor and having a first terminal and a second terminal, the first terminals of the fifth transistor and the sixth transistor being coupled together, and wherein the cross-coupled latch includes a differential output.

12. The circuit of claim 11, wherein the differential output circuit comprises: a first inverter having a first inverter output and having an input coupled to the second terminal of the fourth transistor; as well as A second inverter has a second inverter output and has an input coupled to the second terminal of the third transistor.

13. The circuit according to claim 8, further comprising: A preamplifier circuit has a first terminal coupled to the second terminal of the first transistor and the third transistor control terminal, and has a second terminal coupled to the second terminal of the second transistor and the fourth transistor control terminal.

14. The circuit of claim 13, wherein the preamplifier circuit comprises: a fifth transistor having a fifth transistor control terminal and a first terminal and a second terminal, wherein the first terminal of the fifth transistor is coupled to the first transistor and the cross-coupled latch; as well as A sixth transistor has a sixth transistor control terminal and a first terminal and a second terminal, wherein the first terminal of the sixth transistor is coupled to the second transistor and the cross-coupled latch.

15. A system comprising: an equalizer having an output; an amplifier having an input coupled to the output of the equalizer and having an output; a sampler having a first input coupled to the output of the amplifier, having an offset input, and having an output, the sampler comprising: a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal, the differential input circuit comprising a first transistor and a second transistor, the first transistor having a first transistor control terminal and a first terminal and a second terminal, and the second transistor having a second transistor control terminal and a first terminal and a second terminal; a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal; a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal; a differential output circuit having a first output at a first inverter output, having a second output at a second inverter output, having a third transistor having a third transistor control terminal coupled to the second terminal of the first transistor, and having a fourth transistor having a fourth transistor control terminal coupled to the second terminal of the second transistor; and A deserializer has an input coupled to the output of the sampler.

16. The system of claim 15, wherein the sampler further comprises: A fifth transistor having a fifth transistor control terminal and a first terminal and a second terminal, wherein the first terminal of the fifth transistor is coupled to the second terminal of the first transistor and the second terminal of the second transistor, and wherein the fifth transistor is configured to turn on the first transistor and the second transistor.

17. The system of claim 16, wherein the sampler further comprises: A sixth transistor having a sixth transistor control terminal and a first terminal and a second terminal, wherein the first terminal of the sixth transistor is coupled to a cross-coupled latch, and wherein the sixth transistor is configured to turn on one or more transistors in the cross-coupled latch.

18. The system of claim 15, further comprising: A cross-coupled latch is coupled to the second terminal of the first transistor and the second terminal of the second transistor.

19. The system of claim 15, wherein the sampler further comprises: A preamplifier circuit has a first terminal coupled to the second terminal of the first transistor and the third transistor control terminal, and has a second terminal coupled to the second terminal of the second transistor and the fourth transistor control terminal.

20. The system of claim 19, wherein the preamplifier circuit comprises: a fifth transistor having a fifth transistor control terminal and a first terminal and a second terminal, wherein the first terminal of the fifth transistor is coupled to the first transistor and the cross-coupled latch; as well as A sixth transistor has a sixth transistor control terminal and a first terminal and a second terminal, wherein the first terminal of the sixth transistor is coupled to the second transistor and the cross-coupled latch.

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