Display device and method for manufacturing display device

Abstract

A display device and a method of manufacturing the display device are provided. The display device includes a transistor including an active layer disposed on a substrate and a gate electrode disposed on the active layer, a gate insulating layer disposed between the active layer and the gate electrode, and a first insulating layer disposed on the gate electrode. The first insulating layer may include a first layer covering the active layer, the gate insulating layer, and the gate electrode and including silicon oxide, a second layer disposed on the first layer and including silicon oxynitride, and a third layer disposed on the second layer and including silicon nitride.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0130923, filed in the Korean Intellectual Property Office on September 27, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a display device and a method for manufacturing the display device. Background Art

[0004] As multimedia develops, display devices become more and more important. Therefore, various display devices including light-emitting display devices have been studied and developed. Summary of the invention

[0005] Embodiments provide a display device capable of improving operating characteristics of a transistor and a method of manufacturing the display device.

[0006] However, the aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below.

[0007] According to one aspect of the present disclosure, a display device is provided, the display device comprising: a transistor including an active layer disposed on a substrate and a gate electrode disposed on the active layer, a gate insulating layer disposed between the active layer and the gate electrode, and a first insulating layer disposed on the gate electrode. The first insulating layer may include: a first layer covering the active layer, the gate insulating layer and the gate electrode and including silicon oxide; a second layer disposed on the first layer and including silicon oxynitride; and a third layer disposed on the second layer and including silicon nitride.

[0008] In an embodiment, the thickness of the second layer may be about to about within the range.

[0009] In an implementation, the nitrogen content of the second layer may be in a range of about 1 atomic % to about 10 atomic %.

[0010] In an embodiment, the thickness of the first layer may be about to about within the range.

[0011] In an embodiment, the nitrogen content of the first layer may be less than 1 atomic %.

[0012] In an embodiment, the thickness of the third layer may be about to about within the range.

[0013] In an implementation, the nitrogen content of the third layer may be in the range of about 30 atomic % to about 60 atomic %.

[0014] In an embodiment, in a region where the first insulating layer covers one side of the gate electrode, the distance between the first layer and the third layer may be approximately or larger.

[0015] In an embodiment, the active layer may include an oxide semiconductor.

[0016] In an implementation, the gate insulating layer may be disposed on a portion of the active layer overlapping the gate electrode and exposing other portions of the active layer, and the first insulating layer may directly cover the other portions of the active layer.

[0017] In an embodiment, the transistor may further include at least one of a source electrode disposed on the first insulating layer and connected to a portion of the active layer and a drain electrode disposed on the first insulating layer and connected to another portion of the active layer.

[0018] In an implementation, the transistor may further include a bottom gate electrode disposed between the substrate and the active layer.

[0019] In an embodiment, the display device may further include: a passivation layer disposed on the first insulating layer and covering the transistor, a light emitting element disposed on the passivation layer, and an encapsulation layer covering the light emitting element.

[0020] In an embodiment, the display device may further include: a capacitor electrode disposed on the first insulating layer and overlapping the gate electrode, and a second insulating layer covering the capacitor electrode.

[0021] According to one aspect of the present disclosure, a display device is provided, the display device comprising: a transistor, the transistor comprising an active layer disposed on a substrate and a gate electrode disposed on the active layer; a gate insulating layer, the gate insulating layer disposed between the active layer and the gate electrode; and an insulating layer, the insulating layer disposed on the gate electrode and comprising a first layer and a second layer, the first layer covering the active layer, the gate insulating layer and the gate electrode and comprising silicon oxide, the second layer disposed on the first layer and comprising silicon oxynitride. The thickness of the second layer may be about to about within the range.

[0022] In an implementation, the nitrogen content of the second layer may be in a range of about 1 atomic % to about 10 atomic %.

[0023] In an embodiment, the thickness of the first layer may be about to about within the range.

[0024] In an implementation, the insulating layer may further include a third layer disposed on the second layer and including silicon nitride.

[0025] According to one aspect of the present disclosure, a method for manufacturing a display device is provided, comprising: forming an active layer on a substrate; forming a gate insulating layer and a gate electrode on the active layer; and forming an insulating layer on the gate electrode. Forming the insulating layer may include: forming a first layer covering the active layer, the gate insulating layer and the gate electrode on the substrate and including silicon oxide; forming a second layer including silicon oxynitride on the first layer; and forming a third layer including silicon nitride on the second layer.

[0026] In an embodiment, the second layer may have about to about Thickness.

[0027] According to the foregoing and other embodiments, the display device may include a first insulating layer disposed on a gate electrode of a transistor. In some embodiments, the first insulating layer may include a first layer covering an active layer of the transistor, a gate insulating layer, and a gate electrode of the transistor and including silicon oxide, and a second layer disposed on the first layer and including silicon oxynitride. In some embodiments, the first insulating layer may also include a third layer disposed on the second layer and including silicon nitride.

[0028] Since the active layer and the gate electrode of the transistor are sequentially covered by the first layer, the second layer and / or the third layer of the first insulating layer, the effective channel length and operability characteristics of the transistor can be fully or appropriately ensured, and at the same time, moisture penetration can be effectively prevented. Accordingly, the reliability of the transistor and the display device including the transistor can be ensured.

[0029] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and other effects of the present disclosure will be apparent through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is a schematic plan view showing a display device according to an embodiment;

[0032] Figure 2 It is shown Figure 1 A schematic plan view of a display panel;

[0033] Figure 3 is a schematic cross-sectional view showing a display panel according to an embodiment;

[0034] Figure 4 It is shown Figure 3An enlarged schematic cross-sectional view of a region A1;

[0035] Figure 5 is a schematic cross-sectional view showing a display panel according to an embodiment; and

[0036] Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig.12 is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0037] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the devices or methods disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent settings. Here, various embodiments need not be exclusive, nor do they limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment.

[0038] Unless otherwise specified, the illustrated embodiments should be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0039] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiment can be implemented in different ways, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order. Moreover, similar reference numerals represent similar elements.

[0040] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, the element or layer may be directly on, connected to or coupled to another element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intervening element. In addition, the axis of the first direction D1, the axis of the second direction D2 and the axis of the third direction D3 are not limited to the three axes of a rectangular coordinate system (such as the X-axis, the Y-axis and the Z-axis), and may be interpreted in a broader sense. For example, the axis of the first direction D1, the axis of the second direction D2 and the axis of the third direction D3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of A and B" may be understood to mean only A, only B, or a combination of A and B. Moreover, "at least one of A, B, and C" and "at least one selected from the group consisting of A, B, and C" may be interpreted as any combination of only A, only B, only C, or two or more of A, B, and C. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0042] Spatially relative terms, such as "beneath," "below," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), and the like, may be used herein for descriptive purposes, and thus, to describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "beneath" other elements or features would subsequently be oriented to be "above" the other elements or features. Thus, the term "below" is capable of encompassing both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein should be interpreted accordingly.

[0043] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include the plural forms. In addition, when the terms "comprise", "comprising", "include" and / or "including" are used in this specification, the existence of the stated features, wholes, steps, operations, elements, parts and / or clusters thereof is specified, but the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or clusters thereof is not excluded. It is also noted that, as used herein, the terms "substantially", "about" and similar terms are used as terms of approximation rather than terms of degree, and thus, are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0044] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations resulting from, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the embodiments disclosed herein should not necessarily be construed as limited to the specific illustrated shapes of the regions, but rather include deviations in shape resulting from, for example, manufacturing. In this manner, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus are not necessarily intended to be limiting.

[0045] As is customary in the art, in terms of functional blocks, units and / or modules, some embodiments are shown and described in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and a processor that performs other functions (e.g., one or more programmed microprocessors and associated circuits). Moreover, without departing from the scope of the present invention, each block, unit and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the invention.

[0046] Figure 1 is a schematic plan view showing a display device 100 according to an embodiment. Figure 2 It is shown Figure 1 Schematic plan view of the display panel 110.

[0047] Reference Figure 1 and Figure 2 The display device 100 may be a device for displaying a video or a still image, and may be used as a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an e-book reader, a portable multimedia player (PMP), a navigation device, or an ultra mobile PC (UMPC) and various other products such as a television, a notebook computer, a monitor, an advertising board, or an Internet of Things (IoT) device. These are examples, and the display device 100 may also be applied to other electronic devices.

[0048] In an embodiment, the display device 100 may be a light-emitting display device, such as an organic light-emitting display device including an organic light-emitting diode (OLED), a quantum dot light-emitting display device including a quantum dot emission layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-small light-emitting display device using a micro light-emitting diode or a nano light-emitting diode (micro-LED or nano-LED), but the embodiment is not limited thereto. For example, the display device 100 may also be a display device other than a light-emitting display device. The display device 100 will be described below as, for example, an organic light-emitting display device.

[0049] The display device 100 may include a display panel 110 including pixels PX, and a first driving unit 120 and a second driving unit 130 that provide driving signals to the pixels PX. The display device 100 may also include additional components. For example, the display device 100 may include a power supply unit for supplying a power supply voltage to the pixels PX and the first driving unit 120 and the second driving unit 130, and a timing control unit for controlling the operation of the first driving unit 120 and the second driving unit 130.

[0050] The display panel 110 may include a display area DA and a non-display area NDA. The display area DA may be an area for displaying an image by using pixels PX. The non-display area NDA may be an area other than the display area DA, and an image may not be displayed in the non-display area NDA. In an embodiment, the non-display area NDA may be disposed around the display area DA and may surround the display area DA.

[0051] exist Figure 1 and Figure 2 , a first direction D1, a second direction D2, and a third direction D3 are defined. In an embodiment, the first direction D1 may be a lateral direction of the display panel 110 (e.g., a row direction or an X-axis direction), the second direction D2 may be a longitudinal direction of the display panel 110 (e.g., a column direction or a Y-axis direction), and the third direction D3 may be a thickness direction of the display panel 110 (e.g., a height direction or a Z-axis direction).

[0052] In an embodiment, the display panel 110 may have a planar rectangular shape. For example, the display panel 110 may have two first sides extending in a first direction D1 and two second sides extending in a second direction D2 crossing the first direction D1. Figure 1 and Figure 2The display panel 110 is shown in which the first side in the transverse direction is longer than the second side in the longitudinal direction, but the shape of the display panel 110 is not limited. For example, the display panel 110 may have a shape in which the second side in the longitudinal direction is longer than the first side in the transverse direction, or a shape in which the lengths of the first side and the second side are substantially the same as each other. The display panel 110 may have an angled corner or a rounded corner where the first side intersects the second side.

[0053] The planar shape of the display panel 110 is not limited to a rectangular shape, and various other shapes may also be applicable to the display panel 110. For example, the display panel 110 may have a square shape, a non-rectangular polygonal shape, a circular shape, an elliptical shape, an irregular shape, or other shapes in a plan view.

[0054] In an embodiment, the display panel 110 may be substantially flat on a plane defined by the first direction D1 and the second direction D2, and may have a uniform thickness in the third direction D3. In another example, the display panel 110 may be provided in a three-dimensional (3D) shape having a curve.

[0055] The display panel 110 may be provided as a rigid panel to prevent significant deformation or as a flexible panel bendable, foldable or rollable in at least a portion thereof. The display panel 110 may be provided to the display device 100 in an unbent state or in a bent state in some portions thereof.

[0056] The display panel 110 may include a substrate SUB and pixels PX disposed on the substrate SUB. The pixels PX may be disposed on the substrate SUB in the display area DA.

[0057] The substrate SUB may be used as a base member for manufacturing or providing the display panel 110, and may form a base surface of the display panel 110. The substrate SUB may include a display area DA and a non-display area NDA located around the display area DA.

[0058] The display area DA may have various shapes. For example, the display area DA may have a square shape, a non-square polygonal shape, a circular shape, an elliptical shape, an irregular shape, or other shapes. In an embodiment, the display area DA may have a shape that matches the shape of the display panel 110, but the embodiment is not limited thereto.

[0059] In the display area DA, pixels PX may be provided and / or arranged. For example, the display area DA may include a plurality of pixel areas where the pixels PX are disposed.

[0060] In an embodiment, the display device 100 may be a light-emitting display device, and each of the pixels PX may include a light-emitting element located in an emission region and a pixel circuit connected to the light-emitting element. Here, the term "connection" may cover electrical connection and / or physical connection. The pixel circuit may include a transistor (e.g., a pixel transistor, including a driving transistor that generates a driving current corresponding to a data signal and at least one switching transistor) and at least one capacitor (e.g., a storage capacitor).

[0061] The non-display area NDA may include a driving circuit area on at least one side of the display area DA and a pad area PA where a pad PD is disposed. In the non-display area NDA, at least one driving unit, pad PD, and / or wiring may be disposed.

[0062] In the driving circuit region, at least one driving unit or a portion of at least one driving unit for driving the pixel PX may be provided. For example, circuit components (e.g., driving transistors and capacitors forming a hierarchical circuit of the first driving unit 120) may be provided on the substrate SUB. In an embodiment, the circuit components of the first driving unit 120 may be formed in the display panel 110 together with the pixel PX.

[0063] The pad PD may be disposed in the pad area PA. On the pad area PA, at least one circuit board 140 may be disposed and / or bonded. In an embodiment, the circuit board 140 connected to different pads PD may be disposed on the pad area PA. The pad PD may include a signal pad and a power pad for transmitting a driving signal and a power supply voltage for driving the pixel PX and / or the first driving unit 120 to the display panel 110.

[0064] The first driving unit 120 and the second driving unit 130 may generate a driving signal for controlling the operation timing and brightness of the pixel PX, and may supply the driving signal to the pixel PX. For example, the first driving unit 120 may be a gate driving unit including a scan driver, and may be connected to the pixel PX through a corresponding gate line. The first driving unit 120 may supply a control signal (for example, a control signal for controlling the driving timing of the pixel PX, which includes a scan signal and / or an emission control signal) to the pixel PX. The second driving unit 130 may be a source driving circuit including a source driver, and may be connected to the pixel PX through a corresponding data line. The second driving unit 130 may supply a data signal to the pixel PX.

[0065] In an embodiment, at least one of the first driving unit 120 and the second driving unit 130 or a portion of the first driving unit 120 or the second driving unit 130 may be integrated into the display panel 110. For example, the first driving unit 120 or a portion of the first driving unit 120 may be disposed on the substrate SUB of the display panel 110 in the non-display area NDA.

[0066] Figure 1 An example is shown in which the first drive unit 120 is formed on one side of the display area DA (e.g., in the non-display area NDA on the right side of the display area DA), but the embodiment is not limited thereto. In another example, the first drive unit 120 may be located only on the other side of the display area DA (e.g., in the non-display area NDA only on the left side of the display area DA) or on both sides (e.g., opposite sides) of the display area DA (e.g., in the non-display area NDA on the left and right sides of the display area DA). In another example, a portion of the first drive unit 120 may be located in the non-display area NDA, and another portion of the first drive unit 120 may be located in a non-emission area within the display area DA (e.g., in an area between an emission area of ​​a pixel PX and an emission area of ​​another pixel PX).

[0067] In an embodiment, the other of the first driving unit 120 and the second driving unit 130 or a portion of the other driving unit may be disposed or formed outside the display panel 110, and may be electrically connected to the display panel 110. For example, the second driving unit 130 may be implemented using an integrated circuit chip, and may be disposed on a circuit board 140 electrically connected to the pixel PX of the display panel 110. The second driving unit 130 may be implemented as at least one integrated circuit chip and may be mounted on the non-display area NDA of the display panel 110.

[0068] The circuit board 140 may be connected to the display panel 110 via the pad PD. In an embodiment, the circuit board 140 may be a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF), but the embodiment is not limited thereto. In an embodiment, the circuit board 140 may be connected to the timing control unit and / or the power supply unit through other circuit boards or connectors.

[0069] Figure 3 is a schematic cross-sectional view showing a display panel 110 according to an embodiment. For example, Figure 3 Parts of a display area DA and a non-display area NDA of the display panel 110 are shown. Figure 3 A light-emitting display panel including a light-emitting element ED (eg, OLED) is depicted as an example of the display panel 110 .

[0070] Figure 4It is shown Figure 3 An enlarged schematic cross-sectional view of area A1 of FIG.

[0071] Reference Figure 3 and Figure 4 And further refer to Figure 1 and Figure 2 , the display panel 110 may include a substrate SUB (also referred to as a base layer), a panel circuit layer PCL, a light emitting element layer LEL, and an encapsulation layer ENL. The panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may overlap each other on the substrate SUB. For example, the panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be sequentially disposed or formed on the substrate SUB along the third direction D3 in the display area DA, but the embodiment is not limited thereto. The positions of the panel circuit layer PCL, the light emitting element layer LEL, and / or the encapsulation layer ENL may vary.

[0072] In an embodiment, the display panel 110 may further include additional components provided (or formed) on the top and / or bottom of the encapsulation layer ENL. For example, the display panel 110 may include at least one additional layer, such as a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a protective layer (e.g., a protective film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and the protective layer may be provided (or formed) on the upper surface of the encapsulation layer ENL or between the light emitting element layer LEL and the encapsulation layer ENL.

[0073] The substrate SUB may be a base member for forming the display panel 110, and may be a rigid or flexible substrate (or film). In an embodiment, the substrate SUB may be a rigid substrate including an insulating material such as glass and may not be bendable. In another example, the substrate SUB may include polyimide or another insulating material, and may be a flexible substrate that is bendable, foldable, or rollable. The type and material of the substrate SUB may vary.

[0074] The substrate SUB may include a display area DA and a non-display area NDA. In an embodiment, the display area DA may include a pixel area PXA corresponding to the pixel PX, and the non-display area NDA may include a driving circuit area DRA. For example, the pixel area PXA where the pixel PX is disposed may be defined in the display area DA, and the driving circuit area DRA where the first driving unit 120 is disposed may be defined in the non-display area NDA.

[0075] In an embodiment, the barrier layer BRL may be provided (or formed) on the substrate SUB. For example, the display panel 110 may further include a barrier layer BRL disposed between the substrate SUB and the panel circuit layer PCL. The display panel 110 may not include the barrier layer BRL, and the panel circuit layer PCL may be disposed (eg, directly disposed) on the substrate SUB.

[0076] The blocking layer BRL may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material). The blocking layer BRL may protect the pixel PX from moisture penetrating (or permeating) through the substrate SUB. The material of the blocking layer BRL may vary.

[0077] The panel circuit layer PCL may be disposed on a substrate SUB on which a barrier layer BRL is provided (or formed). The panel circuit layer PCL may include circuit components such as a pixel transistor Tpx and a driving transistor Tdr, and wiring (e.g., a signal line and a power line). In an embodiment, the panel circuit layer PCL may further include an additional conductive pattern layer (e.g., a bridge pattern layer).

[0078] The pixel transistor Tpx may be included in a pixel circuit of the pixel PX and may be located in the display area DA. For example, the pixel transistor Tpx may be disposed in a pixel area PXA of the pixel PX. Figure 3 A pixel transistor Tpx connected to the light emitting element ED of the pixel PX is shown, and the pixel transistor Tpx will be referred to as a first transistor TFT1 hereinafter.

[0079] The driving transistor Tdr may be included in the first driving unit 120 and may be located in the driving circuit area DRA. In an embodiment, the driving circuit area DRA may be disposed in the non-display area NDA. Figure 3 A driving transistor Tdr is shown, which will be referred to as the second transistor TFT2 hereinafter.

[0080] The transistor TFT (e.g., the first transistor TFT1 or the second transistor TFT2) may include an active layer (e.g., the first active layer ACT1 or the second active layer ACT2), and a gate electrode (e.g., the first gate electrode GE1 or the second gate electrode GE2) disposed on the active layer. In an embodiment, the transistor TFT may further include at least one of a bottom gate electrode (e.g., the first bottom gate electrode BG1 or the second bottom gate electrode BG2), a source electrode (e.g., the first source electrode SE1 or the second source electrode SE2), and a drain electrode (e.g., the first drain electrode DE1 or the second drain electrode DE2).

[0081] The panel circuit layer PCL may include a plurality of insulating layers disposed on the substrate SUB. For example, the panel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, a first insulating layer INS1 (also referred to as an interlayer insulating layer), and a passivation layer PSV sequentially disposed on the substrate SUB along the third direction D3.

[0082] In an embodiment, at least one of the plurality of insulating layers provided in the panel circuit layer PCL may be disposed throughout the display area DA and / or the entire driving circuit area DRA. For example, the buffer layer BFL, the first insulating layer INS1, and the passivation layer PSV may be disposed throughout the display area DA and the entire driving circuit area DRA.

[0083] In an embodiment, the gate insulating layer GI may include insulating pattern layers respectively disposed on portions of the active layers of the first transistor TFT1 and the second transistor TFT2. For example, the gate insulating layer GI may include a first gate insulating layer GI1 disposed on a portion of the first active layer ACT1 of the first transistor TFT1 and exposing the other portions of the first active layer ACT1, and a second gate insulating layer GI2 disposed on a portion of the second active layer ACT2 of the second transistor TFT2 and exposing the other portions of the second active layer ACT2, but the embodiment is not limited thereto. For example, the gate insulating layer GI may be disposed in the entire display area DA and / or the entire drive circuit area DRA.

[0084] In an embodiment, the display panel 110 may further include additional conductive layers and / or insulating layers. For example, the display panel 110 may include at least one conductive layer provided (or formed) on the passivation layer PSV, and at least one insulating layer covering the at least one conductive layer. In an embodiment in which the display panel 110 further includes at least one conductive layer on the passivation layer PSV, the at least one conductive layer may include at least one wiring and / or bridge pattern layer (e.g., a bridge pattern layer connecting the first transistor TFT1 and the light emitting element ED).

[0085] The first transistor TFT1 may include a first active layer ACT1 (also referred to as a first active pattern layer or a first semiconductor pattern layer) and a first gate electrode GE1. In an embodiment, the first transistor TFT1 may further include a first bottom gate electrode BG1 (also referred to as a first lower electrode or a first light shielding pattern layer). A buffer layer BFL may be disposed between the first bottom gate electrode BG1 and the first active layer ACT1. A first gate insulating layer GI1 may be disposed between the first active layer ACT1 and the first gate electrode GE1.

[0086] In an embodiment, the first transistor TFT1 may include a first source electrode SE1 and a first drain electrode DE1 connected to different portions of the first active layer ACT1. In another example, the first transistor TFT1 may not include separate source and drain electrodes, and the first source region SR1 and / or the first drain region DR1 of the first active layer ACT1 may be connected to other circuit components, wirings, and / or conductive pattern layers to function as a source electrode and / or a drain electrode of the first transistor TFT1.

[0087] In an embodiment, the first transistor TFT1 may be an N-type transistor. For example, the first transistor TFT1 may be an N-type oxide semiconductor.

[0088] The first bottom gate electrode BG1 may be provided in the first conductive layer CDL1 on the substrate SUB. In an embodiment, the first conductive layer CDL1 may be disposed between the substrate SUB and the buffer layer BFL. For example, the first conductive layer CDL1 may be disposed on the barrier layer BRL and may be covered by the buffer layer BFL.

[0089] The first bottom gate electrode BG1 may be disposed between the substrate SUB and the first active layer ACT1 and may overlap the first active layer ACT1. For example, the first bottom gate electrode BG1 may be disposed below the first active layer ACT1 to overlap at least the first channel region CH1. Since the first bottom gate electrode BG1 is disposed below the first active layer ACT1, external light may be prevented from entering the first active layer ACT1 (for example, the first channel region CH1), and the operating characteristics of the first transistor TFT1 may be stabilized.

[0090] The first bottom gate electrode BG1 and the first active layer ACT1 may be spaced apart from each other by the buffer layer BFL. The first bottom gate electrode BG1 may face the first gate electrode GE1 with the first active layer ACT1 interposed therebetween.

[0091] In an embodiment, the first transistor TFT1 may be a driving transistor of the pixel PX, and the first bottom gate electrode BG1 of the first transistor TFT1 may be connected to the first source electrode SE1. In another example, the first transistor TFT1 may be a switching transistor of the pixel PX, and the first bottom gate electrode BG1 of the first transistor TFT1 may be connected to the first gate electrode GE1. For example, the first transistor TFT1 may be a dual-gate transistor having a source synchronous structure or a gate synchronous structure, and the first bottom gate electrode BG1 may be used as a back gate electrode for adjusting the characteristics of the first transistor TFT1.

[0092] The first active layer ACT1 may be provided in the semiconductor layer SCL on the substrate SUB. In an embodiment, the semiconductor layer SCL may be disposed on the buffer layer BFL and may be covered by the gate insulating layer GI and the first insulating layer INS1.

[0093] The first active layer ACT1 may include a first channel region CH1 and a first source region SR1 and a first drain region DR1 spaced apart from each other across the first channel region CH1, the first channel region CH1 being disposed between the first source region SR1 and the first drain region DR1. For example, the first source region SR1 and the first drain region DR1 may be located on both sides (e.g., opposite sides) of the first channel region CH1. The first channel region CH1 may be a region that remains undoped and maintains semiconductor properties. The first source region SR1 and the first drain region DR1 may be doped regions having a higher carrier concentration (e.g., a higher electron concentration) than the first channel region CH1.

[0094] The first active layer ACT1 may overlap the first bottom gate electrode BG1 and the first gate electrode GE1. For example, a portion of the first active layer ACT1 including the first channel region CH1 may overlap the first bottom gate electrode BG1 and the first gate electrode GE1.

[0095] In an embodiment, the first active layer ACT1 may include an oxide semiconductor. For example, the first active layer ACT1 may be formed of at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), and indium tin gallium zinc oxide (ITGZO) or another oxide semiconductor.

[0096] In an embodiment, the first active layer ACT1 may be made of a high-mobility oxide semiconductor (eg, having a thickness of about 20 cm 2 / Vs or about 30cm 2 / Vs or greater mobility) is formed. For example, the first active layer ACT1 may be formed of IGZO or ITGZO and may have a thickness of about 30 cm 2 / Vs or greater. Using a high-mobility oxide semiconductor for the first active layer ACT1 can ensure the conductivity of the first source region SR1 and the first drain region DR1 without an additional doping process. In addition, using a high-mobility oxide semiconductor for the first active layer ACT1 can provide miniaturization of the first transistor TFT1 to a small size, while still maintaining the desired mobility for the first transistor TFT1, having an active layer width and / or length in the range of several microns.

[0097] The first gate insulating layer GI1 (also referred to as a first gate insulating pattern layer) may be located on the first active layer ACT1. The first gate insulating layer GI1 may be disposed between the first active layer ACT1 and the first gate electrode GE1.

[0098] In an embodiment, the first gate insulating layer GI1 may be disposed only on a portion of the first active layer ACT1 overlapping the first gate electrode GE1, and may not be disposed on other portions of the first active layer ACT1. For example, the first gate insulating layer GI1 may cover a portion of the first active layer ACT1 including the first channel region CH1 and may expose the first source region SR1 and the first drain region DR1. In an embodiment, the first gate insulating layer GI1 may be an island-shaped insulating pattern layer having a shape and size corresponding to the first gate electrode GE1, and may be formed separately and / or independently in each transistor region where the first transistor TFT1 (e.g., pixel transistor Tpx) is formed, but the embodiment is not limited thereto. For example, the first gate insulating layer GI1 may be disposed in the entire display area DA.

[0099] Since the first gate insulating layer GI1 exposes the first source region SR1 and the first drain region DR1, the first source region SR1 and the first drain region DR1 may be sufficiently and easily doped during the manufacture of the display panel 110. For example, during etching of the gate insulating layer GI to expose the first source region SR1 and the first drain region DR1, oxygen vacancies may be generated in the first source region SR1 and the first drain region DR1 due to etching gas. Therefore, the first source region SR1 and the first drain region DR1 may be properly doped in a subsequent process (for example, during formation of the first insulating layer INS1) without a separate doping process.

[0100] In an embodiment, in order to limit the carrier concentration of the first source region SR1 and the first drain region DR1 and / or the mobility of the first active layer ACT1, an oxygen supply layer may be formed between the first gate insulating layer GI1 and the first gate electrode GE1. For example, the first transistor TFT1 may be disposed between the first gate insulating layer GI1 and the first gate electrode GE1 and may include an oxygen supply layer including an oxide semiconductor. The first active layer ACT1 and the oxygen supply layer in the first transistor TFT1 may include the same oxide semiconductor or different oxide semiconductors.

[0101] The first gate electrode GE1 may be provided in the second conductive layer CDL2 on the substrate SUB. In an embodiment, the second conductive layer CDL2 may be disposed on the gate insulating layer GI and may be covered by the first insulating layer INS1. For example, the first gate electrode GE1 may be disposed on the first gate insulating layer GI1 and may be covered by the first insulating layer INS1.

[0102] The first gate electrode GE1 may be disposed on the first active layer ACT1 to overlap the first channel region CH1. The first gate electrode GE1 and the first active layer ACT1 may be separated and / or spaced apart from each other via a first gate insulating layer GI1 interposed therebetween.

[0103] The first source electrode SE1 and the first drain electrode DE1 may be provided in the third conductive layer CDL3 on the substrate SUB. In an embodiment, the third conductive layer CDL3 may be disposed on the first insulating layer INS1 covering (e.g., completely covering) the buffer layer BFL, the semiconductor layer SCL, the gate insulating layer GI, and the second conductive layer CDL2. The third conductive layer CDL3 may be covered by the passivation layer PSV.

[0104] The first source electrode SE1 may be connected to a portion of the first active layer ACT1. For example, the first source electrode SE1 may be connected to the first source region SR1 through at least one contact hole penetrating the first insulating layer INS1. In the case where the first transistor TFT1 is a dual-gate transistor having a source synchronous structure, the first source electrode SE1 may also be connected to the first bottom gate electrode BG1. For example, the first source electrode SE1 may be connected to the first bottom gate electrode BG1 through a contact hole penetrating the buffer layer BFL and the first insulating layer INS1.

[0105] The first drain electrode DE1 may be connected to another portion of the first active layer ACT1. For example, the first drain electrode DE1 may be connected to the first drain region DR1 through a contact hole penetrating the first insulating layer INS1.

[0106] The second transistor TFT2 may include a second active layer ACT2 (also referred to as a second active pattern layer or a second semiconductor pattern layer) and a second gate electrode GE2. In an embodiment, the second transistor TFT2 may further include a second bottom gate electrode BG2 (also referred to as a second lower electrode or a second light shielding pattern layer). A buffer layer BFL may be disposed between the second bottom gate electrode BG2 and the second active layer ACT2. A second gate insulating layer GI2 may be disposed between the second active layer ACT2 and the second gate electrode GE2.

[0107] In an embodiment, the second transistor TFT2 may include a second source electrode SE2 and a second drain electrode DE2 connected to different portions of the second active layer ACT2. In another example, the second transistor TFT2 may not include separate source and drain electrodes, and the second source region SR2 and / or the second drain region DR2 of the second active layer ACT2 may be connected to other circuit components, wirings, and / or conductive pattern layers to serve as a source electrode and / or drain electrode of the second transistor TFT2.

[0108] In an embodiment, the second transistor TFT2 may be an N-type transistor. For example, the second transistor TFT2 may be an N-type oxide semiconductor.

[0109] The second bottom gate electrode BG2 may be provided in the first conductive layer CDL1 on the substrate SUB. For example, the second bottom gate electrode BG2 may be provided in the first conductive layer CDL1 together with the first bottom gate electrode BG1.

[0110] The second bottom gate electrode BG2 may be disposed between the substrate SUB and the second active layer ACT2 and may overlap the second active layer ACT2. For example, the second bottom gate electrode BG2 may be disposed below the second active layer ACT2 to overlap at least the second channel region CH2. Since the second bottom gate electrode BG2 is disposed below the second active layer ACT2, external light may be prevented from entering the second active layer ACT2 (for example, the second channel region CH2), and the operating characteristics of the second transistor TFT2 may be stabilized.

[0111] The second bottom gate electrode BG2 and the second active layer ACT2 may be spaced apart from each other by the buffer layer BFL. The second bottom gate electrode BG2 may face (or overlap) the second gate electrode GE2 with the second active layer ACT2 interposed therebetween.

[0112] In an embodiment, the second transistor TFT2 may be a buffer transistor (e.g., a pull-up transistor or a pull-down transistor) or another switching transistor provided at the output terminal of the first driving unit 120, and the second bottom gate electrode BG2 may be connected to the second gate electrode GE2. For example, the second transistor TFT2 may be a double-gate transistor having a gate synchronization structure, and the second bottom gate electrode BG2 may be used as a back gate electrode for adjusting the characteristics of the second transistor TFT2.

[0113] The second active layer ACT2 may be provided in the semiconductor layer SCL on the substrate SUB. For example, the second active layer ACT2 may be disposed on the buffer layer BFL and may be covered by the second gate insulating layer GI2 and the first insulating layer INS1.

[0114] The second active layer ACT2 may include a second channel region CH2 and a second source region SR2 and a second drain region DR2 spaced apart from each other across the second channel region CH2, the second channel region CH2 being disposed between the second source region SR2 and the second drain region DR2. For example, the second source region SR2 and the second drain region DR2 may be located on both sides (e.g., opposite sides) of the second channel region CH2. The second channel region CH2 may be a region that remains undoped and maintains semiconductor properties. The second source region SR2 and the second drain region DR2 may be doped regions having a higher carrier concentration (e.g., a higher electron concentration) than the second channel region CH2.

[0115] The second active layer ACT2 may overlap the second bottom gate electrode BG2 and the second gate electrode GE2. For example, a portion of the second active layer ACT2 including the second channel region CH2 may overlap the second bottom gate electrode BG2 and the second gate electrode GE2.

[0116] In an embodiment, the second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include any one of the above-mentioned oxide semiconductors used to form the first active layer ACT1 or another oxide semiconductor. In an embodiment, the first active layer ACT1 and the second active layer ACT2 may include the same oxide semiconductor. For example, the first active layer ACT1 and the second active layer ACT2 may be simultaneously formed on the buffer layer BFL using the same oxide semiconductor. Therefore, the manufacture of the display panel 110 may be simplified, and the manufacturing efficiency of the display panel 110 may be improved.

[0117] In an embodiment, the second active layer ACT2 may be formed of a high-mobility oxide semiconductor. Using a high-mobility oxide semiconductor for the second active layer ACT2 may ensure the conductivity of the second source region SR2 and the second drain region DR2 without an additional doping process. In addition, using a high-mobility oxide semiconductor for the second active layer ACT2 may provide miniaturization of the second transistor TFT2 to a small size, with an active layer width and / or length in the range of several microns while still maintaining the desired mobility for the second transistor TFT2.

[0118] The second gate insulating layer GI2 (also referred to as a second gate insulating pattern layer) may be located on the second active layer ACT2. The second gate insulating layer GI2 may be disposed between the second active layer ACT2 and the second gate electrode GE2.

[0119] In an embodiment, the second gate insulating layer GI2 may be disposed only on a portion of the second active layer ACT2 that overlaps with the second gate electrode GE2, and may not be disposed on other portions of the second active layer ACT2. For example, the second gate insulating layer GI2 may cover a portion of the second active layer ACT2 including the second channel region CH2 and may expose the second source region SR2 and the second drain region DR2. In an embodiment, the second gate insulating layer GI2 may be an island-shaped insulating pattern layer having a shape and size corresponding to the second gate electrode GE2, and may be formed separately and / or independently in each transistor region where the second transistor TFT2 (e.g., the driving transistor Tdr) is formed, but the embodiment is not limited thereto. For example, the second gate insulating layer GI2 may be disposed in the entire drive circuit area DRA. For example, the first gate insulating layer GI1 and the second gate insulating layer GI2 may be merged into a single gate insulating layer GI, and may then be disposed in the entire display area DA and the entire drive circuit area DRA.

[0120] Since the second gate insulating layer GI2 exposes the second source region SR2 and the second drain region DR2, the second source region SR2 and the second drain region DR2 may be sufficiently and easily doped during the manufacture of the display panel 110. For example, during etching of the gate insulating layer GI to expose the second source region SR2 and the second drain region DR2, oxygen vacancies may be generated in the second source region SR2 and the second drain region DR2 due to etching gas. Therefore, the second source region SR2 and the second drain region DR2 may be properly doped in a subsequent process (for example, during the formation of the first insulating layer INS1) without a separate doping process.

[0121] In an embodiment, in order to limit the carrier concentration of the second source region SR2 and the second drain region DR2 and / or the mobility of the second active layer ACT2, an oxygen supply layer may be formed between the second gate insulating layer GI2 and the second gate electrode GE2. For example, the second transistor TFT2 may be disposed between the second gate insulating layer GI2 and the second gate electrode GE2, and may include an oxygen supply layer including an oxide semiconductor. The second active layer ACT2 and the oxygen supply layer in the second transistor TFT2 may include the same oxide semiconductor or different oxide semiconductors.

[0122] The second gate electrode GE2 may be provided in the second conductive layer CDL2. For example, the second gate electrode GE2 may be disposed on the gate insulating layer GI (eg, on the second gate insulating layer GI2) and may be covered by the first insulating layer INS1.

[0123] The second gate electrode GE2 may be disposed on the second active layer ACT2 to overlap the second channel region CH2. The second gate electrode GE2 and the second active layer ACT2 may be separated and / or spaced apart from each other via a second gate insulating layer GI2 interposed therebetween.

[0124] The second source electrode SE2 and the second drain electrode DE2 may be provided in the third conductive layer CDL3. For example, the second source electrode SE2 and the second drain electrode DE2 may be disposed on the first insulating layer INS1 and may be covered by the passivation layer PSV.

[0125] The second source electrode SE2 may be connected to a portion of the second active layer ACT2. For example, the second source electrode SE2 may be connected to the second source region SR2 through a contact hole penetrating the first insulating layer INS1.

[0126] The second drain electrode DE2 may be connected to another portion of the second active layer ACT2. For example, the second drain electrode DE2 may be connected to the second drain region DR2 through a contact hole penetrating the first insulating layer INS1.

[0127] The transistor TFT including the first transistor TFT1 and the second transistor TFT2 may be covered by a passivation layer PSV.

[0128] The electrodes, conductive pattern layers and / or wiring provided in each of the conductive layers of the panel circuit layer PCL may include at least one conductive material. For example, the electrodes, conductive pattern layers and / or wiring provided in each of the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg) and at least one of other metals, alloys thereof or other conductive materials. In an embodiment, the electrodes, conductive pattern layers and / or wiring provided in the same conductive layer may be formed simultaneously by the same conductive material.

[0129] In an embodiment, the electrodes, conductive pattern layers and / or wirings provided in each of the conductive layers of the panel circuit layer PCL may have a single-layer structure or a multi-layer structure. For example, the electrodes, conductive pattern layers and / or wirings provided in each of the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may have a single-layer structure or a multi-layer structure.

[0130] For example, refer to Figure 4 , the gate electrodes (e.g., the first gate electrode GE1 and the second gate electrode GE2), the conductive pattern layer and / or the wiring provided in the second conductive layer CDL2 may have a multilayer structure including a first layer CL1, a second layer CL2 and a third layer CL3, and the first layer CL1, the second layer CL2 and the third layer CL3 may include a first conductive material, a second conductive material and a third conductive material, respectively. The first conductive material and the third conductive material may be the same as or different from each other, and the second conductive material may be different from the first conductive material and the third conductive material. For example, the first gate electrode GE1 and the second gate electrode GE2 may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but the embodiment is not limited thereto.

[0131] The passivation layer PSV may be disposed on the third conductive layer CDL3. For example, the passivation layer PSV may be disposed on the first insulating layer INS1 and may cover the third conductive layer CDL3.

[0132] In an embodiment, the passivation layer PSV may have a multi-layer structure including an inorganic insulating layer and an organic insulating layer. For example, the passivation layer PSV may include an inorganic film IOL and an organic film ORL sequentially disposed on the first insulating layer INS1.

[0133] In an embodiment, each of the buffer layer BFL, the gate insulating layer GI, the first insulating layer INS1, and the inorganic film IOL may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material). In an embodiment, the organic film ORL may include at least one organic insulating layer including an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or another organic insulating material). A surface (e.g., an upper surface) of the organic film ORL may be substantially flat.

[0134] In some embodiments, the first insulating layer INS1 may be disposed on the second conductive layer CDL2 and may cover the semiconductor layer SCL, the gate insulating layer GI, and the second conductive layer CDL2. For example, the first insulating layer INS1 may cover the first active layer ACT1 and the second active layer ACT2 provided in the semiconductor layer SCL, the first gate insulating layer GI1 and the second gate insulating layer GI2 provided in the gate insulating layer GI, and the first gate electrode GE1 and the second gate electrode GE2 provided in the second conductive layer CDL2.

[0135] In some embodiments, the first insulating layer INS1 may be a double insulating layer including at least a silicon oxide layer and a silicon oxynitride layer. For example, the first insulating layer INS1 may include a silicon oxide (SiO x ) and a first layer IL1 disposed on the first layer IL1 and including silicon oxynitride (SiO x N y In an embodiment, the first insulating layer INS1 may further include a second layer IL2 disposed on the second layer IL2 and including silicon nitride (SiN x ) of the third layer IL3 (eg, a silicon nitride layer).

[0136] For example, the first layer IL1 of the first insulating layer INS1 may be formed of silicon and oxygen and may not substantially contain nitrogen. For example, the first layer IL1 may be formed as a silicon oxide layer, and the nitrogen content of the first layer IL1 may be less than about 1 atomic %. The first layer IL1 may cover the first and second active layers ACT1 and ACT2, the first and second gate insulating layers GI1 and GI2, and the first and second gate electrodes GE1 and GE2.

[0137] By first covering the active layer of the transistor TFT with the first layer IL1 formed of silicon oxide, the amount of hydrogen infiltrated (or permeated) into the active layer of the transistor TFT during the formation of the second layer IL2 and / or the third layer IL3 (containing nitrogen) can be controlled and / or reduced. For example, by forming the first layer IL1 to cover (e.g., directly cover) the portion of the transistor TFT that is not covered by the gate insulating layer GI (e.g., the first source region SR1 and the second source region SR2 and the first drain region DR1 and the second drain region DR2), an excessive amount of hydrogen infiltrated (or permeated) into the transistor TFT during the formation of the second layer IL2 and / or the third layer IL3 can be prevented or improved, and the effective channel length can be sufficiently extended and / or ensured for the transistor TFT. For example, in the case of forming at least some transistors TFT (e.g., the first transistor TFT1 and the second transistor TFT2) having an active layer of a small size, for example, in the range of a width and / or a length of several micrometers to several tens of micrometers, in order to manufacture a high-resolution display device 100, an effective channel length that can prevent or improve the occurrence of a threshold voltage roll-off phenomenon of the transistor TFT can be ensured. Accordingly, the operation characteristics of the transistor TFT may be sufficiently ensured and / or enhanced, and the yield of the display device 100 may be improved.

[0138] In an embodiment, the thickness of the first layer IL1 of the first insulating layer INS1 may be about to about By forming a The first layer IL1 having a thickness of about 1000 nm or more can effectively ensure a stable spacing distance between the active layer (e.g., the first active layer ACT1 and the second active layer ACT2) of the transistor TFT and the second layer IL2 and / or the third layer IL3 of the first insulating layer INS1, and can prevent excessive penetration (or permeation) of hydrogen into the active layer of the transistor TFT. The first layer IL1 having a thickness of 100 Å or less may easily and stably form a contact hole (eg, a contact hole formed in the first insulating layer INS1 for connecting an active layer of the transistor TFT with a source electrode and / or a drain electrode).

[0139] The second layer IL2 of the first insulating layer INS1 may be formed as a silicon nitride oxide layer composed of silicon, oxygen, and nitrogen, and the nitrogen content of the second layer IL2 may be in the range of about 1 atomic % to about 10 atomic %. In an embodiment, by adjusting the nitrogen content of the second layer IL2, the film quality of the second layer IL2 may be appropriately controlled. For example, by ensuring that the second layer IL2 includes about 1 atomic % or more of nitrogen, the second layer IL2 may be formed to have higher adhesion and more uniform film quality than the first layer IL1.

[0140] By covering the first layer IL1 with the second layer IL2 formed of silicon oxynitride, the amount of hydrogen infiltrated (or permeated) into the active layer of the transistor TFT can be appropriately controlled and / or reduced while preventing or reducing moisture penetration through the first insulating layer INS1. For example, although a gap (e.g., having a slope less than 90 degrees) connected to the first layer IL1 is formed (e.g., in the form of a seam) on one side of each gate electrode, as in Figure 4 As shown in the region A2 of the first layer IL1, moisture penetration can be reduced, prevented, or blocked by covering the first layer IL1 with the second layer IL2 that can be more effectively bonded than the first layer IL1. For example, by controlling the nitrogen content of the second layer IL2 to be about 10 atomic % or less, excessive penetration (or permeation) of hydrogen into the active layer of the transistor TFT can be prevented during the formation of the second layer IL2. In an embodiment, the nitrogen content of the second layer IL2 can be appropriately controlled or set in consideration of the film quality and process capability of the second layer IL2.

[0141] In an embodiment, the thickness of the second layer IL2 of the first insulating layer INS1 may be about to about By forming the second layer IL2 to have a or greater, can stably prevent moisture from penetrating (or permeating). For example, the second layer IL2 is formed to have a thickness of about Even if the thickness of the second layer IL2 is reduced on one side of each gate electrode (e.g., the first gate electrode GE1 or the second gate electrode GE2), the second layer IL2 can be formed to have a thickness that stably prevents moisture from penetrating (or permeating), for example, at least about 100 Å. Therefore, in a region where the first insulating layer INS1 covers one side of each gate electrode, the first layer IL1 and the third layer IL3 of the first insulating layer INS1 may be spaced apart from each other by about 100 Å. or greater distance d (see Figure 4 ). For example, the second layer IL2 is formed to have a thickness of about Even in a region where the first insulating layer INS1 covers one side of each gate electrode, the second insulating layer IL2 may have a total thickness of at least about 100 Å. The first layer IL1 and the third layer IL3 may also be spaced apart from each other by about or greater. Therefore, moisture infiltration (or penetration) through the first insulating layer INS1 can be stably prevented. For example, by forming the second layer IL2 to have a thickness of about or less, a contact hole can be easily and stably formed in the second layer IL2.

[0142] The third layer IL3 of the first insulating layer INS1 may be composed of silicon and nitrogen and may not substantially contain oxygen. For example, the third layer IL3 may be formed as a silicon nitride layer having a nitrogen content of about 30 atomic % to about 60 atomic %, and the oxygen content of the third layer IL3 may be less than about 1 atomic %. For example, the third layer IL3 may contain a larger amount of nitrogen than the second layer IL2, and may have a higher adhesion and a more uniform film quality than the second layer IL2. By covering the second layer IL2 with the third layer IL3, moisture infiltration (or penetration) through the first insulating layer INS1 may be more effectively blocked. For example, since the third layer IL3 is spaced apart from the active layer of the transistor TFT by the first layer IL1 and the second layer IL2, excessive infiltration (or penetration) of hydrogen into the active layer of the transistor TFT may be prevented or reduced during the formation of the third layer IL3.

[0143] In an embodiment, the thickness of the third layer IL3 of the first insulating layer INS1 may be about to about By forming a By forming the third layer IL3 with a thickness of about 100 Å or more, even if the third layer IL3 is partially etched to a certain extent in a subsequent process (e.g., a patterning process for the third conductive layer CDL3), the third layer IL3 can be stably retained on the surface of the second layer IL2. Therefore, moisture infiltration (or penetration) can be effectively blocked. For example, by forming a third conductive layer IL3 with a thickness of about 100 Å or more, the third layer IL3 can be stably retained on the surface of the second layer IL2. The third layer IL3 having a thickness of about 100 Å or less can easily and stably form a contact hole in the third layer IL3. By forming each of the first layer IL1 , the second layer IL2 , and the third layer IL3 of the first insulating layer INS1 with a thickness of 100 Å or less, a contact hole may be reliably formed in the first insulating layer INS1 .

[0144] In an embodiment, each of the first layer IL1, the second layer IL2, and the third layer IL3 of the first insulating layer INS1 may include silicon, oxygen, and nitrogen at a composition ratio as shown in Table 1 below. However, Table 1 shows the composition ratio of atoms included in each of the first layer IL1, the second layer IL2, and the third layer IL3 of the first insulating layer INS1, and the composition ratio of the materials used to form the first layer IL1, the second layer IL2, and the third layer IL3 of the first insulating layer INS1 may vary. For example, each of the first layer IL1, the second layer IL2, and the third layer IL3 of the first insulating layer INS1 may include silicon, oxygen, and / or nitrogen within the aforementioned ranges.

[0145]

Table 1

[0146] Oxygen (O) Silicon (Si) Nitrogen (N) <![CDATA[The third layer (SiN x )]]> 0.5 atomic% 44.8 atomic % 54.7 atomic % <![CDATA[Second layer (SiO x N y )]]> 61.5 atomic% 35.4 atomic% 3.1 atomic % <![CDATA[The first layer (SiO x )]]> 63.2 atomic% 36.7 atomic % 0.1 atomic%

[0147] The light emitting element layer LEL may be disposed on the panel circuit layer PCL including the transistor TFT, the gate insulating layer GI, the first insulating layer INS1 and the passivation layer PSV. For example, the light emitting element layer LEL may be located at least in the display area DA and may be disposed on the passivation layer PSV.

[0148] The light emitting element layer LEL may include a light emitting element ED for the pixel PX. For example, the light emitting element layer LEL may include a pixel defining layer PDL (also referred to as a dam) defining an emission region of the pixel PX, and a light emitting element ED located in the emission region. In an embodiment, the light emitting element layer LEL may also include a spacer SPC disposed on a portion of the pixel defining layer PDL.

[0149] The light emitting element ED may include a first electrode ET1 in an emission region, and a light emitting layer EML and a second electrode ET2 sequentially disposed on the first electrode ET1. The first electrode ET1 of the light emitting element ED may be connected to at least one pixel transistor Tpx (eg, first transistor TFT1) included in the pixel PX.

[0150] The first electrode ET1 of the light emitting element ED may be a single-layer electrode or a multi-layer electrode including at least one conductive material. In an embodiment, the first electrode ET1 may include a highly reflective metal material. For example, the first electrode ET1 may have a single-layer structure including a material such as molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a structure including a material such as ITO, IZO, ZnO, indium oxide (In 2 O 3 ), Ag, Mg, Al, Pt, lead (Pb), Au or Ni (for example, ITO / Mg, ITO / MgF, ITO / Ag or ITO / Ag / ITO).

[0151] The light emitting layer EML of the light emitting element ED may include a polymer material or a low molecular weight material. Light emitted from the light emitting layer EML may contribute to display of an image.

[0152] The second electrode ET2 of the light emitting element ED may include a conductive material. In an embodiment, the second electrode ET2 may be a common film that covers the light emitting layer EML and the pixel defining layer PDL and is formed throughout the entire display area DA. In an embodiment, the second electrode ET2 may be formed of a transparent conductive material (such as ITO, IZO, ZnO, or ITZO) through which light passes, or may be formed of a semi-transparent conductive material (such as Mg, Ag, or an alloy of Mg and Ag).

[0153] The pixel defining layer PDL may have an opening corresponding to the emission region of the pixel PX and may surround the emission region. For example, the pixel defining layer PDL may be formed to cover an edge portion of the first electrode ET1 of the light emitting element ED and may include an opening exposing the rest of the first electrode ET1. The overlapping area of ​​the exposed first electrode ET1 and the light emitting layer EML may be defined as the emission region of the pixel PX. In an embodiment, the pixel defining layer PDL may include at least one organic insulating layer.

[0154] The spacer SPC may be disposed on a portion of the pixel defining layer PDL. The spacer SPC may include at least one organic insulating layer. The spacer SPC and the pixel defining layer PDL may include the same material as each other or may include different materials from each other. The pixel defining layer PDL and the spacer SPC may be sequentially formed by separate mask processes, or may be simultaneously and / or integrally formed using a halftone mask.

[0155] The encapsulation layer ENL may be disposed on the light emitting element layer LEL. The encapsulation layer ENL may cover the light emitting element layer LEL in the display area DA and extend into the non-display area NDA to contact the panel circuit layer PCL. The encapsulation layer ENL may block oxygen or moisture from penetrating into the light emitting element layer LEL and may mitigate any electrical and / or physical effects on the panel circuit layer PCL and the light emitting element layer LEL.

[0156] In an embodiment, the encapsulation layer ENL may include a first encapsulation layer ENL1, a second encapsulation layer ENL2, and a third encapsulation layer ENL3 sequentially disposed on the light emitting element layer LEL. The first encapsulation layer ENL1 and the third encapsulation layer ENL3 may be inorganic encapsulation layers including inorganic materials. The second encapsulation layer ENL2 may be an organic encapsulation layer including organic materials.

[0157] Figure 5 is a schematic cross-sectional view showing a display panel 110 according to an embodiment. Figures 1 to 4 Compared with the implementation method, Figure 5 Portions of the display area DA and the non-display area NDA of the display panel 110 further including the fourth conductive layer CDL4 are depicted.

[0158] Reference Figure 5 And further refer to Figures 1 to 4 The display panel 110 may further include a fourth conductive layer CDL4 and a second insulating layer INS2 disposed between the first insulating layer INS1 and the third conductive layer CDL3. For example, the fourth conductive layer CDL4 may be disposed on the first insulating layer INS1, and the second insulating layer INS2 may cover the fourth conductive layer CDL4.

[0159] The fourth conductive layer CDL4 may include at least one electrode, a conductive pattern layer and / or a wiring. For example, the fourth conductive layer CDL4 may include a first capacitor electrode CE1 forming a capacitor Cst of the pixel PX. In an embodiment, the first capacitor electrode CE1 may overlap with the first gate electrode GE1, and the capacitor Cst (e.g., a storage capacitor of the pixel PX) may be formed between the first capacitor electrode CE1 and the first gate electrode GE1. For example, the first capacitor electrode CE1 of the capacitor Cst may be provided in the fourth conductive layer CDL4, and the second capacitor electrode CE2 of the capacitor Cst may be integrated with the first gate electrode GE1 in the second conductive layer CDL2.

[0160] Since the display panel 110 further includes the fourth conductive layer CDL4, the panel circuit layer PCL may include more conductive layers. Therefore, it is possible to easily and / or sufficiently ensure a space for designing circuit components and / or wiring. For example, even in a high-resolution display device 100 with a reduced pixel area PXA and / or wiring design space, sufficient space may be ensured to reliably arrange the pixels PX, the first driving unit 120, and / or wiring.

[0161] Figures 6 to 12 is a schematic cross-sectional view showing a method for manufacturing the display device 100 according to an embodiment. For example, Figures 6 to 12 Sequentially shows the Figure 3 The step of forming the first transistor TFT1 and the second transistor TFT2 on the substrate SUB during the manufacturing of the display panel 110 .

[0162] Reference Figure 6 And further refer to Figures 1 to 5 , a substrate SUB having a display area DA and a non-display area NDA may be manufactured. In an embodiment, the display area DA defined on the substrate SUB may include a pixel area PXA, and the non-display area NDA may include a driving circuit area DRA.

[0163] In an embodiment, a barrier layer BRL may be formed on the substrate SUB. The barrier layer BRL may be formed in the display area DA and the non-display area NDA. The barrier layer BRL may be formed by a film forming process (e.g., a deposition process) for an insulating film using at least one of the above insulating materials (e.g., an inorganic insulating material).

[0164] Reference Figure 7 And further refer to Figures 1 to 6, a first conductive layer CDL1 including a first bottom gate electrode BG1 and a second bottom gate electrode BG2 may be formed on a substrate SUB (e.g., on a barrier layer BRL). For example, the first bottom gate electrode BG1 may be formed in a pixel area PXA in a display area DA on the substrate SUB, and the second bottom gate electrode BG2 may be formed in a drive circuit area DRA on the substrate SUB. The first bottom gate electrode BG1 and the second bottom gate electrode BG2 may be formed by a film forming process (e.g., a deposition process) for a conductive film using at least one of the above-mentioned conductive materials and a patterning process (e.g., an etching process using a mask).

[0165] Thereafter, a buffer layer BFL covering the first conductive layer CDL1 may be formed on the substrate SUB. The buffer layer BFL may be formed through a film forming process for an insulating film using at least one of the above-described insulating materials (eg, an inorganic insulating material).

[0166] Reference Figure 8 And further refer to Figures 1 to 7 , a semiconductor layer SCL including a first active layer ACT1 and a second active layer ACT2 may be formed on a substrate SUB (e.g., on a buffer layer BFL). For example, a first active layer ACT1 may be formed in a pixel area PXA of a display area DA on a substrate SUB, and a second active layer ACT2 may be formed in a driving circuit area DRA on a substrate SUB. The first active layer ACT1 may be formed to overlap with a first bottom gate electrode BG1, and the second active layer ACT2 may be formed to overlap with a second bottom gate electrode BG2.

[0167] In an embodiment, the first active layer ACT1 and the second active layer ACT2 may be formed simultaneously from the same oxide semiconductor. For example, the first active layer ACT1 and the second active layer ACT2 may be formed in the display area DA and the driving circuit area DRA, respectively, by a film forming process and a patterning process for a semiconductor film using at least one of the above oxide semiconductors.

[0168] Reference Fig. 9 And further refer to Figures 1 to 8, a gate insulating layer GI including a first gate insulating layer GI1 and a second gate insulating layer GI2 and a second conductive layer CDL2 including a first gate electrode GE1 and a second gate electrode GE2 may be formed on a substrate SUB on which a semiconductor layer SCL is disposed. For example, an insulating film covering the semiconductor layer SCL and a conductive film covering the insulating film may be sequentially formed on the substrate SUB. In an embodiment, an insulating film and a conductive film for forming the gate insulating layer GI and the second conductive layer CDL2, respectively, may be formed in the entire display area DA and the entire non-display area NDA. In an embodiment, the insulating film may be formed by a film forming process for an insulating film using at least one of the above-mentioned insulating materials (e.g., an inorganic insulating material). In an embodiment, the conductive film may be formed by a film forming process for a conductive film using at least one of the above-mentioned conductive materials.

[0169] Thereafter, the first gate insulating layer GI1 and the second gate insulating layer GI2 and the first gate electrode GE1 and the second gate electrode GE2 may be formed by patterning the conductive film and the insulating film sequentially or simultaneously. In an embodiment, the conductive film may be etched and used as a mask for patterning the first gate electrode GE1 and the second gate electrode GE2, and the insulating film may be etched using the first gate electrode GE1 and the second gate electrode GE2 as a mask. For example, a mask may be placed at a position where the first gate electrode GE1 and the second gate electrode GE2 are to be formed, and the conductive film may be etched to form the first gate electrode GE1 and the second gate electrode GE2. Thereafter, the insulating film may be etched using a mask placed on the first gate electrode GE1 and the second gate electrode GE2 to form the first gate insulating layer GI1 and the second gate insulating layer GI2 under the first gate electrode GE1 and the second gate electrode GE2. As a result, the first gate insulating layer GI1 may be formed on a portion of the first active layer ACT1 overlapping with the first gate electrode GE1, and the second gate insulating layer GI2 may be formed on a portion of the second active layer ACT2 overlapping with the second gate electrode GE2.

[0170] During the formation of the first gate insulating layer GI1 and the second gate insulating layer GI2, the properties of the first active layer ACT1 and the second active layer ACT2 may be changed so that each of the first active layer ACT1 and the second active layer ACT2 may have different characteristics in different regions. As a result, each of the first active layer ACT1 and the second active layer ACT2 may be divided into a plurality of sections having different characteristics.

[0171] For example, in a region not overlapping with the first gate electrode GE1, bonding of oxides in an oxide semiconductor forming the first active layer ACT1 may be damaged, resulting in oxygen detachment, and oxygen vacancies may occur. Therefore, the first active layer ACT1 may be divided into a plurality of regions (e.g., a first channel region CH1, a first drain region DR1, and a first source region SR1) having different characteristics. In an embodiment, oxygen vacancies may mainly occur in a portion of the first active layer ACT1 that does not overlap with the first gate electrode GE1 (e.g., the first drain region DR1 and the first source region SR1), and may even extend to a portion of the first active layer ACT1 that overlaps with the first gate electrode GE1.

[0172] Similarly, in the region not overlapping with the second gate electrode GE2, oxygen vacancies may occur in the oxide semiconductor forming the second active layer ACT2. Therefore, the second active layer ACT2 may be divided into a plurality of regions (e.g., a second channel region CH2, a second drain region DR2, and a second source region SR2) having different characteristics. In an embodiment, oxygen vacancies may mainly occur in a portion of the second active layer ACT2 that does not overlap with the second gate electrode GE2 (e.g., the second drain region DR2 and the second source region SR2), and may even extend to a portion of the second active layer ACT2 that overlaps with the second gate electrode GE2.

[0173] Reference Fig.10 And further refer to Figures 1 to 9 , a first insulating layer INS1 may be formed on a substrate SUB on which a barrier layer BRL, a first conductive layer CDL1, a buffer layer BFL, a semiconductor layer SCL, a gate insulating layer GI, and a second conductive layer CDL2 are disposed. For example, the first insulating layer INS1 may be formed on the second conductive layer CDL2 to cover the first and second active layers ACT1 and ACT2, the first and second gate insulating layers GI1 and GI2, and the first and second gate electrodes GE1 and GE2. The first insulating layer INS1 may be formed in the entire display area DA and the entire non-display area NDA (e.g., the driving circuit area DRA).

[0174] The first insulating layer INS1 may be formed by a film forming process for an insulating film using at least one of the above insulating materials (e.g., inorganic insulating materials). The formation of the first insulating layer INS1 may include sequentially forming a first layer IL1 (e.g., a silicon oxide layer), a second layer IL2 (e.g., a silicon nitride layer), and a third layer IL3 (e.g., a silicon nitride layer).

[0175] For example, the first insulating layer INS1 may be formed by depositing silicon oxide on the substrate SUB on which the barrier layer BRL, the first conductive layer CDL1, the buffer layer BFL, the semiconductor layer SCL, the gate insulating layer GI, and / or the second conductive layer CDL2 are disposed. The first layer IL1 of the first insulating layer INS1 may be formed to cover the first and second active layers ACT1 and ACT2, the first and second gate insulating layers GI1 and GI2, and the first and second gate electrodes GE1 and GE2. In an embodiment, the first layer IL1 may be formed to have a thickness of about to about Thickness.

[0176] Thereafter, the second layer IL2 of the first insulating layer INS1 may be formed by depositing silicon nitride on the first layer IL1. In an embodiment, the second layer IL2 may be formed to cover (eg, completely cover) the first layer IL1 and may have a thickness of about 100 mm. to about Thickness.

[0177] Thereafter, the third layer IL3 of the first insulating layer INS1 may be formed by depositing silicon nitride on the second layer IL2. In an embodiment, the third layer IL3 may be formed to cover (eg, completely cover) the second layer IL2 and may have a thickness of about 100 mm. to Thickness.

[0178] During the formation of the first insulating layer INS1, hydrogen may be introduced (or permeated) into the first active layer ACT1 and the second active layer ACT2. For example, during the formation of the second layer IL2 and the third layer IL3 of the first insulating layer INS1, hydrogen may be introduced (or permeated) into the first active layer ACT1 and the second active layer ACT2. As a result, portions of the first active layer ACT1 and the second active layer ACT2 around the region previously containing a high concentration of oxygen vacancies may be doped (e.g., N-type doping). For example, the first drain region DR1, the first source region SR1, the second drain region DR2, and the second source region SR2 may be doped.

[0179] In an embodiment, by forming the second layer IL2 and the third layer IL3 of the first insulating layer INS1 on the first layer IL1 of the first insulating layer INS1 covering the first active layer ACT1 and the second active layer ACT2, excessive penetration (or permeation) of hydrogen into the first active layer ACT1 and the second active layer ACT2 may be controlled or reduced. Therefore, excessive expansion of the first drain region DR1, the first source region SR1, the second drain region DR2, and the second source region SR2 may be prevented, and the effective channel lengths of the first channel region CH1 and the second channel region CH2 may be appropriately secured.

[0180] Reference Fig.11 And further refer to Figures 1 to 10 , a contact hole CNT exposing a portion of the first active layer ACT1 and the second active layer ACT2 may be formed in the first insulating layer INS1. For example, the first insulating layer INS1 may be etched to expose a portion of the first drain region DR1, the first source region SR1, the second drain region DR2, and the second source region SR2. In an embodiment, by forming a contact hole CNT having a thickness of about Each layer of the first insulating layer INS1 having a thickness of 10 or less may form a contact hole CNT in the first insulating layer INS1 easily and / or stably. In an embodiment, in the case where the first bottom gate electrode BG1 is connected to the first source electrode SE1, a contact hole CNT exposing a portion of the first bottom gate electrode BG1 may be formed in the first insulating layer INS1 and the buffer layer BFL. Fig.11 , only one contact hole formed in the first insulating layer INS1 and / or the buffer layer BFL is indicated by “CNT”.

[0181] In an embodiment, when the display panel 110 further includes a fourth conductive layer CDL4 and a second insulating layer INS2, as shown in FIG. Figure 5 As shown in , the fourth conductive layer CDL4 and the second insulating layer INS2 may be sequentially formed before the formation of the contact hole CNT. For example, the fourth conductive layer CDL4 may be formed by forming a conductive film on the first insulating layer INS1 and patterning the conductive film, and the second insulating layer INS2 may be formed on the fourth conductive layer CDL4. Thereafter, the contact hole CNT may be formed in the first insulating layer INS1 and the second insulating layer INS2.

[0182] Reference Fig.12 And further refer to Figures 1 to 11 , a third conductive layer CDL3 including a first source electrode SE1, a first drain electrode DE1, a second source electrode SE2, and a second drain electrode DE2 may be formed on the first insulating layer INS1. In an embodiment, in the case where at least one of the first source region SR1, the first drain region DR1, the second source region SR2, and the second drain region DR2 replaces at least one of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2, at least one of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may not be formed.

[0183] The first source electrode SE1 may be formed to be connected to the first source region SR1, and the first drain electrode DE1 may be formed to be connected to the first drain region DR1. In an embodiment, the first source electrode SE1 may also be formed to be connected to the first bottom gate electrode BG1. The second source electrode SE2 may be formed to be connected to the second source region SR2, and the second drain electrode DE2 may be formed to be connected to the second drain region DR2.

[0184] In this way, transistors TFT including first and second transistors TFT1 and TFT2 may be formed in both the display area DA and the driving circuit area DRA. In an embodiment, components provided in the same conductive layer or the same semiconductor layer within the display panel 110 may be manufactured simultaneously.

[0185] After the formation of the transistor TFT, a passivation layer PSV may be formed, such as Figure 3 As shown in . The passivation layer PSV may cover the transistor TFT. Thus, the panel circuit layer PCL of the display panel 110 may be formed.

[0186] In an embodiment, when the display panel 110 includes a light emitting element layer LEL and an encapsulation layer ENL disposed on the panel circuit layer PCL, the light emitting element layer LEL and the encapsulation layer ENL may be sequentially formed on the panel circuit layer PCL. In this way, the display panel 110 and the display device 100 including the display panel 110 may be manufactured.

[0187] In summarizing the detailed description, those skilled in the art will recognize that many changes and modifications may be made to the embodiments without departing substantially from the principles of the invention. Therefore, the embodiments disclosed in the present invention are used in a general and descriptive sense only and not for a limiting purpose.

Claims

1. A display device, comprising: A transistor, the transistor comprising an active layer disposed on a substrate and a gate electrode disposed on the active layer; a gate insulating layer, the gate insulating layer being disposed between the active layer and the gate electrode; as well as a first insulating layer, the first insulating layer being disposed on the gate electrode, Wherein, the first insulating layer comprises: a first layer, the first layer covers the active layer, the gate insulating layer and the gate electrode, the first layer comprises silicon oxide, a second layer disposed on the first layer and comprising silicon oxynitride, and A third layer is disposed on the second layer and includes silicon nitride.

2. The display device according to claim 1, wherein: The thickness of the second layer is to within the range.

3. The display device according to claim 1, wherein: The nitrogen content of the second layer is in the range of 1 atomic % to 10 atomic %.

4. The display device according to claim 1, wherein: The thickness of the first layer is to within the range.

5. The display device according to claim 1, wherein: The nitrogen content of the first layer is less than 1 atomic %.

6. The display device according to claim 1, wherein: The thickness of the third layer is to within the range.

7. The display device according to claim 1, wherein: The nitrogen content of the third layer is in the range of 30 atomic % to 60 atomic %.

8. The display device according to claim 1, wherein: In a region where the first insulating layer covers one side of the gate electrode, the distance between the first layer and the third layer is or larger.

9. The display device according to claim 1, wherein: The active layer includes an oxide semiconductor.

10. The display device according to claim 1, wherein: The gate insulating layer is disposed on a portion of the active layer overlapping the gate electrode and exposing other portions of the active layer, and The first insulating layer directly covers the other portions of the active layer.

11. The display device according to claim 1, wherein: The transistor further includes at least one of a source electrode disposed on the first insulating layer and connected to a portion of the active layer and a drain electrode disposed on the first insulating layer and connected to another portion of the active layer.

12. The display device according to claim 1, wherein: The transistor also includes a bottom gate electrode disposed between the substrate and the active layer.

13. The display device according to claim 1, further comprising: a passivation layer, the passivation layer being disposed on the first insulating layer and covering the transistor; A light emitting element, wherein the light emitting element is disposed on the passivation layer; as well as A packaging layer covers the light emitting element.

14. The display device according to claim 1, further comprising: a capacitor electrode disposed on the first insulating layer and overlapping the gate electrode; as well as A second insulating layer covers the capacitor electrode.

15. A display device, comprising: A transistor, the transistor comprising an active layer disposed on a substrate and a gate electrode disposed on the active layer; a gate insulating layer, the gate insulating layer being disposed between the active layer and the gate electrode; as well as an insulating layer, the insulating layer being disposed on the gate electrode and comprising: a first layer, the first layer covering the active layer, the gate insulating layer and the gate electrode, the first layer comprising silicon oxide, and a second layer disposed on the first layer and comprising silicon oxynitride, Wherein, the thickness of the second layer is to within the range.

16. The display device according to claim 15, wherein: The nitrogen content of the second layer is in the range of 1 atomic % to 10 atomic %.

17. The display device according to claim 15, wherein: The thickness of the first layer is to within the range.

18. The display device according to claim 15, wherein: The insulating layer further includes a third layer disposed on the second layer and including silicon nitride.

19. A method for manufacturing a display device, the method comprising: forming an active layer on a substrate; forming a gate insulating layer and a gate electrode on the active layer; as well as forming an insulating layer on the gate electrode, Wherein, forming the insulating layer comprises: forming a first layer on the substrate, the first layer covering the active layer, the gate insulating layer and the gate electrode and comprising silicon oxide, A second layer is formed on the first layer, the second layer comprising silicon oxynitride, and a third layer is formed on the second layer, the third layer comprising silicon nitride.

20. The method for manufacturing a display device according to claim 19, wherein: The second layer has to Thickness.

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