Driving substrate and display panel

Abstract

The invention provides a driving substrate and a display panel. The driving substrate comprises a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a common electrode layer which are stacked from bottom to top; the driving substrate further comprises a third metal layer, the third metal layer is located on the side, away from the first metal layer, of the second insulating layer, and the third metal layer comprises a plurality of first common electrode wires. The first common electrode wire and the common electrode layer are overlapped together; the first metal layer comprises a gate line for forming a transistor, and the first common electrode line and the gate line have a projection overlapping area. Specifically, a third metal layer is further added in the driving substrate, and the first common electrode wire is designed on the third metal layer, so that the spacing distance between the gate wire and the first common electrode wire is increased, capacitive coupling generated between the first common electrode wire and the gate wire is reduced, and the reliability of the driving substrate is improved. Therefore, the charging rate and the display effect under the high refresh rate can be ensured.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to a driving substrate and a display panel. Background Art

[0002] Large-size display panels play an important role in modern display technology and are widely used in televisions, monitors, public billboards, conference room displays, etc. The technology and manufacturing process of large-size display panels are constantly improving to meet the market demand for high resolution, high brightness, low power consumption and high reliability.

[0003] In the related art, a dual gate architecture is used in the design of large-size display panels to reduce the number of Data ICs (data chips), thereby reducing product costs.

[0004] However, in existing display panels using a dual gate architecture, the capacitive coupling (Cgc) generated between the common electrode wiring (COM) and the gate wiring is relatively large, which will cause problems such as insufficient charging and poor display for large-size and high-refresh rate products. Summary of the invention

[0005] In order to solve the above problems, the present application provides a dynamic substrate and a display panel, which can reduce the capacitive coupling generated between the common electrode wiring and the gate wiring in the display panel adopting the dual gate architecture.

[0006] To solve the above problems, the first technical solution provided by the present application is: providing a driving substrate, the driving substrate comprising a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a common electrode layer stacked from bottom to top;

[0007] The driving substrate further includes a third metal layer, the third metal layer is located on a side of the second insulating layer away from the first metal layer, the third metal layer includes a plurality of first common electrode wirings; and the first common electrode wirings are overlapped with the common electrode layer;

[0008] The first metal layer includes a plurality of gate wirings forming transistors, and a projection of the first common electrode wiring on the bottom of the driving substrate and a projection of the gate wiring on the bottom of the driving substrate have an overlapping area.

[0009] In one embodiment, the third metal layer further includes a second common electrode wiring; the second common electrode wiring is ring-shaped and is disposed around a plurality of the first common electrode wirings, and is connected to the plurality of the first common electrode wirings.

[0010] In one embodiment, the third metal layer also includes multiple third common electrode lines; the extension direction of the multiple third common electrode lines intersects with the extension direction of the multiple first common electrode lines; and the first common electrode lines and the third common electrode lines are both located in the space enclosed by the second common electrode lines in a ring shape; the first common electrode lines, the second common electrode lines and the third common electrode lines are connected.

[0011] In one embodiment, the projection of the third common electrode wiring on the bottom of the driving substrate does not overlap with the projection of the gate wiring on the bottom of the driving substrate at all;

[0012] The driving substrate further includes an isolation column structure, and the isolation column structure is located between two adjacent third common electrode wirings.

[0013] In one embodiment, the driving substrate further includes a third insulating layer, and the third insulating layer is located on a surface of the second insulating layer away from the first metal layer;

[0014] The third metal layer is located between the second insulating layer and the third insulating layer; the common electrode layer is located on the surface of the third insulating layer away from the first metal layer; and a plurality of the first common electrode traces are overlapped with the common electrode layer through via holes on the third insulating layer.

[0015] In one embodiment, the driving substrate further includes a third insulating layer, the third insulating layer is located on a surface of the second insulating layer away from the first metal layer; the common electrode layer is located on a surface of the third insulating layer away from the first metal layer;

[0016] The first common electrode wiring is located on a surface of the common electrode layer away from the first metal layer and overlaps with the common electrode layer; or

[0017] The first common electrode wiring is located on a surface of the common electrode layer close to the first metal layer and overlaps with the common electrode layer.

[0018] In one embodiment, the first metal layer further comprises a plurality of scan lines, and the second metal layer further comprises a plurality of data lines; the driving substrate comprises a plurality of pixel units arranged in an array;

[0019] Wherein, two adjacent columns of pixel units are connected to the same data line;

[0020] In the pixel units in the same row, half of the pixel units are connected to one scanning line, and the other half of the pixel units are connected to another adjacent scanning line.

[0021] In one embodiment, the second metal layer includes source wiring and drain wiring forming a transistor;

[0022] Among them, one of the source wiring and the drain wiring is connected to the data line, and the other is connected to the pixel electrode in the pixel unit.

[0023] In one embodiment, the driving substrate also includes a fourth insulating layer and a pixel electrode layer; the fourth insulating layer covers the common electrode layer, the pixel electrode layer is located on the surface of the fourth insulating layer away from the first metal layer, the pixel electrode layer includes a plurality of pixel electrodes, and the pixel electrode is connected to the source wiring or the drain wiring in the second metal layer through a via.

[0024] In order to solve the above problem, the second technical solution provided in the present application is: to provide a display panel, wherein the display panel comprises the driving substrate described in any one of the above items.

[0025] The beneficial effect of the present application is that, different from the prior art, the present application provides a driving substrate and a display panel, wherein the driving substrate includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a common electrode layer stacked from bottom to top; and the driving substrate also includes a third metal layer, the third metal layer is located on the side of the second insulating layer away from the first metal layer, and the third metal layer includes a plurality of first common electrode traces; and the first common electrode traces are overlapped with the common electrode layer; the first metal layer includes a gate trace forming a transistor, and the projection of the first common electrode trace at the bottom of the driving substrate and the projection of the gate trace at the bottom of the driving substrate have an overlapping area. Specifically, the present application further adds a third metal layer to the driving substrate, and designs the first common electrode trace located in the second metal layer in the prior art to be located in the third metal layer, thereby increasing the spacing distance between the gate trace and the first common electrode trace, and reducing the capacitive coupling generated between the first common electrode trace and the gate trace, thereby facilitating the reduction of the gate load, reducing the delay of the signal on the gate trace, and increasing the charging time, thereby ensuring the charging rate and display effect under high refresh rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0027] Figure 1 It is a partial structural layout of a driving substrate in the prior art;

[0028] Figure 2 for Figure 1 A partial structural cross-sectional view of the middle A area;

[0029] Figure 3 Partial structural layout of the driving substrate provided in this application;

[0030] Figure 4 for Figure 3 A partial structural cross-sectional view of an embodiment of the region A;

[0031] Figure 5 for Figure 3 A partial structural cross-sectional view of another embodiment of the region A;

[0032] Figure 6 for Figure 3 A partial structural cross-sectional view of another embodiment of the middle A region;

[0033] Figure 7 A schematic diagram of the structure of an embodiment of the common electrode routing provided in the present application;

[0034] Figure 8 A schematic diagram of the structure of another embodiment of the common electrode routing provided in the present application;

[0035] Fig. 9 for Figure 3 A partial structural cross-sectional view of an embodiment of the middle B area;

[0036] Fig.10 A schematic structural diagram of an embodiment of a display panel provided in the present application;

[0037] Fig.11 A schematic structural diagram of another embodiment of the display panel provided in the present application.

[0038] Description of labels:

[0039] First metal layer 10; gate wiring 11; scanning line 12;

[0040] A first insulating layer 20;

[0041] Second metal layer 30; data line 32; source wiring 33; drain wiring 34;

[0042] A second insulating layer 40;

[0043] A third insulating layer 50;

[0044] Common electrode layer 60;

[0045] The third metal layer 70; the common electrode wiring 31; the first common electrode wiring 311; the second common electrode wiring 312; the third common electrode wiring 313;

[0046] a fourth insulating layer 80;

[0047] Pixel electrode 90;

[0048] Transistor TFT; pixel unit P; isolation column structure PS;

[0049] Display panel 1000; driving substrate 100;

[0050] First direction Y; second direction X. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] The terms "first", "second", "third", etc. in this application are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first", "second", "third" may explicitly or implicitly include at least one of the features.

[0053] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0054] See also Figure 1 and Figure 2 , Figure 1 It is a partial structural layout of a driving substrate in the prior art; Figure 2 for Figure 1 Partial structural cross-sectional view of area A in the middle.

[0055] in, Figure 1 Oxide products have low leakage current and high stability, suitable for large-size and low-power panels. Figure 1The driving substrate shown in the figure adopts a dual gate architecture to reduce the number of Data ICs. Specifically, in the dual gate architecture, the number of data lines in the second metal layer 30 is reduced by about half, and the other half of the data lines that are not used in the second metal layer 30 are used as common electrode lines 31, and the common electrode lines 31 in different columns are connected in parallel through punching, so that the resistance of the common electrode lines 31 can be reduced.

[0056] See also Figure 2 The driving substrate includes a first metal layer 10, a first insulating layer 20, a second metal layer 30, a second insulating layer 40, a third insulating layer 50 and a common electrode layer 60 stacked from bottom to top; wherein the first insulating layer 20 is used to insulate the first metal layer 10 from the second metal layer 30, and the second insulating layer 40 and the third insulating layer 50 are used to insulate the second metal layer 30 from the common electrode layer 60. The first metal layer 10 includes a gate wiring 11 forming a transistor, the second metal layer 30 includes a common electrode wiring 31, and the common electrode wiring 31 includes a first common electrode wiring 311, the projection of the first common electrode wiring 311 on the bottom of the driving substrate has an overlapping area with the projection of the gate wiring 11 on the bottom of the driving substrate, and the first common electrode wiring 311 is overlapped with the common electrode layer 60 to provide a common voltage signal (com signal) for the common electrode layer 60.

[0057] It can be seen that in the prior art, there is only one insulating layer between the first common electrode wiring 311 and the gate wiring 11, and because the projections of the first common electrode wiring 311 and the gate wiring 11 overlap a lot, and in addition, in order to reduce the delay of the Gate signal, the line width of the gate wiring 11 will be widened, which will cause the capacitive coupling between the gate wiring 11 and the common electrode wiring 31 to increase a lot, thereby increasing the load (Loading) of the gate wiring 11. For large-size and high-refresh-rate products, the loading increases when the charging time is short, so that the product display is poor due to insufficient charging. In addition, since the loading of the first common electrode wiring 311 will also become larger, it will also cause uneven display problems.

[0058] See also Figure 3-Figure 6 , Figure 3 Partial structural layout of the driving substrate provided in this application; Figure 4 for Figure 3 A partial structural cross-sectional view of an embodiment of the region A; Figure 5 for Figure 3 A partial structural cross-sectional view of another embodiment of the region A; Figure 6 for Figure 3 A partial structural cross-sectional view of another embodiment of the region A.

[0059] Specifically, in order to solve the above problems, the present application provides a driving substrate. Similar to the above existing driving substrate, the driving substrate in the embodiment of the present application also includes a first metal layer 10, a first insulating layer 20, a second metal layer 30, a second insulating layer 40 and a common electrode layer 60 stacked from bottom to top. The first metal layer 10 includes a gate wiring 11 forming a transistor TFT, but different from the existing driving substrate, in the driving substrate in the embodiment of the present application, the second metal layer 30 does not include a common electrode wiring 31, and the driving substrate further includes a third metal layer 70, the third metal layer 70 is located on the side of the second insulating layer 40 away from the first metal layer 10, the third metal layer 70 includes the above common electrode wiring 31, and the common electrode wiring 31 includes a plurality of first common electrode wirings 311, and the first common electrode wiring 311 is overlapped with the common electrode layer 60. And the projection of the first common electrode wiring 311 at the bottom of the driving substrate has an overlapping area with the projection of the gate wiring 11 at the bottom of the driving substrate.

[0060] Among them, in the embodiment of the present application, the extension direction of multiple first common electrode lines 311 is the same and is the first direction Y, and the first common electrode lines 311 and the common electrode layer 60 can be overlapped together by directly bonding them together; or, the first common electrode lines 311 and the common electrode layer 60 can be overlapped together by being connected together through vias.

[0061] In the embodiment of the present application, the first insulating layer 20 can be understood as a gate insulating layer (GI), and the second insulating layer 40 can be understood as an inorganic layer, such as a passivation layer (PAS).

[0062] Specifically, compared to Figure 1 and Figure 2 The driving substrate shown in the present application further adds a third metal layer 70, and the common electrode wiring 31 located in the second metal layer 30 in the prior art is designed in the third metal layer 70, so that the first common electrode wiring 311 and the gate wiring 11 are separated by at least two insulating layers, thereby increasing the spacing distance between the gate wiring 11 and the first common electrode wiring 311, and reducing the capacitive coupling (cgc) generated between the first common electrode wiring 311 and the gate wiring 11, which is beneficial to reducing the gate load (Gate Loading), reducing the delay of the signal on the gate wiring 11, and increasing the charging time, thereby ensuring the charging rate and display effect under high refresh rate.

[0063] In the embodiment of the present application, the first metal layer 10 further includes a plurality of scan lines 12, and the plurality of scan lines 12 are electrically connected to the plurality of gate wirings 11, and are used to provide signals to the gate wirings 11. The extension direction of the plurality of scan lines 12 is the same and is the second direction X, and the second direction X intersects the first direction Y; for example, the second direction X is perpendicular to the first direction Y.

[0064] The second metal layer 30 includes a plurality of data lines 32 ; the extension direction of the plurality of data lines 32 is the same as the extension direction of the plurality of first common electrode wirings 311 .

[0065] See also Figure 3 The driving substrate includes a plurality of pixel units P arranged in an array; wherein two adjacent columns of pixel units P are connected to the same data line 32; in the pixel units P in the same row, half of the pixel units P are connected to a scan line 12, for example, connected to the scan line 12(1), and the other half of the pixel units P are connected to another adjacent scan line 12, for example, connected to the scan line 12(2).

[0066] Specifically, through this design, the driving substrate provided by the present application is a dual gate architecture, which can reduce the number of Data ICs and thus save costs.

[0067] Further, see Fig. 9 , Fig. 9 for Figure 3 The second metal layer 30 also includes a source wiring 33 and a drain wiring 34 forming a transistor TFT; wherein one of the source wiring 33 and the drain wiring 34 is connected to the data line 32, and the other is connected to the pixel electrode 90 in the pixel unit P.

[0068] For example, the source wiring 33 is connected to the data line 32, and the drain wiring 34 is connected to the pixel electrode 90. For another example, the drain wiring 34 is connected to the data line 32, and the source wiring 33 is connected to the pixel electrode 90. This is not limited here, and is specifically determined according to the conductivity type of the transistor in the pixel unit P.

[0069] See also Figure 7 , Figure 7 A schematic structural diagram of an embodiment of the common electrode routing provided in the present application; in one embodiment of the present application, the common electrode routing 31 in the third metal layer 70 also includes a second common electrode routing 312; the second common electrode routing 312 is ring-shaped and is arranged around multiple first common electrode routings 311, and is connected to multiple first common electrode routings 311.

[0070] The second common electrode wiring 312 may be designed to correspond to the border area of ​​the panel and serve as a bus of the common electrode wiring 31 .

[0071] Specifically, by setting the second common electrode line 312, the second common electrode line 312 connects multiple first common electrode lines 311 designed to extend along the first direction Y, thereby reducing the resistance of the common electrode line 31 and reducing the load of the common electrode line 31, thereby reducing power consumption.

[0072] See also Figure 8 , Figure 8 A schematic structural diagram of another embodiment of the common electrode routing provided in the present application; in another embodiment of the present application, the common electrode routing 31 in the third metal layer 70 also includes multiple third common electrode routings 313; and the first common electrode routing 311 and the third common electrode routing 313 are both located in the space enclosed by the second common electrode routing 312 in a ring shape; the first common electrode routing 311, the second common electrode routing 312 and the third common electrode routing 313 are connected.

[0073] The extension direction of the plurality of third common electrode wirings 313 intersects with the extension direction of the plurality of first common electrode wirings 311. Figure 8 As shown, the plurality of third common electrode lines 313 are extended along the second direction X, and the extension direction of the plurality of third common electrode lines 313 is perpendicular to the extension direction of the plurality of first common electrode lines 311 .

[0074] Specifically, the first common electrode wiring 311 , the second common electrode wiring 312 and the third common electrode wiring form a mesh structure, which can further reduce the resistance of the common electrode wiring 31 , reduce the load of the common electrode wiring 31 , and further reduce the power consumption of the device.

[0075] Furthermore, combined with Fig. 9 The third common electrode wiring 313 and the gate wiring 11 extend in the same direction, and the projection of the third common electrode wiring 313 on the bottom of the driving substrate does not overlap with the projection of the gate wiring 11 on the bottom of the driving substrate.

[0076] Specifically, the projection of the third common electrode wiring 313 on the bottom of the driving substrate is arranged to be completely non-overlapping with the projection of the gate wiring 11 on the bottom of the driving substrate, thereby reducing the capacitive coupling generated between the common electrode wiring 31 and the gate wiring 11, which is beneficial to reducing the gate load, reducing the delay of the signal on the gate wiring 11, and increasing the charging time, thereby ensuring the charging rate and display effect under high refresh rate.

[0077] For further information, see Fig. 9 The driving substrate further includes a post spacer structure PS, and the post spacer structure PS is located between two adjacent third common electrode traces 313 .

[0078] Among them, the spacer column structure PS plays an important role in maintaining the substrate spacing, preventing short circuits, improving reliability and controlling optical performance in the display panel. Through reasonable design and manufacturing process, the spacer column structure PS can significantly improve the performance and reliability of the display panel.

[0079] Taking OLED display panels as an example, the isolation column structure PS can be used to prevent organic materials from flowing between substrates, ensuring the stability and reliability of the device.

[0080] Of course, the spacer column structure PS can also be applied to LCD display panels to maintain a uniform thickness of the liquid crystal layer and ensure the display effect.

[0081] Specifically, in the embodiment of the present application, an isolation column structure PS is disposed between two adjacent third common electrode lines 313, and the third common electrode lines 313 located on both sides of the isolation column structure PS can limit the slippage of the isolation column structure PS, thereby avoiding light leakage and poor support problems caused by the slippage of the isolation column structure PS.

[0082] See also Figure 4-Figure 6 In the embodiment of the present application, the driving substrate further includes the third insulating layer 50 mentioned above, and the third insulating layer 50 is located on the surface of the second insulating layer 40 away from the first metal layer 10; the common electrode layer 60 is located on the surface of the third insulating layer 50 away from the first metal layer 10.

[0083] The third insulating layer 50 may be understood as an organic layer, such as a planarization layer (PFA).

[0084] Among them, see Figure 6 The third metal layer 70 may be located between the second insulating layer 40 and the third insulating layer 50 ; and the plurality of first common electrode traces 311 are overlapped with the common electrode layer 60 through via holes on the third insulating layer 50 .

[0085] Specifically, compared to Figure 1 and Figure 2 As shown in the driving substrate, in the embodiment of the present application, two insulating layers are placed between the first common electrode wiring 311 and the gate wiring 11, thereby increasing the spacing distance between the gate wiring 11 and the first common electrode wiring 311, reducing the capacitive coupling generated between the first common electrode wiring 311 and the gate wiring 11, which is beneficial to reducing the gate load, reducing the delay of the signal on the gate wiring 11, and increasing the charging time, thereby ensuring the charging rate and display effect under high refresh rate.

[0086] Alternatively, see Figure 4 or Figure 5The third metal layer 70 may also be located on the side of the third insulating layer 50 away from the first metal layer 10 and in contact with the common electrode layer 60. Figure 4 , the first common electrode trace 311 is located on the surface of the common electrode layer 60 away from the first metal layer 10 and overlaps with the common electrode layer 60. For another example, see Figure 5 The first common electrode wiring 311 is located on the surface of the common electrode layer 60 close to the first metal layer 10 and overlaps with the common electrode layer 60 .

[0087] Specifically, compared to Figure 1 and Figure 2 As shown in the driving substrate, in the embodiment of the present application, three insulating layers are spaced between the first common electrode wiring 311 and the gate wiring 11, thereby increasing the spacing distance between the gate wiring 11 and the first common electrode wiring 311, reducing the capacitive coupling generated between the first common electrode wiring 311 and the gate wiring 11, which is beneficial to reducing the gate load, reducing the delay of the signal on the gate wiring 11, and increasing the charging time, thereby ensuring the charging rate and display effect under high refresh rate.

[0088] Compared with Figure 6 In the embodiment shown, in this embodiment, the first common electrode wiring 311 and the common electrode layer 60 can be electrically connected without vias, thereby further reducing the capacitive coupling between the first common electrode wiring 311 and the gate wiring 11 .

[0089] Further, see Figure 4-Figure 6 In an embodiment of the present application, the driving substrate also includes a fourth insulating layer 80 and a pixel electrode layer; the fourth insulating layer 80 covers the common electrode layer 60, the pixel electrode layer is located on the surface of the fourth insulating layer 80 away from the first metal layer 10, and the pixel electrode layer includes a plurality of pixel electrodes 90, and the pixel electrodes 90 are connected to the source wiring 33 or the drain wiring 34 in the second metal layer 30 through vias.

[0090] See also Fig.10 and Fig.11 , Fig.10 A schematic structural diagram of an embodiment of a display panel provided in the present application; Fig.11 A schematic structural diagram of another embodiment of the display panel provided in the present application.

[0091] Specifically, the present application further provides a display panel 1000 , which includes a driving substrate 100 , and the driving substrate 100 includes the driving substrate provided by any of the above embodiments.

[0092] The types of the display panel 1000 include but are not limited to LED display panel, OLED display panel, LCD display panel, etc.

[0093] When the display panel 1000 is an LED or OLED display panel, see Fig.10 The display panel 1000 further includes at least a light emitting layer 200 and a cover plate 300 stacked with the driving substrate 100 . The driving substrate 100 is used to control the operation of the light emitting layer 200 , and the cover plate 300 is used to protect the light emitting layer 200 and the driving substrate 100 .

[0094] When the display panel 1000 is an LCD display panel, see Fig.11 The display panel 1000 further includes at least a liquid crystal layer 400 and a color filter substrate 500 stacked with the driving substrate 100. The driving substrate 100 is used to control the operation of the liquid crystal layer 400, and the color filter substrate 500 is used to change the color of the emitted light.

[0095] Specifically, the display panel 1000 can be applied to mobile phones, televisions, computers, notebooks, smart wearable devices and other fields, thereby improving the user experience of the above electronic devices with display functions.

[0096] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A driving substrate, comprising a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a common electrode layer stacked from bottom to top; It is characterized in that The driving substrate further includes a third metal layer, the third metal layer is located on a side of the second insulating layer away from the first metal layer, the third metal layer includes a plurality of first common electrode wirings; and the first common electrode wirings are overlapped with the common electrode layer; The first metal layer includes a gate wiring forming a transistor, and a projection of the first common electrode wiring on the bottom of the driving substrate and a projection of the gate wiring on the bottom of the driving substrate have an overlapping area.

2. The driving substrate according to claim 1, characterized in that: The third metal layer also includes a second common electrode wiring; the second common electrode wiring is ring-shaped and is arranged around a plurality of the first common electrode wirings, and is connected to the plurality of the first common electrode wirings.

3. The driving substrate according to claim 2, characterized in that: The third metal layer also includes multiple third common electrode lines; the extension direction of the multiple third common electrode lines intersects with the extension direction of the multiple first common electrode lines; and the first common electrode lines and the third common electrode lines are both located in the space enclosed by the second common electrode lines in a ring shape; the first common electrode lines, the second common electrode lines and the third common electrode lines are connected.

4. The driving substrate according to claim 3, characterized in that: The projection of the third common electrode wiring on the bottom of the driving substrate does not overlap with the projection of the gate wiring on the bottom of the driving substrate; The driving substrate further includes an isolation column structure, and the isolation column structure is located between two adjacent third common electrode wirings.

5. The driving substrate according to any one of claims 1 to 4, characterized in that: The driving substrate further includes a third insulating layer, the third insulating layer is located on a surface of the second insulating layer away from the first metal layer; the common electrode layer is located on a surface of the third insulating layer away from the first metal layer; The third metal layer is located between the second insulating layer and the third insulating layer; a plurality of the first common electrode wirings are overlapped with the common electrode layer through via holes on the third insulating layer.

6. The driving substrate according to any one of claims 1 to 4, characterized in that: The driving substrate further includes a third insulating layer, the third insulating layer is located on a surface of the second insulating layer away from the first metal layer; the common electrode layer is located on a surface of the third insulating layer away from the first metal layer; The first common electrode wiring is located on a surface of the common electrode layer away from the first metal layer and overlaps with the common electrode layer; or The first common electrode wiring is located on a surface of the common electrode layer close to the first metal layer and overlaps with the common electrode layer.

7. The driving substrate according to claim 1, characterized in that: The first metal layer further comprises a plurality of scan lines, and the second metal layer comprises a plurality of data lines; the driving substrate comprises a plurality of pixel units arranged in an array; Wherein, two adjacent columns of pixel units are connected to the same data line; In the pixel units in the same row, half of the pixel units are connected to one scanning line, and the other half of the pixel units are connected to another adjacent scanning line.

8. The driving substrate according to claim 7, characterized in that: The second metal layer also includes source wiring and drain wiring forming the transistor; Among them, one of the source wiring and the drain wiring is connected to the data line, and the other is connected to the pixel electrode in the pixel unit.

9. The driving substrate according to claim 8, characterized in that: The driving substrate also includes a fourth insulating layer and a pixel electrode layer; the fourth insulating layer covers the common electrode layer, the pixel electrode layer is located on the surface of the fourth insulating layer away from the first metal layer, the pixel electrode layer includes a plurality of pixel electrodes, and the pixel electrodes are connected to the source wiring or the drain wiring through vias.

10. A display panel, characterized in that: The display panel comprises the driving substrate according to any one of claims 1 to 9.

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