A back-contact battery, its etching-free manufacturing method, and a battery assembly

Abstract

The present invention belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery, a non-etching manufacturing method thereof, and a battery module. The method includes depositing an intrinsic amorphous silicon layer on the backlight side of a silicon wafer; forming alternately distributed first doping regions, second doping regions, and a co-doping region between the first doping region and the second doping region on the outer surface of the intrinsic amorphous silicon layer; disposing a hard mask plate on the outer surface of the co-doping region, and depositing a conductive film layer and a metal electrode on the backlight side. The present invention avoids the use of high-temperature lasers and chemical etching, thereby reducing damage to the battery and environmental pollution, significantly improving the production yield, significantly reducing the production cost, while improving the reliability and service life of the battery, and can obtain good battery efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery, a non-etching manufacturing method thereof, and a battery assembly. Background Art

[0002] In the field of solar cells, back-contact batteries have received attention due to their high efficiency and low temperature coefficient. However, the NP semiconductor layer of traditional back-contact batteries is disposed on the back surface. In order to obtain high battery efficiency, there are some significant defects in the preparation technologies adopted by current battery structures. These technologies usually require growth masks and etching steps to form the back-contact structure of the battery, and these steps involve high-temperature processes such as lasers and the use of acids and bases. These high-temperature and chemical treatments may not only damage the battery wafers, reducing battery performance and reliability, but also cause environmental pollution.

[0003] Moreover, the high-temperature and chemical treatment steps in the prior art increase production costs and limit their application in large-scale production. In addition, these process steps are complex and require high equipment requirements, which are not conducive to large-scale production and cost control.

[0004] It should be noted that this part of the content of the present invention only provides background technologies related to the present invention, and does not necessarily constitute prior art or well-known technologies. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects of the prior art that the preparation process required by the traditional back-contact battery structure needs to use high-temperature lasers and chemical etching steps, which may cause damage to the battery, reduce battery performance and reliability, cause environmental pollution, and have high costs. The present invention provides a back-contact battery, a non-etching manufacturing method thereof, and a battery assembly, which avoid the use of high-temperature lasers and chemical etching, thereby reducing damage to the battery and environmental pollution, significantly improving production yield, significantly reducing production costs, while improving the reliability and service life of the battery, and can obtain good battery efficiency.

[0006] To achieve the above purpose, in the first aspect, the present invention provides a non-etching manufacturing method for a back-contact battery, including the following steps:

[0007] S1. Provide a silicon wafer;

[0008] S2. Deposit an intrinsic amorphous silicon layer on the backlight surface of the silicon wafer;

[0009] S3. Preset an alternately distributed first doping region, a second doping region, and a co-doping region between the first doping region and the second doping region on the outer surface of the intrinsic amorphous silicon layer; one of the first doping region and the second doping region is N-type, and the other is P-type; the doping source of the co-doping region includes doping source A of the first doping region and doping source B of the second doping region;

[0010] First, use a first hard mask to block the preset second doped region and the preset co-doped region on the backlight side, and grow a first doped silicon with a target thickness on the backlight side to form a first doped region; wherein, control the distance D between the first hard mask and the intrinsic amorphous silicon layer to be greater than the target thickness of the first doped silicon;

[0011] S4. Then, use a second hard mask to block the preset first doped region and the preset co-doped region on the backlight side, and grow a second doped silicon with a target thickness to form a second doped region; wherein, the distance d between the second hard mask and the intrinsic amorphous silicon layer is greater than the target thickness of the second doped silicon; meanwhile, a co-doped region is naturally formed in the contact part region between the first doped silicon and the second doped silicon;

[0012] S5. Set a hard mask plate on the outer surface of the co-doped region, and deposit a conductive film layer on the backlight side;

[0013] S6. Form metal electrodes on the outer surfaces of the first doped region and the second doped region respectively.

[0014] In some preferred embodiments of the present invention, the ratio of D to the target thickness of the first doped silicon in S3 is 10 - 20000:1, and / or, the ratio of d to the target thickness of the second doped silicon in S4 is 10 - 20000:1.

[0015] In some preferred embodiments of the present invention, the target thickness of the first doped silicon is controlled to be 8 - 20 nm; and / or, the target thickness of the second doped silicon is controlled to be 8 - 20 nm.

[0016] In some preferred embodiments of the present invention, the width of the co-doped region is 5 - 150 μm; and / or, control D in S3 to be maintained at 0.2 - 200 μm, and d in S4 to be maintained at 0.2 - 200 μm.

[0017] In some preferred embodiments of the present invention, the thickness of the co-doped region is 5 - 30 nm.

[0018] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the doping concentration of dopant A in the co-doped region shows a decreasing distribution, and the doping concentration of dopant B shows an increasing distribution.

[0019] In some more preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the co-doped region is sequentially divided into a first region, a second intermediate region, and a third region, and the second intermediate region includes an A-doped substrate and a concentrated double-doped region formed by at least partially doping B in the A-doped substrate.

[0020] In some preferred embodiments of the present invention, the doping source A contains phosphorus, the doping source B contains boron, the phosphorus doping concentration in the second intermediate region is 1e15 cm -3 -2e20 cm -3 , the boron doping concentration is 1e15 cm -3 -2e20 cm -3 , and the corresponding phosphorus doping concentrations in the first region and the third region are each independently 5e15 cm -3 -2e20 cm -3 , and the boron doping concentrations are each independently 5e15 cm -3 -2e20 cm -3 .

[0021] In some preferred embodiments of the present invention, in the diagonal direction of the co-doping region starting from the inner end of the first doping region close to the silicon wafer, the depth ratio of the concentrated double-doping region in the A-doped substrate is 25%-80%; and / or, the depth of the concentrated double-doping region is 5-30 nm.

[0022] In some preferred embodiments of the present invention, the ratio of the minimum doping concentration of the doping source A in the co-doping region to the doping concentration of the doping source A in the first doping region is 0.01-100:100, and the ratio of the minimum doping concentration of the doping source B in the co-doping region to the doping concentration of the doping source B in the second doping region is 0.01-100:100.

[0023] In some preferred embodiments of the present invention, the phosphorus doping concentration in the co-doping region is 1e15 cm -3 -2e20 cm -3 , the boron doping concentration is 1e15 cm -3 -2e20 cm -3 ; and / or, the flow rates of the phosphorus source corresponding to the growth of the first doped silicon and the second doped silicon are each controlled to be 1-12 sccm, and the flow rate of the boron source is 1-12 sccm.

[0024] In some preferred embodiments of the present invention, the first doped silicon grown in S3 and the second doped silicon grown in S4 are each independently formed by plasma-enhanced chemical vapor deposition or hot-wire chemical vapor deposition.

[0025] In some preferred embodiments of the present invention, the conditions for growing the first doped silicon in S3 include: introducing silane, ammonia, and a gas source corresponding to the doping source A, where the flow rate of silane is 45-50sccm; the conditions for growing the second doped silicon in S4 include: introducing silane and a gas source corresponding to the doping source B, where the flow rate of silane is 45-50sccm; wherein, the gas source corresponding to the doping source A and the gas source corresponding to the doping source B, one of which is a boron source and the other is a phosphorus source, the flow rate of the boron source is 1-12sccm, and the flow rate of the phosphorus source is 1-12sccm.

[0026] Preferably, in the present invention, one of the doping source A of the first doping region and the doping source B of the second doping region is phosphorus and the other is boron, wherein the phosphorus doping concentration is between 2e18cm -3 -2e20cm -3 , the boron doping concentration is 2e18cm -3 -2e20cm -3 .

[0027] In some preferred embodiments of the present invention, the thickness of the intrinsic amorphous silicon layer in S2 is 5-15 nm.

[0028] In some preferred embodiments of the present invention, the first doped silicon and the second doped silicon in S3 are each independently selected from correspondingly doped amorphous silicon or microcrystalline silicon.

[0029] In some preferred embodiments of the present invention, the distance between the hard mask and the backlight surface of the silicon wafer in S5 is controlled to be 0.2-200 μm.

[0030] In some preferred embodiments of the present invention, the thickness of the conductive film layer in S5 is 30-100 nm.

[0031] In some preferred embodiments of the present invention, the conductive film layer in S5 is deposited by magnetron sputtering.

[0032] In some preferred embodiments of the present invention, the thickness of the metal electrode in S6 is 3-20 μm.

[0033] In some preferred embodiments of the present invention, the silicon wafer in S1 is a silicon wafer with a light-receiving surface textured and a back-light surface polished.

[0034] In some preferred embodiments of the present invention, the etching-free manufacturing method of the back contact cell further includes the step of forming a passivation anti-reflection layer on the light-receiving surface of the silicon wafer in S1.

[0035] In a second aspect, the present invention provides a high-reliability back-contact battery, which is manufactured by the etching-free manufacturing method of the back-contact battery described in the first aspect.

[0036] Third aspect, the present invention provides a back-contact battery, comprising a silicon wafer, an intrinsic amorphous silicon layer is disposed on the backlight side of the silicon wafer, a first doped region and a second doped region are alternately disposed outside the intrinsic amorphous silicon layer, and a co-doped region is disposed between the first doped region and the second doped region; one of the first doped region and the second doped region is N-type and the other is P-type; the doping source of the co-doped region comprises doping source A of the first doped region and doping source B of the second doped region; in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the doping concentration of doping source A in the co-doped region decreases and the doping concentration of doping source B increases.

[0037] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the co-doped region is sequentially divided into a first region, a second intermediate region, and a third region, and the second intermediate region comprises an A-doped substrate and a concentrated double-doped region formed by at least partially doping B in the A-doped substrate.

[0038] In some preferred embodiments of the present invention, the doping source A comprises phosphorus, the doping source B comprises boron, and the phosphorus doping concentration in the second intermediate region is 1e15 cm -3 -2e20 cm -3 , and the boron doping concentration is 1e15 cm -3 -2e20 cm -3 , and the corresponding phosphorus doping concentrations in the first region and the third region are each independently 5e15 cm -3 -2e20 cm -3 , and the boron doping concentrations are each independently 5e15 cm -3 -2e20 cm -3 .

[0039] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the depth ratio of the concentrated double-doped region in the A-doped substrate is 25%-80%; and / or, the depth of the concentrated double-doped region is 5-30 nm.

[0040] In some preferred embodiments of the present invention, the ratio of the minimum doping concentration of doping source A in the co-doped region to the doping concentration of doping source A in the first doped region is 0.01-100:100, and the ratio of the minimum doping concentration of doping source B in the co-doped region to the doping concentration of doping source B in the second doped region is 0.01-100:100.

[0041] In some preferred embodiments of the present invention, the phosphorus doping concentration in the co-doped region is 1e15 cm -3 -2e20 cm -3 , and the boron doping concentration is 1e15 cm -3-2e20 cm -3 .

[0042] In some preferred embodiments of the present invention, the ratio of the width of the co-doped region to the width of the first doped region or the second doped region is 0.01 - 0.5:1.

[0043] In some preferred embodiments of the present invention, the ratio of the thickness of the co-doped region to the thickness of the first doped region or the second doped region is 0.5 - 1.4:1, more preferably 0.8 - 1.4:1.

[0044] In some preferred embodiments of the present invention, the width of the co-doped region is 5 - 150 μm.

[0045] In some preferred embodiments of the present invention, the thickness of the co-doped region is 5 - 30 nm.

[0046] In some preferred embodiments of the present invention, the thicknesses of the first doped region and the second doped region are each independently 8 - 20 nm.

[0047] In some preferred embodiments of the present invention, the widths of the first doped region and the second doped region are each independently 100 - 600 μm.

[0048] In some preferred embodiments of the present invention, one of the doping source A of the first doped region and the doping source B of the second doped region is phosphorus and the other is boron, wherein the phosphorus doping concentration is 2e18 cm -3 -2e20 cm -3 , and the boron doping concentration is 2e18 cm -3 -2e20 cm -3 .

[0049] In some preferred embodiments of the present invention, the first doped region and the second doped region are each independently selected from doped amorphous silicon or microcrystalline silicon corresponding to the doping.

[0050] In some preferred embodiments of the present invention, the thickness of the intrinsic amorphous silicon layer is 5 - 15 nm; and / or, the ratio of the thickness of the intrinsic amorphous silicon layer to the thickness of the first doped region or the second doped region is 0.5 - 2:1.

[0051] In some preferred embodiments of the present invention, the back contact cell further includes at least one of the following structures:

[0052] Structure 1: In the width direction, the first doped region and the co-doped region are in contact with each other and the co-doped region and the second doped region are in contact with each other and are continuously distributed as a whole;

[0053] Structure 2: The back contact cell further includes a light-receiving surface passivation and antireflection layer provided on the light-receiving surface of the silicon wafer;

[0054] Structure III: The light-receiving surface of the silicon substrate is a textured surface, and the backlight surface is a polished surface;

[0055] Structure IV: The back-contact battery further includes a conductive film layer and a metal electrode sequentially provided on the outer surfaces of the first doping region and the second doping region. An isolation groove is provided between the conductive film layer provided on the outer surface of the first doping region and the conductive film layer provided on the outer surface of the second doping region, and at least a part of the isolation groove is located on the outer surface of the co-doping region.

[0056] Fourth aspect, the present invention provides a battery module, which includes the high-reliability back-contact battery described in the second aspect, or includes the back-contact battery described in the third aspect.

[0057] Beneficial effects:

[0058] Through the above technical solutions, especially S2-S4, the present invention can form a back-contact battery structure without high-temperature laser processes and chemical etching processes (such as wet etching), which can avoid the application of acids and bases in high-temperature processes and chemical etching, effectively reduce the damage to the battery, significantly improve the production yield, significantly reduce the production cost, and at the same time improve the reliability and service life of the battery, and can obtain good battery efficiency. Moreover, since high-temperature processes such as laser and the use of acids and bases are avoided, the present invention reduces environmental pollution during the preparation process, meeting the requirements of green manufacturing; at the same time, since there is no etching step, the production process is simplified, and the consumption of materials and energy is reduced, thereby significantly reducing the production cost. Moreover, the etching-free manufacturing method of the present invention can be applied to different battery sizes and shapes, has good adaptability, and can meet diverse market demands.

[0059] The present invention uses a hard mask technology to enable precise area control. By controlling the distance D between the first hard mask and the intrinsic amorphous silicon layer to be greater than the target thickness of the first doped silicon, and the distance d between the second hard mask and the intrinsic amorphous silicon layer to be greater than the target thickness of the second doped silicon, a sufficient specific co-doping region is naturally formed in the contact part region of the first doped silicon and the second doped silicon, enabling more precise preparation of the battery structure. The specific co-doping region can effectively insulate and isolate the first doping region and the second doping region, can significantly reduce the conductivity between the first doping region and the second doping region, avoid lateral leakage current, thereby improving the lateral insulation of the back-contact battery. This doping structure, combined with the passivation structure of the intrinsic amorphous silicon layer, can improve the performance such as the consistency and reliability of the battery while obtaining good battery efficiency.

[0060] The back-contact battery of the present invention can effectively insulate and isolate the first doping region and the second doping region by setting the first doping region, the second doping region, and the co-doping region with a specific structure, and the doping concentration of doping source A in the co-doping region shows a decreasing distribution, while the doping concentration of doping source B shows an increasing distribution. The double-doping effect of the co-doping region (i.e., doping two ions simultaneously) can be utilized to significantly reduce the conductivity between the first doping region and the second doping region, avoid lateral leakage current, thereby improving the lateral insulation of the back-contact battery, and enhancing battery performance such as production yield, battery efficiency, battery stability, and reliability, meeting the market demand for high-efficiency solar cells. The present invention can significantly reduce the conductivity between the first doping region and the second doping region (in a specific embodiment, the applicant unexpectedly found that compared with the film layer doped with a single dopant (i.e., only N-type doping or P-type doping) under the same conditions, when co-doping with N-type doping ions and P-type doping ions, the resistivity can increase from 1e3 Ω·cm to 1e5 Ω·cm to 1e7 Ω·cm to 1e10 Ω·cm, and the conductivity can decrease from 1e-3 S / cm to 1e-5 S / cm to 1e-7 S / cm to 1e-10 S / cm). The possible speculative principles include that the difference in the sizes of the two ions leads to local structural distortion, destroying the channels suitable for the migration of single electrons or holes; the two ions create different local environments, resulting in site energy mismatch; and due to the need for the two ions to compete for the migratable sites in the doping substrate, and the doping substrate makes the distribution of the potential barrier become complex due to the doping of multiple ions, etc. Multiple adverse factors lead to a decrease in the carrier concentration and the order of magnitude of the overall mobility, and finally significant insulation is obtained.

[0061] Among them, compared with tunneling oxide layer passivation (the tunneling oxide layer generally needs to be annealed at high temperature to form holes to improve the tunneling ability of carriers, and the high-temperature annealing treatment will crystallize the amorphous silicon, and the conductivity will increase significantly after crystallization), the present invention uses intrinsic amorphous silicon to passivate the first doping region and the second doping region. Using intrinsic amorphous silicon does not require high-temperature annealing treatment, so it can effectively control the conductivity and has a better passivation effect, which is beneficial to controlling the conductivity of the first doping region and the second doping region, thereby effectively controlling the lateral leakage current between the first doping region and the second doping region and facilitating the improvement of battery efficiency. The present invention also cooperates with the setting of a conductive film layer, greatly improving the carrier collection ability of the first doping region and the second doping region, and further improving the battery efficiency.

[0062] Moreover, the structure of the back-contact battery of the present invention, as compared with using materials such as intrinsic amorphous silicon, polycrystalline silicon, or silicon nitride for partitioning, is conducive to reducing the NP junction interface on the silicon wafer surface and improving the passivation effect. And the back-contact battery structure of the present invention enables the formation of the back-contact battery structure without high-temperature laser processes and chemical etching processes, facilitating the simplification of the battery manufacturing process, reducing the production cost, improving the battery stability, and extending the service life of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0064] Figure 1 It is a schematic structural diagram of a specific embodiment of the back-contact battery of the present invention.

[0065] Figure 2 It is a flowchart of the etching-free manufacturing method of the back-contact battery of the present invention.

[0066] Figure 3 It is a process flowchart of a specific embodiment of the etching-free manufacturing method of the present invention.

[0067] DESCRIPTION OF REFERENCE NUMERALS

[0068] 1, silicon wafer; 2, intrinsic amorphous silicon layer; 3, first doping region; 4, second doping region; 5, co-doping region; 6, conductive film layer; 7, metal electrode. mask1, first hard mask; mask2, second hard mask; mask3, hard mask plate. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0069] In the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0070] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0071] The endpoints and any values of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values should be understood to include values close to these ranges. For numerical ranges, the endpoint values of each range, the endpoint values of each range and the individual point values, and the individual point values can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0072] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0073] In a first aspect, the present invention provides a method for manufacturing a back contact cell without etching, such as Figure 2 As shown, the following steps are included:

[0074] S1, provide silicon wafers;

[0075] S2, depositing an intrinsic amorphous silicon layer on the backlit side of the silicon wafer;

[0076] S3, a first doping region, a second doping region and a co-doping region between the first doping region and the second doping region are preset on the outer surface of the intrinsic amorphous silicon layer and are distributed alternately; one of the first doping region and the second doping region is N-type and the other is P-type; the doping source of the co-doping region includes a doping source A of the first doping region and a doping source B of the second doping region;

[0077] First, a first hard mask is used to cover the preset second doping region and the preset co-doping region of the backlight surface, and a first doped silicon with a target thickness is grown on the backlight surface to form a first doped region; wherein a distance D between the first hard mask and the intrinsic amorphous silicon layer is controlled to be greater than the target thickness of the first doped silicon;

[0078] S4. Then, use a second hard mask to cover the preset first doped region and the preset co-doped region on the backlight side, and grow a second doped silicon with a target thickness to form a second doped region; wherein, the distance d between the second hard mask and the intrinsic amorphous silicon layer is greater than the target thickness of the second doped silicon; meanwhile, a co-doped region is naturally formed in a partial region of the contact part between the first doped silicon and the second doped silicon;

[0079] S5. Set a hard mask plate on the outer surface of the co-doped region, and deposit a conductive film layer on the backlight side;

[0080] S6. Form metal electrodes on the outer surfaces of the first doped region and the second doped region respectively.

[0081] The preset first doped region, second doped region and co-doped region alternately distributed on the outer surface of the intrinsic amorphous silicon layer mean that three regions are divided at the positions where the first doped region, second doped region and co-doped region need to be set, which is convenient for subsequent steps. The doping source of the co-doped region includes doping source A of the first doped region and doping source B of the second doped region. It can be understood that when the first doped region is N-type, doping source A is phosphorus, and when the second doped region is P-type, doping source B is boron; conversely, when the first doped region is P-type, doping source A is boron, and when the second doped region is N-type, doping source B is phosphorus.

[0082] When growing the first doped silicon with a target thickness in S3 of the present invention, a first doped region with this target thickness will be formed, and doped silicon of doping source A will be formed in a part of the preset co-doped region close to the second doped region; when growing the second doped silicon with a target thickness in S4, a second doped region with this target thickness will be formed, and doped silicon of doping source B will be formed from the outside to the inside in a part of the preset co-doped region close to the second doped region and at least partially doped with doping source B on the doped silicon of doping source A, thereby forming a co-doped region.

[0083] In some preferred embodiments of the present invention, the ratio of D to the target thickness of the first doped silicon in S3 is 10 - 20000:1, more preferably 10 - 12000:1, and further preferably 10 - 10000:1. For example, it can be any value such as 10:1, 15:1, 20:1, 25:1, 30:1, 40:1, 50:1, 60:1, 70:1, 80:1, 90:1, 100:1, 110:1, 130:1, 150:1, 170:1, 200:1, 230:1, 250:1, 280:1, 300:1, 320:1, 350:1, 370:1, 400:1, 430:1, 450:1, 480:1, 500:1, 530:1, 550:1, 580:1, 600:1, 650:1, 700:1, 750:1, 800:1, 850:1, 890:1, 900:1, 920:1, 950:1, 970:1, 10000:1, 11000:1, 12000:1, 15000:1, 17000:1, 20000:1, etc., and the range between any two point values. By adopting this preferred scheme, it is more conducive to controlling the appropriate width of the co-doped region.

[0084] Preferably in the present invention, the ratio of d to the target thickness of the second doped silicon in S4 is 10 - 20000:1, more preferably 10 - 12000:1, and further preferably 10 - 10000:1. For example, it can be any value such as 10:1, 15:1, 20:1, 25:1, 30:1, 40:1, 50:1, 60:1, 70:1, 80:1, 90:1, 100:1, 110:1, 130:1, 150:1, 170:1, 200:1, 230:1, 250:1, 280:1, 300:1, 320:1, 350:1, 370:1, 400:1, 430:1, 450:1, 480:1, 500:1, 530:1, 550:1, 580:1, 600:1, 650:1, 700:1, 750:1, 800:1, 850:1, 890:1, 900:1, 920:1, 950:1, 970:1, 10000:1, 11000:1, 12000:1, 15000:1, 17000:1, 20000:1, etc., and the range between any two point values. By adopting this preferred scheme, it is more conducive to controlling the appropriate width of the co-doped region.

[0085] In some preferred embodiments of the present invention, the target thickness of the first doped silicon is controlled within 8 - 20 nm. For example, specifically, it can be any value such as 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, etc., and the range between any two point values.

[0086] Preferably, the target thickness of the second doped silicon in the present invention is controlled to be 8 - 20 nm, for example, specifically, it can be any value such as 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, etc., and the range between any two point values.

[0087] In the present invention, using the first doped silicon or the second doped silicon with a preferably appropriate thickness is more conducive to improving the battery efficiency.

[0088] In some preferred embodiments of the present invention, the width of the co-doped region is 5 - 150 μm, for example, specifically, it can be any value such as 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, etc., and the range between any two point values.

[0089] Preferably, in S3, D is maintained at 0.2 - 200 μm, for example, specifically, it can be any value such as 0.2 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm, 200 μm, etc., and the range between any two point values.

[0090] Preferably, in S4, d is maintained at 0.2 - 200 μm, for example, specifically, it can be any value such as 0.2 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm, 200 μm, etc., and the range between any two point values.

[0091] Preferably, in the present invention, when the width of the co-doped region needs to be 5 - 150 μm, D in S3 is controlled to be 0.2 - 200 μm, and d in S4 is controlled to be 0.2 - 200 μm. Adopting this preferred solution is more conducive to controlling the appropriate width of the co-doped region.

[0092] In some preferred embodiments of the present invention, the thickness of the co-doped region is 5 - 30 nm, for example, specifically it can be any value such as 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 12 nm, 14 nm, 15 nm, 17 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, etc. and the range between any two point values. Adopting a co-doped region with an appropriate thickness is more conducive to improving the battery efficiency.

[0093] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the doping concentration of doping source A in the co-doped region shows a decreasing distribution, and the doping concentration of doping source B shows an increasing distribution. Adopting a co-doped region with this doping distribution is more conducive to reducing the leakage current between the first doped region and the second doped region.

[0094] In some more preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the co-doped region is sequentially divided into a first region, a second intermediate region, and a third region. The second intermediate region includes an A-doped substrate and a concentrated double-doped region formed by at least partially doping B in the A-doped substrate. The A-doped substrate refers to a substrate doped with doping source A. The concentrated double-doped region is doped with AB simultaneously, which is more conducive to improving the insulation between the first doped region and the second doped region; in combination with the first region and the third region, it is more conducive to improving the insulation between the first doped region and the second doped region and reducing the leakage current between the first doped region and the second doped region.

[0095] It can be understood that the corresponding doping sources are concentratedly doped in both the first region and the third region, and the doping sources concentratedly doped in the two are different. There may also be a small amount of different doping sources doped in the first region and the third region. For example, when the first region is concentratedly doped with doping source A, it may optionally be doped with a small amount of doping source B.

[0096] In some preferred embodiments of the present invention, the doping source A contains phosphorus, the doping source B contains boron, the phosphorus doping concentration in the second intermediate region is 1e15 cm -3 -2e20 cm -3 、boron doping concentration is 1e15 cm -3 -2e20 cm -3 ,and the corresponding phosphorus doping concentrations in the first region and the third region are each independently 5e15 cm-3 -2e20 cm -3 、 more preferably 2e18 cm -3 -2e20 cm -3 ; the boron doping concentration is independently in the range of 5e15 cm -3 -2e20 cm -3 、 more preferably 2e18 cm -3 -2e20 cm -3 . By using the first region, the second intermediate region, and the third region with appropriate doping concentrations to form a co-doped region with a specific doping distribution, it is more conducive to improving the battery efficiency.

[0097] In some preferred embodiments of the present invention, in the diagonal direction starting from the inner end of the first doped region close to the silicon wafer in the co-doped region, the depth ratio of the concentrated double-doped region in the A-doped substrate is 25% - 80%, for example, specifically it can be any value such as 25%, 27%, 30%, 32%, 35%, 38%, 40%, 42%, 45%, 47%, 80% and the range between any two point values. By using a concentrated double-doped region with an appropriate depth ratio, it is more conducive to improving the insulation between the first doped region and the second doped region and reducing the leakage current between the first doped region and the second doped region.

[0098] In some preferred embodiments of the present invention, the depth of the concentrated double-doped region is 5 - 30 nm, for example, specifically it can be any value such as 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm and the range between any two point values. By using a concentrated double-doped region with an appropriate depth, it is more conducive to improving the insulation between the first doped region and the second doped region and reducing the leakage current between the first doped region and the second doped region.

[0099] In the present invention, the depth of the concentrated double-doped region can be adjusted according to the corresponding deposition time and deposition rate in the process of growing the first doped silicon in S3 and growing the second doped silicon in S4, as long as the target film layer with the required depth can be obtained.

[0100] In some preferred embodiments of the present invention, the ratio of the minimum doping concentration of dopant A in the co-doped region to the doping concentration of dopant A in the first doped region is 0.01 - 100:100, and the ratio of the minimum doping concentration of dopant B in the co-doped region to the doping concentration of dopant B in the second doped region is 0.01 - 100:100. By adopting this preferred scheme, the doping concentrations of the co-doped region, the first doped region, and the second doped region are balanced to form an appropriate concentration gradient, which is more conducive to improving the insulation between the first doped region and the second doped region and reducing the leakage current therebetween.

[0101] The ratio of the minimum doping concentration of dopant A in the co-doped region to the doping concentration of dopant A in the first doped region is 0.01 - 100:100. For example, it can specifically be any value such as 0.01:100, 0.05:100, 0.10:100, 0.20:100, 0.50:100, 0.7:100, 1.0:100, 2:100, 5:100, 7:100, 10:100, 15:100, 20:100, 30:100, 40:100, 50:100, 60:100, 70:100, 80:100, 90:100, 100:100, etc., as well as the range between any two point values. The selection range of the ratio of the minimum doping concentration of dopant B in the co-doped region to the doping concentration of dopant B in the second doped region being 0.01 - 100:100 is the same.

[0102] The minimum doping concentration of dopant A in the co-doped region refers to the minimum doping concentration of dopant A in the first region, the second intermediate region, and the third region; the same applies to the minimum doping concentration of dopant B in the co-doped region.

[0103] In some preferred embodiments of the present invention, the phosphorus doping concentration in the co-doped region is 1e15 cm -3 -2e20 cm -3 and the boron doping concentration is 1e15 cm -3 -2e20 cm -3 .

[0104] In some preferred embodiments of the present invention, the flow rates of the phosphorus sources corresponding to the growth processes of the first doped silicon and the second doped silicon are controlled to be 1 - 12 sccm, more preferably 8 - 12 sccm, and the flow rates of the boron sources are 1 - 12 sccm, more preferably 8 - 12 sccm.

[0105] Preferably in the present invention, in the required co-doped region, the phosphorus doping concentration is 1e15 cm -3 -2e20 cm -3 and the boron doping concentration is 1e15 cm -3 -2e20 cm -3When; during the growth processes of the first doped silicon and the second doped silicon respectively, control the flow rates of the phosphorus sources corresponding thereto to be 1-12 sccm, more preferably 8-12 sccm, and the flow rate of the boron source to be 1-12 sccm, more preferably 8-12 sccm. The flow rates of the phosphorus sources and the boron sources of the first doped silicon and the second doped silicon can be adjusted according to the doping concentration requirements of the co-doped region, which is more conducive to improving the insulation between the first doped region and the second doped region and reducing the leakage current between the first doped region and the second doped region.

[0106] In some preferred embodiments of the present invention, the growth of the first doped silicon in S3 and the growth of the second doped silicon in S4 are each independently formed by plasma enhanced chemical vapor deposition or hot wire chemical vapor deposition. More preferably, plasma enhanced chemical vapor deposition is used, which is beneficial to improving the film layer uniformity and more beneficial to improving the battery efficiency.

[0107] In some preferred embodiments of the present invention, the conditions for growing the first doped silicon in S3 include: introducing silane, ammonia, and the gas source corresponding to the doping source A, where the flow rate of the silane is 45-50 sccm.

[0108] Preferably in the present invention, the conditions for growing the second doped silicon in S4 include: introducing silane and the gas source corresponding to the doping source B, where the flow rate of the silane is 45-50 sccm.

[0109] In the present invention, one of the gas source corresponding to the doping source A and the gas source corresponding to the doping source B is a boron source and the other is a phosphorus source. Further preferably, the flow rate of the boron source is 1-12 sccm, more preferably 8-12 sccm, and the flow rate of the phosphorus source is 1-12 sccm, more preferably 8-12 sccm. The boron source can be, for example, borane, and the phosphorus source can be, for example, phosphine; in practice, the phosphorus source and the boron source can be introduced separately or introduced by hydrogen carrying the corresponding doping source.

[0110] In some preferred embodiments of the present invention, the thickness of the intrinsic amorphous silicon layer in S2 is 5-15 nm. Using an intrinsic amorphous silicon layer with an appropriate thickness is more conducive to taking into account the passivation effect and the series resistance, thereby improving the battery efficiency.

[0111] The method for depositing the intrinsic amorphous silicon in S2 of the present invention can, for example, adopt PECVD technology.

[0112] In some preferred embodiments of the present invention, the first doped silicon and the second doped silicon in S3 are each independently selected from doped amorphous silicon or microcrystalline silicon corresponding thereto, and more preferably amorphous silicon.

[0113] In some preferred embodiments of the present invention, the distance between the hard mask plate and the backlight surface of the silicon wafer in S5 is controlled within 0.2-200 μm, which is more conducive to controlling the width of the co-doped region.

[0114] In some preferred embodiments of the present invention, the thickness of the conductive film layer in S5 is 30-100 nm.

[0115] The conductive film layer of the present invention is preferably a transparent conductive film layer.

[0116] In some preferred embodiments of the present invention, the conductive film layer in S5 is deposited by magnetron sputtering.

[0117] Exemplarily, the magnetron sputtering deposition conditions of the conductive film layer include: a deposition temperature of 50-250° C. and a deposition time of 5-20 s.

[0118] In some preferred embodiments of the present invention, the thickness of the metal electrode in S6 is 3-20 μm.

[0119] In some preferred embodiments of the present invention, the silicon wafer in S1 is a silicon wafer with a light-receiving surface textured and a back-light surface polished.

[0120] In some preferred embodiments of the present invention, the etching-free manufacturing method of the back contact cell further includes the step of forming a passivation anti-reflection layer on the light-receiving surface of the silicon wafer in S1. The passivation anti-reflection layer may, for example, include a passivation layer and an anti-reflection layer arranged in sequence, which are prior arts and can be used in the present invention, and will not be described in detail here.

[0121] The size of the silicon wafer in S1 can be selected according to actual needs, for example, the size can be 156mm×156mm.

[0122] In a second aspect, the present invention provides a high-reliability back-contact battery, which is manufactured by the non-etching manufacturing method of the back-contact battery described in the first aspect. The back-contact battery manufactured by the non-etching manufacturing method of the back-contact battery of the present invention has improved reliability, stability and battery efficiency.

[0123] In a third aspect, the present invention provides a back-contact battery, comprising a silicon wafer, an intrinsic amorphous silicon layer being arranged on the backlight surface of the silicon wafer, a first doping region and a second doping region being arranged alternately outside the intrinsic amorphous silicon layer, and a co-doping region being arranged between the first doping region and the second doping region; one of the first doping region and the second doping region is N-type, and the other is P-type; the doping source of the co-doping region comprises a doping source A of the first doping region and a doping source B of the second doping region.

[0124] In the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the doping concentration of the doping source A in the co-doped region is distributed in a decreasing manner, and the doping concentration of the doping source B is distributed in an increasing manner.

[0125] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the co-doped region is sequentially divided into a first region, a second intermediate region, and a third region. The second intermediate region includes an A-doped substrate and a concentrated double-doped region formed by doping at least part of B in the A-doped substrate.

[0126] In some preferred embodiments of the present invention, the doping source A includes phosphorus, the doping source B includes boron, the phosphorus doping concentration in the second intermediate region is 1e15 cm -3 -2e20 cm -3 and the boron doping concentration is 1e15 cm -3 -2e20 cm -3 . The corresponding phosphorus doping concentrations in the first region and the third region are each independently 5e15 cm -3 -2e20 cm -3 , and the boron doping concentrations are each independently 5e15 cm -3 -2e20 cm -3 .

[0127] In some preferred embodiments of the present invention, in the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the depth ratio of the concentrated double-doped region in the A-doped substrate is 25%-80%.

[0128] In some preferred embodiments of the present invention, the depth of the concentrated double-doped region is 5-30 nm.

[0129] In some preferred embodiments of the present invention, the ratio of the minimum doping concentration of the doping source A in the co-doped region to the doping concentration of the doping source A in the first doped region is 0.01-100:100.

[0130] Preferably in the present invention, the ratio of the minimum doping concentration of the doping source B in the co-doped region to the doping concentration of the doping source B in the second doped region is 0.01-100:100.

[0131] In some preferred embodiments of the present invention, the phosphorus doping concentration in the co-doped region is 1e15 cm -3 -2e20 cm -3 , preferably 1e15 cm -3 -5e19 cm -3 ; and its boron doping concentration is 1e15 cm -3 -2e20 cm -3 .

[0132] In some preferred embodiments of the present invention, the ratio of the width of the co-doped region to the width of the first doped region or the second doped region is 0.01 - 0.5:1, more preferably 0.01 - 0.20:1, and further preferably 0.10 - 0.20:1.

[0133] In some preferred embodiments of the present invention, the ratio of the thickness of the co-doped region to the thickness of the first doped region or the second doped region is 0.5 - 1.4:1, further preferably 0.8 - 1.4:1, and more preferably 0.8 - 1.2:1.

[0134] In some preferred embodiments of the present invention, the width of the co-doped region is 5 - 150 μm.

[0135] In some preferred embodiments of the present invention, the thickness of the co-doped region is 5 - 30 nm.

[0136] In some preferred embodiments of the present invention, the thicknesses of the first doped region and the second doped region are each independently 8 - 20 nm.

[0137] In some preferred embodiments of the present invention, the widths of the first doped region and the second doped region are each independently 100 - 600 μm.

[0138] In some preferred embodiments of the present invention, one of the doping source A of the first doped region and the doping source B of the second doped region is phosphorus, and the other is boron, wherein the phosphorus doping concentration is 2e18 cm -3 -2e20 cm -3 and the boron doping concentration is 2e18 cm -3 -2e20 cm -3 .

[0139] In some preferred embodiments of the present invention, the first doped region and the second doped region are each independently selected from doped amorphous silicon or microcrystalline silicon corresponding to the doping.

[0140] In some preferred embodiments of the present invention, the thickness of the intrinsic amorphous silicon layer is 5 - 15 nm.

[0141] In some preferred embodiments of the present invention, the ratio of the thickness of the intrinsic amorphous silicon layer to the thickness of the first doped region or the second doped region is 0.5 - 2:1.

[0142] In some preferred embodiments of the present invention, in the width direction, the first doped region and the co-doped region are in contact with each other and the co-doped region and the second doped region are in contact with each other and are continuously distributed as a whole.

[0143] In some preferred embodiments of the present invention, the back contact cell further comprises a light-receiving surface passivation anti-reflection layer disposed on the light-receiving surface of the silicon wafer. The light-receiving surface passivation anti-reflection layer may be, for example, a passivation layer and an anti-reflection layer disposed in sequence. The passivation layer and the anti-reflection layer may refer to the front structure of the prior art, and both may be used in the present invention, which is prior art and will not be described in detail herein.

[0144] In some preferred embodiments of the present invention, the light-receiving surface of the silicon substrate is a textured surface, and the backlight surface is a polished surface.

[0145] In some preferred embodiments of the present invention, the back contact battery also includes a conductive film layer and a metal electrode sequentially arranged on the outer surfaces of the first doping region and the second doping region, an isolation trench is arranged between the conductive film layer arranged on the outer surface of the first doping region and the conductive film layer arranged on the outer surface of the second doping region, and at least a portion of the isolation trench is located on the outer surface of the co-doped region.

[0146] The back contact cell of the present invention can be made by the manufacturing method as described in the first aspect, or obtained by other existing processes. The back contact cell of the present invention is conducive to achieving higher photoelectric conversion efficiency, helping to reduce the cost of photovoltaic power generation, while improving cell stability, reliability and cell efficiency, and has broad market demand and good application prospects. And the back contact cell structure of the present invention can form a back contact cell structure without the need for high-temperature laser process and chemical etching process.

[0147] In a fourth aspect, the present invention provides a battery assembly, which includes the high reliability back contact battery described in the second aspect, or includes the back contact battery described in the third aspect. The battery assembly may include any combination of battery modules including the specific back contact battery of the present invention.

[0148] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0149] Example 1

[0150] A back contact battery having a structure as follows Figure 1 As shown, through Figure 3 The non-etching manufacturing method shown is prepared, which specifically includes the following steps:

[0151] S1, providing a silicon wafer 1, performing texturing and cleaning on the silicon wafer 1, so that the light-receiving surface of the silicon wafer 1 is texturized, the backlight surface is polished, and a passivation anti-reflection layer is formed on the light-receiving surface of the silicon wafer 1;

[0152] S2, depositing an intrinsic amorphous silicon layer 2 with a thickness of 7 nm on the backlight surface of the silicon wafer 1 by PECVD;

[0153] S3. On the outer surface of the intrinsic amorphous silicon layer 2, first doping regions 3 (N-type amorphous silicon), second doping regions 4 (P-type amorphous silicon) are preset to be alternately distributed, and a co-doping region 5 is arranged between the first doping region 3 and the second doping region 4; the doping source of the co-doping region 5 includes doping source A of the first doping region 3, i.e., phosphorus, and doping source B of the second doping region 4, i.e., boron.

[0154] First, use the first hard mask mask1 to block the preset second doping region 4 and the preset co-doping region 5 on the backlight surface, and grow the first doped silicon with a thickness of 10 nm on the backlight surface by PECVD to form the first doping region 3; wherein, the distance D between the first hard mask mask1 and the intrinsic amorphous silicon layer 2 is controlled to be maintained at 0.12 mm; during the growth process of the first doped silicon, the gas concentration is: the flow rate of silane is 50 sccm, and the flow rate of the mixed gas of hydrogen carrying phosphine (the volume fraction of hydrogen is 98%) is 100 sccm.

[0155] S4. Then, use the second hard mask mask2 to block the preset first doping region 3 and the preset co-doping region 5 on the backlight surface, and grow the second doped silicon with a thickness of 10 nm by PECVD to form the second doping region 4; wherein, the distance d between the second hard mask mask2 and the intrinsic amorphous silicon layer 2 is maintained at 0.12 mm; meanwhile, the co-doping region 5 is naturally formed in the contact part region of the first doped silicon and the second doped silicon; the width of the co-doping region 5 is 70 μm, and the thickness is 12 nm. The ratio of the thickness of the co-doping region 5 to the thickness of the first doping region 3 and the second doping region 4 is 1.2:1. During the growth process of the second doped silicon, the gas concentration is: the flow rate of silane is 50 sccm, and the flow rate of the mixed gas of hydrogen carrying diborane B2H6 (the volume fraction of hydrogen is 98%) is 150 sccm. The phosphorus doping concentration in the first doping region 3 is 8e19 cm -3 , and the boron doping concentration in the second doping region 4 is 2e19 cm -3 . The width of the first doping region 3 is 430 μm, and the width of the second doping region 4 is 500 μm. After conversion, the ratios of the width of the co-doping region 5 to the width of the first doping region 3 and the second doping region 4 are 0.16:1 and 0.14:1, respectively.

[0156] Detected by secondary ion mass spectrometry (SIMS), in the diagonal direction of the co-doping region 5 starting from the inner end of the first doping region 3 close to the silicon wafer 1 (such as Figure 1(in the direction of the arrow shown), in the co-doped region 5, the doping concentration of dopant A decreases and the doping concentration of dopant B increases. Accordingly, the co-doped region 5 is sequentially divided into a first region, a second intermediate region, and a third region. The second intermediate region includes an A-doped substrate and a concentrated double-doped region formed by partially doping B in the A-doped substrate. The depth ratio of the concentrated double-doped region in the A-doped substrate is 50%; the depth of the concentrated double-doped region is 12 nm. The phosphorus doping concentration in the second intermediate region is 5e15 cm -3 -8e19 cm -3 and the boron doping concentration is 5e15 cm -3 -2e19 cm -3 . The phosphorus doping concentration in the first region is 8e18 cm -3 -8e19 cm -3 and the boron doping concentration is 5e15 cm -3 -2e18 cm -3 ; the phosphorus doping concentration in the third region is 5e15 cm -3 -2e18 cm -3 and the boron doping concentration is 5e18 cm -3 -2e19 cm -3 .

[0157] S5. A hard mask plate mask3 is provided on the outer surface of the co-doped region 5, and a transparent conductive film layer 6 with a thickness of 60 nm is deposited on the backlight surface by magnetron sputtering; the distance between the hard mask plate mask3 and the backlight surface of the silicon wafer 1 is controlled at 50 μm; the deposition temperature is 150 °C and the deposition time is 10 s;

[0158] S6. Copper-silver paste is printed on the outer surfaces of the first doped region 3 and the second doped region 4 respectively to form a metal electrode 7 with a thickness of 10 μm.

[0159] Example 2

[0160] This is carried out with reference to Example 1, except that the width of the co-doped region is adjusted to 120 μm, and D in S3 needs to be controlled at 200 μm and d in S4 needs to be controlled at 200 μm to meet this condition. After conversion, the ratio of D in S3 to the target thickness of the first doped silicon is 20000:1, and the ratio of d in S4 to the target thickness of the second doped silicon is 20000:1. After conversion, the ratios of the width of the co-doped region to the widths of the first doped region and the second doped region are 0.28:1 and 0.24:1 respectively.

[0161] In this example, the phosphorus doping concentration in the second intermediate region is 5e15 cm -3 -8e19 cm -3 and the boron doping concentration is 5e15 cm -3 -2e19 cm-3 In the first region and the third region, the corresponding phosphorus doping concentration is 5e15 cm -3 -8e19 cm -3 , and the boron doping concentration is 5e15 cm -3 -2e19 cm -3 .

[0162] Example 3

[0163] Performed with reference to Example 1, except that the target thickness of the first doped silicon is adjusted to 15 nm; the target thickness of the second doped silicon is adjusted to 15 nm, and the thickness of the co-doped region obtained is 20 nm. After conversion, the ratio of D to the target thickness of the first doped silicon in S3 is 8000:1, and the ratio of d to the target thickness of the second doped silicon in S4 is 8000:1.

[0164] Example 4

[0165] Performed with reference to Example 1, except that in the diagonal direction starting from the inner end of the first doped region close to the silicon wafer in the co-doped region, the depth of the concentrated double-doped region is adjusted so that the depth ratio of the concentrated double-doped region in the A-doped substrate is 70%. The process parameters that need to be adjusted to meet this condition are: adjusting D in S3 to remain at 200 μm, and adjusting d in S4 to remain at 100 μm.

[0166] Example 5

[0167] Performed with reference to Example 1, except that the phosphorus doping concentration in the co-doped region is adjusted to 5e15 cm -3 -8e19 cm -3 and the minimum phosphorus doping concentration is 5e15 cm -3 . The process parameters for adjusting the preparation of the first doped silicon in the corresponding preparation are: the silane flow rate is 50 sccm, and the flow rate of the mixed gas of hydrogen carrying phosphine (hydrogen volume ratio 98%) is 50 sccm. After corresponding detection, the phosphorus doping concentration in the second intermediate region in this example is 5e15 cm -3 -5e19 cm -3 , the boron doping concentration is 5e15 cm -3 -2e19 cm -3 , and the corresponding phosphorus doping concentrations in the first region and the third region are both 8e18 cm -3 -8e19 cm -3 , and the boron doping concentrations are both 2e18 cm -3 -2e19 cm -3 .

[0168] Comparative Example 1

[0169] The method is carried out with reference to Example 1, except that a conventional interdigital structure is adopted instead of a co-doped region, and a conventional preparation process is adopted for this: after forming the intrinsic amorphous silicon layer, an N-type amorphous silicon layer and a mask layer are also formed, and the intrinsic amorphous silicon layer and the N-type amorphous silicon layer form a first semiconductor layer; then a first etching opening is performed on the obtained back surface to etch away the first semiconductor layer and its corresponding mask layer to form a second semiconductor opening region; then cleaning is performed to remove the mask layer and the first semiconductor layer remaining in the second semiconductor opening region; then a second semiconductor layer is deposited on the obtained back surface (i.e., the intrinsic amorphous silicon layer and the P-type amorphous silicon layer formed in sequence), and then a second etching opening is performed on part of the second semiconductor layer on the back surface of the silicon wafer to form a first semiconductor opening region arranged at intervals with the second semiconductor opening region; then a conductive film layer is deposited to fully cover the obtained back surface; and a third etching opening is performed on part of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; and then metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0170] Comparative Example 2

[0171] The process is carried out with reference to Example 1, except that the co-doped region is replaced by an undoped intrinsic amorphous silicon layer; the process that needs to be modified accordingly to meet this condition is:

[0172] In steps S3 and S4, a polymer mask layer is applied instead of a corresponding hard mask for masking. A polymer mask layer is applied to the preset second doping region and co-doping region, an N-type doped amorphous silicon layer, i.e., the first doping region, is deposited, and the polymer mask layer is removed. A polymer mask layer is then applied to the N-type doped amorphous silicon layer and the co-doping region, a P-type doped amorphous silicon layer, i.e., the second doping region, is deposited, and the polymer mask layer is removed; a polymer mask layer is then applied to the first doping region and the second doping region to prepare an intrinsic amorphous silicon layer in the region between the first doping region and the second doping region.

[0173] Comparative Example 3

[0174] The process is carried out with reference to Example 1, except that the intrinsic amorphous silicon layer is replaced by a tunnel oxide layer with a thickness of 1.5 nm.

[0175] Test Case

[0176] The back-contact batteries obtained from the above-mentioned examples and comparative examples were subjected to performance tests, and the results are shown in Table 1. The measurement method for the production line equipment input cost is: the production line investment cost corresponding to an annual production of 1 GW of batteries. The measurement method for the production cycle is the production cycle of the silicon wafer from input to the finished battery. Among them, the production line equipment input costs and production cycles of each example and Comparative Examples 2-3 were respectively converted with Comparative Example 1 as the reference benchmark. The data of Comparative Example 1 was the normalization benchmark of 1.0, and other examples were converted based on Comparative Example 1. For example, the production line equipment input cost of Example 1 / the production line equipment input cost of Comparative Example 1 was 0.8. In addition, the test method for the production yield of the battery is: in a batch, the ratio of the number of qualified back-contact batteries produced in step S6 to the number of silicon wafers input in step S1. The reverse leakage current was measured according to GB / T 6495.

[0177] Table 1

[0178]

[0179] From the above results, it can be seen that compared with the comparative examples, by adopting the embodiment scheme of the present invention, the use of high-temperature lasers and chemical etching is avoided, thereby reducing the damage to the battery and environmental pollution, significantly improving the production yield, significantly reducing the production cost, while improving the reliability and service life of the battery, and obtaining good battery efficiency.

[0180] Furthermore, according to Example 1 and Examples 2-5, it can be seen that by adopting the preferred scheme of the present invention, it is more conducive to improving the production yield, significantly reducing the production cost, while improving the reliability and service life of the battery, and obtaining good battery efficiency.

[0181] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited thereto. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, including any other suitable combination of each technical feature. These simple modifications and combinations should also be regarded as the content disclosed by the present invention and fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a back contact battery without etching, characterized in that: It includes the following steps: S1. Provide a silicon wafer; S2. Deposit an intrinsic amorphous silicon layer on the backlight side of the silicon wafer; S3. Preset first doping regions, second doping regions and a co-doping region between the first doping region and the second doping region which are alternately distributed on the outer surface of the intrinsic amorphous silicon layer; one of the first doping region and the second doping region is N-type and the other is P-type; the doping source of the co-doping region includes doping source A of the first doping region and doping source B of the second doping region; First, use a first hard mask to block the preset second doping region and the preset co-doping region on the backlight side, and grow first doped silicon with a target thickness on the backlight side to form a first doping region; wherein, control the distance D between the first hard mask and the intrinsic amorphous silicon layer to be greater than the target thickness of the first doped silicon; S4. Then use a second hard mask to block the preset first doping region and the preset co-doping region on the backlight side, and grow second doped silicon with a target thickness to form a second doping region; wherein, the distance d between the second hard mask and the intrinsic amorphous silicon layer is greater than the target thickness of the second doped silicon; meanwhile, a co-doping region is naturally formed in the contact part region of the first doped silicon and the second doped silicon; In S3, the ratio of D to the target thickness of the first doped silicon is 10 - 20000:1, in S4, the ratio of d to the target thickness of the second doped silicon is 10 - 20000:1, the target thickness of the first doped silicon is controlled to be 8 - 20 nm; the target thickness of the second doped silicon is controlled to be 8 - 20 nm; S5. Set a hard mask plate on the outer surface of the co-doping region, and deposit a conductive film layer on the backlight side; S6. Form metal electrodes on the outer surfaces of the first doping region and the second doping region respectively.

2. The method for manufacturing a back contact battery without etching according to claim 1, characterized in that: The width of the co-doping region is 5 - 150 μm.

3. The method for manufacturing a back contact battery without etching according to claim 1, characterized in that: Control D in S3 to be maintained at 0.2 - 200 μm, and d in S4 to be maintained at 0.2 - 200 μm.

4. The method for manufacturing a back contact cell without etching according to any one of claims 1 to 3, characterized in that: The thickness of the co-doping region is 5 - 30 nm.

5. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: In the diagonal direction of the co-doping region starting from the inner end of the first doping region close to the silicon wafer, the doping concentration of doping source A in the co-doping region shows a decreasing distribution, and the doping concentration of doping source B shows an increasing distribution.

6. The method for manufacturing a back contact cell without etching according to claim 5, characterized in that: In the diagonal direction of the co-doping region starting from the inner end of the first doping region close to the silicon wafer, the co-doping region is successively divided into a first region, a second intermediate region, and a third region, and the second intermediate region includes an A-doped substrate and a concentrated double-doped region formed by at least partially doping B in the A-doped substrate.

7. The method for manufacturing a back contact cell without etching according to claim 6, characterized in that: The doping source A contains phosphorus, and the doping source B contains boron. The phosphorus doping concentration in the second intermediate region is in the range of 1e15 cm -3 - 2e20 cm -3 , and the boron doping concentration is in the range of 1e15 cm -3 - 2e20 cm -3 . The corresponding phosphorus doping concentrations in the first region and the third region are each independently in the range of 5e15 cm -3 - 2e20 cm -3 , and the boron doping concentrations are each independently in the range of 5e15 cm -3 - 2e20 cm -3 .

8. The method for manufacturing a back contact cell without etching according to claim 6, characterized in that: In the diagonal direction of the co-doping region starting from the inner end of the first doping region close to the silicon wafer, the depth ratio of the concentrated double-doped region in the A-doped substrate is 25% - 80%; and / or, the depth of the concentrated double-doped region is 5 - 30 nm.

9. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: The ratio of the minimum doping concentration of doping source A in the co-doping region to the doping concentration of doping source A in the first doping region is 0.01 - 100:100, and the ratio of the minimum doping concentration of doping source B in the co-doping region to the doping concentration of doping source B in the second doping region is 0.01 - 100:

100.

10. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: One of the doping sources A for the first doping region and the doping source B for the second doping region is phosphorus, and the other is boron. Among them, the phosphorus doping concentration is in the range of 2e18 cm -3 -2e20 cm -3 , and the boron doping concentration is in the range of 2e18 cm -3 -2e20 cm -3 .

11. The method for manufacturing a back contact cell without etching according to any one of claims 7 and 9 to 10, characterized in that: The phosphorus doping concentration in the co-doped region is from 1e15 cm -3 -2e20 cm -3 , the boron doping concentration is from 1e15 cm -3 -2e20 cm -3 ; and / or, Control the flow rate of the phosphorus source corresponding to the growth process of the first doped silicon and the second doped silicon to be 1 - 12 sccm, and the flow rate of the boron source to be 1 - 12 sccm.

12. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: The first doped silicon grown in S3 and the second doped silicon grown in S4 are each independently formed by plasma enhanced chemical vapor deposition or hot wire chemical vapor deposition; and / or, The conditions for growing the first doped silicon in S3 include: introducing silane and the doping source A corresponding to the gas source, where the flow rate of silane is 45-50sccm; the conditions for growing the second doped silicon in S4 include: introducing silane and the doping source B corresponding to the gas source, where the flow rate of silane is 45-50sccm; wherein, the doping source A corresponding to the gas source and the doping source B corresponding to the gas source, one of which is a boron source and the other is a phosphorus source, the flow rate of the boron source is 1-12sccm, and the flow rate of the phosphorus source is 1-12sccm.

13. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: The thickness of the intrinsic amorphous silicon layer in S2 is 5-15 nm; and / or, The first doped silicon and the second doped silicon in S3 are independently selected from correspondingly doped amorphous silicon or microcrystalline silicon; and / or, The thickness of the conductive film layer in S5 is 30-100 nm; and / or, In S5, the conductive film layer is deposited by magnetron sputtering; and / or, The thickness of the metal electrode in S6 is 3-20 μm.

14. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: In S5, the distance between the hard mask and the backlight surface of the silicon wafer is controlled at 0.2-200μm.

15. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: The silicon wafer in S1 is a silicon wafer with a textured light-receiving surface and a polished backlight surface.

16. The method for manufacturing a back contact cell without etching according to claim 1, characterized in that: The etching-free manufacturing method of the back contact cell also includes the step of forming a passivation anti-reflection layer on the light-receiving surface of the silicon wafer in S1.

17. A back-contact battery, characterized in that, It is obtained by the etching-free manufacturing method of the back-contact battery as described in claim 1; the back-contact battery includes a silicon wafer, an intrinsic amorphous silicon layer is provided on the backlight side of the silicon wafer, and a first doping region and a second doping region are alternately distributed outside the intrinsic amorphous silicon layer, and a co-doping region is provided between the first doping region and the second doping region; one of the first doping region and the second doping region is N-type and the other is P-type; the doping source of the co-doping region includes doping source A of the first doping region and doping source B of the second doping region; in the diagonal direction of the co-doping region starting from the inner end close to the silicon wafer of the first doping region, the doping concentration of doping source A in the co-doping region decreases and the doping concentration of doping source B increases; the phosphorus doping concentration in the co-doping region is 1e15 cm -3 -2e20 cm -3 , and the boron doping concentration is 1e15 cm -3 -2e20 cm -3 .

18. The back contact battery according to claim 17, wherein, In the diagonal direction of the co-doped region with the inner end of the first doped region close to the silicon wafer as the starting point, the co-doped region is divided into a first region, a second middle region, and a third region in sequence. The second middle region includes an A-doped substrate and a concentrated double-doped region formed by at least partially doping B in the A-doped substrate.

19. The back contact battery according to claim 18, characterized in that, The doping source A contains phosphorus, and the doping source B contains boron. The phosphorus doping concentration in the second intermediate region is in the range of 1e15 cm -3 -2e20 cm -3 , and the boron doping concentration is in the range of 1e15 cm -3 -2e20 cm -3 . The corresponding phosphorus doping concentrations in the first region and the third region are each independently in the range of 5e15 cm -3 -2e20 cm -3 , and the boron doping concentrations are each independently in the range of 5e15 cm -3 -2e20 cm -3 .

20. The back-contact battery according to claim 18, wherein, In the diagonal direction of the co-doped region starting from the inner end of the first doped region close to the silicon wafer, the depth of the concentrated double-doped region in the A-doped substrate accounts for 25%-80%; and / or the depth of the concentrated double-doped region is 5-30nm.

21. The back-contact battery according to any one of claims 17-20, characterized in that, The ratio of the minimum doping concentration of doping source A in the co-doping region to the doping concentration of doping source A in the first doping region is 0.01-100:100, and the ratio of the minimum doping concentration of doping source B in the co-doping region to the doping concentration of doping source B in the second doping region is 0.01-100:

100.

22. The back contact battery according to claim 17, wherein, The ratio of the width of the co-doped region to the width of the first doped region or the second doped region is 0.01-0.5:1; and / or, The ratio of the thickness of the co-doped region to the thickness of the first doped region or the second doped region is 0.5-1.4:

1.

23. The back-contact battery according to claim 17 or 22, characterized in that, The width of the co-doped region is 5-150 μm; and / or, The thickness of the co-doped region is 5-30 nm; and / or, The thickness of the first doping region and the second doping region are independently 8-20 nm; and / or, The widths of the first doping region and the second doping region are independently 100-600 μm; and / or, One of the doping sources A for the first doping region and the doping source B for the second doping region is phosphorus, and the other is boron, where the phosphorus doping concentration is in the range of 2e18 cm -3 -2e20 cm -3 , and the boron doping concentration is in the range of 2e18 cm -3 -2e20 cm -3 ; and / or, The first doped region and the second doped region are independently selected from correspondingly doped amorphous silicon or microcrystalline silicon.

24. The back-contact battery according to claim 17, wherein The thickness of the intrinsic amorphous silicon layer is 5-15 nm; and / or the ratio of the thickness of the intrinsic amorphous silicon layer to the thickness of the first doping region or the second doping region is 0.5-2:

1.

25. The back-contact battery according to claim 17, wherein The back contact cell also includes at least one of the following structures: Structure 1: In the width direction, the first doped region and the co-doped region are in contact with each other and the co-doped region and the second doped region are in contact with each other, and the whole is continuously distributed. Structure 2: The back contact cell further includes a light-receiving surface passivation and antireflection layer provided on the light-receiving surface of the silicon wafer. Structure 3: The light-receiving surface of the silicon substrate is a textured surface, and the backlight surface is a polished surface. Structure 4: The back contact cell further includes a conductive film layer and a metal electrode sequentially provided on the outer surfaces of the first doped region and the second doped region. An isolation groove is provided between the conductive film layer provided on the outer surface of the first doped region and the conductive film layer provided on the outer surface of the second doped region, and at least a part of the isolation groove is located on the outer surface of the co-doped region.

26. A battery assembly, characterized in that, It includes the back contact cell according to any one of claims 17-25.

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