Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises a substrate, an insulating layer, a first organic part, a shielding structure and a first optical unit, the insulating layer is disposed on the substrate and includes a first opening. The first organic portion is disposed in the first opening of the insulating layer. The shielding structure is arranged on the insulating layer and comprises a retaining wall and a first opening. The first optical unit is arranged in the first opening of the shielding structure. The retaining wall of the shielding structure is overlapped with the first opening of the insulating layer. The reliability of the electronic device provided by the invention can be improved.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to a flexible display device. Background Art

[0002] When a flexible electronic device is bent, the external anti-reflection layer is prone to peeling. If the anti-reflection layer is formed inside the flexible electronic device (for example, to form a filter unit or an anti-reflection organic layer) to improve the above phenomenon, the inorganic film layer in the flexible electronic device will easily produce cracks extending in one direction due to the influence of the bending stress after the flexible electronic device is bent, which reduces the reliability of the flexible electronic device. Furthermore, the display surface of the flexible electronic device is prone to problems such as color mixing and / or contrast due to repeated bending and / or process deviation. Summary of the invention

[0003] Some embodiments of the present disclosure are directed to an electronic device having relatively good reliability and / or relatively good display effect.

[0004] According to some embodiments of the present disclosure, an electronic device is provided, which includes a substrate, an insulating layer, a first organic part, a shielding structure, and a first optical unit. The insulating layer is disposed on the substrate and includes a first opening. The first organic part is disposed in the first opening of the insulating layer. The shielding structure is disposed on the insulating layer and includes a retaining wall and the first opening. The first optical unit is disposed in the first opening of the shielding structure. The retaining wall of the shielding structure overlaps with the first opening of the insulating layer.

[0005] In order to make the above features and advantages of the present disclosure more obvious and understandable, embodiments are given below with reference to the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A A partial top view of an electronic device according to an embodiment of the present disclosure;

[0007] Figure 1B Based on Figure 1A A partial cross-sectional schematic diagram of the first embodiment of the section line AA';

[0008] Figure 2 Based on Figure 1A A partial cross-sectional schematic diagram of the second embodiment of the section line AA';

[0009] Figure 3A Based on Figure 1A A partial cross-sectional schematic diagram of the third embodiment of the section line AA';

[0010] Figure 3B Based on Figure 1A A partial cross-sectional schematic diagram of the fourth embodiment of the section line AA';

[0011] Figure 4 Based on Figure 1A A partial cross-sectional schematic diagram of the fifth embodiment of the invention taken along the section line AA';

[0012] Figure 5 Based on Figure 1A A partial cross-sectional schematic diagram of the sixth embodiment taken along the section line AA';

[0013] Figure 6 Show Figure 5 A partial cross-sectional schematic diagram of an embodiment of a peripheral area of ​​an electronic device 10f;

[0014] Fig. 7A A three-dimensional schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0015] Figure 7B Based on Fig. 7A A partially enlarged top view of a region R1 of an embodiment;

[0016] Fig. 8A Show Fig. 7A A three-dimensional schematic diagram of an electronic device after being folded;

[0017] Figure 8B Based on Fig. 8A A partially enlarged top view of an embodiment in a region R2;

[0018] Fig. 9A A partial top view schematically shows the arrangement relationship between the sensing structure and the first opening of the insulating layer in the electronic device according to an embodiment of the present disclosure;

[0019] Fig. 9B It is a partial top view schematic diagram of the arrangement relationship between the sensing structure, the first opening of the insulating layer and the optical unit in the electronic device of the first embodiment of the present disclosure;

[0020] Fig. 10A A partial top view schematically showing the arrangement relationship between the sensing structure, the first opening of the insulating layer and the optical unit in the electronic device according to the second embodiment of the present disclosure;

[0021] Fig. 10B A partial top view schematically showing the arrangement relationship between the sensing structure, the first opening of the insulating layer and the optical unit in the electronic device according to the third embodiment of the present disclosure;

[0022] Fig. 10C It is a partial top view schematically showing the disposition relationship among the sensing structure, the first opening of the insulating layer and the optical unit in the electronic device of the fourth embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0024] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to facilitate the understanding of the readers and the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not intended to limit the scope of the present disclosure.

[0025] Certain words are used throughout the specification and the claims that follow to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, the words "include", "contain", "have" and the like are open-ended words, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "include", "contain" and / or "have" are used in the description of the present disclosure, they specify the existence of corresponding features, regions, steps, operations and / or components, but do not exclude the existence of one or more corresponding features, regions, steps, operations and / or components.

[0026] Directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. In the accompanying drawings, each figure shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0027] When a corresponding component (such as a film layer or region) is referred to as being "on another component", it may be directly on the other component, or other components may exist between the two. On the other hand, when a component is referred to as being "directly on another component", there is no component between the two unless otherwise specified in the specification. In addition, when a component is referred to as being "on another component", the two have a top-down relationship in the top view direction, and the component may be above or below the other component, and this top-down relationship depends on the orientation of the device.

[0028] The terms "equal to" or "same as", "substantially" or "approximately" are generally interpreted as within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.

[0029] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the elements. They do not imply or represent any previous ordinal numbers of the element (or elements), nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make the element with a certain name clearly distinguishable from another element with the same name. The claims and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the claim.

[0030] It should be noted that the following embodiments may replace, reorganize, or mix features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features between embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0031] The electrical connection or electrical connection described in the present disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there is a switch, diode, capacitor, inductor, other suitable components, or a combination of the above components between the endpoints of the components on the two circuits, but it is not limited to these.

[0032] In the present disclosure, the thickness, length, width and area can be measured by an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but it is not limited to this. In addition, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0033] Figure 1A is a partial top view of an electronic device according to an embodiment of the present disclosure, and Figure 1B in accordance with Figure 1A A schematic partial cross-sectional view of the first embodiment along the section line AA'.

[0034] Please also refer to Figure 1A as well as Figure 1B, the electronic device 10a of this embodiment includes a substrate SB, an insulating layer PV1, a first organic part Or1, a shielding structure SS and a first optical unit CF1. In this embodiment, the electronic device 10a may be a display device including a touch function, but the present disclosure is not limited thereto. In some embodiments, the electronic device 10a may also include a buffer layer BF, a circuit structure CIL, a flat layer PL1, a light emitting structure LE, an encapsulation layer EL, a sensing structure SE, a shielding structure SS, an optical unit CF, a flat layer PL2 and a cover plate CP, but the present disclosure is not limited thereto. In some embodiments, the sensing structure SE can be used to sense a user's finger, a stylus and suitable external objects, but the present disclosure is not limited thereto.

[0035] The substrate SB may include a flexible substrate, wherein the material of the substrate SB may include plastic. For example, the substrate SB may include polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), or other suitable materials or a combination of the above materials.

[0036] The buffer layer BF is, for example, disposed on the substrate SB. The buffer layer BF may, for example, have relatively good bonding properties with a film layer subsequently formed thereon, but the present disclosure is not limited thereto. The material of the buffer layer BF may, for example, be an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials). In some embodiments, the buffer layer BF may be a single-layer structure or a multi-layer structure, but the present disclosure is not limited thereto.

[0037] The circuit structure CIL is, for example, disposed on the substrate SB. In the present embodiment, the circuit structure CIL is disposed on the buffer layer BF and may include an insulating layer PV1 and a transistor TFT, but the present disclosure is not limited thereto.

[0038] The insulating layer PV1 is, for example, disposed on the substrate SB. In the present embodiment, the insulating layer PV1 may be a multi-layer structure, and may be used to separate different conductive layers in the transistor TFT. In detail, the insulating layer PV1 may include an insulating layer GI, an insulating layer IL1, and an insulating layer IL2, wherein the insulating layer GI is disposed between the semiconductor layer SE and the gate G of the transistor TFT, the insulating layer IL1 is disposed between the source S (or drain D) and the gate G of the transistor TFT, and the insulating layer IL2 covers the source S and the drain D of the transistor TFT. The material of the insulating layer PV1 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto.

[0039] In the present embodiment, the insulating layer PV1 includes a plurality of first openings PV1_OP1a. The profile of the first opening PV1_OP1a of the insulating layer PV1 is, for example, defined by the side surface of the insulating layer IL2, the side surface of the insulating layer IL1, the side surface of the insulating layer GI, and the top surface of the buffer layer BF, wherein the side surface of the insulating layer IL2 is connected to the side surface of the insulating layer IL1, the side surface of the insulating layer IL1 is connected to the side surface of the insulating layer GI, and the side surface of the insulating layer GI is connected to the top surface of the buffer layer BF, but the present disclosure is not limited thereto. In some embodiments, the profile of the first opening PV1_OP1a of the insulating layer PV1 is in the shape of an inverted trapezoid in the cross-sectional view of the electronic device 10a, but the present disclosure is not limited thereto. In the present embodiment, the first opening PV1_OP1a of the insulating layer PV1 has a width w1 in the direction sd, wherein the width w1 can be defined as the width of the lower bottom of the first opening PV1_OP1a of the insulating layer PV1, but the present disclosure is not limited thereto. The above-mentioned direction sd is, for example, parallel to the surface (XY plane) of the substrate SB defined by the direction X and the direction Y, and can be, for example, parallel to the line connecting the centers CF_C (including the centers CF1_C, CF2_C, and CF3_C) of adjacent optical units CF (including the first optical unit CF1, the second optical unit CF2, and the third optical unit CF3). For example, the direction sd can be parallel to the line L connecting the center CF2_C of the second optical unit CF2 and the center CF3_C of the third optical unit CF3, but the present disclosure is not limited thereto.

[0040] The profile of the first opening PV1_OP1a of the insulating layer PV1 can be defined by the sidewall PV1_SS and the bottom surface PV1_BS, for example. When the width w1 is defined as the width of the bottom of the first opening PV1_OP1a of the insulating layer PV1, it is also the width of the bottom surface PV1_BS in the direction sd, but the present disclosure is not limited thereto. In other embodiments, when the width w1 is defined as the width of the upper bottom of the first opening PV1_OP1a of the insulating layer PV1, it is the width of the upper bottom surface PV1_TS (at Figure 1B In other words, the width, length and distance are measured on the same basis regardless of the top view or the cross-section view.

[0041] The center CF_C of the optical unit CF is, for example, defined by a minimum virtual rectangle SV that can enclose the optical unit CF, wherein the intersection of two diagonal lines SV_D1 and SV_D2 of the minimum virtual rectangle SV is the center CF_C of the optical pattern CF. Figure 1AThe intersection of the diagonal lines SV_D1 and SV_D2 of the minimum virtual rectangle SV enclosing the second optical unit CF2 is the center CF2_C of the second optical unit CF2. In some embodiments, the width w1 of the first opening PV1_OP1a of the insulating layer PV1 satisfies the following relationship: 0.1 μm≤w1≤15 μm.

[0042] In the present embodiment, the first opening PV1_OP1a may have a length L1 in the extension direction dOP1 thereof, wherein the extension direction dOP1 of the first opening PV1_OP1a is the length L1 of the smallest first opening PV1_OP1a. Figure 1A In some embodiments, the extension direction dOP1 of the first opening PV1_OP1a may be parallel to the direction X, but the present disclosure is not limited thereto. In some embodiments, the length L1 and the width w1 of the first opening PV1_OP1a of the insulating layer PV1 may satisfy the following relationship: L1 / w1>2, wherein the length L1 of the first opening PV1_OP1a is the minimum length of the first opening PV1_OP1a in the Figure 1A The minimum width of the first opening PV1_OP1a is defined by the long side direction in the top view shown in FIG. Figure 1A For example, the ratio of the length L1 to the width w1 of the first opening PV1_OP1a of the insulating layer PV1 may be greater than 2, greater than 10, or greater than 1000, but the present disclosure is not limited thereto. In addition, when the opening in the top view is not in the form of a long straight line, the opening may be surrounded by a minimum virtual rectangle, and the extension direction may be defined by the long side direction of the enclosed minimum virtual rectangle, or the length, i.e., the width, of the opening may be defined by the minimum virtual rectangle.

[0043] In addition, in the present embodiment, the insulating layer PV1 may further include a second opening PV1_OP2a adjacent to the first opening PV1_OP1a, wherein the profile of the second opening PV1_OP2a of the insulating layer PV1 may be the same as or similar to the profile of the first opening PV1_OP1a of the insulating layer PV1, but the present disclosure is not limited thereto. In other embodiments, the profile of the second opening PV1_OP2a of the insulating layer PV1 may be different from the profile of the first opening PV1_OP1a of the insulating layer PV1.

[0044] Based on this, when one or more insulating layers in the insulating layer PV1 are cracked due to bending or other factors, the first opening PV1_OP1a and / or the second opening PV1_OP2a of the insulating layer PV1 can block the extension path of the crack, thereby reducing the possibility of the transistor TFT being invaded by external moisture.

[0045] The transistor TFT may, for example, include the aforementioned gate G, source S, drain D, and semiconductor layer SE, but the present disclosure is not limited thereto. The gate G partially overlaps with the semiconductor layer SE in the top-view direction n of the substrate SB, for example, wherein the region where the semiconductor layer SE overlaps with the gate G may be regarded as a channel region CH, and the semiconductor layer SE may have a source region and a drain region located on opposite sides of the channel region CH. The source S and the drain D are, for example, separated from each other, and each is electrically connected to the semiconductor layer SE. In some embodiments, the material of the semiconductor layer SE may include amorphous silicon, low-temperature polycrystalline silicon (LTPS), metal oxide, other suitable materials or combinations thereof (e.g., a combination of low-temperature polycrystalline silicon and metal oxide, i.e., low-temperature polycrystalline silicon oxide (LTPO)), wherein the metal oxide may include indium gallium zinc oxide (IGZO). In the present embodiment, the material of the semiconductor layer SE includes low-temperature polycrystalline silicon, but the present disclosure is not limited thereto. In the present embodiment, the source electrode S and the drain electrode D can be electrically connected to the source region and the drain region of the semiconductor layer SE through the hole VS and the hole VD penetrating the insulating layer IL1 and the insulating layer GI, respectively, but the present disclosure is not limited thereto. The transistor TFT of the present embodiment is, for example, a top-gate thin film transistor. However, although the present embodiment takes the top-gate thin film transistor as an example, the present disclosure is not limited thereto.

[0046] The planar layer PL1 is, for example, disposed on the substrate SB and partially covers the circuit structure CIL. From another perspective, the planar layer PL1 may, for example, include an opening PL1_OP that exposes a portion of the drain D of the transistor TFT. The material of the planar layer PL1 may, for example, be an organic material (e.g., polytetrafluoroethylene, polyimide, polyparaxylene, benzocyclobutene or other suitable materials), but the present disclosure is not limited thereto. In the present embodiment, the planar layer PL1 may have a relatively flat top surface so that the film layer subsequently formed thereon has a relatively good yield. In the present embodiment, the planar layer PL1 includes a first organic portion Or1. The first organic portion Or1 is, for example, disposed in a first opening PV1_OP1a of the insulating layer PV1.

[0047] In this embodiment, by disposing the first organic portion Or1 in the first opening PV1_OP1a of the insulating layer PV1, a relatively flat top surface can be provided above the first opening PV1_OP1a, and the first opening PV1_OP1a filled with the first organic portion Or1 can have a more stable structure, so that the film layer subsequently formed thereon has a relatively good yield.

[0048] The light emitting structure LE is, for example, disposed on the planar layer PL1. In some embodiments, the light emitting structure LE includes a first electrode E1, a light emitting layer L, a second electrode E2, and a pixel definition layer PDL.

[0049] The first electrode E1 is, for example, disposed on the planar layer PL1, and is, for example, electrically connected to the drain electrode D of the transistor TFT through the opening PL1_OP of the planar layer PL1. In some embodiments, the first electrode E1 may be used as an anode of the light-emitting unit LE and / or a pixel electrode of the transistor TFT, but the disclosure is not limited thereto. The material of the first electrode E1 may include metal, metal oxide, other suitable materials or combinations thereof, but the disclosure is not limited thereto.

[0050] The light-emitting layer L is, for example, disposed on the first electrode E1. In some embodiments, the light-emitting layer L may include, for example, a suitable structure and material thereof. For example, the light-emitting layer L may include an organic material, but the present disclosure is not limited thereto.

[0051] The second electrode E2 is, for example, disposed on the first electrode E1. In some embodiments, the second electrode E2 can be used as a cathode of the light emitting unit LE, but the disclosure is not limited thereto. The material of the second electrode E2 can include metal, metal oxide, other suitable materials or combinations thereof, but the disclosure is not limited thereto.

[0052] The pixel definition layer PDL is, for example, disposed on the flat layer PL1. In the present embodiment, the pixel definition layer PDL partially covers the first electrode E1. From another perspective, the pixel definition layer PDL includes, for example, an opening PDL_OP exposing a portion of the first electrode E1, wherein the light emitting layer L may, for example, be disposed in the opening PDL_OP, but the present disclosure is not limited thereto. The pixel definition layer PDL may, for example, include a transparent material or a light shielding material, but the present disclosure is not limited thereto. In the present embodiment, the opening PDL_OP of the pixel definition layer PDL does not overlap with the first opening PV1_OP1a of the insulating layer PV1, which can reduce the possibility of optical problems such as uneven brightness caused by the first opening PV1_OP1a of the insulating layer PV1.

[0053] The encapsulation layer EL is, for example, disposed on the light emitting structure LE. In the present embodiment, the encapsulation layer EL covers the light emitting structure LE. In some embodiments, the encapsulation layer EL may be a single-layer structure or a multi-layer structure, but the present disclosure is not limited thereto. The material of the encapsulation layer EL may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material (e.g., polytetrafluoroethylene, polyimide, polyparaxylene, benzocyclobutene, or other suitable materials), or a combination thereof, but the present disclosure is not limited thereto. For example, the encapsulation layer EL may be a stacked structure of inorganic material / organic material / inorganic material, but the present disclosure is not limited thereto. In the present embodiment, the encapsulation layer EL may have a relatively flat top surface similar to the flat layer PL, so that the film layer subsequently formed thereon has a relatively good yield.

[0054] The sensing structure SE is, for example, disposed on the insulating layer PV1 and partially overlaps the first opening PV1_OP1a of the insulating layer PV1. In the present embodiment, the sensing structure SE is disposed on the encapsulation layer EL and includes a first unit U1, a second unit U2 and a bridge portion BR. The first unit U1 and the second unit U2 are, for example, disposed on the encapsulation layer EL. In the present embodiment, the first unit U1, the second unit U2 and the bridge portion BR may be, for example, the sensing electrode Rx of the sensing structure SE. In detail, the conductive layer in the sensing structure SE may include the sensing electrode Rx and the driving electrode Tx, wherein the sensing electrode Rx and the driving electrode Tx may, for example, have a rhombus and / or metal grid shape in the top view direction of the substrate SB1, but the present disclosure is not limited thereto. The insulating layer PV2 is, for example, disposed on the encapsulation layer EL and has an opening PV2_OP exposing the first unit U1 and the second unit U2. The bridge portion BR is, for example, disposed on the insulating layer PV2 and connected to the first unit U1 and the second unit U2. In the present embodiment, the bridge portion BR belongs to a different layer from the first unit U1 and the second unit U2, and can be electrically connected to the first unit U1 and the second unit U2 through the opening PV2_OP penetrating the insulating layer PV2. The insulating layer PV3 is, for example, disposed on the insulating layer PV2 and covers the bridge portion BR. In some embodiments, the material of the sensing electrode Rx and the driving electrode Tx may include a transparent conductive material or a metal material, and the material of the insulating layer PV2 and the insulating layer PV3 may include an inorganic material (for example: silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto.

[0055] The shielding structure SS is, for example, disposed on the insulating layer PV1, and includes, for example, a retaining wall WA and a first opening SS_OP1. In the present embodiment, the shielding structure SS is disposed on the sensing structure SE, wherein the first opening SS_OP1 of the shielding structure SS can expose a portion of the insulating layer PV3 of the sensing structure SE. In some embodiments, the shielding structure SS can further include a second opening SS_OP2 and a third opening SS_OP3, wherein the second opening SS_OP2 and the third opening SS_OP3 of the shielding structure SS can also expose a portion of the insulating layer PV3 of the sensing structure SE. The retaining wall WA is, for example, disposed between the first opening SS_OP1 and the second opening SS_OP2 of the shielding structure SS and / or between the second opening SS_OP2 and the third opening SS_OP3 of the shielding structure SS. In some embodiments, the retaining wall WA may include a multilayer structure. In the present embodiment, the retaining wall WA may include a stacked structure formed by a first sub-layer WA1 and a second sub-layer WA2, but the present disclosure is not limited thereto. The retaining wall WA may, for example, have a width w2 in the direction sd, wherein the width w2 may, for example, be defined as the maximum width of one of the first sub-layer WA1 and the second sub-layer WA2 in the direction sd, but the present disclosure is not limited thereto. The above-mentioned direction sd is, for example, parallel to the surface (XY plane) of the substrate SB defined by the directions X and Y. In the present embodiment, the width w2 of the retaining wall WA is the width of the first sub-layer WA1 in the direction sd, but the present disclosure is not limited thereto. In some embodiments, the shielding structure SS may include a light-shielding material. For example, the material of the shielding structure SS may, for example, include a black resin or a metal material with low reflectivity, but the present disclosure is not limited thereto.

[0056] In some embodiments, the width w2 of the retaining wall WA of the shielding structure SS satisfies the following relationship: 8μm≤w2≤15μm. In the present embodiment, the width w2 of the retaining wall WA of the shielding structure SS may be greater than or equal to the width w1 of the first opening PV1_OP1a of the insulating layer PV1. That is, the width w2 of the retaining wall WA of the shielding structure SS and the width w1 of the first opening PV1_OP1a of the insulating layer PV1 satisfy the following relationship: w1≤w2. In some embodiments, the width w2 of the retaining wall WA of the shielding structure SS and the width w1 of the first opening PV1_OP1a of the insulating layer PV1 satisfy the following relationship: 1≤w2 / w1≤150.

[0057] In the present embodiment, the retaining wall WA of the shielding structure SS overlaps with the first opening PV1_OP1a of the insulating layer PV1. In detail, the portion (first sub-layer WA1) with the maximum width in the retaining wall WA of the shielding structure SS overlaps with the first opening PV1_OP1a of the insulating layer PV1 in the top-down direction n of the substrate SB. Based on this, when the electronic device 10a is in operation, the uneven brightness, dark lines and / or other optical defects that may be generated due to the formation of the first opening PV1_OP1a of the insulating layer PV1 can be shielded by the shielding structure SS, so that the electronic device 10a of the present embodiment can have a good display effect. In addition, in the present embodiment, the retaining wall WA of the shielding structure SS also overlaps with the second opening PV1_OP2a of the insulating layer PV1, which can also achieve the above-mentioned effect. It is worth noting that although the present embodiment shows that a shielding structure SS overlaps with a corresponding first opening PV1_OP1a of the insulating layer PV1, the present disclosure is not limited to this.

[0058] In the present embodiment, a distance d1 may be provided between a center line c1 of the first opening SS_OP1 of the shielding structure SS and a center line c2 of the first opening PV1_OP1a of the insulating layer PV1, wherein the center line c1 of the first opening SS_OP1 of the shielding structure SS is a line passing through the center of the lower bottom of the first opening SS_OP1, and the center line c2 of the first opening PV1_OP1a of the insulating layer PV1 is a line passing through the center of the lower bottom of the first opening PV1_OP1a. Alternatively, in the cross-sectional view, the center line c1 of the first opening SS_OP1 of the shielding structure SS is a line passing through the center of the minimum width of the first opening SS_OP1, and the center line c2 of the first opening PV1_OP1a of the insulating layer PV1 is a line passing through the center of the minimum width of the first opening PV1_OP1a. In some embodiments, the distance d1 satisfies the following relationship: 0μm≤d1≤10μm.

[0059] The optical unit CF is disposed on the sensing structure SE, for example. In some embodiments, the optical unit CF may have functions such as light filtering, wavelength conversion, and / or other optical functions, which are not limited in this disclosure. In this embodiment, the optical unit CF includes a first optical unit CF1. The first optical unit CF1 is disposed in the first opening SS_OP1 of the shielding structure SS, for example. In some embodiments, the first optical unit CF1 may include a red light filtering pattern, a green light filtering pattern, or a blue light filtering pattern, which are not limited in this disclosure. In this embodiment, the optical unit CF further includes a second optical unit CF2 and a third optical unit CF3. The second optical unit CF2 is disposed in the second opening SS_OP2 of the shielding structure SS, and the third optical unit CF3 is disposed in the third opening SS_OP3 of the shielding structure SS, for example. In some embodiments, the optical functions included in the first optical unit CF1, the second optical unit CF2, and the third optical unit CF3 may be different from each other, which are not limited in this disclosure.

[0060] In this embodiment, the first optical unit CF1, the second optical unit CF2, and the third optical unit CF3 may partially overlap the first sub-layer WA1 of the barrier wall WA, and the second sub-layer WA2 of the barrier wall WA may partially overlap the first optical unit CF1, the second optical unit CF2, and the third optical unit CF3, which are not limited in this disclosure.

[0061] In some embodiments, the width w3 of the first optical unit CF1 may satisfy the following relationship: 10 μm ≤ w3 ≤ 20 μm, which are not limited in this disclosure.

[0062] In this embodiment, the width w3 of the first optical unit CF1 is greater than or equal to the width w1 of the first opening PV1_OP1a of the insulating layer PV1. Specifically, the first optical unit CF1 may have a width w3 in the direction sd, where the width w3 is the width of the portion of the first optical unit CF1 that does not overlap the shielding structure SS in the top view direction n of the substrate SB. In some embodiments, the width w3 of the first optical unit CF1 and the width w1 of the first opening PV1_OP1 of the insulating layer PV1 satisfy the following relationship: 1 < w3 / w1 ≤ 200. When the width w3 and the width w1 satisfy the above relationship, the shielding structure SS may have a relatively good antireflection effect. Specifically, when w3 / w1 ≤ 1, the width w1 of the first opening PV1_OP1a of the insulating layer PV1 will be greater than the width w3 of the first optical unit CF1, which causes a recessed phenomenon in the first optical unit CF1 and / or the shielding structure SS and affects the antireflection effect of the shielding structure SS. In addition, when w3 / w1 > 200, the width w1 of the first opening PV1_OP1a of the insulating layer PV1 will be too small, and it may not have the effect of reducing stress (such as bending stress).

[0063] In some embodiments, in the top view of the electronic device 10a, the angle ω between the line connecting the centers of adjacent optical units located on both sides of the first opening PV1_OP1a of the insulating layer PV1 (for example, the line L connecting the center CF2_C of the second optical unit CF2 and the center CF3_C of the third optical unit CF3) and the extension direction dOP1 of the first opening PV1_OP1a is greater than or equal to 30° and less than or equal to 50°, but the present disclosure is not limited to this. It is worth noting that the above-mentioned angle ω is based on the acute angle between the line L connecting the center CF2_C of the second optical unit CF2 and the center CF3_C of the third optical unit CF3 and the extension direction dOP1 of the first opening PV1_OP1a as an example.

[0064] The planar layer PL2 is disposed on the insulating layer PV3 and overlaps the shielding structure SS and the optical unit CF. The material of the planar layer PL2 may be an organic material (eg, polytetrafluoroethylene, polyimide, polyparaxylene, benzocyclobutene or other suitable materials), but the disclosure is not limited thereto.

[0065] The cover plate CP may be disposed on the flat layer PL2, for example. The material of the cover plate CP may include glass, plastic, or a combination thereof. In the present embodiment, the material of the cover plate CP includes plastic, glass, or a combination thereof, but the present disclosure is not limited thereto.

[0066] In the present embodiment, the shielding structure SS can be used as an anti-reflection layer of the electronic device 10a. Based on this, compared with the structure in which the anti-reflection layer is attached to the cover plate CP, the electronic device 10a of the present embodiment can reduce the stress of the electronic device 10a when it is bent by setting the shielding structure SS on the insulating layer PV3 inside the electronic device 10a, and can improve the reliability of the electronic device 10a. In detail, when the electronic device 10a is bent, the design of setting the shielding structure SS inside the electronic device 10a and the design of the first opening PV1_OP1a of the insulating layer PV1 can reduce the stress of the electronic device 10a when it is bent, and because the shielding structure SS is not easy to peel off from the insulating layer PV3, it can improve the reliability of the electronic device 10a.

[0067] The electronic device 10a of the present embodiment can be formed by, for example, performing the following process, but it should be noted that the manufacturing method of the electronic device disclosed in the present invention is not limited thereto.

[0068] Step (1): Provide a substrate SB. The material of the substrate SB can be, for example, as described in the above embodiment, and will not be described in detail herein.

[0069] Step (2) is performed: forming the circuit structure CIL and the first opening PV1_OP1a of the insulating layer PV1.

[0070] In some embodiments, the circuit structure CIL may be formed on the substrate SB by performing the following steps, but the present disclosure is not limited thereto.

[0071] Step (a): forming a buffer layer BF on the substrate SB. The buffer layer BF may be formed on the substrate SB by, for example, chemical vapor deposition or other suitable processes, but the present disclosure is not limited thereto.

[0072] Step (b): forming a semiconductor layer SE on the buffer layer BF. The semiconductor layer SE may be formed by, for example, first forming a semiconductor material layer (not shown) on the buffer layer BF using chemical vapor deposition or other suitable processes, and then performing a patterning process on the semiconductor material layer, but the present disclosure is not limited thereto.

[0073] Step (c): forming an insulating layer GI, a gate G and an insulating layer IL1 on the buffer layer BF, wherein the insulating layer GI is, for example, disposed on the buffer layer BF, the gate G is, for example, disposed on the insulating layer GI, and the insulating layer IL1 is, for example, disposed on the insulating layer GI and, for example, overlaps the gate G.

[0074] The method for forming the insulating layer GI can, for example, be by first forming a first insulating material layer (not shown) on the buffer layer BF using chemical vapor deposition or other suitable processes, and then patterning the first insulating material layer to form an opening that exposes a portion of the semiconductor layer SE, but the present disclosure is not limited to this.

[0075] The gate G may be formed by, for example, first forming a gate material layer (not shown) on the insulating layer GI using physical vapor deposition, metal chemical vapor deposition or other suitable processes, and then patterning the gate material layer, but the present disclosure is not limited thereto.

[0076] The insulating layer IL1 may be formed by, for example, first forming a second insulating material layer (not shown) on the first insulating material layer using chemical vapor deposition or other suitable processes, and then patterning the first insulating material layer and the second insulating material layer to form openings VS and openings VD that expose a portion of the semiconductor layer SE.

[0077] Step (d): forming a source electrode S and a drain electrode D on the insulating layer IL1. The source electrode S and the drain electrode D may be formed by, for example, first forming a source electrode and a drain electrode material layer (not shown) on the insulating layer IL1 by physical vapor deposition, metal chemical vapor deposition or other suitable processes, and then patterning the source electrode and the drain electrode material layer, but the present disclosure is not limited thereto.

[0078] Step (e): forming an insulating layer IL2 on the source electrode S and a drain electrode D on the insulating layer IL1. The insulating layer IL2 may be formed by, for example, chemical vapor deposition or other suitable processes, but the present disclosure is not limited thereto. It is worth noting that the insulating layer GI, the insulating layer IL1 and the insulating layer IL2 are formed into the insulating layer PV1.

[0079] After completing the above step (2), step (3) is performed: forming a light emitting structure LE on the insulating layer IL2. The light emitting structure LE can be formed by a suitable process depending on the material included in the light emitting layer L. For example, the light emitting structure LE can be formed by performing an evaporation process or by a mass transfer method, but the present disclosure is not limited thereto. It is worth noting that before forming the light emitting structure LE, a planar layer PL1 can be formed by, for example, a coating process to overlap the circuit structure CIL, wherein the planar layer PL1 includes a first organic portion Or1, and the first organic portion Or1 is formed in the first opening PV1_OP1a of the insulating layer PV1.

[0080] Step (4) is performed: forming an encapsulation layer EL on the light emitting structure LE. The encapsulation layer EL may be formed by, for example, chemical vapor deposition, coating or other suitable processes, but the present disclosure is not limited thereto.

[0081] Step (5) is performed: forming a sensing structure SE on the flat layer PL2. The sensing electrode Rx and the driving electrode Tx in the sensing structure SE can be formed, for example, by using a sputtering method or other suitable processes, but the present disclosure is not limited thereto. In addition, the insulating layer PV2 disposed on the bridge portion BR of the driving electrode Tx and the sensing electrode Rx and the insulating layer PV3 disposed on the first unit U1 and the second unit U2 of the sensing electrode Rx can be formed, for example, by using a chemical vapor deposition method or other suitable processes, but the present disclosure is not limited thereto.

[0082] Step (6) is performed: forming a shielding structure SS on the sensing structure SE, wherein the shielding structure SS includes an opening SS_OP1 and an opening SS_OP2. The shielding structure SS can be formed by, for example, a printing process, a coating process or other suitable processes, but the present disclosure is not limited thereto.

[0083] Step (7) is performed: forming an optical unit CF on the sensing structure SE, wherein the first optical unit CF1 and the second optical unit CF2 in the optical unit CF are respectively disposed in the opening SS_OP1 and the opening SS_OP2 of the shielding structure SS. The optical unit CF can be formed, for example, by using a printing process, a coating process or other suitable processes, but the present disclosure is not limited thereto.

[0084] Step (8) is performed: forming a planar layer PL2 on the shielding structure SS and the optical unit CF. The planar layer PL2 may be formed by, for example, a coating process or other suitable processes, but the present disclosure is not limited thereto.

[0085] Step (9) is performed: forming a cover plate CP on the flat layer PL2.

[0086] At this point, the manufacturing of the electronic device 10 a of this embodiment is completed, but the method of manufacturing the electronic device 10 a disclosed in this disclosure is not limited thereto.

[0087] Figure 2 in accordance with Figure 1A The partial cross-sectional diagram of the second embodiment of the invention is shown along the section line AA'. It should be noted that: Figure 2 The embodiments can be used Figure 1A to Figure 1B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0088] Please refer to Figure 2 The main differences between the electronic device 10b of this embodiment and the electronic device 10a described above are: (1) the shielding structure SS' is formed by at least two optical units in the optical unit CF; (2) the depth T1 of the first opening PV1_OP1b and the depth T2 of the second opening PV1_OP2b in the insulating layer PV1 are different. In this embodiment, the different depths T1 of the first opening PV1_OP1b and T2 of the second opening PV1_OP2b can be used to block different cracks caused by stress caused by bending the electronic device 10b.

[0089] In the present embodiment, the shielding structure SS' is formed by the overlapping portions of the first optical unit CF1, the second optical unit CF2 and the third optical unit CF3 in the top-view direction n of the substrate SB, so that the combination of the shielding structure SS' and the optical unit CF can have a light shielding and / or anti-reflection effect. The shielding structure SS' may, for example, also have a width w2 in the direction sd, wherein the width w2 may, for example, be defined as the maximum width of the overlapping portions of at least two optical units in the direction sd, but the present disclosure is not limited thereto. In addition, in the present embodiment, the shielding structure SS' also overlaps with the first opening PV1_OP1b of the insulating layer PV1. In detail, the shielding structure SS' (the overlapping portion of at least two optical units) overlaps with the first opening PV1_OP1b of the insulating layer PV1 in the top-view direction n of the substrate SB.

[0090] Therefore, when the electronic device 10b operates, uneven brightness, dark lines and / or other optical defects that may be generated by the formation of the first opening PV1_OP1b of the insulating layer PV1 can be shielded by the shielding structure SS′, so that the electronic device 10b of this embodiment can have a good display effect.

[0091] In the present embodiment, the profile of the second opening PV1_OP2b of the insulating layer PV1 is, for example, defined by the side surface of the insulating layer IL2, the side surface of the insulating layer IL1, and the top surface of the insulating layer GI, wherein the side surface of the insulating layer IL2 is connected to the side surface of the insulating layer IL1, and the side surface of the insulating layer IL1 is connected to the top surface of the insulating layer GI. From another perspective, the second opening PV1_OP2b of the insulating layer PV1 exposes a portion of the insulating layer GI, and the first opening PV1_OP1b of the insulating layer PV1 exposes a portion of the buffer layer BF. Based on this, in the present embodiment, the depth T1 of the first opening PV1_OP1b in the insulating layer PV1 may be greater than the depth T2 of the second opening PV1_OP2b, but the present disclosure is not limited thereto.

[0092] Figure 3A Based on Figure 1A It should be noted that, Figure 3A The embodiments can be used separately Figure 1A to Figure 1B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0093] Please refer to Figure 3A The main differences between the electronic device 10c of this embodiment and the above-mentioned electronic device 10a are: (1) the circuit structure CIL' further includes a transistor TFT'; (2) the profile of the first opening PV1_OP1c of the insulating layer PV1' is in the form of two overlapping inverted trapezoids in the cross-sectional view of the electronic device 10c.

[0094] In this embodiment, the circuit structure CIL′ includes an insulating layer PV1 ′, the transistor TFT and the transistor TFT′ of the above-mentioned embodiment, a connecting electrode CE1 , a connecting electrode CE2 , and a planar layer PL3 .

[0095] Compared with the insulating layer PV1 of the above embodiment, the insulating layer PV1' further includes an insulating layer IL3 and an insulating layer IL4. In the present embodiment, the insulating layer IL3 is disposed between the insulating layer IL1 and the insulating layer IL2 and overlaps the gate G' of the transistor TFT', and the insulating layer IL4 is disposed on the insulating layer IL2 and partially overlaps the semiconductor layer SE'. The materials of the insulating layer IL3 and the insulating layer IL4 may be, for example, inorganic materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto.

[0096] The transistor TFT' may, for example, include a gate G', a source S', a drain D' and a semiconductor layer SE', but the present disclosure is not limited thereto. The gate G', for example, partially overlaps with the semiconductor layer SE' in the top-view direction n of the substrate SB. The source S' and the drain D' are, for example, separated from each other and are each electrically connected to the semiconductor layer SE'. In some embodiments, the material of the semiconductor layer SE' may include amorphous silicon, low-temperature polycrystalline silicon (LTPS), metal oxide, other suitable materials or a combination thereof. In the present embodiment, the material of the semiconductor layer SE' of the transistor TFT' includes metal oxide, and the material of the semiconductor layer SE of the transistor TFT includes low-temperature polycrystalline silicon, but the present disclosure is not limited thereto. In addition, in the present embodiment, the transistor TFT' is a bottom-gate transistor structure, and the transistor TFT is a top-gate transistor structure, but the present disclosure is not limited thereto. In the present embodiment, the source S' and the drain D' may each be electrically connected to the semiconductor layer SE' through a hole VS' and a hole VD' that penetrate the insulating layer IL4, but the present disclosure is not limited thereto.

[0097] The connection electrode CE1 is, for example, disposed on the insulating layer IL1, and may, for example, belong to the same layer as the gate electrode G' of the transistor TFT'. In the present embodiment, the connection electrode CE1 may be electrically connected to the drain electrode D of the transistor TFT through the opening IL3_OP of the insulating layer IL3, but the present disclosure is not limited thereto. Although not shown in the drawings, the connection electrode CE1 may, for example, electrically connect the transistor TFT to the transistor TFT adjacent thereto.

[0098] The connection electrode CE2 is, for example, disposed on the planar layer PL1 , and may be electrically connected to the drain electrode D′ of the transistor TFT′ through the opening PL1_OP of the planar layer PL1 , but the disclosure is not limited thereto.

[0099] The planar layer PL3 is, for example, disposed on the planar layer PL1 and partially overlaps the connection electrode CE2. From another perspective, the planar layer PL3 may, for example, include an opening PL3_OP exposing a portion of the connection electrode CE2, so that the first electrode E1 of the light-emitting unit LE can be electrically connected to the connection electrode CE2 through the opening PL3_OP, thereby electrically connecting the light-emitting unit LE to the transistor TFT'. The material of the planar layer PL3 may, for example, be an organic material (e.g., polytetrafluoroethylene, polyimide, polyparaxylene, benzocyclobutene or other suitable materials), but the present disclosure is not limited thereto.

[0100] In the present embodiment, the first opening PV1_OP1c of the insulating layer PV1′ is formed by performing two patterning processes. Therefore, the first opening PV1_OP1c may present an overlapped state between the pattern opening Tr1 and the pattern opening Tr2 in the cross-sectional view of the electronic device 10c, wherein the pattern opening Tr1 is located between the pattern opening Tr2 and the substrate SB.

[0101] In detail, the profile of the first opening PV1_OP1c of the insulating layer PV1' is, for example, defined by the side surface of the insulating layer IL4, the side surface of the insulating layer IL2, a portion of the bottom surface of the insulating layer IL2, the side surface of the insulating layer IL3, the side surface of the insulating layer IL1, the side surface of the insulating layer GI and the top surface of the buffer layer BF, wherein the side surface of the insulating layer IL4 is connected to the side surface of the insulating layer IL2, the side surface of the insulating layer IL2 is connected to a portion of the bottom surface of the insulating layer IL2, a portion of the bottom surface of the insulating layer IL2 is connected to the side surface of the insulating layer IL3, the side surface of the insulating layer IL3 is connected to the side surface of the insulating layer IL1, the side surface of the insulating layer IL1 is connected to the side surface of the insulating layer GI, and the side surface of the insulating layer GI is connected to the top surface of the buffer layer BF, but the present disclosure is not limited to this. In addition, in the present embodiment, the insulating layer PV1' may further include a second opening PV1_OP2c adjacent to the first opening PV1_OP1c, wherein the profile of the second opening PV1_OP2c of the insulating layer PV1' may be the same as or similar to the profile of the first opening PV1_OP1c of the insulating layer PV1', but the present disclosure is not limited thereto. In some embodiments, the profile of the second opening PV1_OP2c and the profile of the first opening PV1_OP1c may include an arc profile, which may be used to reduce the possibility of cracks forming in the second opening PV1_OP2c and / or the first opening PV1_OP1c during the formation process.

[0102] In some embodiments, the depth T3 of the first opening PV1_OP1c in the insulating layer PV1 may satisfy the following relationship: 0.5 μm≤T3≤5 μm, but the disclosure is not limited thereto.

[0103] From another perspective, in the cross-sectional view of the electronic device 10c, the first opening PV1_OP1c of the insulating layer PV1' includes a first width w11, a second width w12, and a third width w13 in the direction sd, wherein the third width w13 is between the first width w11 and the second width w12, and the second width w12 is closer to the substrate SB than the first width w11. In detail, the first width w11 may be defined as, for example, the width of the bottom Tr2_B of the graphic opening Tr2 (e.g., the distance between adjacent insulating layers IL2 in the direction sd), the second width w12 may be defined as, for example, the width of the bottom Tr1_B of the graphic opening Tr1 (e.g., the distance between adjacent insulating layers GI in the direction sd), and the third width w13 may be defined as, for example, the width of the top Tr1_T of the graphic opening Tr1 (e.g., the distance between adjacent insulating layers IL3 in the direction sd). Based on this, in the present embodiment, the third width w13 may be greater than the first width w11, and the third width w13 may be greater than the second width w12. In addition, in some embodiments, the first width w11 , the second width w12 , and the third width w13 of the first opening PV1_OP1c of the insulating layer PV1 ′ also satisfy the following relationships: 0.1 μm≤w11≤15 μm, 0.1 μm≤w12≤15 μm, 0.1 μm≤w13≤15 μm.

[0104] In the present embodiment, by designing the first width w11, the second width w12 and the third width w13 of the first opening PV1_OP1c of the insulating layer PV1' to comply with the above relationship, the electronic device 10c can be easily bent, reduce the generation of cracks and have a relatively large component layout space. In contrast, when the first width w11, the second width w12 and the third width w13 of the first opening PV1_OP1c of the insulating layer PV1' are less than 0.1 μm, the first opening PV1_OP1c may be difficult to form; and when the first width w11, the second width w12 and the third width w13 of the first opening PV1_OP1c of the insulating layer PV1' are greater than 15 μm, the component layout space of the electronic device 10c will be reduced.

[0105] Figure 3B Based on Figure 1A It should be noted that, Figure 3B The embodiments can be used Figure 3A The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0106] Please refer to Figure 3BThe main differences between the electronic device 10d of this embodiment and the above-mentioned electronic device 10c are: (1) the first organic portion Or1' includes a curved surface; (2) part of the conductive wires in the electronic device 10d cross the first opening PV1_OP1d of the insulating layer PV1'.

[0107] In this embodiment, after forming the insulating layer IL1 and before forming the gate G' of the transistor TFT', the organic part Or11 is filled in the pattern opening Tr1'. The organic part Or11 can be formed, for example, by performing a printing process, so its top surface in the cross-sectional view of the electronic device 10d can be, for example, a curved surface. The curved surface design can reduce the stress of the layer, but the present disclosure is not limited thereto.

[0108] Then, a first metal layer is formed on the insulating layer IL1, wherein the first metal layer may be located on the organic portion Or11. That is, the first metal layer may, for example, cross the first opening PV1_OP1d of the insulating layer PV1', but the disclosure is not limited thereto. In the present embodiment, the first metal layer includes a gate G' that partially overlaps with the semiconductor layer SE' of the transistor TFT'.

[0109] In addition, in the present embodiment, after forming the insulating layer IL4 and before forming the source electrode S' of the transistor TFT', the organic portion Or12 is filled in the pattern opening Tr2'. The organic portion Or12 may be formed, for example, by performing a printing process, so its top surface in the cross-sectional view of the electronic device 10d may be, for example, a curved surface. The curved surface design may reduce the stress of the layer, but the present disclosure is not limited thereto.

[0110] Afterwards, a second metal layer is formed on the insulating layer IL4, wherein the second metal layer may be located on the organic portion Or12. That is, the second metal layer may, for example, cross the first opening PV1_OP1d of the insulating layer PV1' to reduce the component layout space occupied in the electronic device 10d, but the present disclosure is not limited thereto. In the present embodiment, the second metal layer includes a source electrode S' electrically connected to the semiconductor layer SE' of the transistor TFT'.

[0111] In this embodiment, the organic portion Or11 and the organic portion Or12 may be formed as a first organic portion Or1 ′, but the present disclosure is not limited thereto.

[0112] In this embodiment, the first metal layer (including the gate G' of the transistor TFT') and the second metal layer (including the source S' of the transistor TFT') can also cross the second opening PV1_OP2d of the insulating layer PV1' to reduce the component layout space occupied in the electronic device 10d, but the present disclosure is not limited thereto.

[0113] In some embodiments, the center line c3 of the graphic opening Tr1' may be aligned with the center line c4 of the graphic opening Tr2'. In detail, in the first opening PV1_OP1d of the insulating layer PV1', the center line c3 of the graphic opening Tr1' is, for example, aligned with the center line c4 of the graphic opening Tr2' in the top-view direction n of the substrate SB, wherein the "alignment" mentioned here may, for example, refer to overlapping in the top-view direction n. By aligning the center line c3 of the graphic opening Tr1' with the center line c4 of the graphic opening Tr2', the component layout space occupied by the first opening PV1_OP1d in the electronic device 10d can be reduced; however, the present disclosure is not limited to this. In other embodiments, the center line c3 of the graphic opening Tr1' may not be aligned with the center line c4 of the graphic opening Tr2'. In detail, in the second opening PV1_OP2d of the insulating layer PV1', the center line c3 of the graphic opening Tr1' is, for example, not aligned with the center line c4 of the graphic opening Tr2' in the top-view direction n of the substrate SB. By making the center line c3 of the pattern opening Tr1 ′ not aligned with the center line c4 of the pattern opening Tr2 ′, different cracks generated by stress caused by bending the electronic device 10 d can be blocked.

[0114] Figure 4 Based on Figure 1A It should be noted that, Figure 4 The embodiments can be used Figure 3B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0115] Please refer to Figure 4 The main difference between the electronic device 10e of this embodiment and the above-mentioned electronic device 10d is that part of the conductive wires in the electronic device 10e may also be located in the first opening PV1_OP1e of the insulating layer PV1′.

[0116] In the present embodiment, the first metal layer (including the gate G' of the transistor TFT') may be located in the first opening PV1_OP1e of the insulating layer PV1', and may extend to the insulating layer IL1 through the first opening PV1_OP1e to the adjacent insulating layer IL1, but the present disclosure is not limited thereto. In the present embodiment, the electronic device 10e may further include a conductive layer M0, wherein the conductive layer M0 is disposed between the substrate SB and the buffer layer BF, and is exposed by the hole VG'. In the present embodiment, the gate G1' and the metal element G2' of some transistors TFT' may be electrically connected to the conductive layer M0 through the hole VG'. Based on this, the gate G1' and the metal element G2' of some transistors TFT' disposed on the adjacent insulating layer IL1 may be electrically connected to each other through the conductive layer M0.

[0117] In the present embodiment, the electronic device 10d may further include a connection electrode CE2', wherein the connection electrode CE2' is electrically connected to the source electrode S1' and the metal element S2' of the transistor TFT' through the opening PL1_OP' of the planar layer PL1, but the present disclosure is not limited thereto. Based on this, the source electrode S1' and the metal element S2' disposed on the adjacent planar layer PL1 may be electrically connected to each other through the connection electrode CE2'.

[0118] In some embodiments, the material of the first organic portion Or1 in the planar layer PL1 may include a light shielding material to shield the gate G′ in the first opening PV1_OP1e of the insulating layer PV1′, but the disclosure is not limited thereto.

[0119] Figure 5 Based on Figure 1A It should be noted that, Figure 5 The embodiments can be used separately Figure 1A to Figure 1B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0120] Please refer to Figure 5 The main differences between the electronic device 10f of this embodiment and the above-mentioned electronic device 10a are: (1) the light emitting structure LE' includes an inorganic light emitting diode mLED; and (2) a shielding structure SS overlaps with the corresponding plurality of first openings PV1_OP1f of the insulating layer PV1.

[0121] In the present embodiment, the inorganic light emitting diode mLED in the light emitting structure LE' may include a micro light emitting diode. For example, the light emitting structure LE' may be a polycrystalline micro light emitting diode, but the present disclosure is not limited thereto. In detail, the inorganic light emitting diode mLED may include a first semiconductor layer SE1, a second semiconductor layer SE2, a light emitting layer L', a first electrode E1', and a second electrode E2'.

[0122] The first semiconductor layer SE1 and the second semiconductor layer SE2 may, for example, each include an N-type doped semiconductor and a P-type doped semiconductor; or each include a P-type doped semiconductor and an N-type doped semiconductor. The materials of the first semiconductor layer SE1 and the second semiconductor layer SE2 may, for example, include gallium nitride (GaN), indium gallium nitride (InGaN), gallium arsenide (GaAs), aluminum gallium indium phosphide (AlGaInP) or other materials composed of group IIIA and group VA elements or other suitable materials, but the present disclosure is not limited thereto. The light-emitting layer L' may, for example, have a quantum well (QW), which may, for example, be a single quantum well (SQW), a multiple quantum well (MQW) or other quantum wells. Based on this, the holes and electrons provided by the first semiconductor layer SE1 and the second semiconductor layer SE2 may combine in the light-emitting layer L' and emit light energy.

[0123] The first electrode E1' and the second electrode E2' may be, for example, electrically connected to the first semiconductor layer SE1 and the second semiconductor layer SE2, respectively. In some embodiments, the first electrode E1' may be connected to the drain electrode D of the transistor TFT, so that the inorganic light emitting diode mLED may be driven by the transistor TFT. The first electrode E1' and the second electrode E2' may, for example, include suitable conductive materials, but the present disclosure is not limited thereto.

[0124] In this embodiment, the electronic device 10f may further include a connecting electrode CE3 and a bonding structure BS.

[0125] The connection electrode CE3 is, for example, disposed on the planar layer PL1, and includes a connection electrode CE31 and a connection electrode CE32, wherein the connection electrode CE31 is electrically connected to the first electrode E1', and the connection electrode CE32 is electrically connected to the second electrode E2'. In the present embodiment, the connection electrode CE1 may be electrically connected to the drain electrode D of the transistor TFT through a hole VCE3 penetrating the planar layer PL1 and the insulating layer IL2, but the present disclosure is not limited thereto. The connection electrode CE3 may, for example, include a suitable conductive material, but the present disclosure is not limited thereto.

[0126] The bonding structure BS is, for example, disposed on the connection electrode CE3, and includes a bonding structure BS1 and a bonding structure BS2, wherein the bonding structure BS1 is electrically connected to the first electrode E1' and the connection electrode CE31, and the bonding structure BS2 is electrically connected to the second electrode E2' and the connection electrode CE32, so that the inorganic light emitting diode mLED can be electrically connected to the transistor TFT. The bonding structure BS may, for example, include a suitable conductive material, but the present disclosure is not limited thereto.

[0127] In this embodiment, the electronic device 10f further includes a filling layer FL.

[0128] The filling layer FL is, for example, disposed in the opening PDL_OP defined by the pixel definition layer PDL, and is, for example, disposed adjacent to or around the inorganic light emitting diode mLED. The filling layer FL can be, for example, used to fix or protect the inorganic light emitting diode mLED. In some embodiments, the filling layer FL may include a transparent material. For example, the material of the filling layer FL may include epoxy resin, acrylic, other suitable materials, or a combination thereof, but the present disclosure is not limited thereto.

[0129] In the present embodiment, one shielding structure SS may overlap with a plurality of first openings PV1_OP1f of the corresponding insulating layer PV1. In detail, one shielding structure SS may overlap with two first openings PV1_OP1f of the insulating layer PV1, for example, in the top-view direction of the substrate SB, but the present disclosure is not limited thereto. From another perspective, a plurality of first openings PV1_OP1f may be formed between adjacent transistors, but the present disclosure is not limited thereto. In the present embodiment, one shielding structure SS may overlap with a second opening PV1_OP2f of the corresponding insulating layer PV1, for example, in the top-view direction n of the substrate SB.

[0130] Figure 6 Show Figure 5 A partial cross-sectional diagram of an embodiment of the peripheral area of ​​the electronic device 10f. It should be noted that, Figure 5 The embodiments can be used in their own way Figure 1A to Figure 1B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0131] Please refer to Figure 6 A gate driver on panel GOP is provided in the peripheral area PA of the electronic device 10f, wherein the structure of the gate driver on panel GOP may be the same as or similar to the structure of the circuit structure CIL in the active area AA, and the gate driver on panel GOP may be provided on at least one side of the active area AA, but the present disclosure is not limited thereto.

[0132] The gate driving circuit GOP includes, for example, a transistor G_TFT1 and a transistor G_TFT2 . The transistor G_TFT1 and the transistor G_TFT2 are adjacent to each other, and the transistor G_TFT1 is closer to the active area AA of the electronic device 10 f than the transistor G_TFT2 , but the disclosure is not limited thereto.

[0133] In some embodiments, a plurality of first openings PV1_OP1f may be disposed between the transistor G_TFT1 and the transistor G_TFT2. In this embodiment, two first openings PV1_OP1f are disposed between the transistor G_TFT1 and the transistor G_TFT2, but the disclosure is not limited thereto.

[0134] In the present embodiment, a first opening PV1_OP1f is disposed between the transistor G_TFT1 and the transistor TFT located in the active area AA, but the present disclosure is not limited thereto.

[0135] Fig. 7A is a three-dimensional schematic diagram of an electronic device according to an embodiment of the present disclosure, and Figure 7B Based on Fig. 7A A partial enlarged top view of an embodiment of the region R1 is shown in FIG. Figure 7B The embodiments can be used separately Figure 1A The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0136] Please refer to Fig. 7A The electronic device 20 of this embodiment is a foldable electronic device, specifically a foldable mobile phone. In this embodiment, the electronic device 20 includes a display panel P and a frame F.

[0137] The display panel P, for example, includes a display area P1 and a camera area P2 located at the edge of the display panel P, wherein the display area P1 can be used to display a picture, and the camera area P2 can be used to capture external scenes, and can also be used to display a picture. In this embodiment, the display panel P also includes a bending axis FA, wherein the electronic device 20 can be folded relative to the bending axis FA. In some embodiments, when the electronic device 20 is folded, the display area P1 may include a display area P11 and a display area P12 divided by the bending axis FA, wherein the display surface of the display area P11 and the display surface of the display area P12 can each face different directions.

[0138] In some embodiments, the display area P1 may include a keyboard (not shown), which can be operated by a user and provide a corresponding command signal to a processor (not shown) in the electronic device 20 after the operation. The processor can, for example, enable the display panel P to display a screen or update a screen based on this command signal.

[0139] The frame F surrounds the display panel P and is combined with the display panel P, for example, but the present disclosure is not limited thereto.

[0140] Please refer to Figure 7B , the region R1 shows the configuration of the optical unit CF in the display region P1 and the first opening PV1_OP1a of the insulating layer PV1 , and the configuration of the optical unit CF′ and the first opening PV1_OP1a′ of the insulating layer PV1 in the camera region P2 .

[0141] In this embodiment, based on the consideration that the contrast in the camera area P2 may be smaller than the contrast in the display area P1, the size of the optical unit CF' in the camera area P2 may be larger than the size of the optical unit CF in the display area P1. That is, the width w3' of the optical unit CF' in the camera area P2 in the direction sd may be, for example, larger than the width w3 of the optical unit CF in the display area P1 in the direction sd.

[0142] In addition, in the present embodiment, based on the consideration that the contrast in the camera area P2 may be smaller than the contrast in the display area P1, the distance between adjacent optical units CF' in the camera area P2 may be greater than the distance between adjacent optical units CF in the display area P1. Based on this, the size of the first opening PV1_OP1a' provided in the camera area P2 may be larger than the size of the first opening PV1_OP1a provided in the display area P1. That is, the width w1' of the first opening PV1_OP1a' in the camera area P2 may be, for example, greater than the width w1 of the first opening PV1_OP1a in the display area P1.

[0143] Fig. 8A Show Fig. 7A A three-dimensional schematic diagram of the electronic device 20 after being folded, and Figure 8B Based on Fig. 8A A partial enlarged top view of an embodiment of the region R2 is shown in FIG. It is worth noting that: Fig. 8A The “folded” state of the electronic device 20 shown may include a state where the display surface of the display area P11 faces the display surface of the display area P12 and / or a state where the electronic device 20 cannot be folded any further.

[0144] In the present embodiment, in the region R2 , the insulating layer PV1 includes a first opening PV1_OP1a , a second opening PV1_OP2a , a third opening PV1_OP3a , and a fourth opening PV1_OP4a , wherein the first opening PV1_OP1a is adjacent to the second opening PV1_OP2a , and the third opening PV1_OP3a is adjacent to the fourth opening PV1_OP4a .

[0145] In some embodiments, the first opening PV1_OP1a and the second opening PV1_OP2a have a first extension direction dOP1, and the third opening PV1_OP3a and the fourth opening PV1_OP4a have a second extension direction dOP2, wherein the extension direction of the bending axis FA is the same as the first extension direction dOP1. In this embodiment, the distance between the first opening PV1_OP1a and the second opening PV1_OP2a is different from the distance between the third opening PV1_OP3a and the fourth opening PV1_OP4a. From another perspective, the density of the first opening PV1_OP1a and the second opening PV1_OP2a in the electronic device 20 is different from the density of the third opening PV1_OP3a and the fourth opening PV1_OP4a. That is, the number of the first opening PV1_OP1a and the second opening PV1_OP2a in the same cross-sectional area is greater than the number of the third opening PV1_OP3a and the fourth opening PV1_OP4a in the same cross-sectional area.

[0146] Specifically, the distance A1 between the first opening PV1_OP1a and the second opening PV1_OP2a in the second extension direction dOP2 is smaller than the distance A2 between the third opening PV1_OP3a and the fourth opening PV1_OP4a in the first extension direction dOP1. That is, the density of the first opening PV1_OP1a and the second opening PV1_OP2a in the electronic device 20 is greater than the density of the third opening PV1_OP3a and the fourth opening PV1_OP4a.

[0147] Through the above-mentioned design, the extension direction of the bending axis FA is the same as the first extension direction dOP1 of the first opening PV1_OP1a and the second opening PV1_OP2a with a higher density, and the possibility of cracks in the inorganic film layer (such as the insulating layer in the circuit structure CIL) can be further reduced when the electronic device 20 is folded. In other embodiments, the number of the first opening PV1_OP1a and the second opening PV1_OP2a formed in the electronic device 20 can be increased without forming the third opening PV1_OP3a and the fourth opening PV1_OP4a, but the present disclosure is not limited thereto.

[0148] Fig. 9A is a partial top view schematically showing the arrangement relationship between the sensing structure and the first opening of the insulating layer in the electronic device according to an embodiment of the present disclosure, and Fig. 9B This is a partial top view schematic diagram of the arrangement relationship between the sensing structure, the first opening of the insulating layer and the optical unit in the electronic device of the first embodiment of the present disclosure. It should be noted that, Fig. 9A as well as Fig. 9B The embodiments can be used separately Figure 1A to Figure 1BThe component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0149] Please also refer to Fig. 9A as well as Fig. 9B , the sensing structure SE in the electronic device 30a of the present embodiment includes a sensing electrode Rx and a driving electrode Tx, wherein the sensing electrode Rx has a first unit U1, a second unit U2, and a bridge portion BR for electrically connecting the first unit U1 and the second unit U2, but the present disclosure is not limited thereto. As described in the above embodiment, the first unit U1 and the second unit U2 can be electrically connected to the bridge portion BR, for example, through the opening PV2_OP of the insulating layer PV2 (exposing the first unit U1 and the second unit U2). In the present embodiment, the sensing electrode Rx includes a plurality of branch portions Rx_br, and the driving electrode Tx includes a plurality of branch portions Tx_br.

[0150] The sensing structure SE, for example, partially overlaps the first opening PV1_OP1a of the insulating layer PV1. In detail, the bridging portion BR of the sensing structure SE may, for example, at least partially overlap the first opening PV1_OP1a of the insulating layer PV1; or the sensing electrode Rx and / or the driving electrode Tx of the sensing structure SE may, for example, partially overlap the first opening PV1_OP1a of the insulating layer PV1, but the present disclosure is not limited to this. In some embodiments, in a top view of the electronic device 30a, an angle α between an extension direction dbr of a branch portion Rx_br of the sensing electrode Rx and / or a branch portion Tx_br of the driving electrode Tx of the sensing structure SE and an extension direction dOP1 of the first opening PV1_OP1a of the insulating layer PV1 is greater than or equal to 30° to less than or equal to 50°.

[0151] In the present embodiment, in the top view of the electronic device 30a, the first opening PV1_OP1a of the insulating layer PV1 has a width w1, the branch portion Tx_br (or branch portion Rx_br) of the sensing structure SE has a width w4, and the width w1 of the first opening PV1_OP1a of the insulating layer PV1 and the width w4 of the branch portion Tx_br (or branch portion Rx_br) satisfy the following relationship: 0.5≤w1 / w4≤2.

[0152] Fig. 10A is a partial top view schematically showing the arrangement relationship between the sensing structure, the first opening of the insulating layer and the optical unit in the electronic device of the second embodiment of the present disclosure, Fig. 10B is a partial top view schematically showing the arrangement relationship between the sensing structure, the first opening of the insulating layer and the optical unit in the electronic device of the third embodiment of the present disclosure, and Fig. 10CThis is a partial top view schematic diagram of the arrangement relationship between the sensing structure, the first opening of the insulating layer and the optical unit in the electronic device of the fourth embodiment of the present disclosure. It should be noted that, FIG. 10A to FIG. 10C The embodiments can be used in their own way Fig. 9B The component numbers and partial contents of the embodiments are shown in the figure, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

[0153] Please refer to Fig. 10A In the electronic device 30 b of the present embodiment, the insulating layer PV1 further includes a third opening PV1_OP3 a and a fourth opening PV1_OP4 a , wherein the third opening PV1_OP3 a is adjacent to the fourth opening PV1_OP4 a .

[0154] In some embodiments, the first opening PV1_OP1a and the second opening PV1_OP2a have a first extension direction dOP1, and the third opening PV1_OP3a and the fourth opening PV1_OP4a have a second extension direction dOP2, wherein the second extension direction dOP2 may be parallel to the direction Y, but the present disclosure is not limited thereto. In the present embodiment, the distance between the first opening PV1_OP1a and the second opening PV1_OP2a is different from the distance between the third opening PV1_OP3a and the fourth opening PV1_OP4a. From another perspective, the density of the first opening PV1_OP1a and the second opening PV1_OP2a in the electronic device 30b is different from the density of the third opening PV1_OP3a and the fourth opening PV1_OP4a. That is, the number of the first opening PV1_OP1a and the second opening PV1_OP2a in the same cross-sectional area is greater than the number of the third opening PV1_OP3a and the fourth opening PV1_OP4a in the same cross-sectional area.

[0155] In this embodiment, in the top view of the electronic device 30b, the angle β between the extension direction dbr of the branch portion Rx_br of the sensing electrode Rx and / or the branch portion Tx_br of the driving electrode Tx of the sensing structure SE and the extension direction dOP2 of the third opening PV1_OP3a (or the fourth opening PV1_OP4a) of the insulating layer PV1 is greater than or equal to 30° and less than or equal to 50°.

[0156] Please refer to Fig. 10B, the first opening PV1_OP1g included in the insulating layer PV1 in the electronic device 30c of the present embodiment has a wavy shape, wherein the wavy first opening PV1_OP1g may periodically rise and fall along the direction X. In detail, the first opening PV1_OP1g of the insulating layer PV1 overlaps with the branch portion Rx_br of the sensing electrode Rx and / or the branch portion Tx_br of the driving electrode Tx in the top view direction n of the substrate SB, so that the first opening PV1_OP1g of the insulating layer PV1 may present a wavy shape in the top view of the electronic device 30c.

[0157] Please refer to Fig. 10C In the electronic device 30d of the present embodiment, the first opening PV1_OP1h included in the insulating layer PV1 has a segmented shape. In detail, one first opening PV1_OP1h of the insulating layer PV1 can extend from one first optical unit CF1 to another adjacent first optical unit CF1, thereby forming a plurality of segmented first openings PV1_OP1h, wherein the angle θ between the extension direction dbr of the branch portion Rx_br of the sensing electrode Rx of the sensing structure SE and / or the branch portion Tx_br of the driving electrode Tx and the extension direction dOP1 of the first opening PV1_OP1h of the insulating layer PV1 can be greater than or equal to 30° and less than or equal to 50°.

[0158] In summary, in the electronic device provided in some embodiments of the present disclosure, the anti-reflection layer (shielding structure) is disposed inside the electronic device to reduce the possibility of peeling of the shielding structure, thereby improving the reliability of the electronic device.

[0159] In the electronic device provided in other embodiments of the present disclosure, a plurality of openings extending along a direction are provided in the insulating layer of the electronic device to separate the driving elements in the circuit structure. When cracks appear in one or more insulating layers due to factors such as bending, at least one of the openings in the insulating layer can block the extension path of the crack, thereby reducing the possibility of most of the driving elements being invaded by external moisture, thereby improving the reliability of the electronic device.

[0160] In the electronic devices provided in some other embodiments of the present disclosure, by designing the shielding structure to overlap the openings of the insulating layer, when the electronic device is bent, the stress of the electronic device when it is bent can be reduced, and because the shielding structure is not easily peeled off, the reliability of the electronic device can be further improved. Furthermore, when the electronic device is operating, the uneven brightness, dark lines and / or other optical defects that may be generated due to the formation of the openings of the insulating layer can be shielded by the shielding structure, so that the electronic device can have a good display effect.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electronic device, characterized in that: include: substrate; An insulating layer, disposed on the substrate and comprising a first opening; a first organic portion, disposed in the first opening of the insulating layer; A shielding structure, disposed on the insulating layer and comprising a retaining wall and a first opening; as well as A first optical unit is disposed in the first opening of the shielding structure, The blocking wall of the shielding structure overlaps with the first opening of the insulating layer. 2 . The electronic device according to claim 1 , wherein in one direction, a width of the blocking wall of the shielding structure is greater than or equal to a width of the first opening of the insulating layer.

3. The electronic device according to claim 2, wherein the width of the retaining wall of the shielding structure and the width of the first opening of the insulating layer satisfy the following relationship: 1≤w2 / w1≤150, Wherein w1 is the width of the first opening of the insulating layer, and w2 is the width of the retaining wall of the shielding structure.

4. The electronic device according to claim 1, wherein in the cross-sectional view of the electronic device, a distance exists between a center line of the first opening of the shielding structure and a center line of the first opening of the insulating layer, and the distance satisfies the following relationship: 0μm≤d1≤10μm, Wherein d1 is the distance. 5 . The electronic device according to claim 1 , wherein in one direction, a width of the first optical unit is greater than or equal to a width of the first opening of the insulating layer.

6. The electronic device according to claim 5, wherein the width of the first optical unit and the width of the first opening of the insulating layer satisfy the following relationship: 1 <w3 / w1≤200, Wherein w1 is the width of the first opening of the insulating layer, and w3 is the width of the first optical unit.

7. The electronic device according to claim 1 further comprises a second optical unit, wherein the shielding structure comprises a second opening, the retaining wall of the shielding structure is arranged between the first opening of the shielding structure and the second opening of the shielding structure, the second optical unit is arranged in the second opening of the shielding structure, the insulating layer comprises a second opening adjacent to the first opening of the insulating layer, and the retaining wall of the shielding structure overlaps with the second opening of the insulating layer.

8. The electronic device according to claim 1, wherein the insulating layer comprises a second opening, a third opening, and a fourth opening, The first opening of the insulating layer is adjacent to the second opening of the insulating layer, and the first opening of the insulating layer and the second opening of the insulating layer have a first extension direction, The third opening of the insulating layer is adjacent to the fourth opening of the insulating layer, the third opening of the insulating layer and the fourth opening of the insulating layer have a second extension direction, and the first extension direction is different from the second extension direction, In the top view of the electronic device, a distance between the first opening of the insulating layer and the second opening of the insulating layer is different from a distance between the third opening of the insulating layer and the fourth opening of the insulating layer. 9 . The electronic device according to claim 1 , wherein the first organic portion comprises a curved surface. 10 . The electronic device according to claim 1 , wherein a material of the first organic portion comprises a light shielding material.

11. An electronic device according to claim 1, wherein in a cross-sectional view of the electronic device, the first opening of the insulating layer includes a first width, a second width and a third width, the third width is between the first width and the second width, the second width is closer to the substrate than the first width, the third width is greater than the first width, and the third width is greater than the second width. 12 . The electronic device according to claim 1 , further comprising a conductive line, wherein the conductive line is disposed on the substrate and crosses the first opening of the insulating layer. 13 . The electronic device according to claim 1 , further comprising a conductive line, wherein the conductive line is disposed on the substrate and located in the first opening of the insulating layer.

14. The electronic device according to claim 1, further comprising a sensing structure, wherein the sensing structure is disposed on the insulating layer and partially overlaps the first opening of the insulating layer. In the top view of the electronic device, the first opening of the insulating layer has a width, the branch portion of the sensing structure has a width, and the width of the first opening of the insulating layer and the width of the branch portion satisfy the following relationship: 0.5≤w1 / w4≤2, Wherein w1 is the width of the first opening of the insulating layer, and w4 is the width of the branch portion of the sensing structure.

15. The electronic device according to claim 1, further comprising a sensing structure, wherein the sensing structure is disposed on the insulating layer and partially overlaps the first opening of the insulating layer. Wherein, in the top view of the electronic device, an angle between the branch portion of the sensing structure and the first extension direction of the first opening of the insulating layer is greater than or equal to 30° and less than or equal to 50°.

16. The electronic device according to claim 1 further comprises a sensing structure, wherein the sensing structure is disposed on the insulating layer and comprises a first unit, a second unit and a bridging portion, the bridging portion connecting the first unit and the second unit, wherein the bridging portion at least partially overlaps the first opening of the insulating layer.

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