Gate drive circuit for semiconductor switching element, motor control system, and semiconductor device

Abstract

In a gate drive circuit for a semiconductor switching element that is driven and controlled by two independent gate electrodes, the time constant of the voltage of the gate electrodes is set to be longer than when a first gate electrode (Gs) is turned off and when a second gate electrode (Gc) is turned off, and the time constant of the voltage of the gate electrodes is set to be longer than when the first gate electrode (Gs) is turned off. The voltage V * of the second gate electrode (Gc) at the time when the maximum power is applied when the semiconductor switching element (31) is turned off satisfies formula (1). Formula (1) 0 < = V * < = predetermined value < + Vp (In the formula, + Vp is a gate drive voltage when the semiconductor switching element is turned on).

Description

Technical Field

[0001] The present invention relates to a gate drive circuit of a semiconductor switching element, a motor control system and a semiconductor device. Background Art

[0002] As the world moves toward a decarbonized society, the market for electric vehicles (EVs), power grids, and railways is growing steadily. In applications in this market, power converters are used that output AC current based on DC power supplied by a DC power source to drive motors. Key components of power converters include semiconductor switching elements and gate drive circuits that drive them.

[0003] Semiconductor switch elements are required to have low losses and high withstand capability to cut off a large current flowing through them without being damaged. In addition to the high withstand capability of semiconductor switch elements themselves, there are also methods for increasing the withstand capability of gate drive and circuits. Various studies have been conducted on gate drive methods and drive circuits for achieving such high withstand capability.

[0004] Patent Document 1 discloses a method of softly turning off a gate when a load is short-circuited, thereby suppressing an excessive voltage surge applied to a semiconductor switching element.

[0005] Patent Document 2 discloses a device that detects abnormal current and abnormal temperature during operation and protects semiconductor switching elements.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2016-136819

[0009] Patent Document 2: Japanese Patent Application Laid-Open No. 6-125256 Summary of the invention

[0010] Problems to be solved by the invention

[0011] FIG. 22 of Patent Document 1 describes the following technology: in a dual-gate IGBT having a first gate electrode and a second gate electrode, when a load short circuit occurs, the charge accumulated in the second gate electrode is discharged via a second soft-off circuit (resistor 5+switch S5) to increase the voltage throughput.

[0012] However, in the application of the above-mentioned technology, it is a problem that the effect of improving the turn-off withstand capability of semiconductor switch elements (for example, dual-gate IGBT) is not sufficiently obtained. The details will be described later.

[0013] The present invention is proposed to solve the above-mentioned problems, and an object of the present invention is to provide a gate drive circuit of a semiconductor switch element, a motor control system, and a semiconductor device capable of realizing a high breakdown resistance of the semiconductor switch element.

[0014] Solutions to Solve Problems

[0015] In order to achieve the above object, the gate drive circuit of the semiconductor switch element of the present invention is driven and controlled by two independent gate electrodes, and is characterized in that the time constant of the gate electrode voltage when the second gate electrode is turned off is set longer than when the first gate electrode is turned off, and the voltage V of the second gate electrode at the moment when the maximum power is applied when the semiconductor switch element is turned off is ＊ Satisfying formula (1),

[0016] Formula (1) 0≤V ＊ ≤Predetermined value<+Vp

[0017] Wherein, +Vp is the gate drive voltage when the semiconductor switch element is turned on.

[0018] Other aspects of the present invention will be described in the embodiments described below.

[0019] Effects of the Invention

[0020] According to the present invention, it is possible to realize high breakdown resistance of a semiconductor switching element. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a diagram showing the overall configuration of a motor control system using the power conversion device according to the first embodiment.

[0022] Figure 2 It is a diagram showing a circuit of the gate driving device according to the first embodiment.

[0023] Figure 3 This is a diagram showing a driving method of a dual-gate IGBT in a normally-off state.

[0024] Figure 4 This is a diagram showing a driving method of a dual-gate IGBT in the case of simultaneous OFF.

[0025] Figure 5 This is a diagram showing the transition of stored carriers in a dual-gate IGBT in a normally-off state.

[0026] Figure 6 This is a diagram showing the transition of stored carriers in a dual-gate IGBT when both are turned off simultaneously.

[0027] Figure 7This is a diagram showing the cause of reduction in breakdown voltage of the IGBTs in the case of simultaneous turn-off.

[0028] Figure 8 1 is a diagram showing an example of a turn-off waveform according to the present embodiment in the case of simultaneous turning off.

[0029] Fig. 9 1 is a diagram showing an example of a turn-off waveform of a comparative example in the case of simultaneous disconnection.

[0030] Fig.10 It is a diagram showing a mechanism for increasing the gate voltage of the second gate electrode according to the first embodiment.

[0031] Fig.11 It is a diagram showing a circuit of a gate driving device according to a second embodiment.

[0032] Fig.12 This is a diagram showing gate voltage instructions in the case of simultaneous off according to the second embodiment.

[0033] Fig.13 It is a diagram showing a gate voltage command in the normally OFF state according to the second embodiment.

[0034] Fig.14 It is a diagram showing an example (variation 1) of a semiconductor switch element.

[0035] Fig.15 It is a diagram showing an example (variation 2) of a semiconductor switch element. DETAILED DESCRIPTION

[0036] Hereinafter, a mode for carrying out the present invention (hereinafter referred to as “embodiment”) will be described with reference to the drawings as appropriate.

[0037] 《First Implementation Mode》

[0038] Figure 1 1 is a diagram showing the overall configuration of a motor control system 100 using a power conversion device according to the first embodiment. The power conversion device is a device that converts electric power using a power semiconductor device. Here, the motor control system 100 using an inverter circuit is described.

[0039] The motor control system 100 is composed of a DC power supply 10, an inverter circuit 20, a motor 70, etc. The inverter circuit 20 includes a smoothing capacitor 21, three-phase inverter units 30 of U, V, and W phases (U-phase inverter unit 30U, V-phase inverter unit 30V, and W-phase inverter unit 30W), and a command logic unit 22. The inverter circuit 20 outputs AC power based on the DC power supplied by the DC power supply to drive the motor 70. A smoothing capacitor 21 is provided between the DC power supply 10 (power supply voltage = Vcc) and the positive connection line 23 and the negative connection line 24 of the inverter circuit 20.

[0040] The inverter unit 30 is composed of an upper branch and a lower branch, and has a series circuit of semiconductor switching elements 31. The semiconductor switching elements 31 of each of the upper branch and the lower branch are composed of a dual-gate IGBT (hereinafter referred to as IGBT). A gate signal is sent to the dual-gate IGBT from the gate drive device 40. The high potential side terminal of the IGBT of the upper branch is connected to the first end (positive electrode connection line 23) of the smoothing capacitor 21. The high potential side terminal of the IGBT of the lower branch is connected to the low potential side terminal of the IGBT of the upper branch. The low potential side terminal of the IGBT of the lower branch is connected to the second end (negative electrode connection line 24) of the smoothing capacitor 21. In addition, regarding the dual-gate IGBT, refer to Figure 2 to Figure 6 Here, IGBT is the abbreviation of Insulated Gate Bipolar Transistor.

[0041] In each phase, the connection point 33 between the low potential terminal of the upper IGBT and the high potential terminal of the lower IGBT is connected to one end of the winding of the motor 70. The other end of the winding of each phase is connected to the neutral point. The motor 70 is, for example, an induction motor.

[0042] A freewheeling diode 32 (flying diode) is connected in antiparallel to each IGBT. As the freewheeling diode 32, various diodes such as a pn junction diode, a Schottky barrier diode, and a diode combining a pn junction and a Schottky junction can be used.

[0043] The command logic unit 22 outputs an on command indicating an on state or an off command indicating an off state to the gate drive device 40 as a drive command signal P for the semiconductor switch element 31. Thus, the command logic unit 22 turns the upper semiconductor switch element 31 and the lower semiconductor switch element 31 on alternately in each phase in order to control the control amount of the motor 70 to the command value. The control amount is, for example, the torque of the motor.

[0044] The gate driving device 40 is provided corresponding to each semiconductor switch element 31 , obtains the driving command signal P from the command logic unit 22 , and based on the obtained driving command signal P, turns the semiconductor switch element 31 to an on state or an off state.

[0045] Figure 2 1 is a diagram showing a circuit of the gate driving device 40 according to the first embodiment. Figure 1 The semiconductor switch element 31 and gate drive device 40 of the lower arm of the U phase in the inverter circuit 20 shown are similarly configured as the semiconductor switch elements and gate drive devices of the upper arm of the U phase, the upper and lower arms of the V phase, and the W phase.

[0046] The following describes the structure and operation of the semiconductor switch element 31 of the lower arm of the U phase and its gate drive device 40 , but the structures and operations of other semiconductor switch elements and their gate drive devices are the same.

[0047] The gate driving device 40 is configured to include a positive side power supply 41, a first PMOSFET 42, a second PMOSFET 43, on-side gate resistors Rgcon and Rgson, a delay control unit 44, a negative side power supply 45, off-side gate resistors Rgcoff and Rgsoff, a first NMOSFET 46, and a second NMOSFET 47. Here, PMOSFET is a P-type Metal-Oxide-Semiconductor Field-Effect Transistor, and NMOSFET is an N-type Metal-Oxide-Semiconductor Field-Effect Transistor.

[0048] The output portion of the gate driving device 40 is connected to the first gate electrode Gs and the second gate electrode Gc of the semiconductor switch element 31. The reference potential of the gate driving device 40 is connected to the emitter terminal E of the semiconductor switch element 31.

[0049] In addition, the command logic unit 22 is connected to the input portion of the gate driving device 40. The source of the first PMOSFET 42 is connected to the positive side power supply 41. The drain of the first PMOSFET 42 is connected to one end of the on-side gate resistor Rgson, and the drain of the first NMOSFET 46 is connected to one end of the off-side gate resistor Rgsoff. The other end of the on-side gate resistor Rgson and the other end of the off-side gate resistor Rgsoff are both connected to the output portion of the gate driving device 40. The source of the first NMOSFET 46 is connected to the negative side power supply 45. The gate of the first PMOSFET 42 and the gate of the first NMOSFET 46 are both connected to the output portion of the delay control unit 44.

[0050] Similarly, the source of the second PMOSFET 43 is connected to the positive side power supply 41. The drain of the second PMOSFET 43 is connected to one end of the on-side gate resistor Rgcon, and the drain of the second NMOSFET 47 is connected to one end of the off-side gate resistor Rgcoff. The other end of the on-side gate resistor Rgcon and the other end of the off-side gate resistor Rgcoff are both connected to the output of the gate driving device 40. The source of the second NMOSFET 47 is connected to the negative side power supply 45. The gate of the second PMOSFET 43 and the gate of the second NMOSFET 47 are both connected to the output of the delay control unit 44.

[0051] [Action Description]

[0052] The drive command signal P is input from the command logic unit 22 to the gate drive device 40. During the input of the drive command signal P, the gate drive device 40 operates the delay control unit to turn on the PMOSFET and turn off the NMOSFET. As a result, the gate drive device 40 flows a current (gate current) from the positive power supply 41 to the first and second gates of the semiconductor switch element 31 via the on-side gate resistor. At this time, the gate-emitter capacitance of the semiconductor switch element 31 is charged and a voltage exceeding the threshold voltage of the semiconductor switch element 31 (for example, Vp = +15V) is applied, and the gate drive device 40 turns on the semiconductor switch element 31 and causes current to flow to the semiconductor switch element (conduction). The switching speed of conduction is controlled by adjusting the resistance values ​​of the on-side gate resistors Rgcon and Rgson.

[0053] Normally, during conduction, the first and second gate electrodes are turned on at the same time. That is, during conduction, the time difference set by the delay control unit 44 is made zero, but a delay may be provided.

[0054] In addition, the gate drive device 40 operates the delay control unit to turn off the PMOSFET and turn on the NMOSFET during the period when the drive command signal P is not input from the command logic unit 22. As a result, the gate current flows from the gate of the semiconductor switch element 31 to the negative power supply via the disconnected side gate resistor. At this time, the gate-emitter capacitance of the semiconductor switch element 31 is discharged and a voltage lower than the threshold voltage of the semiconductor switch element (for example, -Vm = -15V) is applied, so that the semiconductor switch element 31 is disconnected and the current of the semiconductor switch element 31 is cut off (turned off). The switching speed of the turn-off is controlled by adjusting the resistance values ​​of the disconnected side gate resistors Rgcoff and Rgsoff.

[0055] Normally, the second gate electrode Gc is turned off before the first gate electrode Gs. That is, the turn-off is performed so that the time difference set by the delay control unit 44 is tdoff (≥0). In the case where all gates are turned off urgently due to system abnormality, the delay can also be made zero (tdoff≈0). Figure 3 , Figure 4 This will be described later in the text.

[0056] The relationship between the voltage of the gate electrode when off and the switching of the MOSFET will be described.

[0057] Figure 3 This is a diagram showing the driving method of the dual-gate IGBT in the case of normal off (a case where the second gate electrode Gc is turned off before the first gate electrode Gs). When the second gate electrode Gc is turned off, the second PMOSFET 43 is turned off and the second NMOSFET 47 is turned on. And after tdoff, when the first gate electrode Gs is turned off, the first PMOSFET 42 is turned off and the first NMOSFET 46 is turned on.

[0058] Figure 4 1 is a diagram showing a driving method of a dual-gate IGBT in a case where both the second gate electrode Gc and the first gate electrode Gs are turned off at the same time. When the second gate electrode Gc is turned off, the second PMOSFET 43 is turned off and the second NMOSFET 47 is turned on. At the same time, when the first gate electrode Gs is turned off, the first PMOSFET 42 is turned off and the first NMOSFET 46 is turned on.

[0059] [Detailed explanation of the issue of improving disconnection tolerance]

[0060] Figure 5 1 is a diagram showing the transition of stored carriers in a double-gate IGBT in a normally off state. Figure 5As shown in FIG. 1 , the dual-gate IGBT has a first gate electrode Gs and a second gate electrode Gc, and the first gate electrode Gs and the second gate electrode Gc are used to control the accumulation of carriers inside the IGBT. As described above, before the IGBT is about to be turned off, the second gate electrode Gc is first turned off (t=t0). After the second gate electrode Gc is turned off, the supply of electrons from the gate of the second gate electrode Gc stops, so Figure 5 As shown, the accumulated carriers (=minority carriers, holes) inside the IGBT decrease over time along with the lifetime of the carriers.

[0061] After a certain period of time has passed since the second gate electrode Gc was disconnected, if the first gate electrode Gs is turned off, the IGBT is turned off (t=t1). After tdoff, the concentration of accumulated carriers inside the IGBT becomes sufficiently low, so the turn-off loss is reduced. However, depending on the control mode of the IGBT, it is necessary to turn off the IGBT at a sufficiently short tdoff or tdoff≈0. For example, there can be a situation where all gates are disconnected urgently due to system abnormalities, etc.

[0062] Figure 6 This is a diagram showing the transition of stored carriers in a dual-gate IGBT when both are turned off simultaneously. Figure 7 This is a diagram showing the cause of reduction in breakdown voltage of the IGBTs in the case of simultaneous turn-off. Figure 6 In the case of , the IGBT is turned off in a state where the accumulated carrier concentration inside the IGBT is high. If the gate of the second gate electrode Gc is turned off in a negative bias state, Figure 7 As shown in FIG. 1 , a hole accumulation layer is formed under the gate. At this time, since the current flowing through the IGBT is concentrated in the area where the hole accumulation layer is formed, the electric field strength in this area increases, causing dynamic avalanche, and the IGBT is locked and destroyed due to the generated avalanche current. In other words, there is a problem of reduced IGBT destruction tolerance.

[0063] [Improvement Methods]

[0064] In the present embodiment, there is provided a problem for improving the degradation of the breakdown resistance of the IGBT accompanying the formation of the hole accumulation layer under the gate as described above.

[0065] Figure 8 2 is a diagram showing an example of a turn-off waveform of the present embodiment in the case of simultaneous disconnection. Figure 8 As shown, in this embodiment, the time constant τGs when the first gate electrode Gs is turned off is adjusted. Figure 2The off-side gate resistance Rgcoff of the second gate electrode Gc is increased to lengthen the time constant τGc when the second gate electrode Gc is turned off. Here, the time constant τGs is defined by the time difference from the moment t1 when the first gate electrode Gs starts to turn off to the moment when the gate voltage (VGsE) of the first gate electrode Gs reaches 1 / 3 (+VP / 3) of the positive side power supply voltage of the gate driving device (the time constant τGc is also defined in the same way). In addition, the time constant when the first gate electrode Gs is turned off refers to the time constant after the off instruction of the first gate electrode Gs. The same is true for the time constant when the second gate electrode Gc is turned off.

[0066] In addition, Figure 8 In the equation, tdoff≈0, which means that the IGBT is turned off when the accumulated carrier concentration inside the IGBT is high, that is, the IGBT off tolerance is the lowest. Figure 8 As shown, in this embodiment, adjusting Figure 3 The off-side gate resistance Rgcoff of the second gate electrode Gc is set so that the power consumption of the switching element is the maximum when it is turned off, that is, the collector-emitter voltage VCE is substantially equal to the power supply voltage Vcc ( Figure 8 The peak power of the second gate electrode is t2), and the voltage VGcE of the second gate electrode is greater than 0 V and less than +VP / 3. By adjusting the off-side gate resistance Rgcoff, the voltage VGcE of the second gate electrode can be adjusted.

[0067] That is, the gate drive circuit of the dual-gate IGBT (semiconductor switch element) is characterized in that, in the gate drive circuit of the semiconductor switch element driven and controlled by two independent gate electrodes, the time constant of the gate electrode voltage when the second gate electrode Gc is turned off is set longer than when the first gate electrode Gs is turned off, and the voltage V of the second gate electrode Gc at the moment when the maximum power is applied when the dual-gate IGBT is turned off is set longer. ＊ Satisfying formula (1):

[0068] Formula (1) 0≤V ＊ ≤predetermined value<+Vp.

[0069] Wherein, +Vp is the gate drive voltage when the semiconductor switch element is turned on.

[0070] The predetermined value is the threshold voltage Vth of the semiconductor switch element. Specifically, the predetermined value is preferably +Vp / 2. Furthermore, as described above, the predetermined value is more preferably +Vp / 3.

[0071] If V ＊ In negative bias (V ＊ <0V), then Figure 7As shown in FIG. 1 , a hole accumulation layer is formed under the gate. At this time, since the current flowing through the IGBT is concentrated in the area where the hole accumulation layer is formed, the electric field strength in this area increases, causing dynamic avalanche, and the IGBT is locked and destroyed due to the generated avalanche current. That is, the IGBT breakdown tolerance is reduced. Therefore, from the perspective of high breakdown tolerance, it is preferred that 0≤V ＊ .

[0072] For example, if V ＊ Greater than +VP / 3 (V ＊ >+VP / 3), then in most voltage-controlled semiconductor switching elements (such as IGBTs), V ＊ Since V is greater than the threshold voltage (Vth), the time it takes to disconnect the electron channel to the IGBT during shutdown becomes longer, and the switching loss (shutdown loss) increases dramatically. Therefore, from the perspective of reducing losses, V is more preferably ＊ ≤+VP / 3.

[0073] Therefore, at the time when the power consumption of the switching element is the largest (the time when the maximum power is applied) during the off state, the gate voltage of the second gate electrode Gc is controlled to be 0≤V ＊ ≤+VP / 3, so no Figure 7 Therefore, it is difficult to cause dynamic avalanche in this area, preventing the IGBT from being latched up and improving the breakdown resistance of the IGBT.

[0074] Fig. 9 1 is a diagram showing an example of a turn-off waveform of a comparative example in the case of simultaneous disconnection. Fig. 9 As a comparative example, the case where the time constant τGs=τGc is shown. When the time shifts to time t2, the semiconductor switch element as a device exceeds the dielectric strength and is broken.

[0075] Fig.10 1 is a diagram showing a mechanism for increasing the gate voltage of the second gate electrode Gc in the first embodiment. Fig.10 As shown in the figure, when the collector-emitter voltage VCE increases during turn-off (when dv / dt is applied), the current (Cres×dv / dt) flowing through the feedback capacitor Cres between the collector and the gate flows through the gate resistor Rgcoff on the off side. Therefore, by increasing (adjusting) Fig.10 The off-side gate resistance Rgcoff of the second gate electrode Gc is increased, thereby increasing (controlling) the voltage drop of the off-side gate resistance Rgcoff. As a result, Figure 8 At the time of the peak power (t2), the voltage VGcE of the second gate electrode can be adjusted to be larger than 0 V and smaller than +VP / 3. Thus, a high breakdown withstand capability of the semiconductor switch element 31 can be achieved.

[0076] Second Implementation Method

[0077] Fig.11 4 is a circuit diagram of a gate driving device 40A according to the second embodiment. The difference from the first embodiment is that, instead of using the off-side gate resistance Rgcoff of the second gate electrode Gc to control the time constant τGc when the second gate electrode Gc is turned off, an intermediate power supply 50 (power supply voltage = V ＊＊ ), when the semiconductor switch element 31 is turned off, the voltage VGcE of the second gate electrode Gc is disconnected in two stages.

[0078] The circuit diagram of the gate driving device 40A according to the second embodiment (see Fig.11 ) is a circuit diagram of the gate driving device 40 of the first embodiment (see Figure 2 ) is different in structure in that an intermediate power supply 50, a third NMOSFET 51 (gate switch), and a switching control unit 52 are provided instead of the off-side gate resistor Rgcoff of the second gate electrode Gc.

[0079] The source of the second NMOSFET 47 is connected to the intermediate power supply 50, the drain is connected to the output of the gate drive device (the second gate electrode Gc), and the gate is connected to the output of the command signal Q of the switching control unit 52. The source of the third NMOSFET 51 is connected to the negative power supply, the drain is connected to the output of the gate drive device (the second gate electrode Gc), and the gate is connected to the output of the command signal R of the switching control unit 52. The input of the switching control unit 52 is connected to the output of the delay control unit 44. The other connection methods and structures are similar to the circuit of the gate drive device 40 of the first embodiment (see Figure 2 )same.

[0080] [Action Description]

[0081] Since the operation other than the shutdown operation is the same as that of the first embodiment, the shutdown operation will be described in detail.

[0082] Fig.12 This is a diagram showing gate voltage instructions in the case of simultaneous off according to the second embodiment. Fig.12 For example, in a situation where all gates are urgently disconnected due to a system abnormality, the command logic unit 22 sends a simultaneous disconnection command signal (P′) to the delay control unit 44 instead of the drive command signal (P).

[0083] like Fig.12 As shown, at time t0 when the drive instruction signal (P′) sent from the instruction logic unit 22 to the delay control unit 44 becomes an OFF instruction, the delay control unit 44 sends an instruction signal (not shown) to the switching control unit 52 .

[0084] Therefore, the switching control unit 52 sends the command signal Q only during the predetermined time Δt, and then turns off the second PMOSFET 43, and turns on the second NMOSFET 47 only during the predetermined time Δt, thereby reducing the voltage VGcE of the second gate electrode Gc to V of the intermediate voltage. ＊＊ Furthermore, the switching control unit 52 sends the command signal R after a predetermined time Δt has passed, and after the second NMOSFET 47 is turned off, the third NMOSFET 51 is turned on, thereby reducing the voltage VGcE of the second gate electrode Gc to the negative power supply voltage (−Vm) of the gate driving device 40A.

[0085] After receiving the simultaneous off command signal (P′), the delay control unit 44 sends the command signal S without delay (tdoff=0), and then turns off the first PMOSFET 42 and turns on the first NMOSFET 46, thereby turning off the first gate electrode Gs and turning off the semiconductor switch element.

[0086] At this time, since the first gate electrode Gs and the second gate electrode Gc are disconnected at approximately the same time, Figure 8 Therefore, similar to the operation in the first embodiment, the maximum power consumption of the switching element during shutdown, that is, the collector-emitter voltage VCE is substantially equal to the power supply voltage Vcc ( Figure 8 The peak power: t2), the voltage VGcE of the second gate electrode Gc can be controlled to be greater than 0V and less than +VP / 3.

[0087] Therefore, at the time when the power consumption of the switching element is the largest during turn-off, the gate voltage of the second gate electrode Gc can be controlled to be 0≤V ＊ ≤+VP / 3, so no Figure 7 Therefore, it is difficult to cause dynamic avalanche in this area, preventing the IGBT from being latched up and improving the breakdown resistance of the IGBT.

[0088] Fig.13 1 is a diagram showing a gate voltage command in a normally OFF state according to the second embodiment. Fig.12 After receiving the driving command signal P sent from the command logic unit 22 to the delay control unit 44, the delay control unit 44 sends the command signal S after a delay of tdoff, and then turns off the first PMOSFET 42 and turns on the first NMOSFET 46, thereby turning off the first gate electrode Gs and turning off the semiconductor switch element. As a result, the voltage VGcE of the second gate electrode Gc can be controlled to be greater than 0V and less than +VP / 3, which is the same as the operation in the first embodiment.

[0089] [Modification of semiconductor switch element]

[0090] Fig.14 It is a diagram showing an example (variation 1) of a semiconductor switch element. Fig.14 The semiconductor switch element is formed by connecting the collector electrodes CE and the emitter electrodes EE of a first chip Hc which is a chip with higher hole injection efficiency from the collector side and a second chip Hs which is a chip with lower hole injection efficiency from the collector side in parallel.

[0091] The second gate electrode Gc is connected to the gate of the first chip Hc, and both the first gate electrode Gs and the second gate electrode Gc are connected to the gate of the second chip Hs.

[0092] By spatially separating a first chip Hc with high conduction and small conduction loss and a second chip Hs with high speed and small switching loss, if a driving combination with a delay (tdoff) is set between the disconnection of the second gate electrode Gc and the disconnection of the first gate electrode Gs in the gate driving device 40 of this embodiment, it has the advantage of further improving the effect of reducing the loss generated in the semiconductor switching element.

[0093] Fig.15 It is a diagram showing an example (variation 2) of a semiconductor switch element. Fig.15 The semiconductor switching element is not grounded to the gate at the bottom of the p-base layer sandwiched by the gate (equivalent to Fig.15 Δ) is provided with an n-type semiconductor (DHB) having an impurity concentration higher than that of the n-drift layer.

[0094] Since the DHB having a higher impurity concentration than the n-drift layer is provided, the electric field intensity at the junction between the p-base layer and the DHB becomes high, and a dynamic avalanche occurs at this location when the device is turned off.

[0095] Since the DHB is not connected to the gate and is set away from the gate by a distance Δ, the area where dynamic avalanche occurs is also away from the gate. Therefore, if combined with the driving method of this embodiment, the dynamic avalanche near the gate can be further suppressed to prevent the IGBT from being locked and destroyed due to the generated avalanche current. That is, there is an advantage of further improving the destruction tolerance of the IGBT.

[0096] [Delay(tdoff)]

[0097] The control of lengthening the disconnection time constant by disconnecting the side gate resistance Rgcoff as described above (first embodiment), or the control of two-stage disconnection (second embodiment) can also be implemented only when the first gate electrode Gs and the second gate electrode Gc are disconnected at the same time (for example, a simultaneous disconnection instruction signal (P') is sent from the instruction logic unit 22 to the delay control unit 44 to shut down without delay tdoff=0).

[0098] [Configuration example of inverter]

[0099] The semiconductor switching element is not limited to IGBT as long as it is voltage-driven. It can be applied even if the semiconductor material is Si, SiC, GaN, gallium oxide, etc. It is not limited to hybrid vehicles, electric vehicles, and power conversion devices for railways, but can be used in all power conversion devices.

[0100] The gate drive circuit of the semiconductor switching element, the motor control system, and the semiconductor device according to the present embodiment described above have the following features.

[0101] (1) In a gate drive circuit of a semiconductor switch element driven and controlled by two independent gate electrodes, the time constant of the gate electrode voltage when the second gate electrode Gc is turned off is set longer than when the first gate electrode Gs is turned off, and the voltage V of the second gate electrode at the time when the maximum power is applied when the semiconductor switch element is turned off is set longer than when the first gate electrode Gs is turned off. ＊ Satisfying formula (1),

[0102] Formula (1) 0≤V ＊ ≤Predetermined value<+Vp

[0103] Where +Vp is the gate drive voltage when the semiconductor switch element is turned on.

[0104] This makes it possible to achieve high breakdown resistance of the semiconductor switch element.

[0105] (2) In the gate drive circuit of the semiconductor switch element of (1), the time when the maximum power is applied when the semiconductor switch element is turned off is the time when the collector-emitter voltage (VCE) of the semiconductor switch element is substantially equal to the power supply voltage (eg, Vcc) when the semiconductor switch element is turned off.

[0106] (3) In the gate drive circuit of the semiconductor switch element of (1), the gate drive circuit has an off-side gate resistor Rgcoff for controlling the time constant when the second gate electrode Gc is turned off, and the voltage drop under the gate resistor is controlled by adjusting the off-side gate resistor Rgcoff. The off-side gate resistor Rgcoff can be adjusted manually using a variable resistor, or the variable resistor can be adjusted according to an instruction from the instruction logic unit 22, for example.

[0107] (4) In a gate drive circuit of a semiconductor switching element driven and controlled by two independent gate electrodes, when the first gate electrode Gs is disconnected, the voltage of the first gate electrode is instructed to drop to the negative power supply voltage (e.g., -Vm), and when the second gate electrode Gc is disconnected, the voltage of the second gate electrode Gc is instructed to drop to the negative power supply voltage (e.g., -Vm) in two stages.

[0108] (5) In the gate drive circuit of the semiconductor switch element of (4), the gate drive circuit has a power supply of a first voltage (e.g., an intermediate voltage 50), a gate switch (e.g., a third NMOSFET 51), and a switching control unit 52. The switching control unit 52 first reduces the voltage (VGCE) of the second gate electrode to a first voltage (e.g., power supply voltage = V ＊＊ ), after a predetermined time (Δt), the voltage of the second gate electrode is reduced to the negative side power supply voltage (eg -Vm) of the gate driving circuit.

[0109] (6) In the gate drive circuit of the semiconductor switching element of any one of (1) to (5), the semiconductor switching element is preferably constructed by connecting the collector electrodes of a first chip Hc which is a chip with a higher hole injection efficiency from the collector side and the emitter electrodes of a second chip Hs which is a chip with a lower hole injection efficiency from the collector side in parallel.

[0110] (7) In the gate driving circuit of the semiconductor switch element of (6), the second gate electrode Gc is connected to the gate of the first chip Hc, and both the first gate electrode Gs and the second gate electrode Gc are connected to the gate of the second chip Hs.

[0111] (8) In the gate driving circuit of the semiconductor switch element of (6), the semiconductor switch element 31 has an n-type semiconductor (DHB) having an impurity concentration higher than that of the n drift layer, which is not in contact with the gate, under the p base layer sandwiched by the gate.

[0112] (9) In the gate drive circuit of the semiconductor switch element of (1) or (4), it is preferable to perform control when the first gate electrode Gs and the second gate electrode Gc receive the off signal at the same time.

[0113] (10) In the gate drive circuit of the semiconductor switch element of (1), the predetermined value is a threshold voltage Vth of the semiconductor switch element.

[0114] (11) In the gate drive circuit of the semiconductor switch element of (1), the predetermined value is +Vp / 3.

[0115] (12) The motor control system 100 includes semiconductor switching elements 31 of each branch in the inverter circuit 20 and a gate drive device 40. The gate drive device 40 is a gate drive circuit of the semiconductor switching element of any one of (1) to (5). Based on the DC power supplied from the DC power supply to the inverter circuit 20, the inverter circuit 20 outputs AC current to drive the motor 70.

[0116] (13) The motor control system 100 includes semiconductor switching elements 31 of each branch in the inverter circuit 20 and a gate drive device 40. The gate drive device 40 is a gate drive circuit of the semiconductor switching element (6). Based on the DC power supplied from the DC power supply to the inverter circuit 20, the inverter circuit 20 outputs AC current to drive the motor 70.

[0117] (14) A semiconductor device comprising: a semiconductor switch element 31 driven and controlled by two independent gate electrodes; and a gate drive circuit for the semiconductor switch element according to any one of (1) to (5).

[0118] (15) A semiconductor device comprising: a semiconductor switch element 31 driven and controlled by two independent gate electrodes; and a gate drive circuit for the semiconductor switch element of (6).

[0119] Explanation of symbols

[0120] 10—DC power supply, 20—inverter circuit, 21—smoothing capacitor, 22—command logic unit, 23—positive electrode connection line, 24—negative electrode connection line, 30—inverter unit, 31—semiconductor switch element, 32—circuit diode, 33—connection point, 40, 40A—gate drive device (gate drive circuit), 41—positive side power supply, 42—first PMOSFET, 43—second PMOSFET, 44—delay control unit, 45—negative side power supply, 46—first NMOSFET, 47—second NMOSFET, 50— Intermediate power supply (power supply of the first voltage), 51—third NMOSFET (gate switch), 52—switching control unit, 70—motor, 100—motor control system, Gs—first gate electrode, Gc—second gate electrode, Hc—first chip, Hs—second chip, Rgcon, Rgson—on-side gate resistance, Rgcoff, Rgsoff—off-side gate resistance (gate resistance), Vth—threshold voltage, VCE—collector-emitter voltage, Vcc—power supply voltage, τGs, τGc—time constants.

Claims

1. A gate drive circuit for a semiconductor switch element, driven and controlled by two independent gate electrodes, characterized in that: The time constant of the gate electrode voltage when the second gate electrode is turned off is set longer than that when the first gate electrode is turned off. The voltage V of the second gate electrode at the time when the maximum power is applied when the semiconductor switch element is turned off is ＊ Satisfying formula (1), Formula (1) 0≤V ＊ ≤Predetermined value<+Vp Wherein, +Vp is the gate drive voltage when the semiconductor switch element is turned on.

2. The gate drive circuit of the semiconductor switch element according to claim 1, characterized in that: The time when the maximum power is applied when the semiconductor switch element is turned off is the time when the collector-emitter voltage of the semiconductor switch element is substantially equal to the power supply voltage when the semiconductor switch element is turned off.

3. The gate drive circuit of the semiconductor switch element according to claim 1, characterized in that: The gate driving circuit includes a gate resistor for controlling a time constant when the second gate electrode is turned off, and a voltage drop at the gate resistor is controlled by adjusting the gate resistor.

4. A gate drive circuit for a semiconductor switch element, driven and controlled by two independent gate electrodes, characterized in that: When the first gate electrode is turned off, the voltage of the first gate electrode is instructed to drop to the negative side power supply voltage. When the second gate electrode is turned off, the voltage of the second gate electrode is commanded to drop to the negative power supply voltage in two stages.

5. The gate drive circuit of the semiconductor switch element according to claim 4, characterized in that: The gate drive circuit comprises a power supply of a first voltage, a gate switch and a switching control unit. The switching control unit first drops the voltage of the second gate electrode to the first voltage, and then drops the voltage of the second gate electrode to the negative power supply voltage of the gate driving circuit after a predetermined time has passed.

6. The gate drive circuit of a semiconductor switch element according to any one of claims 1 to 5, characterized in that: The semiconductor switch element is configured by connecting collector electrodes and emitter electrodes of a first chip having a high hole injection efficiency from the collector side and a second chip having a low hole injection efficiency from the collector side in parallel.

7. The gate drive circuit of the semiconductor switch element according to claim 6, characterized in that: The second gate electrode is connected to the gate of the first chip, and both the first gate electrode and the second gate electrode are connected to the gate of the second chip.

8. The gate drive circuit of the semiconductor switch element according to claim 6, characterized in that: The semiconductor switch element has an n-type semiconductor having a higher impurity concentration than the n-drift layer, provided below the p-base layer sandwiched by the gates and not in contact with the gates.

9. The gate drive circuit of a semiconductor switch element according to claim 1 or 4, characterized in that: The control is performed when the first gate electrode and the second gate electrode simultaneously receive an off signal.

10. The gate drive circuit of the semiconductor switch element according to claim 1, characterized in that: The predetermined value is a threshold voltage of the semiconductor switch element.

11. The gate drive circuit of the semiconductor switch element according to claim 1, characterized in that: The above-mentioned predetermined value is +Vp / 3.

12. A motor control system, characterized in that: The inverter circuit includes semiconductor switching elements and gate drive devices. The gate drive device is a gate drive circuit of a semiconductor switch element according to any one of claims 1 to 5, The inverter circuit outputs an AC current based on the DC power supplied from the DC power source to the inverter circuit to drive the motor.

13. A motor control system, characterized in that: The inverter circuit includes semiconductor switching elements and gate drive devices. The gate driving device is a gate driving circuit of a semiconductor switch element according to claim 6, The inverter circuit outputs an AC current based on the DC power supplied from the DC power source to the inverter circuit to drive the motor.

14. A semiconductor device, characterized in that: have: A semiconductor switch element driven and controlled by two independent gate electrodes; and A gate drive circuit for a semiconductor switch element according to any one of claims 1 to 5.

15. A semiconductor device, characterized in that: have: A semiconductor switch element driven and controlled by two independent gate electrodes; and The gate drive circuit of the semiconductor switch element according to claim 6.

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