Phase lock circuit

Abstract

A phase-locked loop system includes a phase detector for detecting a phase difference between a reference signal and an output of a controllable oscillator circuit. A loop filter may filter an output of the loop filter, and an integrator may integrate the output of the loop filter. An integrator output may be added to the output of the loop filter and may be input to the controllable oscillator circuit, and at least one of a phase and a frequency of the controllable oscillator output may be modified. The loop filter may achieve 40 dB roll-off per decimal and improve attenuation of reference signal noise and local oscillator noise.

Description

[0001] priority

[0002] This application claims priority to commonly owned U.S. Patent Application No. 63 / 436,931 filed on January 4, 2023, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure relates to phase-locked circuits, including but not limited to phase-locked loops (PLLs). Background Art

[0004] In an electronic system, a phase-locked circuit can be used to generate a clock source. The phase-locked circuit can be a phase-locked loop (PLL). The PLL can include a phase detector, a loop filter, and a controllable oscillator circuit. The PLL can receive an input from a reference signal and can generate an output at the output of the controllable oscillator circuit.

[0005] The PLL can be designed to attenuate noise from several noise sources. High frequency noise can be referred to as jitter, while low frequency noise can be referred to as drift. In one example among various examples, the PLL can be designed to attenuate noise in a reference signal, which can also be referred to as reference jitter. The loop filter can be designed as a low pass filter with a low cutoff frequency to eliminate high frequency noise in the reference signal. In one example among various examples, the PLL can be designed to attenuate noise in a local oscillator circuit output. The loop filter can be designed as a high pass filter to filter noise in an oscillator output.

[0006] A PLL can use a higher-order loop filter to attenuate noise to a greater extent than a first-order loop filter. The system designer must target the cutoff frequency of the loop filter to a specific noise source, i.e., a low-pass filter to attenuate reference jitter, or a high-pass filter to attenuate local oscillator noise with the same cutoff frequency.

[0007] What is needed is a PLL that can achieve high order attenuation of both reference noise and oscillator noise. Summary of the invention

[0008] The examples herein implement a phase-locked circuit that achieves high-order attenuation of both reference signal jitter and oscillator jitter.

[0009] According to one aspect, a controllable oscillator circuit generates an oscillation signal. A phase detector circuit generates a phase difference output based on a first input and a second input, the first input being coupled to a reference signal and the second input being coupled to the oscillation signal generated by the controllable oscillator circuit. A loop filter having a frequency selective roll-off filters the phase difference output to generate a filtered phase difference output. A multiplier applies a gain setting to the filtered phase difference output. An integrator integrates the output of the multiplier, and an adder sums the filtered phase difference output and the output of the integrator, wherein the controllable oscillator circuit modifies at least one of a phase and a frequency of the oscillation signal based on the output of the adder.

[0010] According to one aspect, a system includes a first controllable oscillator circuit for generating a phase-locked output. A first phase detector circuit generates a first phase difference output based on a first input and a second input, the first input being coupled to a reference signal and the second input being coupled to the output of the first controllable oscillator circuit. A first loop filter with a frequency selective roll-off filters the first phase difference output to generate a first filtered phase difference output. The first controllable oscillator circuit modifies at least one of a phase and a frequency of a first oscillator signal based on a sum of the first filtered phase difference output and the second filtered phase difference output. A second controllable oscillator circuit generates an oscillation signal at the output of the second controllable oscillator circuit. A second phase detector circuit generates a second phase difference output based on a first input and a second input, the first input receiving the second oscillator signal and the second input being coupled to the output of the second controllable oscillator circuit. A second loop filter with a frequency selective roll-off filters the second phase difference output to generate a second filtered phase difference output, and wherein the second controllable oscillator circuit modifies at least one of a phase and a frequency of the first oscillator signal based on the second filtered phase difference output.

[0011] According to one aspect, an example implementation of the present invention includes the following operations: receiving inputs from a reference signal, a first oscillator signal, and a second oscillator signal; detecting a first phase difference between the reference signal and an output oscillation signal of a first controllable oscillator circuit to generate a first phase difference; detecting a second phase difference between the second oscillator signal and the output oscillation signal of a second controllable oscillator circuit to generate a second phase difference; filtering the first phase difference with a first frequency selective filter; filtering the second phase difference with a second frequency selective filter; driving the first controllable oscillator circuit with the first oscillator signal and an output of an adder, the adder adding the outputs of the first frequency selective filter and the second frequency selective filter, and the output of the adder is used to modify at least one of the phase and frequency of the output oscillation signal of the first controllable oscillator circuit; driving the second controllable oscillator circuit with the first oscillator signal and the output of the second frequency selective filter, the output of the second frequency selective filter being used to modify at least one of the phase and frequency of the output oscillation signal of the second controllable oscillator circuit; and outputting the output oscillation signal of the first controllable oscillator circuit as a phase locked output. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings show examples of phase-locked circuits.

[0013] Figure 1 One of various examples of phase-locked circuits is shown.

[0014] Figure 2 One of various examples of frequency response of a phase locked circuit is shown.

[0015] Figure 3 One of various examples of loop filters is shown.

[0016] Figure 4 One of various examples of frequency response of a phase locked circuit is shown.

[0017] Figure 5 Shows Figure 4 A zoomed-in view of the frequency response of the

[0018] Figure 6 Another example of the various examples of loop filters is shown.

[0019] Figure 7 One of various examples of frequency response of a phase locked circuit is shown.

[0020] Figure 8 Shows Figure 7 A zoomed-in view of the frequency response of the

[0021] Fig. 9One of various examples of dual phase-locked systems is shown.

[0022] Fig.10 One of various examples of frequency response of a dual phase-locked system is shown.

[0023] Fig.11 Shows Fig.10 A zoomed-in view of the frequency response of the

[0024] Fig.12 A method of generating an oscillating signal is shown. DETAILED DESCRIPTION

[0025] Figure 1 An example of various examples of a phase-locked circuit 100 is shown. The phase-locked circuit 100 receives a reference signal 110. The reference signal 110 may be a periodic clock signal provided by a crystal oscillator or by another signal source. The reference signal 110 may include high frequency noise. The noise may also be referred to as jitter. The phase detector circuit 120 may detect a phase difference between the reference signal 110 and a controllable oscillator output 190 of a controllable oscillator circuit 130, and generate a phase difference output based on the phase difference between the reference signal 110 and the controllable oscillator output 190 of the controllable oscillator circuit 130. The controllable oscillator output 190 may be an oscillation signal. The local oscillator 135 may provide an input to the controllable oscillator circuit 130.

[0026] The loop filter 140 may receive the phase difference output of the phase detector circuit 120 and may filter the phase difference output of the phase detector circuit 120 to generate a filtered phase difference output as a loop filter output. The loop filter 140 may be a finite impulse response (FIR) or infinite impulse response (IIR) filter. The loop filter 140 may be a frequency selective filter. The filter order and coefficients of the loop filter 140 may set a specific frequency selective roll-off and may determine the bandwidth of the phase locked circuit 100. A gain setting 155 may be applied at the output of the loop filter 140. The integrator 150 may integrate the output of the gain setting 155 and may generate an integrated signal. The integrator 150 may apply a low pass filter response to the output of the loop filter 140. The output of the integrator 150 may be a first input to the adder 160, and the output of the integrator 150 is applied as a second input to the adder 160. The output of the adder 160 may provide an input to the controllable oscillator circuit 130. The controllable oscillator circuit 130 may generate a controllable oscillator output 190 , and the controllable oscillator circuit 130 may modify at least one of a phase and a frequency of the controllable oscillator output 190 based on the output of the adder 160 .

[0027] The controllable oscillator circuit 130 may be implemented as a current-starved inverter chain, a CMOS inverter chain with switched shunt capacitors, a selectable multiplexer, or another architecture not explicitly mentioned. The controllable oscillator output 190 may be a signal phase-locked to the reference signal 110 by the phase-locked circuit 100 .

[0028] In one example among various examples, the closed-loop response of the phase-locked circuit 100 may be a low-pass response. Based on the design of the phase-locked circuit 100, the low-pass response may attenuate high-frequency noise from the reference signal 110. Based on the design of the phase-locked circuit 100, the high-pass response may attenuate low-frequency noise from the local oscillator 135, which provides a clock for the entire circuit.

[0029] Figure 2 Show according to Figure 1 The illustrated example is one of various examples of a frequency response 200 of a first order phase locked circuit 100 .

[0030] Trace 210 shows the frequency response of noise from the local oscillator 135 to the controllable oscillator circuit 130 measured at the controllable oscillator output 190. The phase locked circuit 100 may apply a high pass response and may attenuate low frequency noise from the local oscillator 135.

[0031] Trace 220 shows the frequency response of noise from the reference signal 110 measured at the controllable oscillator output 190. The phase locked circuit 100 may apply a low pass response and may attenuate high frequency noise from the reference signal 110.

[0032] Figure 2 The frequency response shown represents the response of a first order loop filter. The frequency response rolls off at 20 dB per decade, as Figure 2 Point 221 shows the trace 220 at 1 Hz (10 0 ), point 222 shows the response of trace 220 at 10 Hz (10 1 ) The response is approximately -19 dB at point 221 and approximately -39 dB at point 222, which illustrates a 20 dB per decade roll-off for the first order loop filter.

[0033] The frequency responses shown in traces 210 and 220 are illustrative and not limiting. Different designs of loop filter 140 or different values ​​of gain setting 155 may result in different Figure 2 The corner frequency (corner frequency) shown in FIG has a response with a corner frequency at different positions.

[0034] Figure 3 1 shows one example of various examples of loop filter 300. Loop filter 300 may be represented as follows Figure 1 1 is one example of various examples of loop filter 140 shown. Input signal 305 may be provided to loop filter 140. Input signal 305 may be coupled to a plurality of gain circuits. Figure 3 In the example shown in , input signal 305 may be coupled to three gain circuits, but this is not meant to be limiting.

[0035] exist Figure 3 In the example shown in FIG. , the first gain circuit 310 may apply C p The output of the first gain circuit 310 may be input to the first adder 370. The second gain circuit 320 may apply C p2 The output of the second gain circuit 320 may be input to the first input of the second adder 360. The third gain circuit 330 may apply C p *C p2 The output of the third gain circuit 330 may be input to a first input of the third adder 340. p2 The value of may define a second pole in the response of loop filter 300 and may define the frequency at which loop filter 300 rolls off at a rate of 40 dB / decade.

[0036] The output of the third gain circuit 330 may be input to a first input of a third adder 340. A second input of the third adder 340 may be coupled to the output of the delay circuit 350. The output of the third adder 340 may be coupled to the input of the delay circuit 350 and to the second input of the second adder 360. The feedback path from the output of the third adder 340 to the delay circuit 350 to the second input of the third adder 340 may implement an integration function.

[0037] The output of the second gain circuit 320 may be coupled to a second input of the second adder 360 .

[0038] The output of the first gain circuit 310 may be input to a first input of a first adder 370. The output of the second adder 360 may be coupled to a second input of the first adder 370. The output of the first adder 370 may be a loop filter output 390.

[0039] Figure 4 4 shows one example of various examples of frequency response 400. Frequency response 400 may be represented as shown in FIG. Figure 1 The response of one example of the various examples of the described phase-locked circuit 100 includes the phase-locked circuit 100 as shown in reference Figure 3 The loop filter 300 is described.

[0040] Traces 410, 411, 412, and 413 may illustrate the frequency response of noise from the controllable oscillator circuit 130 for different implementations of the loop filter 300, as measured at the controllable oscillator output 190. Traces 410, 411, 412, and 413 may illustrate the frequency response of the loop filter 300 with different values ​​of coefficients Cp and Cp2. The loop filter 300 may apply a high pass response to the noise from the local oscillator 135, and may attenuate low frequency noise from the local oscillator 135. Traces 420, 421, 422, and 423 may illustrate the frequency response of noise from the reference signal 110 for different implementations of the loop filter 300, as measured at the controllable oscillator output 190. Traces 420, 421, 422, and 423 may illustrate the frequency response of the loop filter 300 with different values ​​of coefficients Cp and Cp2. The loop filter 300 may apply a low-pass response to the noise from the reference signal 110 and may attenuate high frequency noise from the reference signal 110 .

[0041] Loop filter 300 may apply an attenuation with a 40 dB per decade roll-off to the noise from local oscillator 135, such as Figure 4 Point 417 shows that the trace 410 is at 5*10 -1 Hz, and point 418 shows the response of trace 410 at a frequency ten times lower, 5*10 -2 The response is approximately -13 dB at point 417 and approximately -53 dB at point 418, which illustrates a 40 dB per decade roll-off for loop filter 300. Similar roll-offs can be seen for traces 420, 421, 422, and 423.

[0042] Figure 5 An enlarged view 500 of the frequency response 400 is shown. Note that Figure 5 The vertical axis spans from 0.5dB to 1dB, where Figure 4 The vertical axis in spans -70 dB to 0 dB. Traces 520, 521, 522, and 523 illustrate varying overshoot levels in the frequency response of noise from the controllable oscillator circuit 130 for different implementations of the loop filter 300. Traces 510 and 511 illustrate varying roll-off levels in the frequency response of noise from the reference signal 110 for different implementations of the loop filter 300. Different values ​​of gain settings in the first gain circuit 310, the second gain circuit 320, and the third gain circuit 330 may result in different overshoot and roll-off characteristics.

[0043] Figure 61 shows one example of various examples of loop filter 600. Loop filter 600 may be represented as follows: Figure 1 One example of various examples of loop filter 140 shown in FIG. Figure 1 The input signal 605 of the phase difference output of the phase detector 120 shown in FIG. 1 is provided to the loop filter 600. The input signal 605 can be coupled to the first gain circuit 610. The output of the first gain circuit 610 can be coupled to the second gain circuit 620. The output of the second gain circuit 620 can be coupled to the first input of the adder 640. The adder 640 can be part of an integrator that includes the adder 640 and a feedback path that includes a delay circuit 650 and a third gain circuit 660. The output of the adder 640 can be coupled to the input of the delay circuit 650. The output of the delay circuit 650 can be coupled to the third gain circuit 660, and the output of the third gain circuit 660 can be coupled to the second input of the adder 640. The output of the adder 640 can be the loop filter output 690.

[0044] The adder 640 , the delay circuit 650 , and the third gain circuit 660 may include an integrator 680 .

[0045] exist Figure 6 In the example shown in FIG. , the first gain circuit 610 may apply C p The second gain circuit 620 can be applied The third gain circuit 660 can be applied Gain setting. C p2 The value of may define a second pole in the response of loop filter 600 and may define the frequency at which loop filter 600 rolls off at a rate of 40 dB / decade.

[0046] Figure 7 700 is shown as one example among various examples of frequency response 700. Frequency response 700 may be represented as shown in FIG. Figure 1 The response of one example of the various examples of the described phase-locked circuit 100 includes the phase-locked circuit 100 as shown in reference Figure 6 Loop filter 600 is described.

[0047] Traces 710, 711, 712, and 713 may illustrate the frequency response of noise from the controllable oscillator circuit 130 for different implementations of the loop filter 600, as measured at the controllable oscillator output 190. Traces 710, 711, 712, and 713 may illustrate the frequency response of noise from the controllable oscillator circuit 130, as measured at the controllable oscillator output 190, for different implementations of the loop filter 600. p and C p2The frequency response of the loop filter 600 for different values ​​of . The loop filter 600 can apply a high pass response to the noise from the local oscillator 135 and can attenuate the low frequency noise from the local oscillator 135. Traces 720, 721, 722, and 723 can show the frequency response of the noise from the reference signal 110 for different specific implementations of the loop filter 600, as measured at the controllable oscillator output 190. Traces 720, 721, 722, and 723 can show the frequency response of the noise from the reference signal 110 for different specific implementations of the loop filter 600, as measured at the controllable oscillator output 190. p and C p2 The frequency response of the loop filter 600 for different values ​​of . The loop filter 600 may apply a low-pass response to the noise from the reference signal 110 and may attenuate high frequency noise from the reference signal 110.

[0048] The loop filter 600 may apply attenuation with a 40 dB per decade roll-off to the noise from the reference signal 110 in the controllable oscillator output 190, such as Figure 7 Point 717 shows that the trace 721 is at 3*10 - 1 Hz, and point 718 shows the response of trace 721 at a frequency ten times higher, 3*10 0 The response is approximately -18 dB at point 717 and approximately -58 dB at point 718, which illustrates the 40 dB per decade roll-off of loop filter 600.

[0049] Figure 8 An enlarged view 800 of the frequency response 700 is shown. Note that Figure 8 The vertical axis spans from -0.5dB to 1dB, where Figure 7 The vertical axis in spans -70 dB to +2 dB. Traces 820 and 821 show varying roll-off levels in the frequency response of noise from the local oscillator 135 for different implementations of the loop filter 600. Traces 810, 811, 812, and 813 show varying overshoot levels in the frequency response of noise from the controllable oscillator circuit 130 for different implementations of the loop filter 600. Different values ​​of gain settings in the first gain circuit 610, the second gain circuit 620, and the third gain circuit 660 may result in different overshoot and roll-off characteristics.

[0050] Fig. 9An example of a dual phase lock system 900 is shown, which includes a first phase lock circuit 970 and a second phase lock circuit 975. The first phase lock circuit 970 can receive a reference signal 910 as an input to the first phase lock circuit 970. The reference signal 910 can be input to a positive input of a first phase detector circuit 920. The output of the first controllable oscillator circuit 930 can be input to a negative input of the first phase detector circuit 920. The output of the first phase detector circuit 920 can be coupled to an input of a first loop filter 940. The output of the first phase detector circuit 920 can be a first phase difference output. The first loop filter 940 can be a reference signal. Figure 3 or Figure 6 The described loop filter, or first loop filter 940, may be different specific implementations of the loop filter. The first loop filter 940 may be a frequency selective filter. The filter order and coefficients of the first loop filter 940 may set a specific frequency selective roll-off and may determine the bandwidth of the dual phase locked system 900.

[0051] The output of the first loop filter 940 can be coupled to a first input of an adder 950. The output of the adder 950 can be coupled to a first input of a first controllable oscillator circuit 930. A second input of the first controllable oscillator circuit 930 can be coupled to a first oscillator signal 901. The first oscillator signal 901 can also be referred to as a local oscillator signal. The first oscillator signal 901 can be generated by a low-cost crystal oscillator (XO). The output of the first controllable oscillator circuit 930 can be a dual phase-locked system output 990. The dual phase-locked system output 990 can also be referred to as a phase-locked output.

[0052] The second phase locked circuit 975 may receive a second oscillator signal 911 as an input to the second phase locked circuit 975. The second oscillator signal 911 may be generated by a stable oven controlled crystal oscillator (OCXO), a temperature controlled oscillator (TCXO), or another type of stable oscillator not specifically mentioned. The second oscillator signal 911 may be input to the positive input of the second phase detector circuit 921. The output of the second controllable oscillator circuit 931 may be input to the negative input of the second phase detector circuit 921. The output of the second controllable oscillator 931 may be an oscillation signal. The output of the second phase detector circuit 921 may be coupled to the input of the second loop filter 941. The second loop filter 941 may be as described in reference Figure 3 or Figure 6 The described loop filter, or second loop filter 941, may be different specific implementations of the loop filter. The second loop filter 941 may be a frequency selective filter. The filter order and coefficients of the second loop filter 941 may set a specific frequency selective roll-off and may determine the bandwidth of the dual phase locked system 900.

[0053] The output of the second loop filter 941 may be coupled to a first input of the second controllable oscillator circuit 931. The second input of the second controllable oscillator circuit 931 may be coupled to the first oscillator signal 901. The output of the second loop filter 941 may be coupled to a second input of the adder 950.

[0054] In operation, the first loop filter 940 may be a loop filter having a predetermined frequency response. In operation, the second loop filter 941 may be a loop filter having a predetermined frequency response. The dual phase-locked system 900 may apply low-pass filtering to the noise from the reference signal 910. The dual phase-locked system 900 may apply high-pass filtering to the noise from the first oscillator signal 901. The dual phase-locked system 900 may apply band-pass filtering to the noise from the second oscillator signal 911.

[0055] Fig.10 1 shows one example of various examples of frequency response 1000. Frequency response 1000 may be represented as shown in FIG. Fig. 9 A response of one of the various examples of dual phase locked system 900 described.

[0056] Traces 1020, 1021, 1022, and 1023 may illustrate the frequency response of noise from the reference signal 910 for different implementations of the first loop filter 940 and the second loop filter 941, as measured at the dual phase-locked system output 990. The first loop filter 940 and the second loop filter 941 may apply a low-pass response to the noise from the reference signal 910 and may attenuate high frequency noise from the reference signal 910.

[0057] Traces 1010, 1011, 1012, and 1013 may illustrate the frequency response of the noise from the first oscillator signal 901 for different implementations of the first loop filter 940 and the second loop filter 941, as measured at the dual phase-locked system output 990. The first loop filter 940 and the second loop filter 941 may apply a high-pass response to the noise from the first oscillator signal 901 and may attenuate low frequency noise from the first oscillator signal 901.

[0058] Traces 1030, 1031, and 1032 may illustrate the frequency response of the noise from the second oscillator signal 911 for different implementations of the first loop filter 940 and the second loop filter 941, as measured at the dual phase-locked system output 990. The first loop filter 940 and the second loop filter 941 may apply a bandpass response to the noise from the second oscillator signal 911, and may attenuate high frequency noise and low frequency noise from the second oscillator signal 911.

[0059] The first loop filter 940 and the second loop filter 941 may apply an attenuation with a 40 dB roll-off per decade to the noise from the reference signal 910, such as Fig.10 Point 1017 shows that trace 1023 is at 3*10 -1 Hz, and point 1018 shows the response of trace 1023 at a frequency ten times higher, 3*10 0 Hz. The response is approximately -18 dB at point 1017 and approximately -58 dB at point 1018, illustrating a 40 dB per decade roll-off of the combined response of the first loop filter 940 and the second loop filter 941. A similar 40 dB per decade roll-off in trace 1011 is shown between points 1027 and 1028 for the noise from the first oscillator signal 901. The dashed lines from points 1027 and 1028 to the graph axes have been omitted to improve the readability of the graph.

[0060] Fig.11 A magnified view 1100 of the frequency response 1000 is shown. Note that Fig.11 The vertical axis spans from -0.5dB to 1dB, where Figure 7 The vertical axis in spans -70 dB to +2 dB. Traces 1120 and 1121 show varying roll-off levels in the frequency response of noise from the reference signal 910 for different implementations of the first loop filter 940 and the second loop filter 941. Traces 1130, 1131, 1132, 1133, and 1134 show varying overshoot levels in the frequency response of noise from the second oscillator signal 911 for different implementations of the first loop filter 940 and the second loop filter 941. Traces 1110, 1111, and 1112 show varying roll-off levels in the frequency response of noise from the first oscillator signal 901 for different implementations of the first loop filter 940 and the second loop filter 941.

[0061] Fig.12 A method of generating an oscillating signal is shown.

[0062] At operation 1205 , a reference signal, a first oscillator signal, and a second oscillator signal may be received as inputs.

[0063] At operation 1210 , a first phase difference between a reference signal and an output of a first controllable oscillator circuit may be detected, for example, by the first phase detector circuit 920 to generate a first phase difference.

[0064] At operation 1220 , a second phase difference between the second oscillator signal and the output of the second controllable oscillator circuit may be detected, for example, by the second phase detector circuit 921 to generate a second phase difference.

[0065] At operation 1230, the first phase difference may be filtered with a first frequency selective filter (eg, by the first loop filter 940). At operation 1235, the second phase difference may be filtered with a second frequency selective filter (eg, by the second loop filter 941).

[0066] At operation 1240, the first controllable oscillator circuit can be driven with the first oscillator signal and the output of the adder, for example, the first controllable oscillator circuit 930 can be driven by the output of the adder 950. The adder can sum the output of the first frequency selective filter and the output of the second frequency selective filter. The output of the adder can modify at least one of the phase and frequency of the output oscillator signal of the first controllable oscillator circuit.

[0067] At operation 1250, a second controllable oscillator circuit may be driven with the first oscillator signal and the output of the second frequency selective filter, for example, the second controllable oscillator circuit 931 may be driven by the first oscillator signal 901 and the output of the second loop filter 941. The output of the second frequency selective filter may modify at least one of the phase and frequency of the output oscillator signal of the second controllable oscillator circuit.

[0068] At operation 1260 , the output of the first controllable oscillator circuit may be provided as a phase-locked output.

Claims

1. A device, comprising: a controllable oscillator circuit, the controllable oscillator circuit being used to generate an oscillation signal, the controllable oscillator circuit receiving an input from a local oscillator; a phase detector circuit for generating a phase difference output based on a first input coupled to a reference signal and a second input coupled to the oscillating signal generated by the controllable oscillator circuit; a loop filter having a frequency selective roll-off to filter the phase difference output to generate a filtered phase difference output; a multiplier for applying a gain setting to the filtered phase difference output; a first integrator, the first integrator being used to integrate the output of the multiplier; as well as an adder for summing the filtered phase difference output and the output of the first integrator, wherein: The controllable oscillator circuit is used to modify at least one of a phase and a frequency of the oscillating signal based on an output of the adder.

2. The apparatus according to claim 1, wherein: The loop filter is used to receive an input signal; The input signal is coupled to a first gain circuit, a second gain circuit, and a third gain circuit; The output of the first gain circuit is coupled to a first input of a first adder; The output of the second gain circuit is coupled to a first input of a second adder; The output of the third gain circuit is coupled to the integrator input; The integrator output is coupled to a second input of the second adder; The output of the second adder is coupled to the second input of the first adder; and The output of the first adder is coupled to the loop filter output.

3. The apparatus of claim 2, wherein the loop filter is configured to attenuate noise in the reference signal.

4. The apparatus of any one of claims 2 to 3, wherein the loop filter is used to attenuate noise in the input from the local oscillator.

5. The apparatus of any one of claims 2 to 4, wherein the first gain circuit is for applying a first gain setting, the second gain circuit is for applying a second gain setting, and the third gain circuit is for applying a third gain setting.

6. The apparatus according to any one of claims 1 to 5, wherein: The loop filter is used to receive an input signal; The input signal is coupled to a first gain circuit; The output of the first gain circuit is coupled to a second gain circuit; The output of the second gain circuit is coupled to a second integrator; The second integrator includes a third adder; The feedback path includes a delay circuit connected in series with the third gain circuit; The output of the second gain circuit is coupled to the first input of the third adder; the output of the third gain circuit is coupled to the second input of the third adder; and The loop filter output is coupled to the output of the third adder.

7. A system, comprising: a first controllable oscillator circuit for generating a phase-locked output; a first phase detector circuit for generating a first phase difference output based on a first input and a second input, the first input being coupled to a reference signal and the second input being coupled to an output of the first controllable oscillator circuit; a first loop filter having a frequency selective roll-off to filter the first phase difference output to generate a first filtered phase difference output, and wherein: a first controllable oscillator circuit that modifies at least one of a phase and a frequency of a first oscillator signal based on a sum of the first filtered phase difference output and the second filtered phase difference output; a second controllable oscillator circuit for generating an oscillating signal at an output of the second controllable oscillator circuit; a second phase detector circuit for generating a second phase difference output based on a first input and a second input, the first input receiving a second oscillator signal and the second input coupled to an output of the second controllable oscillator circuit, and a second loop filter having a frequency selective roll-off to filter the second phase difference output to generate the second filtered phase difference output, wherein: The second controllable oscillator circuit is for modifying at least one of a phase and a frequency of the first oscillator signal based on the second filtered phase difference output.

8. The system of claim 7, the first frequency selective filter comprising a low pass filter and the second frequency selective filter comprising a low pass filter.

9. The apparatus of any one of claims 7 to 8, the first loop filter receiving an input signal, the input signal being coupled to a first gain circuit, a second gain circuit, and a third gain circuit, wherein an output of the first gain circuit is coupled to a first input of a first adder, an output of the second gain circuit is coupled to a first input of a second adder, and an output of the third gain circuit is coupled to an integrator input, the integrator output is coupled to a second input of the second adder, an output of the second adder is coupled to a second input of the first adder, and an output of the first adder is coupled to the first loop filter output.

10. The apparatus of any one of claims 7 to 9, the second loop filter receiving an input signal, the input signal being coupled to a first gain circuit, an output of the first gain circuit being coupled to a second gain circuit, an output of the second gain circuit being coupled to an integrator, the integrator comprising an adder, a feedback path comprising a delay circuit in series with a third gain circuit, wherein the output of the second gain circuit is coupled to a first input of the adder, the output of the third gain circuit is coupled to a second input of the adder, and the second loop filter output is coupled to the output of the adder.

11. A method comprising: receiving inputs from a reference signal, a first oscillator signal, and a second oscillator signal; detecting a first phase difference between the reference signal and an output oscillation signal of a first controllable oscillator circuit to generate a first phase difference; detecting a second phase difference between the second oscillator signal and an output oscillation signal of a second controllable oscillator circuit to generate a second phase difference; filtering the first phase difference using a first frequency selective filter; filtering the second phase difference using a second frequency selective filter; driving the first controllable oscillator circuit with the first oscillator signal and the output of an adder, the adder adding the outputs of the first frequency selective filter and the second frequency selective filter, and the output of the adder being used to modify at least one of the phase and the frequency of the output oscillation signal of the first controllable oscillator circuit; driving the second controllable oscillator circuit with the first oscillator signal and the output of the second frequency selective filter, and the output of the second frequency selective filter being used to modify at least one of the phase and the frequency of the output oscillation signal of the second controllable oscillator circuit; as well as The output oscillation signal of the first controllable oscillator circuit is output as a phase locked output.

12. The method of claim 11, wherein the first frequency selective filter comprises a low pass filter.

13. The method of any one of claims 11 to 12, wherein the second frequency selective filter comprises a low pass filter.

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