Incremental encoder signal capacity expansion synchronous circuit

Abstract

The invention provides an incremental encoder signal capacity expansion synchronous circuit, which is positioned between an incremental encoder or a normalization circuit and a rear-end processing circuit, and comprises a jitter elimination circuit module, a shaping circuit module and a signal conversion circuit module which are arranged in sequence, the jitter elimination circuit module comprises a resistor unit and a diode unit which are arranged in parallel and a capacitor unit which is connected with the resistor unit and the diode unit respectively, and the front ends of the resistor unit and the diode unit are connected with the incremental encoder or an output signal unit of the normalization circuit; the shaping circuit module comprises a digital circuit unit connected with the jitter elimination circuit module, the digital circuit unit is used for converting irregular trend signals output from the jitter elimination circuit module into standard TTL level, and the signal conversion circuit module comprises an RS-422 driving chip connected with the digital circuit unit. The RS-422 driving chip is used for converting a standard TTL (Transistor-Transistor Logic) level into a differential signal;

Description

Technical Field

[0001] The invention relates to the technical field of circuit control, and in particular to an incremental encoder signal expansion synchronization circuit. Background Art

[0002] In the existing technology, incremental encoders are mostly used in the fields of electronic circuit design, automated control, precision measurement, instrument design, rail transit detection, etc. to control signal transmission. At present, the signals output by incremental encoders are generally single-ended distribution, and their application in application scenarios such as multi-axis synchronous control, automated production lines, and triggering multi-device actions is very limited. In addition, the signals output by incremental encoders receive a lot of interference during transmission to the back-end processing circuit, which makes the signals reaching the back-end processing circuit not pure enough, affecting the system stability and reliability. Summary of the invention

[0003] In view of the shortcomings of the prior art, the purpose of the present invention is to provide an incremental encoder signal expansion synchronization circuit, aiming to solve the technical problem that in the prior art, the signals output by the incremental encoder are generally single-ended distribution, and are very limited in application scenarios such as multi-axis synchronous control, automated production lines, and triggering multi-device actions. In addition, the signals output by the incremental encoder receive a lot of interference during transmission to the back-end processing circuit, which makes the signal reaching the back-end processing circuit not pure enough, affecting the stability and reliability of the system.

[0004] In order to achieve the above object, the present invention is implemented by the following technical solutions:

[0005] A signal expansion synchronization circuit for an incremental encoder is located between an incremental encoder or a normalization circuit and a back-end processing circuit, and is characterized in that the signal expansion synchronization circuit for the incremental encoder includes an anti-jitter circuit module, a shaping circuit module, and a signal conversion circuit module which are arranged in sequence, the anti-jitter circuit module includes a resistor unit and a diode unit which are arranged in parallel with each other, and a capacitor unit which is respectively connected to the resistor unit and the diode unit, the front ends of the resistor unit and the diode unit are connected to the output signal unit of the incremental encoder or the normalization circuit, the shaping circuit module includes a digital circuit unit connected to the anti-jitter circuit module, the digital circuit unit is used to convert an irregular trend signal output from the anti-jitter circuit module into a standard TTL level, the signal conversion circuit module includes an RS-422 driver chip connected to the digital circuit unit, and the RS-422 driver chip is used to convert the standard TTL level into a differential signal.

[0006] According to one aspect of the above technical solution, the output signal unit of the incremental encoder or the normalization circuit includes an A-phase single-ended signal and a B-phase single-ended signal.

[0007] According to one aspect of the above technical solution, the resistance unit includes a resistor R1 connected to the A-phase single-ended signal, and a resistor R2 connected to the B-phase single-ended signal, the diode unit includes a diode D1 connected to the A-phase single-ended signal, and a diode D2 connected to the B-phase single-ended signal, and the capacitor unit includes a capacitor C1 connected to the resistor R1 and the diode D1, respectively, and a capacitor C2 connected to the resistor R2 and the diode D2, respectively.

[0008] According to one aspect of the above technical solution, ends of the capacitor C1 and the capacitor C2 are both grounded.

[0009] According to one aspect of the above technical solution, the digital circuit unit includes an OR gate U1A and an OR gate U1C connected to the resistor R1, and an OR gate U1B and an OR gate U1D connected to the resistor R2.

[0010] According to one aspect of the above technical solution, the RS-422 driver chip includes a first IC chip U2 and a second IC chip U3.

[0011] According to one aspect of the above technical solution, one end of the first IC chip U2 is connected to the OR gate U1A through pin 1, and the other end is connected to the back-end processing circuit through pins 2 and 3; one end of the second IC chip U3 is connected to the OR gate U1A through pin 1, and the other end is connected to the back-end processing circuit through pins 2 and 3; one end of the first IC chip U2 is connected to the OR gate U1C through pin 9, and the other end is connected to the back-end processing circuit through pins 10 and 11; one end of the second IC chip U3 is connected to the OR gate U1C through pin 9, and the other end is connected to the back-end processing circuit through pins 10 and 11.

[0012] According to one aspect of the above technical solution, one end of the first IC chip U2 is connected to the OR gate U1B through pin 7, and the other end is connected to the back-end processing circuit through pins 6 and 5; one end of the second IC chip U3 is connected to the OR gate U1B through pin 7, and the other end is connected to the back-end processing circuit through pins 6 and 5; one end of the first IC chip U2 is connected to the OR gate U1D through pin 15, and the other end is connected to the back-end processing circuit through pins 14 and 13; one end of the second IC chip U3 is connected to the OR gate U1D through pin 15, and the other end is connected to the back-end processing circuit through pins 14 and 13.

[0013] According to one aspect of the above technical solution, the first IC chip U2 is connected to the voltage supply terminal through the 4th pin, and is connected to the ground terminal through the 12th pin and the 8th pin.

[0014] According to one aspect of the above technical solution, the second IC chip U3 is connected to the voltage supply terminal through the 4th pin, and is connected to the ground terminal through the 12th pin and the 8th pin.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] By setting an incremental encoder signal expansion synchronization circuit between the incremental encoder or normalization circuit and the back-end processing circuit, including an anti-jitter circuit module, a shaping circuit module, and a signal conversion circuit module which are arranged in sequence, when the signal sent by the incremental encoder or the normalization circuit is received, the burrs and noise in the signal are first filtered out by the combination of the resistance unit, the diode unit and the capacitor unit in the anti-jitter circuit module to ensure that the signal is smooth and stable; then the signal after the anti-jitter processing is reshaped into a standard square wave pulse signal by the digital circuit unit in the shaping circuit unit. The reason is that the output signal of the encoder is transmitted over a long distance or is interfered with. The edge may become irregular. The shaping circuit module can restore the input signal to a standard TTL level square wave signal through logic circuits such as Schmitt triggers to improve the signal's anti-interference ability and ensure that the signal can be accurately identified and processed in different terminals of the back-end processing circuit, further improving the accuracy of signal transmission. Finally, the RS-422 driver chip in the signal conversion circuit module converts the single-ended TTL signal output by the encoder into two differential signals with opposite phases to each other, which can provide strong anti-interference ability and signal integrity in long-distance transmission, facilitate stable transmission of signals over long distances or between multiple terminals, thereby realizing synchronous control of different terminal devices.

[0017] The incremental encoder signal expansion synchronization circuit in the present invention can realize the functions of: synchronous data collection by multiple terminals, triggering actions of multiple application terminals, signal isolation and amplification, improving system reliability, and facilitating system expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the incremental encoder signal expansion synchronization circuit in the entire control circuit in the first embodiment of the present invention;

[0019] Figure 2 for Figure 1 Structural diagram of the incremental encoder signal expansion synchronization circuit Figure 1 ;

[0020] Figure 3 for Figure 1 Structural diagram of the incremental encoder signal expansion synchronization circuit Figure 2 ;

[0021] Description of main component symbols:

[0022]

[0023] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0024] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0025] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0027] See also Figures 1 to 3 , shown is an incremental encoder signal expansion synchronization circuit 20 in the first embodiment of the present invention, which is located between the incremental encoder or normalization circuit 10 and the back-end processing circuit 30, and the incremental encoder signal expansion synchronization circuit 20 includes an anti-jitter circuit module 21, a shaping circuit module 22, and a signal conversion circuit module 23 arranged in sequence, the anti-jitter circuit module 21 includes a resistor unit and a diode unit arranged in parallel with each other, and a capacitor unit connected to the resistor unit and the diode unit respectively, the front end of the resistor unit and the diode unit is connected to the output signal unit of the incremental encoder or normalization circuit 10, the shaping circuit module 22 includes a digital circuit unit connected to the anti-jitter circuit module 21, the digital circuit unit is used to convert the irregular trend signal output from the anti-jitter circuit module 21 into a standard TTL level, the signal conversion circuit module 23 includes an RS-422 driver chip connected to the digital circuit unit, and the RS-422 driver chip is used to convert the standard TTL level into a differential signal.

[0028] It can be understood that the present invention sets an incremental encoder signal expansion synchronization circuit 30 between the incremental encoder or normalization circuit 10 and the back-end processing circuit, which includes an anti-jitter circuit module 21, a shaping circuit module 22, and a signal conversion circuit module 23 arranged in sequence. After receiving the signal sent by the incremental encoder or normalization circuit 10, the burrs and noise in the signal are first filtered out by the combination of the resistor unit, the diode unit and the capacitor unit in the anti-jitter circuit module 21 to ensure that the signal is smooth and stable; then, the signal after the anti-jitter processing is reshaped into a standard square wave pulse signal by the digital circuit unit in the shaping circuit unit. The reason is that the output signal of the encoder is transmitted over a long distance or After being interfered, the edge of the signal may become irregular. The shaping circuit module 22 can restore the input signal to a standard TTL level square wave signal through a logic circuit such as a Schmitt trigger to improve the signal's anti-interference ability, ensure that the signal can be accurately identified and processed in different terminals of the back-end processing circuit, and further improve the accuracy of signal transmission; finally, the RS-422 driver chip in the signal conversion circuit module 23 converts the single-ended TTL signal output by the encoder into two differential signals with opposite phases to each other, which can provide strong anti-interference ability and signal integrity in long-distance transmission, facilitate stable transmission of signals over long distances or between multiple terminals, thereby realizing synchronous control of different terminal devices;

[0029] The incremental encoder signal expansion synchronization circuit in the present invention can realize the following functions: synchronous data collection by multiple terminals, triggering the actions of multiple application terminals, signal isolation and amplification, improving the reliability of the system, and facilitating system expansion;

[0030] Specifically, multiple terminals synchronously collect data: In some complex industrial control systems, multiple devices (such as motion controllers, PLCs, position feedback devices, etc.) may need to share the signal of the same encoder. Through signal expansion, the encoder's pulse signal can be distributed to multiple terminal devices, enabling multiple control systems to synchronously obtain position signals, thereby synchronously controlling and monitoring;

[0031] Triggering actions of multiple application terminals: After the incremental encoder signal is expanded, the signal can trigger the execution of multiple different application terminals at the same time. For example, in some application scenarios, the encoder pulse signal may need to trigger several control systems at the same time to start, stop or adjust different device operations. Through expansion, synchronization signals can be sent to multiple devices at the same time to ensure the time consistency of their actions;

[0032] Signal isolation and amplification: During the signal expansion process, signal isolation or buffers are usually used to protect the encoder output. There may be different electrical noise or interference between multiple terminal devices. Isolation after signal expansion can reduce interference, protect the encoder and ensure signal integrity. At the same time, the expansion circuit can amplify the signal, so that the encoder signal can maintain stable transmission over a longer distance without being affected by cable loss;

[0033] Improve system reliability: If multiple devices need to receive signals from the same encoder, directly connecting the encoder signal in parallel to multiple devices may cause signal attenuation and increased noise, which in turn affects system reliability. Through capacity expansion, the encoder signal can be independently and stably provided to each terminal device to avoid signal distortion or errors caused by excessive load. In situations where multiple devices work together, signal capacity expansion can ensure stable transmission of encoder signals and reduce the risk of single point failures;

[0034] Facilitate system expansion: Encoder signal expansion can facilitate system expansion. When adding new devices or terminals to the original system, encoder signals can be directly obtained from the signal expansion device without changing the existing hardware architecture. This can reduce the additional wiring and debugging work caused by system expansion.

[0035] Specifically, in this embodiment, the output signal unit of the incremental encoder or normalization circuit 10 includes an A-phase single-ended signal 11 and a B-phase single-ended signal 12; the resistor unit includes a resistor R1 connected to the A-phase single-ended signal 11, and a resistor R2 connected to the B-phase single-ended signal 12; the diode unit includes a diode D1 connected to the A-phase single-ended signal 11, and a diode D2 connected to the B-phase single-ended signal 12; the capacitor unit includes a capacitor C1 connected to the resistor R1 and the diode D1, respectively, and a capacitor C2 connected to the resistor R2 and the diode D2, respectively; ends of the capacitor C1 and the capacitor C2 are both grounded.

[0036] It can be understood that in this embodiment, taking two single-ended signals (A-phase single-ended signal 11 and B-phase single-ended signal 12) as an example, during the transmission of the output signal unit of the incremental encoder or normalization circuit 10, burrs or noise may appear on the signal edge due to mechanical movement, jitter or interference. The de-jitter circuit filters out these burr signals through a combination of resistor R1 (R1=470Ω), capacitor C1 (C1=10pF) and diode D1 (D1=1N5819G), ensuring that the transmission of the A-phase single-ended signal 11 is smoother and more stable; similarly, the combination of resistor R2 (R2=470Ω), capacitor C2 (C2=10pF) and diode D2 (D2=1N5819G) filters out these burr signals, ensuring that the transmission of the B-phase single-ended signal 12 is smoother and more stable.

[0037] The principle is that the de-jitter circuit absorbs sudden high-frequency interference (burr signal) through the charging and discharging process of the capacitor. At the same time, the diode provides protection, and the resistor and capacitor form a low-pass filter, which can filter out unnecessary high-frequency noise and avoid false triggering of the signal. It effectively eliminates the burr signal caused by mechanical jitter or electrical noise, ensuring that the encoder's pulse signal is cleaner and more stable, which is convenient for subsequent shaping circuit processing.

[0038] Furthermore, the digital circuit unit includes an OR gate U1A and an OR gate U1C connected to the resistor R1, and an OR gate U1B and an OR gate U1D connected to the resistor R2.

[0039] It can be understood that the main function of the shaping circuit module 22 is to reshape the signal after de-jittering into a standard square wave pulse signal. After the encoder output signal is transmitted over a long distance or is interfered with, the edge of the signal may become irregular. The shaping circuit restores the input signal to a standard TTL level square wave signal through logic circuits such as Schmitt triggers.

[0040] The principle is that the OR gate U1A and the OR gate U1C can identify the high and low levels of the A-phase single-ended signal 11 after de-bouncing, and convert the irregular trend signal into a clear rising level signal or a falling level signal (standard TTL level) through the state output; similarly, the OR gate U1B and the OR gate U1D can identify the high and low levels of the B-phase single-ended signal 12 after de-bouncing, and convert the irregular trend signal into a clear rising level signal or a falling level signal through the state output. This shaping method can enhance the signal's anti-interference ability and ensure the stability of the signal, and shape the de-bouncing signal into a stable pulse signal, ensuring that the signal can be accurately identified and processed in different terminals, further improving the accuracy of signal transmission.

[0041] Furthermore, the RS-422 driver chip includes a first IC chip U2 and a second IC chip U3.

[0042] Specifically, one end of the first IC chip U2 is connected to the OR gate U1A through the 1st pin, and the other end is connected to the back-end processing circuit through the 2nd and 3rd pins, one end of the second IC chip U3 is connected to the OR gate U1A through the 1st pin, and the other end is connected to the back-end processing circuit through the 2nd and 3rd pins, one end of the first IC chip U2 is connected to the OR gate U1C through the 9th pin, and the other end is connected to the back-end processing circuit through the 10th and 11th pins, one end of the second IC chip U3 is connected to the OR gate U1C through the 9th pin, and the other end is connected to the back-end processing circuit through the 10th and 11th pins; one end of the first IC chip U2 is connected to the OR gate U1B through the 7th pin, and the other end is connected to the back-end processing circuit through the 6th and 11th pins. Pin 5 is connected to the back-end processing circuit, one end of the second IC chip U3 is connected to the OR gate U1B through pin 7, and the other end is connected to the back-end processing circuit through pins 6 and 5, one end of the first IC chip U2 is connected to the OR gate U1D through pin 15, and the other end is connected to the back-end processing circuit through pins 14 and 13, one end of the second IC chip U3 is connected to the OR gate U1D through pin 15, and the other end is connected to the back-end processing circuit through pins 14 and 13; the first IC chip U2 is connected to the voltage supply end through pin 4, and is connected to the ground end through pins 12 and 8; the second IC chip U3 is connected to the voltage supply end through pin 4, and is connected to the ground end through pins 12 and 8.

[0043] It can be understood that RS-422 is a differential signal transmission standard that can provide strong anti-interference ability and signal integrity in long-distance transmission. The function of the single-ended to RS-422 circuit is to convert the single-ended TTL signal of the encoder into a differential signal, which is convenient for the signal to be transmitted over long distances or between multiple terminals. The principle is to convert the single-ended signal into two differential signals that are inverted to each other through a differential driver (such as the RS-422 driver chip AM26LS31CDR). Differential transmission can maintain signal integrity in a high-noise environment, because the receiving end identifies the signal by comparing the voltage difference between the two signal lines, thereby offsetting external interference. The converted RS-422 differential signal has high anti-interference ability and is suitable for long-distance signal transmission in an industrial environment. It can ensure that the encoder's signal can remain stable even in long-distance transmission, thereby realizing synchronous control of different terminal devices.

[0044] In the specific embodiment, the shaped A-phase single-ended signal 11 passes through the 1st pin of the first IC chip U2 and the 1st pin of the second IC chip U3, and is output from the 2nd and 3rd pins of the first IC chip U2 and the second IC chip U3, as well as passes through the 9th pin of the first IC chip U2 and the 9th pin of the second IC chip U3, and is output from the 10th and 11th pins of the first IC chip U2 and the second IC chip U3; the shaped B-phase single-ended signal 12 passes through the 7th pin of the first IC chip U2 and the 7th pin of the second IC chip U3, and is output from the 6th and 5th pins of the first IC chip U2 and the second IC chip U3, as well as passes through the 15th pin of the first IC chip U2 and the 15th pin of the second IC chip U3, and is output from the 14th and 13th pins of the first IC chip U2 and the second IC chip U3.

[0045] In summary, the incremental encoder signal expansion synchronization circuit in the above embodiments of the present invention can realize: synchronous data collection by multiple terminals, triggering the actions of multiple application terminals, signal isolation and amplification, improving system reliability, and facilitating system expansion.

[0046] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0047] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An incremental encoder signal expansion synchronization circuit, located between the incremental encoder or normalization circuit and the back-end processing circuit, characterized in that: The incremental encoder signal expansion synchronization circuit includes an anti-jitter circuit module, a shaping circuit module, and a signal conversion circuit module which are arranged in sequence. The anti-jitter circuit module includes a resistor unit and a diode unit which are arranged in parallel with each other, and a capacitor unit which is respectively connected to the resistor unit and the diode unit. The front ends of the resistor unit and the diode unit are connected to the output signal unit of the incremental encoder or the normalization circuit. The shaping circuit module includes a digital circuit unit connected to the anti-jitter circuit module. The digital circuit unit is used to convert the irregular trend signal output from the anti-jitter circuit module into a standard TTL level. The signal conversion circuit module includes an RS-422 driver chip connected to the digital circuit unit. The RS-422 driver chip is used to convert the standard TTL level into a differential signal.

2. The incremental encoder signal expansion synchronization circuit according to claim 1, characterized in that: The output signal unit of the incremental encoder or the normalization circuit includes an A-phase single-ended signal and a B-phase single-ended signal.

3. The incremental encoder signal expansion synchronization circuit according to claim 2, characterized in that: The resistance unit includes a resistor R1 connected to the A-phase single-ended signal, and a resistor R2 connected to the B-phase single-ended signal. The diode unit includes a diode D1 connected to the A-phase single-ended signal, and a diode D2 connected to the B-phase single-ended signal. The capacitor unit includes a capacitor C1 connected to the resistor R1 and the diode D1, respectively, and a capacitor C2 connected to the resistor R2 and the diode D2, respectively.

4. The incremental encoder signal expansion synchronization circuit according to claim 3, characterized in that: Ends of the capacitor C1 and the capacitor C2 are both grounded.

5. The incremental encoder signal expansion synchronization circuit according to claim 3, characterized in that: The digital circuit unit includes an OR gate U1A and an OR gate U1C connected to the resistor R1, and an OR gate U1B and an OR gate U1D connected to the resistor R2.

6. The incremental encoder signal expansion synchronization circuit according to claim 5, characterized in that: The RS-422 driver chip includes a first IC chip U2 and a second IC chip U3.

7. The incremental encoder signal expansion synchronization circuit according to claim 6, characterized in that: One end of the first IC chip U2 is connected to the OR gate U1A through pin 1, and the other end is connected to the back-end processing circuit through pins 2 and 3; one end of the second IC chip U3 is connected to the OR gate U1A through pin 1, and the other end is connected to the back-end processing circuit through pins 2 and 3; one end of the first IC chip U2 is connected to the OR gate U1C through pin 9, and the other end is connected to the back-end processing circuit through pins 10 and 11; one end of the second IC chip U3 is connected to the OR gate U1C through pin 9, and the other end is connected to the back-end processing circuit through pins 10 and 11.

8. The incremental encoder signal expansion synchronization circuit according to claim 7, characterized in that: One end of the first IC chip U2 is connected to the OR gate U1B through pin 7, and the other end is connected to the back-end processing circuit through pins 6 and 5. One end of the second IC chip U3 is connected to the OR gate U1B through pin 7, and the other end is connected to the back-end processing circuit through pins 6 and 5. One end of the first IC chip U2 is connected to the OR gate U1D through pin 15, and the other end is connected to the back-end processing circuit through pins 14 and 13. One end of the second IC chip U3 is connected to the OR gate U1D through pin 15, and the other end is connected to the back-end processing circuit through pins 14 and 13.

9. The incremental encoder signal expansion synchronization circuit according to claim 8, characterized in that: The first IC chip U2 is connected to the voltage supply terminal through the 4th pin, and is connected to the ground terminal through the 12th pin and the 8th pin.

10. The incremental encoder signal expansion synchronization circuit according to claim 9, characterized in that: The second IC chip U3 is connected to the voltage supply terminal through the 4th pin, and is connected to the ground terminal through the 12th pin and the 8th pin.

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