Surface enhanced Raman spectroscopy chip on textured substrate

Abstract

A method of manufacturing a chip for surface enhanced Raman spectroscopy (SERS) includes: providing a substrate; texturing the surface of the substrate to randomly form a plurality of pillars on the surface until a desired average pillar height, average pillar width, and / or pillar density is achieved; depositing a metal onto the surface of the textured substrate; and thermally annealing the metal such that the metal forms a layer surrounding the pillar.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 542,143 filed on October 3, 2023 and U.S. Provisional Patent Application No. 63 / 542,884 filed on October 6, 2023. The disclosures of U.S. Provisional Patent Application No. 63 / 542,143 and U.S. Provisional Patent Application No. 63 / 542,884 are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to Raman spectroscopy devices and, more particularly, to surface enhanced Raman spectroscopy (SERS) chips on textured substrates. Background Art

[0004] Many Raman spectroscopy devices are commercially available for a variety of spectroscopy applications. Providing users with accessories for these Raman spectroscopy products is a logical step. Considering that many applications of Raman spectroscopy require low concentrations and / or fragile samples, it is necessary to provide users with SERS chips that allow for higher sensitivity while using lower laser powers and smaller sample sizes.

[0005] SERS chips are a common research area in academia. Current research areas include, but are not limited to: increased electric field enhancement through smaller nanogaps between metal nanoparticles, lithography-free manufacturing, higher laser-induced damage threshold (LIDT), single-molecule detection, lower background fluorescence, broadband response, and higher reproducibility. While all of these sub-research areas are innovative in their own right, there has long been a need for a SERS chip that can simultaneously address many of these issues, including lithography-free manufacturing, higher LIDT, lower background fluorescence, broadband response, long shelf life, and higher reproducibility. Previous attempts have not been successful because, generally speaking, only one or two of these issues are addressed in the work of any given academic group. In addition, commercial vendors typically design these chips to address one major problem at a time. For example, there is a SERS chip on the market that can withstand a very high laser threshold, but it cannot be used for excitation wavelengths other than 785 nanometers. In addition, there is a SERS chip that does not require lithography but has a significant fluorescence background signal. Summary of the invention

[0006] Traditionally, SERS chips rely on the tight tolerances of lithography and other nanofabrication techniques to reduce the inter-particle distance in the XY plane and allow extremely high electric field enhancements. For chips that utilize "random" nanoparticles or non-periodic surfaces, the substrate on which the chip is manufactured is typically flat in the XY direction with minimal surface roughness or features in the Z axis. In one embodiment of the present disclosure, the SERS chip utilizes a textured substrate, which is typically the opposite of traditional methods with a flat substrate. Although the present disclosure proposes a design that is opposite to the traditional design, the innovation lies in changing the gap distance between the metal surfaces in the vertical direction (z-axis) of the nanopillars to allow for a broadband response.

[0007] According to one embodiment of the present disclosure, a surface enhanced Raman spectroscopy (SERS) chip on a substrate (e.g., fused silica (FS) or Al2O3 sapphire substrate) represents a combination of a textured surface for plasmon response with additional metal deposition (primarily gold, but may also include silver, aluminum, and other metals with negative real dielectric constants in the Raman excitation range). The varying column width allows for a broadband plasmon response to incident light as one moves from the tip to the base. This plasmon response results in a significant electric field enhancement, which allows for enhanced nonlinear Raman scattering effects. In addition, adjusting the height of the column and the thickness of the gold outer coating can change the SERS enhancement and fluorescence response. These parameters (column height and metal thickness) can be adjusted to optimize the SERS signal and minimize the fluorescence signal in existing Raman systems as well as Raman systems utilizing embodiments of the present disclosure.

[0008] An embodiment of the present disclosure provides a method for manufacturing a chip for surface enhanced Raman spectroscopy (SERS), comprising: providing a substrate; texturing the surface of the substrate to randomly form a plurality of pillars on the surface until a desired average pillar height, average pillar width and / or pillar density is reached; depositing a metal onto the surface of the textured substrate; and thermally annealing the metal so that the metal forms a layer surrounding the pillars.

[0009] An embodiment of the present disclosure provides a chip for surface enhanced Raman spectroscopy (SERS), comprising: a substrate having a textured surface, a plurality of columns randomly formed on the textured surface, the columns having a desired average column height, average column width and / or column density; wherein the plurality of columns are surrounded by a thermally annealed metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A high-level process for fabricating a SERS chip according to one embodiment is shown.

[0011] Figure 2 The light-matter interaction of the excitation laser and the gold coating of a SERS chip according to one embodiment is shown.

[0012] Figure 3 A side view of a SERS chip according to one embodiment is shown, highlighting the random pillar height and periodicity.

[0013] Figure 4 Shown is the performance of a blank FS flat substrate sample compared to a flat FS substrate sample with gold deposited on the surface according to one embodiment.

[0014] Figure 5 The performance of an unannealed sample compared to an annealed sample according to one embodiment is shown.

[0015] Figure 6 A performance comparison of a planar substrate and a textured substrate is shown according to one embodiment.

[0016] Figure 7 A performance comparison of a textured substrate sample according to one embodiment and a textured substrate sample with a bottom gold mirror is shown.

[0017] Figure 8 A performance comparison of the back side of a substrate and the front side of a substrate according to one embodiment is shown. DETAILED DESCRIPTION

[0018] The description of the illustrative embodiments according to the principles of the present disclosure is intended to be read in conjunction with the accompanying drawings, which are considered to be part of the entire written description. In the description of the embodiments disclosed herein, any reference to direction or orientation is merely for the convenience of description and is not intended to limit the scope of the present disclosure in any way. Related terms, such as "below", "above", "horizontally", "vertically", "above", "below", "up", "down", "top" and "bottom" and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) should be interpreted as referring to the direction described subsequently or shown in the drawings discussed. These related terms are only for the convenience of description, and unless explicitly stated, the device is not required to be constructed or operated in a specific direction. Terms such as "attachment", "attachment", "connection", "coupling", "interconnection" refer to a relationship in which structures are fixed or attached to each other directly or indirectly through an intermediate structure, as well as removable or rigid attachments or relationships, unless otherwise explicitly described. In addition, the features and benefits of the present disclosure are illustrated by reference to exemplary embodiments. Therefore, the present disclosure should not be expressly limited to exemplary embodiments showing some possible non-limiting combinations of features, which may exist alone or in other combinations of features; the scope of the present disclosure being defined by the appended claims.

[0019] The present disclosure describes the best mode of implementing the present disclosure currently expected. The description is not intended to be understood in a limiting sense, but rather to provide examples of the present disclosure presented for illustrative purposes only, by reference to the accompanying drawings, to inform those of ordinary skill in the art of the advantages and configurations of the present disclosure. In the various views of the accompanying drawings, the same reference numerals represent the same or similar parts.

[0020] It is important to note that the disclosed embodiments are merely examples of the many advantageous uses of the innovative teachings herein. In general, statements in the specification of this application do not necessarily limit any of the various claimed disclosures. Furthermore, some statements may apply to some inventive features but not to others. In general, unless otherwise noted, singular elements may be plural and vice versa without loss of generality.

[0021] Figure 1 The fabrication of a SERS chip according to one embodiment is shown (only one column is shown for clarity). Step 110: The process starts with a polished FS substrate (e.g., a 4-inch wafer with a thickness of 1 mm, but other sizes of substrates are possible). This substrate material is intentionally chosen because it is transparent in the visible light range. In addition, FS or quartz is chosen because of its chemical inertness and commercial availability, which is compatible with many pre-treatment and post-treatment supplements. General literature typically uses substrates such as silicon or textiles because existing manufacturing methods are suitable for these substrates and metals can adhere well to them. However, one embodiment of the present disclosure selects a FS substrate to allow the SERS signal to be measured from the textured and coated sides as well as the non-textured sides.

[0022] Because light can be radiated through the structure, one embodiment of the present disclosure can achieve a unique measurement form of through-substrate SERS. Figure 8 It can be seen that the Raman signal from the back side of the substrate is comparable to that from the front side. The normalized peak at the back side is 80% to 90% of the front side intensity.

[0023] Step 120: A modified maskless texturing process by reactive ion etching (RIE) is employed to modify the resulting pillars to an optimized height. In one embodiment, the texturing process is based on an etching method for producing a textured surface with an additive film, as disclosed in U.S. Patent Application No. 18 / 234,506, the contents of which are incorporated herein by reference.

[0024] In other embodiments, the texture can be produced by dry etching, wet etching, laser ablation, or chemical wet processing. In addition, in one embodiment, the height of the pillars is adjusted based on the excitation wavelength and the molecule of interest. In one embodiment, the pillar height can vary from 100-1500 nanometers, and the periodicity can vary from 50-500 nanometers. Note that the period value is an average measure of the distance from the peak of one pillar to the peak of the next pillar, which depends on the width and density of the pillars.

[0025] Step 130: After texturing, a layer of metal is deposited on the textured surface. Note that different metals are suitable for making SERS chips designed for different laser excitation wavelengths. In one embodiment, gold is used in the chip for 785 nanometer laser excitation. In another embodiment, other metals, such as silver, aluminum, copper, palladium, nickel and platinum, are used in the chip for 532 nanometer laser excitation. In the present disclosure, for simplicity, gold is used as an example to illustrate various aspects of the proposed SERS chip. It should be understood that the substantially same inventive principles illustrated in the example of gold can be applied to other metals, such as silver, aluminum, copper, palladium, nickel, platinum and alloys of two or more metals. In one embodiment, a combination of multiple metals can be deposited on the textured surface simultaneously, and the proportions of the multiple metals can be the same or different. In one embodiment, different individual metals, metal mixtures or alloys are sequentially deposited on the textured surface.

[0026] In an exemplary embodiment, a relatively thick layer of gold is deposited on the textured surface. In one embodiment, no adhesion layer is applied to the substrate. Traditionally, the gold deposition of SERS chips is very thin (approximately 1-50 nanometers). In one embodiment of the present disclosure, the deposit is referred to as a thick gold layer of >50 nanometers. In one embodiment, enough gold is deposited so that the recesses between the posts are filled with gold.

[0027] Optionally, a thin chromium adhesion layer is applied to the substrate before the gold is deposited to allow the gold to adhere. In one embodiment, additional layers of material (metal or dielectric) may be applied to the substrate for adhesion, molecular functionalization, or passivation.

[0028] Step 140: Finally, a thermal annealing process is used to change the morphology of the deposited gold so that we obtain a uniform layer that wraps around the pillars. In one embodiment, after the metal deposition, the substrate is placed in a N2-purged oven. In an example embodiment of gold deposition, the substrate is then annealed at 150 degrees Celsius for 60 minutes. It should be understood that the annealing temperature and duration depends on the composition of the metal deposit, as well as the desired Raman scattering parameters. In one embodiment, the annealing is performed under a specific atmosphere, for example, N2, H2, Ar, etc.

[0029] Once the sample is fabricated, the wafer is cut into smaller chips (e.g., 4.5 mm x 4.5 mm), or a single circular substrate is used for larger chips. In addition, according to one embodiment, the chip is modified to a metal-insulator-metal (MIM) structure with a metal mirror added under the chip, depending on the excitation laser. This allows any transmitted light to be reflected back onto the active gold layer for a second interaction.

[0030] The physical mechanism for understanding how these SERS chips work is based on the surface plasmon resonance (SPR) phenomenon. Specifically, the SERS chip is configured to excite surface plasmon polaritons (SPP) and localized surface plasmon resonance (LSPR) through light-matter interactions of an excitation laser and a gold coating. Figure 2 As shown, incident light can excite SPPs on a thin gold layer. From the tip to the base, the width of the pillar changes, allowing the gap distance between the gold surfaces to be varied. As the gap distance changes, SPPs can induce image charges in the opposing gold surfaces under different resonance conditions. The multiple modes supported in the pillars allow for broadband light trapping in the pillars. Once light is trapped in the pillars, the chip can induce a gap LSPR mode that produces a high electric field intensity along the entire height of the pillar. This enhanced electric field can increase the nonlinear response of Raman scattering and provide high detection sensitivity of the SERS chip. In addition, the thickness of the gold is adjusted to allow relatively high absorption of the Raman excitation light while maintaining high reflectivity in the Raman shift region, thereby providing a preferential scattering direction for the Raman shifted light.

[0031] Figure 3 FIG. 4 shows a side view of a SERS chip according to one embodiment. Figure 3 It can be seen that the pillars 310 are randomly formed on the substrate, and the pillars 310 are encapsulated by the gold layer 320. The average pillar height, average pillar width, and / or pillar density can be adjusted during the texturing process.

[0032] Figure 4-7 Used to illustrate how a textured SERS chip according to one embodiment of the present invention can provide a higher Raman signal than an untextured sample. In this demonstration, a series of samples coated with trans-1,2-bis(4-pyridyl)ethylene (BPE) molecules were tested. Each sample received 2.5 microliters of a 100 mM ethanol-based BPE solution. Figure 4 is a comparison of the performance of a blank FS flat substrate and a flat FS substrate with gold deposited on the surface. It can be seen that the addition of gold allows the detection of low Raman signals of BPE. Figure 5 In , it is shown how thermal annealing can further enhance the signal by changing the morphology of the gold layer to allow greater absorption of the excitation light. Figure 6is a comparison of the performance of the thermally annealed sample with a sample with a textured substrate, also with gold deposition and thermal annealing. It can be clearly seen that the texture again enhances the signal. Figure 7 A configuration is shown where a bottom gold mirror is added below the textured substrate. This structure is a Metal-Insulator-Metal (MIM) configuration. This structure again provides further enhancement since any transmitted light reflects off the back mirror and has a second interaction with the active gold layer and pillars.

[0033] Regarding substrate performance, in other areas such as lifetime, repeatability, and laser damage, embodiments of the present invention can achieve favorable performance characteristics, namely, substrate lifetime > 1 year, point-to-point repeatability < 16%, and substrates can withstand more than 5W / cm 2 CW laser power.

[0034] Although the present disclosure has been described in detail and several described embodiments have been described in detail, it is not intended that the present disclosure should be limited to any such details or embodiments or to any particular embodiment, but rather should be interpreted with reference to the appended claims so that such claims are given the broadest interpretation in light of the prior art so as to effectively cover the intended scope of the present disclosure.

Claims

1. A method for manufacturing a chip for surface enhanced Raman spectroscopy (SERS), comprising: providing a substrate; texturing the surface of the substrate to randomly form a plurality of pillars on the surface until a desired average pillar height, average pillar width, and / or pillar density is achieved; depositing metal onto the surface of the textured substrate; and The metal is thermally annealed so that the metal forms a layer surrounding the pillar. 2 . The method of claim 1 , further comprising coating the surface of the textured substrate with an additional material layer for adhesion, molecular functionalization or passivation before depositing the metal onto the surface of the textured substrate.

3. The method of claim 1, further comprising providing a metal mirror under the substrate so that transmitted light passing through the substrate is reflected back onto the metal layer for a second light-matter interaction.

4. The method of claim 1, wherein the width of each pillar varies from tip to base, resulting in a gap distance between two adjacent pillars varying along the tip to base direction.

5. The method of claim 4, wherein the desired average pillar height, average pillar width and / or pillar density is selected to support multiple localized surface plasmon resonance (LSPR) modes when the surface is illuminated by laser light of a specific wavelength.

6. The method of claim 1, wherein the height of the pillars varies between 100-1500 nanometers and the periodicity varies between 50-500 nanometers.

7. The method of claim 1, wherein the metal comprises at least one of the following: gold, silver, aluminum, copper, palladium, nickel, and platinum.

8. The method of claim 1, wherein a plurality of metals are deposited on the textured surface simultaneously or sequentially.

9. The method of claim 1, wherein the deposited metal has a thickness of at least 50 nanometers.

10. The method according to claim 1, wherein the substrate is a fused silica (FS) substrate, a quartz substrate, or an Al2O3 sapphire substrate.

11. The method of claim 1, wherein texturing of the surface of the substrate comprises reactive ion etching (RIE), dry etching, wet etching, laser ablation, or a chemical wet process.

12. The method of claim 1, further comprising configuring a chip for SERS from a side of the substrate having a metal coating and an opposite side of the substrate having no metal coating.

13. The method according to claim 1, wherein the annealing is performed under an atmosphere including at least one of N2, H2 and Ar.

14. A chip for surface enhanced Raman spectroscopy (SERS), comprising: a substrate having a textured surface on which a plurality of pillars having a desired average pillar height, average pillar width, and / or pillar density are randomly formed; Wherein the plurality of pillars are surrounded by a thermally annealed metal layer.

15. The chip of claim 14, further comprising a metal mirror placed under the substrate so that the transmitted light passing through the substrate is reflected back onto the metal layer for a second light-matter interaction.

16. The chip of claim 14, wherein the width of each pillar varies from tip to base, resulting in a gap distance between two adjacent pillars varying along the tip to base direction.

17. The chip of claim 14, wherein the metal comprises at least one of: gold, silver, aluminum, copper, palladium, nickel, and platinum.

18. The chip according to claim 14, wherein the substrate is a fused silica (FS) substrate, a quartz substrate, or an Al2O3 sapphire substrate.

19. The chip of claim 14, wherein the height of the pillars varies between 100-1500 nanometers and the periodicity varies between 50-500 nanometers.

20. The chip of claim 14, further comprising one or more additional material layers for adhesion, molecular functionalization or passivation.

21. The chip of claim 14, wherein the metal has a thickness of at least 50 nanometers.

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