A cable defect analysis terminal and method based on clock synchronization

Abstract

The present invention discloses a cable defect analysis terminal and method based on clock synchronization, and relates to the technical field of power defect detection. The terminal includes: a timing linkage module, which is used to record the precise time when the fault occurs; a fault pulse detection module, which is used to detect the fault signal and generate pulses to input the timing linkage module; a conditioning module, which is used to pre-process the signal; a low-speed conditioning module, which is used to shape the signal into a DC voltage signal; a synchronous acquisition module, which is used to synchronously acquire the input channel signals; a DC sampling module, which acquires multiple channel DC voltage signals output by the low-speed conditioning module; a microcontroller module, which receives the signals of each module and performs reading, calculation and processing, and generates control instructions after processing and sends them to the corresponding module. The present invention uses the fault pulse detection module to capture the fault signal in a hardware manner, which can realize efficient, fast and low-cost cable defect identification.

Description

Technical Field

[0001] The present invention relates to the technical field of power defect detection, and in particular to a cable defect analysis terminal and method based on clock synchronization. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] With the development of society, the development of power terminals is becoming larger and larger, and the safety of power cable operation is becoming more and more prominent. Once a fault occurs, a large-scale power outage will occur, seriously affecting production and life. At present, there are many means for cable defect location analysis, most of which are expensive and consume large power, and some also require power outage detection.

[0004] Normally, in order to capture fault signals, most solutions use high-frequency A / D acquisition, and determine the acquisition point corresponding to the fault signal by setting the threshold or waveform comparison through software, and then determine the time when the fault occurs. However, this solution is heavily dependent on the frequency of A / D acquisition. The actual fault occurrence point should be located between two acquisition points. The higher the frequency, the shorter the interval between the two acquisition points, and the higher the capture accuracy. Therefore, in order to improve the capture accuracy, it is necessary to increase the A / D acquisition frequency. At the same time, since the detection of cables requires multiple channels to be carried out simultaneously, if fault capture is carried out through this solution, multi-channel synchronous acquisition is required, which further increases the requirements for devices, and the cost and power consumption will be greatly increased.

[0005] In summary, how to overcome the defects of high cost, low efficiency and delay in capturing fault signals of existing equipment has become an urgent problem to be solved in the existing technology. Summary of the invention

[0006] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a cable defect analysis terminal and method based on clock synchronization, in which the fault pulse detection module captures the fault signal by hardware, the module has a built-in high-precision hardware trigger circuit, and the threshold can be set by the D / A conversion circuit. When the fault signal exceeds the threshold, the high-precision hardware trigger circuit outputs the fault pulse, and the timing linkage module captures and generates a hardware timestamp. It can achieve efficient, fast and low-cost cable defect identification.

[0007] In order to achieve the above object, the present invention is implemented through the following technical solutions:

[0008] A first aspect of the present invention provides a cable defect analysis terminal based on clock synchronization, comprising:

[0009] The timing linkage module is connected to other devices that need to be linked, and the clock synchronization terminal performs timing to record the exact time when the fault occurs, forming a high-precision hardware timestamp;

[0010] Fault pulse detection module, used to detect fault signal and generate pulse input to timing linkage module;

[0011] A conditioning module, used for pre-processing the signal and then inputting it into the synchronous acquisition module and the fault pulse detection module respectively;

[0012] A low-speed conditioning module is used to shape the signal into a DC voltage signal and input it into a DC sampling module;

[0013] A synchronous acquisition module is used to synchronously acquire the input signals of each channel and input them into the microcontroller module;

[0014] A DC sampling module collects multiple channel DC voltage signals output by the low-speed conditioning module and inputs them into the controller module;

[0015] The microcontroller module receives the signals from each module and performs reading, calculation and processing. After processing, it generates control instructions and sends them to the corresponding modules.

[0016] Furthermore, the microcontroller module includes MCU1 and MCU2. MCU2 is connected to the DC sampling module and MCU1 to read the data collected by the DC sampling module and transmit it to MCU1. MCU1 is responsible for the overall scheduling and data processing of the terminal.

[0017] Furthermore, it also includes a D / A conversion circuit, which is connected to the MCU1 and the fault pulse detection module, generates a corresponding voltage signal according to the instruction of the MCU1, and sends it to the fault pulse detection module.

[0018] Furthermore, it also includes a communication module, which is connected to the clock synchronization terminal externally and to the MCU1 internally to realize the communication function.

[0019] Furthermore, it also includes a sensor, which is connected to the conditioning module and the low-speed conditioning module. The sensor is in the form of a Rogowski coil and is installed on the high-voltage cable main cable and the grounding wire to obtain the cable operation signal.

[0020] Furthermore, the number of channels of the synchronous acquisition module, DC sampling module, conditioning module, and low-speed conditioning module remains consistent with that of the terminal.

[0021] Furthermore, the timing linkage module has a built-in clock, which is synchronized by a clock synchronization terminal and has a high-precision pulse capture function. The timing linkage module has two interfaces reserved, the first interface is used to capture pulses from the fault pulse detection module, and the second interface is reserved for the calibration function.

[0022] Furthermore, before the fault signal is detected, a signal generator is used to simulate the fault signal to calibrate the capture time function of the terminal.

[0023] Furthermore, the terminal includes multiple working modes, and each working mode can be switched, and the working modes include: normal working mode, hardware triggered acquisition mode, software intelligent acquisition mode, synchronous acquisition mode, manual acquisition mode and linkage acquisition mode.

[0024] A second aspect of the present invention provides a defect analysis method based on the cable defect analysis terminal based on clock synchronization according to the first aspect, comprising the following steps:

[0025] When the cable current suddenly changes, the cable operation signal is obtained and the signal is adjusted and processed through the conditioning module and the low-speed conditioning module;

[0026] The signal is input into the fault pulse detection module for fault detection, and the synchronous acquisition module is used to synchronously acquire the signal, and the timing linkage module is used to link the signal acquisition;

[0027] The collected signals are input into the microcontroller for reading, calculation and processing, and after processing, control instructions are generated and sent to the corresponding modules.

[0028] One or more of the above technical solutions have the following beneficial effects:

[0029] The present invention discloses a cable defect analysis terminal and method based on clock synchronization. The terminal adopts low-frequency sampling with a frequency not greater than 2 MHz, and adopts multi-point positioning and hardware timestamp capture to ensure positioning accuracy, thereby achieving cable defect positioning and analysis without relying on high-frequency sampling and adopting a low-cost, low-power solution, which greatly reduces the cost and difficulty in practical applications and facilitates promotion and application.

[0030] The current of the high-voltage cable is in a state of real-time change. Conventional means use single-point sampling, which can only analyze the abnormal situation at a single location. The synchronous sampling mode of this terminal can simultaneously sample the entire cable or cable segment, and realize synchronous collection and synchronous analysis of the normal operation status of the cable, which greatly improves the judgment of the operation status of the entire cable.

[0031] Multiple devices often use their own collection methods and sampling times. Because they are good at different things, they often miss some abnormal signals. The linkage collection mode of this terminal can realize the simultaneous collection of multiple devices and multiple means, and realize the simultaneous collection and analysis of multiple dimensions and multiple devices, which is of great significance.

[0032] Advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0034] Figure 1 This is a structural diagram of a cable defect analysis terminal based on clock synchronization in Embodiment 1 of the present invention;

[0035] Figure 2 This is a schematic diagram of the terminal calibration structure in the first embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of a timing linkage module in Embodiment 1 of the present invention;

[0037] Figure 4 Schematic diagram of a hardware trigger circuit in Embodiment 1 of the present invention. DETAILED DESCRIPTION

[0038] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0039] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "include" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or their combinations;

[0040] Embodiment 1:

[0041] Embodiment 1 of the present invention provides a cable defect analysis terminal based on clock synchronization, such as Figure 1 As shown, it includes a communication module, a timing linkage module, a microcontroller module, a D / A conversion circuit, a fault pulse detection module, a sensor, a conditioning module, a synchronous acquisition module, a low-speed conditioning module, and a DC sampling module. Among them, the cable defect analysis terminal of this embodiment is divided into two types: 8 channels and 16 channels. The number of channels of the synchronous acquisition module, the DC sampling module, the conditioning module, and the low-speed conditioning module is consistent with that of the terminal.

[0042] In this embodiment, for high-voltage cables buried underground or in tunnels, the cable defect analysis terminal is installed at the high-voltage cable joint, grounding box or other locations that require key monitoring, and the sensor is installed on the grounding wire and the high-voltage cable main cable; for overhead cables, the cable defect analysis terminal is installed on the high-voltage towers at both ends of the overhead line, and the sensor is installed on the grounding wire.

[0043] The terminal needs to be timed externally, and the time-keeping methods include but are not limited to: GNSS module second pulse method, IE1588V2 network time-keeping, field bus-based time-keeping, etc. The built-in clock of the terminal's timing linkage module is continuously calibrated through time-keeping to ensure the accuracy of the clock.

[0044] In order to avoid the device error caused by the introduction of high-precision hardware trigger circuits and improve the capture accuracy of hardware timestamps, before using them for fault signal detection, the terminal uses a combination of hardware and software to use a signal generator to simulate fault signals to calibrate the terminal's capture time function. Specifically, the following steps are included:

[0045] Step 1: Obtain calibration parameters before leaving the factory: Test the terminal from two dimensions: input signal frequency and amplitude.

[0046] Step 2: If Figure 2 As shown, a signal generator is used to simulate a fault signal, which is connected to the terminal sensor input interface and the standard reference device at the same time. The output pulse of the standard reference device is connected to the second interface of the timing linkage module of the terminal to be calibrated. According to the above table, signals of different frequency bands and amplitudes are sent in sequence. The first interface and the second interface of the timing linkage module of the terminal to be calibrated capture the input pulses at the same time, and the generation times are t1 and t2 respectively. MCU1 reads t1 and t2, and calculates the difference between t1 and t2, which is read out by the communication interface and recorded in the table according to different frequency and amplitude parameters to form calibration parameters. After the tests are completed in sequence, the calibration parameters are sent to the terminal through the communication interface and recorded to the external memory by the MCU. So far, it is ensured that the capture accuracy of the equipment before leaving the factory is consistent with that of the standard reference equipment.

[0047] In actual use, once a fault pulse occurs, the timing linkage module captures the time when the pulse occurs and forms a preliminary hardware timestamp. After collecting the A / D data, MCU1 judges the signal waveform, determines the amplitude and frequency when the signal is triggered, and then selects the corresponding calibration parameters to calibrate the preliminary hardware timestamp to form the final hardware timestamp and report it to the platform. The cable defect analysis terminal of this embodiment achieves low-power, low-cost analysis and positioning through low-frequency A / D sampling combined with hardware capture.

[0048] The specific contents are as follows:

[0049] The timing linkage module is connected to the clock synchronization terminal and other devices that need to be linked externally, and is connected to MCU1 and the fault pulse detection module internally. The clock synchronization terminal performs timing to record the exact time when the fault occurs and form a high-precision hardware timestamp.

[0050] like Figure 3 As shown, the timing linkage module has a built-in bidirectional linkage interface, which includes an input detection circuit interface and an output drive circuit interface. The bidirectional linkage interface is connected to the device that needs to be linked through the linkage bus, and can not only receive the linkage signal of the external device, but also send the linkage signal through this interface. After the pulse signal output by the terminal fault pulse detection module enters the timing linkage module, it enters the clock and capture chip one way and is connected to the bidirectional linkage interface one way. When the fault pulse detection module of this terminal outputs a pulse, the signal enters the output drive circuit of the bidirectional linkage interface, and then is connected to other devices through the linkage bus; when the external device is linked, the signal is detected by the input detection circuit of the bidirectional linkage interface through the linkage bus, connected to the clock and capture chip for accurate timestamp capture, and output to the pin of MCU1, informing MCU1 to perform linkage collection.

[0051] In a specific implementation, the timing linkage module has a built-in clock, which is synchronized by a clock synchronization terminal and has a high-precision pulse capture function. The timing linkage module has two interfaces reserved. The first interface is used to capture pulses from a fault pulse detection module, and the second interface is reserved for a calibration function and records the exact time when the fault occurs to form a high-precision hardware timestamp. Through the bidirectional linkage interface, it can be linked to external devices and can also accept external signals to trigger its own functions.

[0052] The fault pulse detection module is connected with the timing linkage module and the conditioning module. It is used to detect the fault signal and generate pulses to input into the timing linkage module.

[0053] This module has a built-in high-precision hardware trigger circuit. After the signal from the conditioning module enters the fault pulse detection module, it is associated with the voltage signal generated by the D / A conversion circuit to generate a pulse signal and enter the timing linkage module.

[0054] Among them, after the signal of the conditioning module enters the fault pulse detection module, the specific steps of associating the signal with the voltage signal generated by the D / A conversion circuit are as follows:

[0055] MCU1 receives platform instructions and controls the D / A conversion circuit to generate a corresponding voltage signal as a threshold. The platform can manually set the threshold by the operator, or the platform can automatically set the threshold by a specified proportion of the value collected in the normal state to form an automatic threshold.

[0056] like Figure 4As shown in the figure, the hardware trigger circuit is mainly composed of a high-precision comparator, a high-performance LDO and a filter circuit. The power supply adopts a high-performance LDO, which has the characteristics of high-precision output and high noise suppression, reduces noise interference and improves trigger accuracy. The filter circuit is used to filter the voltage signal generated by the D / A conversion circuit to improve the stability of the signal, and then enters the high-precision comparator as a threshold signal; the signal output by the conditioning module enters the high-precision comparator and is compared with the threshold signal. When the threshold is exceeded, the hardware trigger circuit outputs a pulse.

[0057] The conditioning module is used to pre-process the signal and then input it into the synchronous acquisition module and the fault pulse detection module respectively. Through the pre-processing steps, the signal is filtered, rectified, amplified and enhanced.

[0058] In a specific implementation, the conditioning module is connected to the sensor, the synchronous acquisition module, and the fault pulse detection module respectively. After the signal enters the conditioning module, it is processed by high-frequency interference filtering, signal amplification, etc., and then sent to the synchronous acquisition module and the fault pulse detection module respectively.

[0059] The low-speed conditioning module is used to shape the signal into a DC voltage signal and input it into the DC sampling module.

[0060] In a specific implementation, the low-speed conditioning module is connected to the DC sampling module and the sensor, and the signal collected by the sensor is rectified, filtered, amplified, etc., and then shaped into a DC voltage signal and sent to the DC sampling module.

[0061] In this embodiment, one conditioning module and one low-speed conditioning module are provided. The conditioning module has a higher sampling frequency than the low-speed conditioning module, focuses on abnormal signals with higher frequencies, and has a larger measurement range. Therefore, it is connected to the fault detection module to facilitate the acquisition of fault signals, and cannot perform strong filtering to prevent effective high-frequency signals from being filtered out. The low-speed conditioning module pays more attention to power frequency signals, has a smaller measurement range, and only needs to cover the range of cable operating current. It has a relatively strong built-in filtering circuit, and has a higher accuracy in acquiring power frequency operating current. Therefore, it is connected to the DC sampling module. The two modules work together and complement each other.

[0062] The synchronous acquisition module is used to synchronously acquire the input signals of each channel and input them into the microcontroller module.

[0063] In a specific implementation, the synchronous acquisition module uses a medium-to-low speed acquisition chip within 2 MHZ, is connected to the MCU1 and the conditioning module, supports a maximum of 8 channels or 16 channels, and each channel uses synchronous acquisition.

[0064] The DC sampling module is connected to the low-speed current regulation module and MCU2, collects multiple channel DC voltage signals output by the low-speed conditioning module, and inputs them into MCU2 in the controller module, and then inputs them into MCU1 by MCU2.

[0065] In this embodiment, the DC sampling module cooperates with the low-speed sampling module, and the sampling frequency is low, so that the industrial frequency operating current is accurately sampled, and the operating current of the cable under normal conditions can be paid attention to.

[0066] The microcontroller module receives the signals from each module and performs reading, calculation and processing. After processing, it generates control instructions and sends them to the corresponding modules. Among them, the microcontroller module includes MCU1 and MCU2. MCU2 is connected to the DC sampling module and MCU1 to read the data collected by the DC sampling module and transmit it to MCU1. MCU1 is responsible for the overall scheduling and data processing of the terminal.

[0067] In a specific implementation, MCU1 is respectively connected to the communication module, the timing linkage module, the external memory, MCU2, the D / A conversion circuit, and the synchronous acquisition module. Realize real-time communication with the clock synchronization terminal, read the fault hardware timestamp of the timing linkage module, store the collected data in the external memory, read the state and data of MCU2, control the D / A conversion circuit to generate a specific voltage signal, and read and process the data of the synchronous acquisition module. Built-in multiple algorithms and multiple working modes. MCU2 is connected to the DC sampling module and MCU1, reads the data collected by the DC sampling module, and transmits it to MCU1.

[0068] The D / A conversion circuit is connected to the MCU1 and the fault pulse detection module, generates a corresponding voltage signal according to the instruction of the MCU1, and sends it to the fault pulse detection module.

[0069] The communication module is connected to the clock synchronization terminal externally and to the MCU1 internally to realize the communication function. In this embodiment, the communication module can be selected as an RS485 communication module or an Ethernet communication module.

[0070] The sensor is connected to the conditioning module and the low-speed conditioning module. The sensor is in the form of a Rogowski coil and is divided into two sizes. It is installed on the main cable of the high-voltage cable and the grounding wire to obtain the cable operation signal.

[0071] The terminal includes multiple working modes, and each working mode can be switched, including: normal working mode, hardware trigger acquisition mode, software intelligent acquisition mode, synchronous acquisition mode, manual acquisition mode and linkage acquisition mode. The specific contents of each mode are as follows:

[0072] 1. Normal working mode: The terminal remains connected to the upper platform, and is timed by external devices. All modules remain working. MCU1 performs real-time analysis on the collected data, and the upper platform schedules data storage and upload. When receiving platform instructions, the collected data is stored and uploaded; the platform periodically sends instructions to the device for collection, and the time is configurable.

[0073] 2. Hardware trigger acquisition mode: When the fault pulse detection module outputs a pulse, it indicates that a fault may have occurred. Regardless of any other mode currently in place, enter the hardware trigger acquisition mode immediately. At this time, the timing linkage module captures and records the exact time when the pulse occurs, generates a hardware timestamp, and is stored and uploaded to the platform by MCU1; MCU1 stores and uploads the data collected 5 to 10 power frequency cycles before and after the event; at the same time, the timing linkage module outputs a linkage signal to link other external devices for synchronous work.

[0074] 3. Software intelligent acquisition mode: In normal operation, when MCU1 filters the collected data in real time and eliminates interference, it is found that the data is obviously abnormal and exceeds the threshold set by the software. At this time, it is judged that the cable may have an abnormal signal. The terminal enters the software intelligent acquisition mode, records the time of the event, and forms a software timestamp, which is stored and uploaded to the platform by MCU1. The data collected in multiple power frequency cycles before and after the event is stored and uploaded; at the same time, the timing linkage module outputs a linkage signal to link other external devices for synchronous work.

[0075] 4. Synchronous acquisition mode: The upper platform issues instructions. After receiving the instructions, each defect location terminal collects sensor data at the same time according to the time point of the instructions and the precise time in the timing synchronization module, and stores and uploads the data to achieve multi-terminal synchronous data acquisition, laying the foundation for the synchronous analysis of the entire section of the high-voltage cable or multi-point synchronous analysis. This mode is mainly used to analyze the normal operation data of the cable. Through the synchronous acquisition mode, the terminals installed in each section of the cable can obtain the waveforms and data at different positions of the cable at the same time, which is of great significance for analyzing the cable operation status and grounding loop. If there is no synchronous acquisition, even if the data of each section is collected, but it does not occur at the same time, then effective comparative analysis cannot be performed.

[0076] 5. Manual collection mode: When the operator needs to focus on monitoring a certain section of cable, he can manually click buttons and issue commands through the upper platform to obtain data from a terminal installed on this cable. After receiving the command, the terminal collects, stores and uploads the data.

[0077] 6. Linkage collection mode: This mode is used for linkage collection of multiple terminals. It can cooperate with other monitoring terminals, such as partial discharge terminals, gas monitoring terminals, etc. It can capture cable signals when other terminals detect abnormalities, and is used for joint analysis of multiple terminals. The timing linkage module has a two-way linkage interface. Other devices can use the two-way linkage interface to link this terminal to collect and upload data. When other terminals detect abnormalities, they send signals to the two-way linkage interface of the timing linkage module. After the timing linkage module receives the pulse signal, the terminal enters the linkage collection mode. The signal is captured by the timing linkage module, and the exact time when the pulse occurs is recorded to form a hardware timestamp, which is stored by MCU1 and uploaded to the platform; MCU1 stores and uploads the data collected in multiple power frequency cycles before and after the event. After the data of various terminals are uploaded to the platform, the data of various terminals can be obtained through the platform for joint analysis.

[0078] The working process of the cable defect analysis terminal in this embodiment is as follows:

[0079] After the cable defect analysis terminal is powered on, it is connected to the upper platform and after external timing, it enters the normal working state.

[0080] During normal operation: the terminal monitors the working status of each module in real time, monitors and analyzes the data collected by the synchronous acquisition module and the DC sampling module, receives instructions issued by the platform, and collects, stores and uploads data according to the instructions. During normal operation, the high-voltage cable works in a normal state, and each module collects normal power frequency current signals. When someone issues an acquisition instruction on the platform, the terminal can enter the manual acquisition mode to store and report the data of the synchronous acquisition module and the DC sampling module at the current time point.

[0081] When the cable current suddenly changes:

[0082] 1) If the fault pulse detection module outputs a pulse, the terminal immediately enters the hardware trigger acquisition mode, the timing linkage module locks the pulse occurrence time to generate a hardware timestamp, stores the data collected from multiple power frequency cycles before and after the event, and uploads the stored data and hardware timestamp to the platform. Due to the time synchronization of the terminal, when a fault occurs, multiple terminals will trigger the hardware acquisition mode, and each terminal will generate a hardware timestamp. Based on the signal transmission theory, the platform can locate the location of the fault according to the different arrival times at each terminal. At the same time, since positioning can be achieved at two points, the time of multiple points can be counted, abnormal points can be excluded, and the mean method can be used to improve the positioning accuracy.

[0083] 2) If the fault pulse detection module does not output a pulse, MCU1 filters the collected data in real time, eliminates interference, and finds that the data is obviously abnormal and exceeds the threshold set by the software. At this time, it is judged that the cable may have an abnormal signal, and the terminal enters the software intelligent collection mode, and the data is stored and uploaded to the platform; if it does not exceed the threshold, it enters the normal working state. The software threshold can be manually set and issued by the platform, or it can be set to an adaptive mode. The terminal automatically sets the threshold after self-analysis based on the values ​​collected during normal operation. The automatically set threshold will change adaptively according to the changes in the high-voltage cable current, ensuring that as many abnormal signals as possible are obtained while eliminating interference from normal data to the greatest extent possible.

[0084] When the platform issues a synchronous collection instruction, after receiving the instruction, each terminal will collect sensor data at the same time according to the time point of the instruction and the precise time in the timing synchronization module, and store and upload the data to realize multi-terminal synchronous data collection.

[0085] When the timing linkage module receives the linkage signal from other devices, the terminal enters the linkage acquisition mode. The signal is captured by the timing linkage module, and the exact time when the pulse occurs is recorded to form a hardware timestamp, which is stored and uploaded to the platform. The terminal stores and uploads the data collected from multiple power frequency cycles before and after the linkage signal occurs.

[0086] Embodiment 2:

[0087] Embodiment 2 of the present invention provides a defect analysis method of the cable defect analysis terminal based on clock synchronization according to Embodiment 1, comprising the following steps:

[0088] When the cable current suddenly changes, the cable operation signal is obtained and the signal is adjusted and processed through the conditioning module and the low-speed conditioning module;

[0089] The signal is input into the fault pulse detection module for fault detection, and the synchronous acquisition module is used to synchronously acquire the signal, and the timing linkage module is used to link the signal acquisition;

[0090] The collected signals are input into the microcontroller for reading, calculation and processing, and after processing, control instructions are generated and sent to the corresponding modules.

[0091] The steps involved in the above embodiment 2 correspond to those in embodiment 1. For the specific implementation method, please refer to the relevant description part of embodiment 1.

[0092] Those skilled in the art should understand that the modules or steps of the present invention described above can be implemented by a general-purpose computer device, or alternatively, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. The present invention is not limited to any specific combination of hardware and software.

[0093] Although the above describes the specific implementation mode of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without creative work are still within the scope of protection of the present invention.

Claims

1. A cable defect analysis terminal based on clock synchronization, characterized in that: include: The timing linkage module is connected to other devices that need to be linked, and the clock synchronization terminal performs timing to record the exact time when the fault occurs, forming a high-precision hardware timestamp; Fault pulse detection module, used to detect fault signal and generate pulse input to timing linkage module; A conditioning module, used for pre-processing the signal and then inputting it into the synchronous acquisition module and the fault pulse detection module respectively; A low-speed conditioning module is used to shape the signal into a DC voltage signal and input it into a DC sampling module; A synchronous acquisition module is used to synchronously acquire the input signals of each channel and input them into the microcontroller module; A DC sampling module collects multiple channel DC voltage signals output by the low-speed conditioning module and inputs them into the controller module; The microcontroller module receives the signals from each module and performs reading, calculation and processing. After processing, it generates control instructions and sends them to the corresponding modules.

2. The cable defect analysis terminal based on clock synchronization according to claim 1, characterized in that: The microcontroller module includes MCU1 and MCU2. MCU2 is connected to the DC sampling module and MCU1 to read the data collected by the DC sampling module and transmit it to MCU1. MCU1 is responsible for the overall scheduling and data processing of the terminal.

3. The cable defect analysis terminal based on clock synchronization as claimed in claim 2, characterized in that: It also includes a D / A conversion circuit, which is connected to the MCU1 and the fault pulse detection module, generates a corresponding voltage signal according to the instruction of the MCU1, and sends it to the fault pulse detection module.

4. The cable defect analysis terminal based on clock synchronization as claimed in claim 2, characterized in that: It also includes a communication module, which is connected to the clock synchronization terminal externally and to the MCU1 internally to realize the communication function.

5. The cable defect analysis terminal based on clock synchronization according to claim 1, characterized in that: It also includes a sensor, which is connected to the conditioning module and the low-speed conditioning module. The sensor is in the form of a Rogowski coil and is installed on the high-voltage cable main cable and the grounding wire to obtain the cable operation signal.

6. The cable defect analysis terminal based on clock synchronization according to claim 1, characterized in that: The number of channels of the synchronous acquisition module, DC sampling module, conditioning module, and low-speed conditioning module remains consistent with that of the terminal.

7. The cable defect analysis terminal based on clock synchronization according to claim 1, characterized in that: The timing linkage module has a built-in clock and is timed by a clock synchronization terminal. It has a high-precision pulse capture function. The timing linkage module has two interfaces reserved. The first interface is used to capture pulses from the fault pulse detection module, and the second interface is reserved for the calibration function.

8. The cable defect analysis terminal based on clock synchronization according to claim 1, characterized in that: Before being used for fault signal detection, a signal generator is used to simulate a fault signal to calibrate the capture time function of the terminal.

9. The cable defect analysis terminal based on clock synchronization according to claim 1, characterized in that: The terminal includes multiple working modes, and each working mode can be switched. The working modes include: normal working mode, hardware triggered acquisition mode, software intelligent acquisition mode, synchronous acquisition mode, manual acquisition mode and linkage acquisition mode.

10. A defect analysis method based on the cable defect analysis terminal based on clock synchronization according to any one of claims 1 to 9, characterized in that: The following steps are involved: When the cable current suddenly changes, the cable operation signal is obtained and the signal is adjusted and processed through the conditioning module and the low-speed conditioning module; The signal is input into the fault pulse detection module for fault detection, and the synchronous acquisition module is used to synchronously acquire the signal, and the timing linkage module is used to link the signal acquisition; The collected signals are input into the microcontroller for reading, calculation and processing, and after processing, control instructions are generated and sent to the corresponding modules.

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