Chip Testing Method, Device, Storage Medium and Electronic Device

Abstract

The present application discloses a chip testing method, apparatus, storage medium and electronic device. Among them, the chip testing method includes determining the number of signal channels and testing requirements of a chip to be tested; determining a target channel configuration method from preset channel configuration methods according to the number of signal channels and testing requirements; configuring test channels for the chip according to the target channel configuration method, each test channel corresponding to a signal channel group, and each signal channel group including at least two signal channels; using a multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group; testing the target channel, and returning to execute the step of using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group until all signal channels are tested. This solution can reduce the testing cost of chip testing.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of chip technology, and in particular, to a chip testing method, device, storage medium, and electronic device. Background Art

[0002] In the field of chip design and manufacturing, the functional and performance testing of chips is a key link to ensure their quality and reliability. With the rapid development of chip technology, the number and complexity of signal channels integrated inside the chips have increased significantly, posing higher requirements for chip testing methods.

[0003] Currently, chip testing usually adopts the all-channel testing method, that is, directly connecting all signal channels of the chip through a testing device for testing. However, with the wide application of high-complexity chips such as multi-core processors, SoCs (System-on-Chip), and AI acceleration chips, the number of signal channels and functional modules of modern chips is increasing continuously. The all-channel testing requires the testing device to have an interface equal to the number of signal channels of the chip, which poses high requirements for the hardware resources of the testing device and increases the testing cost and complexity. Summary of the Invention

[0004] Embodiments of the present application provide a chip testing method, device, storage medium, and electronic device, which can reduce the testing cost of chip testing.

[0005] In a first aspect, embodiments of the present application provide a chip testing method, including:

[0006] Determine the number of signal channels and testing requirements of the chip to be tested;

[0007] According to the number of signal channels and the testing requirements, determine a target channel configuration method from preset channel configuration methods;

[0008] Configure test channels for the chip according to the target channel configuration method, each test channel corresponding to a signal channel group, and each signal channel group including at least two of the signal channels;

[0009] Use a multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group;

[0010] Test the target channel, and return to the step of using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group until all the signal channels are tested.

[0011] In the chip testing method provided by the embodiments of the present application, the configuring test channels for the chip according to the target channel configuration method includes:

[0012] It should be noted that there is an error in the original text. The description in should be "which can reduce the testing cost of chip testing" instead of "which can increase the testing cost of chip testing". The above translation has been corrected accordingly.Group several of the signal channels;

[0013] Configure a test channel for each group of the signal channels according to the grouping result, and add redundant test channels and / or parallel test channels according to the target channel configuration method.

[0014] In the chip testing method provided by the embodiment of the present application, each of the signal channel groups includes 4 of the signal channels, and the preset channel configuration methods include a 4n + 1 channel configuration method and a 4n + 4 channel configuration method.

[0015] In the chip testing method provided by the embodiment of the present application, the step of using a multiplexing module to select, from the corresponding signal channel group, the target channel currently corresponding to each of the test channels includes:

[0016] Generate a selection control signal for the target channel according to the test plan;

[0017] Use the multiplexing module to receive and parse the selection control signal to locate the target channel currently corresponding to each of the test channels.

[0018] In the chip testing method provided by the embodiment of the present application, after using the multiplexing module to receive and parse the control signal to locate the target channel currently corresponding to each of the test channels, the method further includes:

[0019] Adjust the internal connection path through the multiplexing module to connect each of the test channels to the target channel in the corresponding signal channel group.

[0020] In the chip testing method provided by the embodiment of the present application, the test plan includes the test parameters and test sequence of each of the signal channels.

[0021] In the chip testing method provided by the embodiment of the present application, the method further includes:

[0022] Collect the test results of each of the signal channels;

[0023] Analyze the test results to evaluate the performance and reliability of the chip;

[0024] When a fault is found, perform a fault isolation test through the redundant channel.

[0025] In a second aspect, an embodiment of the present application provides a chip testing device, including:

[0026] A first determination unit, configured to determine the number of signal channels and the test requirements of the chip to be tested;

[0027] A second determination unit, configured to determine a target channel configuration method from the preset channel configuration methods according to the number of signal channels and the test requirements;

[0028] A channel configuration unit, configured to configure test channels for the chip according to the target channel configuration method, each of the test channels corresponding to a signal channel group, and each of the signal channel groups including at least two of the signal channels;

[0029] A target selection unit, configured to use a multiplexing module to select, from the corresponding signal channel group, the target channel currently corresponding to each of the test channels;

[0030] A channel test unit, configured to test the target channel, and return to execute the step of using the multiplexing module to select, from the corresponding signal channel group, the target channel currently corresponding to each of the test channels until all of the signal channels are tested;

[0031] In a third aspect, the present application provides a storage medium storing multiple instructions adapted to be loaded by a processor to execute the chip testing method according to any one of the above.

[0032] In a fourth aspect, the present application provides an electronic device including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the computer program, the chip testing method according to any one of the above is implemented.

[0033] In summary, the chip testing method provided by the embodiments of the present application includes determining the number of signal channels and test requirements of a chip to be tested; determining a target channel configuration method from preset channel configuration methods according to the number of signal channels and the test requirements; configuring test channels for the chip according to the target channel configuration method, each of the test channels corresponding to a signal channel group, and each of the signal channel groups including at least two of the signal channels; using a multiplexing module to select, from the corresponding signal channel group, the target channel currently corresponding to each of the test channels; testing the target channel, and returning to execute the step of using the multiplexing module to select, from the corresponding signal channel group, the target channel currently corresponding to each of the test channels until all of the signal channels are tested. Through multiplexing technology, this solution can reduce the number of test channels and lower the test cost. Description of the Drawings

[0034] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those skilled in the art, other accompanying drawings can be obtained without creative efforts based on these drawings.

[0035] Figure 1It is a schematic flowchart of the chip testing method provided by an embodiment of the present application.

[0036] Figure 2 It is a schematic flowchart of the chip testing device provided by an embodiment of the present application.

[0037] Figure 3 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0038] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0039] It should be noted that in this document, the term "including", "comprising" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the presence of additional identical elements in the process, method, article or device including that element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0040] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] In subsequent descriptions, the use of suffixes such as "module", "component" or "unit" to represent elements is only for the convenience of the description of the present application, and they have no specific meaning in themselves. Therefore, "module", "component" or "unit" can be used interchangeably.

[0042] In the description of this application, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to this application. In addition, terms such as "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0043] Currently, chip testing usually adopts a full-channel testing method, that is, directly connecting all signal channels of the chip through a testing device for testing. However, with the wide application of high-complexity chips such as multi-core processors, SoCs (System-on-Chip), and AI acceleration chips, the number of signal channels and functional modules of modern chips is increasing continuously. Full-channel testing requires the testing device to have the same number of interfaces as the number of signal channels of the chip, which places high requirements on the hardware resources of the testing device and increases the testing cost and complexity.

[0044] Based on this, the embodiments of this application provide a chip testing method, device, storage medium, and electronic device. Specifically, the chip testing device can be integrated in an electronic device, which can be a server or a terminal device, etc.; among them, the terminal can include a mobile phone, a wearable intelligent device, a tablet computer, a laptop computer, and a personal computer (PC), etc.; the server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0045] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments does not limit the priority order of the embodiments.

[0046] Please refer to Figure 1 , Figure 1 which is a schematic flowchart of the chip testing method provided by the embodiments of this application. The specific process of the chip testing method can be as follows:

[0047] 101. Determine the number of signal channels and testing requirements of the chip to be tested.

[0048] For example, the number of signal channels can be determined by checking the technical specification document of the chip to be tested. The technical specification document usually clearly marks information such as the number of input / output signal channels of the chip, signal types (such as analog signals, digital signals), and channel functions. The number of all available signal channels can also be counted according to the pin definition of the chip to be tested.

[0049] Among them, the test requirements may include functional test requirements, performance test requirements, reliability test requirements, and redundant channel test requirements.

[0050] In some embodiments, the main metrics to be tested can be listed according to the expected functions of the chip. For example: throughput, stability, and bit error rate tests of data channels. Verification of the frequency, duty cycle, and jitter characteristics of clock signals.

[0051] 102. Determine the target channel configuration mode from the preset channel configuration modes according to the number of signal channels and the test requirements.

[0052] Among them, the preset channel configuration modes include 4n + 1 channel configuration mode and 4n + 4 channel configuration mode.

[0053] In the 4n + 1 channel configuration mode, each test channel corresponds to 4 signal channels, and the remaining channels are allocated to the last test channel. In the 4n + 4 channel configuration mode, each test channel corresponds to 4 signal channels, and the extra channels can be used for redundant or parallel testing.

[0054] Among them, the 4n + 1 channel configuration mode is applicable to scenarios where the number of channels is slightly higher than 4n, providing an additional channel for special testing or fault redundancy. During the testing process, this additional channel can be used to monitor or test a specific channel, enhancing flexibility.

[0055] The 4n + 4 channel configuration mode is applicable to scenarios with high-density signal channels. The extra channels are used for redundant design, supporting stronger parallel capabilities. During the testing process, the extra channels can be used for redundancy to ensure that the testing can still be carried out even if a certain channel fails.

[0056] For example, when the number of signal channels is M, if M mod 4 = 0, the 4n + 4 channel configuration mode can be selected to increase the redundancy capability; if M mod 4 ≠ 0, the 4n + 1 channel configuration mode can be selected to reduce the waste of unused channels.

[0057] In some embodiments, the target channel configuration mode can be further determined in combination with the test requirements. For example, if the test requirements require more parallel capabilities, the 4n + 4 channel configuration mode is preferentially selected. If the channel switching is frequent and the test priorities are clear, the 4n + 1 channel configuration mode is more efficient. When redundancy is needed, the configuration with more redundant channels (such as 4n + 4) is preferentially selected.

[0058] 103. Configure the test channels for the chip according to the target channel configuration mode.

[0059] In the embodiments of the present application, each test channel corresponds to a signal channel group, and each signal channel group includes at least two signal channels. Among them, each signal channel group corresponds to 4 signal channels.

[0060] Specifically, a number of signal channels can be grouped; a test channel is configured for each group of signal channels according to the grouping result, and redundant test channels and / or parallel test channels are added according to the target channel configuration method.

[0061] For the 4n + 1 channel configuration method, N 测试信道 = 。For the 4n + 4 channel configuration method, N 测试信道 = 。Among them, represents rounding up.

[0062] 104. Use the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group.

[0063] Specifically, a selection control signal for the target channel can be generated according to the test plan; the multiplexing module is used to receive and parse the selection control signal to locate the target channel currently corresponding to each test channel.

[0064] Among them, the test plan can include the test parameters and test order of each signal channel. During the specific implementation process, the target channels can be selected in sequence according to the test order.

[0065] In some embodiments, after determining the target channel, the internal connection path can be adjusted through the multiplexing module to connect each test channel to the target channel in the corresponding signal channel group.

[0066] 105. Test the target channel, and return to the step of using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group until all signal channels are tested.

[0067] After the test is completed, the test results of each signal channel can also be collected; the test results are analyzed to evaluate the performance and reliability of the chip; when a fault is found, a fault isolation test is performed through the redundant channel.

[0068] After all channels are tested, the data can be summarized to generate a final test report.

[0069] In summary, the chip testing method provided by the embodiments of the present application includes determining the number of signal channels and testing requirements of the chip to be tested; determining a target channel configuration method from preset channel configuration methods according to the number of signal channels and testing requirements; configuring test channels for the chip according to the target channel configuration method, where each test channel corresponds to a signal channel group, and each signal channel group includes at least two signal channels; using a multiplexing module to select the target channel corresponding to each test channel from the corresponding signal channel group; testing the target channel, and returning to the step of using the multiplexing module to select the target channel corresponding to each test channel from the corresponding signal channel group until all signal channels are tested. This solution can reduce the number of test channels and lower the testing cost through multiplexing technology. Moreover, through the target channel switching and parallel testing mechanisms, the testing time can be significantly shortened. By using redundant channel design and a multiplexing module, the fault tolerance of the testing system is improved. It can also ensure that all signal channels can be efficiently tested, guaranteeing the comprehensiveness and accuracy of chip function and performance verification.

[0070] To facilitate better implementation of the chip testing method provided by the embodiments of the present application, the embodiments of the present application also provide a chip testing device. The meanings of the nouns are the same as those in the above chip testing method, and the specific implementation details can refer to the description in the method embodiments.

[0071] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of the chip testing device provided by the embodiments of the present application. The chip testing device may include a first determination unit 201, a second determination unit 202, a channel configuration unit 203, a target selection unit 204, and a channel testing unit 205. Among them,

[0072] The first determination unit 201 is used to determine the number of signal channels and testing requirements of the chip to be tested;

[0073] The second determination unit 202 is used to determine a target channel configuration method from preset channel configuration methods according to the number of signal channels and testing requirements;

[0074] The channel configuration unit 203 is used to configure test channels for the chip according to the target channel configuration method, where each test channel corresponds to a signal channel group, and each signal channel group includes at least two signal channels;

[0075] The target selection unit 204 is used to use a multiplexing module to select the target channel corresponding to each test channel from the corresponding signal channel group;

[0076] A channel test unit 205 is configured to test a target channel and return to execute the step of selecting, by using a multiplexing module, the target channel currently corresponding to each test channel from the corresponding signal channel group until all signal channels are tested.

[0077] For the specific implementation manners of the above units, reference may be made to the embodiments of the chip test method described above, which will not be elaborated herein one by one.

[0078] In summary, the chip test device provided by the embodiment of the present application can determine the number of signal channels and test requirements of a chip to be tested through the first determination unit 201; the second determination unit 202 determines a target channel configuration manner from a preset channel configuration manner according to the number of signal channels and test requirements; the channel configuration unit 203 configures test channels for the chip according to the target channel configuration manner, each test channel corresponds to a signal channel group, and each signal channel group includes at least two signal channels; the target selection unit 204 uses a multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group; the channel test unit 205 tests the target channel and returns to execute the step of selecting, by using the multiplexing module, the target channel currently corresponding to each test channel from the corresponding signal channel group until all signal channels are tested. Through the multiplexing technology, this solution can reduce the number of test channels and the test cost. Moreover, through the target channel switching and parallel test mechanisms, the test time can be significantly shortened. By using the redundant channel design and the multiplexing module, the fault tolerance of the test system is improved. It can also ensure that all signal channels can be efficiently tested, guaranteeing the comprehensiveness and accuracy of the chip function and performance verification.

[0079] The embodiment of the present application further provides an electronic device, which may integrate the chip test device of the embodiment of the present application, as Figure 3 shown, which shows a schematic structural diagram of the electronic device involved in the embodiment of the present application. Specifically:

[0080] The electronic device may include a processor 301 with one or more processing cores and a memory 302 with one or more computer-readable storage media and other components. Those skilled in the art can understand that Figure 3 the structural diagram of the electronic device shown in

[0081] The processor 301 is the control center of the electronic device, connecting various parts of the entire electronic device through various interfaces and circuits. By running or executing software programs stored in the memory 302 and / or this application, and by invoking the data stored in the memory 302, it executes various functions of the electronic device and processes data, thereby monitoring the electronic device as a whole. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor. Among them, the application processor mainly processes operations on storage media, user interfaces, application programs, etc., and the modem processor mainly processes wireless communications. It can be understood that the above-mentioned modem processor may not be integrated into the processor 301 either.

[0082] The memory 302 can be used to store software programs and this application. The processor 301 executes various functional applications and data processing by running the software programs and this application stored in the memory 302. The memory 302 mainly includes a program storage area and a data storage area. Among them, the program storage area can store applications required for operating storage media, at least one function (such as sound playback function, image playback function, etc.); the data storage area can store data created according to the use of the electronic device, etc. In addition, the memory 302 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. Correspondingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0083] Although not shown, the electronic device may also include a display unit, an input unit, a power supply, etc., which will not be elaborated here. Specifically in this embodiment, the processor 301 in the electronic device will load the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 will run the application programs stored in the memory 302 to implement various functions as follows:

[0084] Determine the number of signal channels and test requirements of the chip to be tested;

[0085] According to the number of signal channels and test requirements, determine the target channel configuration method from the preset channel configuration methods;

[0086] Configure test channels for the chip according to the target channel configuration method. Each test channel corresponds to a signal channel group, and each signal channel group includes at least two signal channels;

[0087] Use the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group;

[0088] Test the target channel, and return to execute the step of selecting the currently corresponding target channel for each test channel from the corresponding signal channel group until all signal channels are tested.

[0089] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling related hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0090] For this reason, an embodiment of the present application provides a storage medium, in which multiple instructions are stored, and the instructions can be loaded by a processor to execute the steps in any of the generation methods provided by the embodiments of the present application. For example, the instructions can execute the following steps:

[0091] Determine the number of signal channels and test requirements of the chip to be tested;

[0092] According to the number of signal channels and test requirements, determine the target channel configuration method from the preset channel configuration methods;

[0093] Configure test channels for the chip according to the target channel configuration method. Each test channel corresponds to a signal channel group, and each signal channel group includes at least two signal channels;

[0094] Use the multiplexing module to select the currently corresponding target channel for each test channel from the corresponding signal channel group;

[0095] Test the target channel, and return to execute the step of using the multiplexing module to select the currently corresponding target channel for each test channel from the corresponding signal channel group until all signal channels are tested.

[0096] For the specific implementation of each of the above operations, reference can be made to the previous embodiments and will not be elaborated here.

[0097] Among them, the storage medium may include: read-only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, etc.

[0098] Since the instructions stored in the storage medium can execute the steps in any of the methods provided by the embodiments of the present application, the beneficial effects that can be achieved by any of the methods provided by the embodiments of the present application can be realized. For details, refer to the previous embodiments and will not be elaborated here.

[0099] The above has introduced in detail the chip testing method, device, storage medium, and electronic device provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the core idea of this application; at the same time, for those skilled in the art, according to the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A chip testing method, characterized in that, Including: Determine the number of signal channels and test requirements of the chip to be tested; According to the number of signal channels and the test requirements, determine the target channel configuration method from the preset channel configuration methods; Group a number of the signal channels; configure a test channel for each group of the signal channels according to the grouping result, and add redundant test channels and / or parallel test channels according to the target channel configuration method. Each of the test channels corresponds to a signal channel group, and each signal channel group includes 4 of the signal channels. The preset channel configuration methods include a 4n + 1 channel configuration method and a 4n + 4 channel configuration method; when the number of signal channels is M, if M mod 4 = 0, then select the 4n + 4 channel configuration method; if M mod 4 ≠ 0, then select the 4n + 1 channel configuration method; for the 4n + 1 channel configuration method, N 测试信道 = ; for the 4n + 4 channel configuration method, N 测试信道 = ; where represents rounding up, and N 测试信道 represents the number of test channels Use a multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group; Test the target channel, and return to execute the step of using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group until all the signal channels are tested.

2. The chip testing method according to claim 1, wherein The step of using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group includes: Generate a selection control signal for the target channel according to the test plan; Use the multiplexing module to receive and parse the selection control signal to locate the target channel currently corresponding to each test channel.

3. The chip testing method according to claim 2, characterized in that After using the multiplexing module to receive and parse the control signal to locate the target channel currently corresponding to each test channel, it further includes: Adjust the internal connection path through the multiplexing module to connect each test channel to the target channel in the corresponding signal channel group.

4. The chip testing method according to claim 2, wherein The test plan includes the test parameters and test sequence of each signal channel.

5. The chip testing method according to claim 1, wherein It also includes: Collect the test results of each signal channel; Analyze the test results to evaluate the performance and reliability of the chip; When a fault is found, perform a fault isolation test through the redundant channel.

6. A chip testing device, characterized in that, Including: A first determination unit for determining the number of signal channels and test requirements of the chip to be tested; A second determination unit for determining the target channel configuration method from the preset channel configuration methods according to the number of signal channels and the test requirements; A channel configuration unit is configured to group a plurality of the signal channels; configure a test channel for each group of the signal channels according to the grouping result, and add redundant test channels and / or parallel test channels according to a target channel configuration method. Each of the test channels corresponds to a signal channel group, and each signal channel group includes 4 of the signal channels. The preset channel configuration methods include a 4n + 1 channel configuration method and a 4n + 4 channel configuration method; when the number of signal channels is M, if M mod 4 = 0, then the 4n + 4 channel configuration method is selected; if M mod 4 ≠ 0, then the 4n + 1 channel configuration method is selected; for the 4n + 1 channel configuration method, N 测试信道 = ; for the 4n + 4 channel configuration method, N 测试信道 = ; where denotes rounding up, and N 测试信道 denotes the number of test channels. A target selection unit for using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group; A channel test unit for testing the target channel and returning to execute the step of using the multiplexing module to select the target channel currently corresponding to each test channel from the corresponding signal channel group until all the signal channels are tested.

7. A storage medium, characterized in that, The storage medium stores multiple instructions, and the instructions are suitable for being loaded by a processor to execute the chip test method according to any one of claims 1-5.

8. An electronic device, characterized in that, Including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the computer program, the chip test method according to any one of claims 1-5 is implemented.

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