Photosensitive chip and distance measuring device

Abstract

The present application provides a photosensitive chip and a distance measurement device, the photosensitive chip includes a SPAD pixel array, a pixel row and column control circuit and a readout circuit; the SPAD pixel array includes a plurality of SPAD pixel units, the SPAD pixel units are used to collect photons to output pulse signals; the pixel row and column control circuit includes a plurality of gating subcircuits, the plurality of gating subcircuits correspond to the plurality of SPAD pixel units one by one, the gating subcircuits include a first enabling unit, a second enabling unit and an output circuit, the output circuit is connected to the first enabling unit and the second enabling unit, and is used to output a response signal to activate the SPAD pixel unit corresponding to the gating subcircuit; the readout circuit is used to receive the response signal to output a histogram, and the histogram is used to record the number of pulse signals. The solution provided by the present application can realize the rapid gating of the SPAD pixel array, which helps to improve the accuracy and stability of distance measurement.

Description

Technical Field

[0001] The present application relates to the field of sensor technology, and in particular, to a photosensitive chip and a distance measuring device. Background Art

[0002] A single-photon avalanche photodiode (SPAD) pixel array is a highly sensitive photodetector array that can detect single photons at very low light levels. The SPAD pixel array consists of many independent pixel units, and each pixel can contain a SPAD for detecting photons.

[0003] With the development of technology, SPAD pixel arrays have gradually been used to form DTOF (Direct-Time-Of-Flight, DTOF) systems. The corresponding serial gating technology allows the system to activate and read pixel units in the SPAD array one by one or in groups to reduce the complexity of data transmission and improve processing efficiency. In order to obtain higher point frequencies and larger field of view, the scale of SPAD arrays is getting larger and larger, called large-array SPAD pixel arrays. The system will turn on or off some pixel units according to demand to achieve specific ranging requirements. For photon detection in large-array SPAD pixel arrays, there are problems with long gating time and low independence in the pixel activation method, and fast and accurate pixel gating cannot be achieved.

[0004] Based on this, how to achieve fast and accurate gating of the SPAD pixel array is an urgent problem to be solved. Summary of the invention

[0005] The present application provides a photosensitive chip and a distance measurement device, which can realize fast and flexible gating of a single SPAD pixel unit or a large array SPAD, helping to improve the accuracy and stability of distance measurement.

[0006] In a first aspect, a photosensitive chip is provided, which includes a SPAD pixel array, a pixel row and column control circuit, and a readout circuit; the SPAD pixel array includes a plurality of SPAD pixel units, and the SPAD pixel units are used to collect photons to output pulse signals; the pixel row and column control circuit includes a plurality of gating subcircuits, and the plurality of gating subcircuits correspond one-to-one to the plurality of SPAD pixel units, and the gating subcircuit includes a first enabling unit, a second enabling unit, and an output circuit, and the output circuit is connected to the first enabling unit and the second enabling unit, and is used to output a response signal to activate the SPAD pixel unit corresponding to the gating subcircuit; the readout circuit includes a sampling subcircuit, a TDC subcircuit, and a histogram processing subcircuit, and the readout circuit is used to receive the response signal to output a histogram, and the histogram is used to record the number of pulse signals.

[0007] Through the technical solution of the embodiment of the present application, each SPAD pixel unit is provided with a corresponding gating subcircuit, and any SPAD pixel unit is gated and activated by the first enabling unit and the second enabling unit. The cooperation of the two enabling units can accurately locate the SPAD pixel unit, which helps to enhance the signal acquisition efficiency and thus improve the accuracy of pixel activation. The histogram processing subcircuit can match the SPAD pixel unit activation information with the time information, realize the sorting and summarization of the SPAD pixel unit activation events, and output them in an intuitive manner, thereby improving the efficiency of signal processing.

[0008] In combination with the first aspect, in certain implementations of the first aspect, the first enabling unit is used to calibrate the SPAD pixel unit; the second enabling unit is used to select the SPAD pixel unit; the first enabling unit and the second enabling unit cooperate to activate the SPAD pixel unit.

[0009] Through the technical solution of the embodiment of the present application, based on the cooperation of two enabling units, the SPAD pixel unit can be operated in two processes to realize the identification and determination of the activated SPAD pixel unit, thereby ensuring the accuracy of the SPAD pixel unit activation, reducing the activation and signal acquisition of erroneous pixels, and effectively reducing the signal-to-noise ratio.

[0010] In combination with the first aspect, in some implementations of the first aspect, the first enabling unit and the second enabling unit cooperate to realize the activation of the SPAD pixel unit, including: when the SPAD pixel unit is calibrated by the first enabling unit and is selected by the second enabling unit, the SPAD pixel unit is activated. Wherein, the first enabling unit includes a second AND gate and a D flip-flop, the second AND gate includes three input terminals and an output terminal, the three input terminals are used to respectively receive the first enabling signal, the first selection signal and the second selection signal and output the signal to the D flip-flop through the logic AND operation of the second AND gate through the output terminal; the D flip-flop includes a clock input terminal connected to the output terminal of the second AND gate, a data input terminal for inputting a high level signal, a reset terminal for inputting a reset signal, and an output terminal for outputting a first response signal, and the first response signal of the first enabling unit is obtained by the signal cooperation between the clock input terminal, the data input terminal and the reset terminal input signal. The second enabling unit includes a third input AND gate, the third input AND gate includes three input terminals and an output terminal, the three input terminals are used to respectively input the second enabling signal, the first selection signal and the second selection signal and output the second response signal through the logic AND operation through the output terminal of the third AND gate. The output circuit includes a first AND gate, which includes two input terminals and an output terminal. The two input terminals are used to receive a first response signal and a second response signal respectively and output a pixel activation signal through a logic AND operation via the output terminal to control the SPAD pixel unit in the SPAD pixel array.

[0011] Through the technical solution of the embodiment of the present application, the calibration enabling process and the gating enabling process cooperate with each other, and the gating subcircuit can calibrate and gate all SPAD pixel units to accurately find the SPAD pixel units that need to be activated. The process can accurately locate on a single SPAD pixel unit to achieve the opening or closing control of any single SPAD pixel unit, while ensuring the gating speed, thereby improving the efficiency and accuracy of SPAD pixel unit activation.

[0012] In combination with the first aspect, in some implementations of the first aspect, the pixel row and column control circuit includes a first selection signal input terminal and a second selection signal input terminal, and the first selection signal input terminal and the second selection signal input terminal have pixel symmetry.

[0013] Through the technical solution of the embodiment of the present application, the arrangement of the row and column enable input terminals satisfies symmetry, that is, they are symmetrical about the diagonal of the pixel array. The SPAD pixel unit is quickly enabled by sharing the row and column enable input terminals, which reduces the circuit redundancy of each SPAD pixel unit having a row and column enable input terminal. This enables rapid activation control of the SPAD pixel unit, reduces the occupied area of ​​the pixel row and column control circuit, and is conducive to the miniaturization of the photosensitive chip.

[0014] In combination with the first aspect, in certain implementations of the first aspect, the photosensitive chip also includes a pixel front-end circuit, the pixel front-end circuit includes a SPAD pixel circuit corresponding one-to-one to multiple SPAD pixel units; the SPAD pixel circuit includes a protection circuit, the protection circuit is connected between the quenching sub-circuit and the pixel diode, the protection circuit includes a current limiting resistor and a protection diode, and the protection circuit is used to protect the SPAD pixel unit under high voltage conditions.

[0015] Through the technical solution of the embodiment of the present application, the protection circuit and the current limiting resistor can make the clamping effect of the diode within a controllable range, thereby improving the protection effect of the protection circuit and enhancing the safety of the device. The structure is simple in design and occupies a small layout area, which facilitates the process of manufacturing integrated circuits and simplifies the integration of the readout circuit.

[0016] In combination with the first aspect, in some implementations of the first aspect, the TDC subcircuit of the readout circuit includes at least two TDC units, and the TDC unit includes a timer and an adder.

[0017] The TDC subcircuit performs clock synchronization on the activation signal of the SPAD pixel unit. The statistical value of the synchronous adder is synchronized with the time value of the timer. At the same time, the numerical values ​​of the synchronous adder and the timer are input into the histogram processing circuit. The histogram processing circuit can count the numerical values ​​counted by the synchronous adder and the count value of the timer to obtain a real-time histogram, wherein the value of the timer represents the time axis of the histogram, i.e., the horizontal axis, and the value of the synchronous adder represents the quantity value of the histogram, i.e., the vertical axis.

[0018] Through the technical solution of the embodiment of the present application, the readout circuit can perform real-time statistics on photon detection events, and ultimately obtain highly accurate and real-time statistical results, thereby improving the performance of signal acquisition.

[0019] In combination with the first aspect, in certain implementations of the first aspect, the TDC subcircuit may further include a threshold control unit, which is used to calculate a threshold of photons to distinguish and identify background light.

[0020] Through the technical solution of the embodiment of the present application, the threshold control unit counts the pulse signal within a preset time. If the number of collected photons reaches a preset threshold, it means that most of the photons collected by the threshold control unit are photons in the light beam reflected back to the ranging device, and a stop signal is sent to indicate the reset of the SPAD pixel array. By distinguishing the reflected pulse light beam and the background light signal in real time through the threshold control unit, the false trigger signal caused by background light interference or dark count can be effectively reduced, thereby improving the accuracy of photon detection.

[0021] In combination with the first aspect, in certain implementations of the first aspect, the histogram processing subcircuit of the readout circuit is connected to the TDC subcircuit, and the histogram processing subcircuit is used to receive the counts output by the TDC unit to integrate them into a histogram; wherein the horizontal axis of the histogram represents time information, and the vertical axis of the histogram represents the number of pulse signals per unit time.

[0022] Through the technical solution of the embodiment of the present application, the histogram processing subcircuit integrates and summarizes the output signals of the synchronous adder and the timer, which can realize the real-time output of the histogram, provide intuitive and efficient data analysis, and improve the efficiency of data output analysis.

[0023] In combination with the first aspect, in certain implementations of the first aspect, the sampling subcircuit of the readout circuit includes a first shaping synchronization unit and a second shaping synchronization unit; the first shaping synchronization unit is connected to the SPAD pixel array, and the first shaping synchronization unit is used to shape and synchronize the pulse signal output by the SPAD pixel array; the second shaping synchronization unit is connected to the control and processor and the clock source, and the second shaping synchronization unit is used to shape and synchronize the instructions issued by the control and processor and the control signal output by the clock source.

[0024] Through the technical solution of the embodiment of the present application, shaping and synchronizing the pulse signal can make the signals have clock synchronization, facilitate information processing of subsequent circuits, and improve the efficiency and accuracy of signal acquisition and processing.

[0025] In combination with the first aspect, in certain implementations of the first aspect, the shaping synchronization unit includes at least a first synchronization trigger, a second synchronization trigger and a third synchronization trigger, and the first synchronization trigger, the second synchronization trigger and the third synchronization trigger cooperate to achieve shaping synchronization of the signal input to the shaping synchronization unit; the complementary output end of the third synchronization trigger is connected to the reset end of the first synchronization trigger, the second synchronization trigger and the third synchronization trigger to activate the first synchronization trigger, the second synchronization trigger and the third synchronization trigger.

[0026] Through the technical solution of the embodiment of the present application, three synchronous triggers with the same structure cooperate with each other to realize signal transmission and reset control, thereby saving devices in the circuit and improving signal synchronization and processing performance.

[0027] In a second aspect, a distance measuring device is provided, comprising a transmitter, a collector, and a control and processor; the transmitter is used to emit a first light beam to a target object; the collector comprises a photosensitive chip as implemented in any one of the first aspects, and is used to collect a second light beam reflected by the target object to obtain a histogram; the control and processor is used to calculate the distance between the target object and the distance measuring device according to the histogram. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of a system 100 of a distance measurement device provided in an embodiment of the present application;

[0029] Figure 2 is a schematic structural diagram of a photosensitive chip 200 provided in an embodiment of the present application;

[0030] Figure 3 is a schematic structural diagram of another photosensitive chip 300 provided in an embodiment of the present application;

[0031] Figure 4 is a structural schematic diagram of a gating subcircuit 400 provided in an embodiment of the present application;

[0032] Figure 5 is a circuit diagram of another gating subcircuit 500 provided in an embodiment of the present application;

[0033] Figure 6 is a working timing logic diagram of the gating subcircuit provided in an embodiment of the present application;

[0034] Figure 7Schematic diagram of the SPAD pixel unit gating process provided by an embodiment of the present application;

[0035] Figure 8 is a schematic diagram of a gating process of a SPAD pixel array provided in an embodiment of the present application;

[0036] Fig. 9 is a schematic diagram of a gating process when a bad pixel exists in a SPAD pixel array provided in an embodiment of the present application;

[0037] Fig.10 is a structural schematic diagram of a pixel row and column control circuit provided in an embodiment of the present application;

[0038] Fig.11 is a schematic diagram of the structure of a readout circuit 600 provided in an embodiment of the present application;

[0039] Fig.12 is a working timing diagram of the readout circuit provided in an embodiment of the present application;

[0040] Fig.13 It is a schematic diagram of a histogram provided in an embodiment of the present application;

[0041] Fig.14 is a schematic diagram of the circuit structure of a shaping synchronization unit provided in an embodiment of the present application;

[0042] Fig.15 Schematic diagram of a pixel front-end circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0044] Figure 1 A schematic diagram of a system 100 of a distance measuring device provided in an embodiment of the present application. The system 100 of the distance measuring device includes a DTOF module 101, which is used to emit a transmission light beam 103 and receive a reflected light beam 104 reflected by a target object 102. The DTOF module 101 includes a transmitter 110, a collector 120, and a control and processor 130 connected to the transmitter 110 and the collector 120. The transmitter 110 is used to continuously emit a transmission light beam 103 to an external target object 102, and the transmission light beam 103 is amplitude modulated in timing and has a fixed time interval, i.e., a pulse period. After being emitted, the transmission light beam 103 reaches the surface of the target object 102, wherein at least a portion of the transmission light beam 103 is reflected to form a reflected light beam 104, and at least a portion of the reflected light beam 104 is received by the collector 120 and converted into a corresponding electrical signal.

[0045] The collector 120 collects photons in the reflected light beam 104 and outputs a histogram of the number of photons per unit time, which is used to indicate the time taken for the photons in the emission light beam 103 to be emitted and received; the control and processor 130 calculates the distance between the DTOF module 101 and the target object 102 based on the histogram. Specifically, the control and processor 130 synchronizes the trigger signals of the emitter 110 and the collector 120, and receives and processes the histogram generated by the collector 120 to calculate the flight time of the reflected light beam 104 relative to the emission light beam 103, and then calculates the depth information of the target object 102 according to the calculated flight time.

[0046] See also Figure 1 The transmitter 110 includes one or more light sources 111, an emission optical element 112, and a driver 113. The light source 111 is used to continuously emit an emission light beam 103 with a fixed time interval to the target object 102. Under the control of the driver 113 or the control and processor 130, the light source 111 projects an amplitude-modulated emission light beam 103 to the emission optical element 112 at a certain pulse period. The emission light beam 103 is projected onto the target object 102 through the emission optical element 112 to form a corresponding illumination spot. After receiving the emission light beam 103 emitted by the light source 111, the emission optical element 112 projects the received emission light beam 103 to the target object 102 in space, and the emission optical element 112 can also modulate the pulse emission light beam 103.

[0047] Exemplarily, the emission light beam 103 may be, for example, a pulse modulated light beam, a square wave modulated light beam, a sine wave modulated light beam, etc. The light source 111 may be, for example, a single light source such as a light-emitting diode (LED), an edge-emitting laser (EEL), a vertical cavity surface-emitting laser (VCSEL), etc., or a VCSEL array light source chip formed by generating multiple VCSELs on a single semiconductor substrate. The emission optical element 112 may be, for example, a lens (a lens group composed of multiple single-piece lenses), a diffractive optical element (DOE), a diffuser, a metasurface optical element, a micro-lens array (MLA), a mask, a reflector, a galvanometer of a micro-electromechanical system, etc., or a combination of multiple thereof. In addition, the modulation method may, for example, include at least one of collimation, beam expansion, diffraction, and shaping.

[0048] Continue to see Figure 1The collector 120 includes a photosensitive chip 121, a filter unit 122, and a receiving optical element 123. The receiving optical element 123 is used to receive the reflected light beam 104 reflected by the target object 102, and image it on the photosensitive chip 121. The photosensitive chip 121 includes a plurality of pixels, at least one of which collects photons in the reflected light beam 104, and outputs a corresponding histogram to the control and processor 130 after calculation.

[0049] Exemplarily, the pixels in the photosensitive chip 121 can be at least one of single-photon devices such as SPAD, silicon photomultiplier (SiPM), etc. In the embodiment of the present application, the photosensitive chip 121 includes a SPAD array composed of a plurality of SPAD pixels, and the SPAD array can respond to a received single photon to output a photon signal indicating the corresponding arrival time of the received photon at each SPAD pixel.

[0050] Continue to see Figure 1 The receiving optical element 123 is used to receive at least part of the reflected light beam 104 reflected by the target object 102 and image it on the photosensitive chip 121. In some embodiments, the filtering unit 122 is configured as a narrow-band filter that matches the wavelength of the light source 111, and is used to filter out ambient light in other bands to reduce interference.

[0051] Taking the system 100 of the distance measuring device as an example, in the existing ranging method, the system 100 turns on or off some pixels according to the needs to achieve specific ranging needs. The control process of turning the pixels on or off is called pixel gating. Specifically, the system activates and reads the pixel units in the SPAD array one by one or in groups to reduce the complexity of data transmission and improve processing efficiency. With the development of technology, in order to obtain higher point frequencies and field angles, the scale of SPAD arrays is set to be larger and larger, which is called large-array SPAD. Existing system pixel gating methods include serial and row-column gating methods, which can realize the gating and closing of any pixel, but for large-array SPAD, as the number of pixels increases, the time required for pixel gating will increase accordingly, affecting work efficiency, or it is impossible to achieve independent control of any SPAD pixel unit.

[0052] Based on the above problems, the present application proposes a photosensitive chip that can control the rows and columns of the SPAD pixel array, so as to be able to control a single pixel while ensuring the technical speed of the gating, and can achieve rapid gating of large-array SPADs, which helps to improve the accuracy and stability of the device in distance measurement, while reducing the area of ​​the circuit board diagram and saving costs.

[0053] Figure 2FIG. 2 shows a schematic diagram of the structure of a photosensitive chip 200 provided in an embodiment of the present application. The photosensitive chip 200 may be, for example, Figure 1 The photosensitive chip 121 in the system 100 is shown.

[0054] like Figure 2 As shown, the photosensitive chip 200 includes a SPAD pixel array, a pixel row and column control circuit, and a readout circuit. Among them, the SPAD pixel array includes a plurality of SPAD pixel units, and the SPAD pixel units are used to collect photons to output pulse signals; the pixel row and column control circuit includes a plurality of gating subcircuits, and the plurality of gating subcircuits correspond to the plurality of SPAD pixel units one by one, and the gating subcircuit includes a first enabling unit, a second enabling unit, and an output circuit, and the output circuit is connected to the first enabling unit and the second enabling unit, and is used to output a response signal to activate the SPAD pixel unit corresponding to the gating subcircuit; the readout circuit includes a sampling subcircuit, a time-digital converter (Time-Digital-Converter, TDC) subcircuit, and a histogram processing subcircuit, and the readout circuit is used to receive a pulse signal to output a histogram, and the histogram is used to record the number of pulse signals.

[0055] In the embodiment of the present application, each SPAD pixel unit in the photosensitive chip 200 is provided with a corresponding gating subcircuit, and any SPAD pixel unit is gating-activated by the first enabling unit and the second enabling unit in the gating subcircuit. The cooperation between the two enabling units can accurately locate the SPAD pixel unit, which helps to enhance the signal collection efficiency and thereby improve the accuracy of pixel activation.

[0056] See also Figure 2 The SPAD pixel array of the photosensitive chip 200 is provided with a plurality of SPAD pixel units arranged in a two-dimensional dot matrix, each SPAD pixel unit may contain a SPAD to detect a single photon, and the SPAD pixel array is used to collect photons in the light beam reflected to the photosensitive chip 200 and convert them into a small amount of electrons, so that the SPAD pixel array triggers an avalanche effect, thereby generating an avalanche current for collecting photon detection events. The light beam may be as follows: Figure 1 System 100 is shown with a reflected light beam 104 reflected from a target object 102 .

[0057] Among them, the avalanche effect refers to the state where the SPAD operates at a reverse bias voltage close to or exceeding the avalanche breakdown voltage. When a single photon is absorbed by the SPAD, the photogenerated carriers (electrons or holes) generated are accelerated by the strong electric field and ionized through internal collisions to generate more electron-hole pairs, resulting in current doubling, forming an "avalanche effect" and generating an electrical signal that can be detected (i.e., avalanche current).

[0058] Through the avalanche effect and the avalanche current, each SPAD pixel unit in the SPAD pixel array can trigger a high current when receiving a photon, so as to provide real-time feedback on the event of detecting the photon, thereby realizing real-time photon detection in the photosensitive chip 200 and improving the accuracy and timeliness of the signal.

[0059] Continue to see Figure 2 The pixel row and column control circuit is used to parse the received control signal to obtain the address of the pixel unit, and generate the working timing of the pixel unit according to the pixel address, so as to control the opening or closing of the pixel unit at the corresponding address in the SPAD pixel array. When a pixel in the SPAD pixel array is turned on, it means that the pixel can be used to collect photons in the light beam reflected to the photosensitive chip 200 to collect the reflection signal of the light beam. The control signal received by the pixel row and column control circuit can be sent by the SPAD control module.

[0060] In some embodiments, the pixel row and column control circuit can also be used to read the photon signal generated by the photons in the light beam collected by the pixel. The pixel unit is the pixel unit turned on at the corresponding position of the aforementioned SPAD pixel array. The pixel row and column control circuit sends the photon signal to the readout circuit for data processing.

[0061] Specifically, the gating subcircuit includes a first enabling unit, a second enabling unit and an output circuit, wherein the first enabling unit is used to calibrate the pixel unit. After the calibration process is completed, the second enabling unit is used to gate the pixel unit. When the pixel unit is calibrated and gated at the same time, the pixel unit is activated or turned on to detect photons in the reflected light beam.

[0062] Continue to see Figure 2 The readout circuit is used to sample the pulse signal output by the pixel front-end circuit, perform time-to-digital conversion, and output a histogram. The sampling subcircuit in the readout circuit is used to sample the pulse signal under the control of the clock signal to detect the flight time of the pulse beam through the TDC subcircuit, that is, the time interval from the start of emission to the time when the photon detection event occurs. Among them, the clock signal is emitted by the clock generator, and the pulse signal is the electrical signal generated by the pixel unit after receiving the photon.

[0063] Specifically, the sampling subcircuit is used to sample the pulse signal within a certain sampling time interval to detect the occurrence of a photon detection event. When a pulse signal is sampled, that is, a photon detection event occurs, the time signal of the pulse light beam is detected by the TDC subcircuit. The time signal is generated based on the time interval from the start of emission to the time when the photon detection event occurs, and is used to indicate the flight time of the pulse light beam from emission to reception.

[0064] It should be noted that, under the control of the clock signal of the clock generator, the sampling subcircuit continues sampling until it is reset and waits for the next sampling; the pulse beam can be as follows Figure 1 The emission light beam 103 in the system 100 is shown; the sampling time interval of the sampling subcircuit can be, for example, nanoseconds or microseconds, which is not specifically limited in the present application.

[0065] The histogram processing subcircuit includes multiple storage units, which can also be called time bins, and each time bin corresponds to a different time interval. Specifically, after the time signal is obtained using the TDC subcircuit, the signal will be input into the histogram processing subcircuit, matched to the corresponding storage unit in the histogram processing subcircuit, that is, the time bin corresponding to the time interval, and the corresponding time signal will be recorded in the histogram so that the count value in the time bin is increased by 1. After repeatedly emitting multiple pulse light beams to the target object, the time signals of multiple detections are input into the corresponding time bins of the histogram processing subcircuit and stored. At this time, the corresponding photon count values ​​under different time bins are recorded in the histogram processing subcircuit, and finally the histogram processing subcircuit generates a histogram containing the flight times corresponding to the multiple pulse light beams.

[0066] By collecting and integrating the signals of the TDC sub-circuit through the histogram processing sub-circuit, the SPAD pixel unit activation information can be matched with the time information, the SPAD pixel unit activation events can be sorted and summarized, and output in an intuitive manner, thereby improving the efficiency of signal processing.

[0067] Figure 3 FIG. 1 shows a schematic diagram of the structure of another photosensitive chip 300 provided in an embodiment of the present application. The photosensitive chip 300 may be, for example, Figure 1 The photosensitive chip 121 in the system 100 shown in FIG. Figure 2 The photosensitive chip 200 is shown.

[0068] like Figure 3 As shown, the photosensitive chip 300 includes a state control module, which is electrically connected to the control and processor via a serial peripheral interface (SPI) interface, and is electrically connected to the SPAD control module and the clock source respectively. The state control module is used to generate corresponding instructions according to the program and send them to other modules to control the overall operating state of the photosensitive chip 300.

[0069] The SPI interface is a high-speed synchronous communication bus used for communication between the microcontroller and various peripheral devices. The control and processor can be, for example, Figure 1In the control and processor 130 of the system 100 shown in FIG, the program may be pre-embedded in the control and processor and transmitted via the SPI interface to instruct the state control module to work.

[0070] See also Figure 3 The photosensitive chip 300 also includes a SPAD control module, which is used to receive instructions from the overall state control module and / or an external control signal provided externally to generate an address corresponding to a pixel unit in the SPAD pixel array that needs to respond, and generate a corresponding control signal based on the address and send it to the pixel row and column control circuit.

[0071] Exemplarily, the SPAD control module can generate instructions for controlling p×q pixels in the SPAD pixel array, so as to enable p×q pixels to work simultaneously through the pixel row and column control circuit, and can also generate instructions for a single pixel to control each pixel in the SPAD pixel array to work independently. Wherein, p represents the number of rows of the enabled pixel array, q represents the number of columns of the enabled pixel array, p is greater than or equal to 1 and less than or equal to the number of rows of the SPAD pixel array, q is greater than or equal to 1 and less than or equal to the number of columns of the SPAD pixel array, the values ​​of p and q may be the same or different, and the present application does not specifically limit their values.

[0072] Continue to see Figure 3 , the photosensitive chip 300 also includes a pixel front-end circuit, which is electrically connected to the SPAD pixel array and is used to process the signal received from the SPAD pixel unit and convert it into a format to facilitate subsequent information processing. Specifically, the pixel front-end circuit includes a plurality of SPAD pixel circuits corresponding to the SPAD pixel units one by one, and the SPAD pixel circuit includes a quenching subcircuit and a signal reading subcircuit. The quenching subcircuit is used to sense and suppress the avalanche current of the SPAD pixel unit when the SPAD pixel unit generates an avalanche effect, and reset the SPAD pixel unit to restore it to the initial detection state, that is, the state before the avalanche effect occurs, so as to perform the next round of photon detection; the signal reading subcircuit is used to generate a pulse signal corresponding to the avalanche effect to the readout circuit, and the pulse signal represents that the SPAD pixel unit detects a photon to indicate a photon detection event, so it is also called a photon signal.

[0073] It should be noted that SPAD refers to an avalanche photodiode (APD) with an operating voltage higher than the breakdown voltage, or Geiger mode APD. Geiger mode refers to the operating mode of the APD when the reverse bias voltage is higher than its avalanche voltage. The quenching subcircuit is a circuit used to control the avalanche current of the APD operating in Geiger mode. In Geiger mode, the reverse bias voltage of the APD is higher than the breakdown voltage, so that the internal electric field is strong enough so that the photocurrent can obtain a great gain. When a single photon is incident on the APD, it can trigger the avalanche effect, thereby generating an extremely high current to achieve single photon detection. When the avalanche current is not controlled in the device, the current will continue to increase and damage the device. Therefore, the quenching subcircuit is used to quickly stop the avalanche effect after detecting a photon to protect the APD from damage and enable it to prepare for the next photon detection.

[0074] Optionally, the principles of the quenching circuit include passive quenching, active quenching and mixed quenching. Specifically, the passive quenching method is to connect a large resistor in series on the APD, and use the voltage divider principle of the resistor to reduce the avalanche voltage on the APD, thereby stopping the avalanche effect; the active quenching method is to force the reverse bias voltage of the APD to be reduced through an additional control structure after the avalanche current is detected to achieve rapid quenching. Mixed quenching combines active and passive quenching mechanisms, and generally includes two types of quenching circuits, active and passive, to improve the controllability of the APD operation and suppress the dark count rate. The quenching subcircuit in the pixel front-end circuit provided in the present application can adopt any of passive quenching, active quenching and mixed quenching, and the present application does not make specific limitations on this.

[0075] Continue to see Figure 3 , the photosensitive chip 300 also includes a clock source, which may include a phase-locked loop (PLL) and a clock generator (CLK Gen), and the clock source is also connected to an external crystal oscillator (Crystal, XTAL), which is used to provide a reference clock signal source for the clock source. The lock loop is used to synchronize the phase of an oscillator with the phase of the input signal through its phase locking mechanism. In the embodiment of the present application, the lock loop can ensure that the output clock signal is consistent with the input clock signal in phase; the clock generator is used to generate an accurate clock signal, which can be used to synchronize various operations in digital circuits. The clock generator can be set in an electronic system, such as a microprocessor, a communication device, and a computer motherboard, which require a stable clock signal to coordinate data transmission and processing. In the embodiment of the present application, the clock generator is used to generate a reference clock signal and send the signal to the state control module to ensure the synchronization of data transmission and processing in the photosensitive chip 300.

[0076] In addition to the clock source, the photosensitive chip 300 also includes a timing generation circuit, which is electrically connected to the SPAD control module and the state control module, respectively, for receiving instructions from the state control module and generating a readout operation timing of the readout circuit to control the working state of each sub-circuit in the readout circuit. The readout circuit can be, for example, Figure 2 The readout circuit in the photosensitive chip 300 is shown.

[0077] Exemplarily, the state control module can generate corresponding instructions in combination with the reference clock signal of the clock generator and the received external control signal, and send them to the firing control module and the SPAD control module connected thereto, and generate corresponding firing signals and control signals to control the on or off of the emitter and the SPAD pixel array, respectively. Optionally, the corresponding instructions generated by the state control module can also be sent to the timing generation circuit, and the timing generation circuit generates the corresponding readout working timing according to the corresponding instructions to control the working state of the sub-circuit in the readout circuit.

[0078] Continue to see Figure 3 The photosensitive chip 300 also includes a firing control module and a data output module. Specifically, the firing control module is used to receive instructions from the state control module to generate a firing signal corresponding to the time when the transmitter transmits a pulse beam to the target object, and send it to the transmitter (such as Figure 1 The transmitter 110 in the system 100 is used to control the transmitter to transmit a pulsed light beam (such as Figure 1 In addition, the firing signal can also be synchronously sent to the readout circuit and processed by the TDC subcircuit to obtain a time signal indicating the flight time of the pulsed light beam from emission to reception. The data output module includes a data packaging circuit and a high-speed interface, which is used to package the histogram processing subcircuit after the readout circuit obtains the histogram to make it conform to the processing format of the control and processor, and output it to the control and processor through a high-speed data output interface.

[0079] In addition to the above-mentioned circuit modules, the photosensitive chip 300 also includes other modules, which may include, for example, a power management module and / or a temperature sensor. The power management module is used to provide a power source for the photosensitive chip 300, and the temperature sensor is used to measure the temperature of the entire photosensitive chip 300. When the temperature exceeds the standard, the photosensitive chip 300 is turned off in time or the cooling device is turned on to avoid damaging the photosensitive chip 300.

[0080] Combine the following Figure 4 and Figure 5 The structure of the gating subcircuit in the aforementioned pixel row and column control circuit is described in detail.

[0081] Figure 4 A schematic structural diagram of a gating subcircuit 400 provided in an embodiment of the present application is shown. The gating subcircuit 400 includes a first enabling unit, a second enabling unit, and an output circuit.

[0082] like Figure 4 As shown, the first enabling unit is used to calibrate the SPAD pixel unit, and the second enabling unit is used to gate the SPAD pixel unit. The first enabling unit and the second enabling unit cooperate to activate the SPAD pixel unit.

[0083] See also Figure 4 In the circuit, the first enabling unit is used to receive the first enabling signal, the first selecting signal, the second selecting signal, the clearing and resetting signal and the high level signal (VH), so as to output the first response signal through the signal coordination among the first enabling signal, the first selecting signal, the second selecting signal, the clearing and resetting signal and the high level signal; the second enabling unit is used to receive the first selecting signal, the second selecting signal and the second enabling signal, and output the second response signal through the signal coordination among the signals; the output circuit is used to receive the first response signal and the second response signal output by the first enabling unit and the second enabling unit, and output the output signal of the selecting sub-circuit 400 in combination with the first response signal and the second response signal to activate the corresponding pixel for response.

[0084] The above-mentioned first enabling unit and second enabling unit cooperate to realize the activation of SPAD pixel unit, including: when the SPAD pixel unit is calibrated by the first enabling unit and is gated by the second enabling unit, the SPAD pixel unit is activated. Specifically, the first enabling unit first operates all SPAD pixel units to calibrate a single SPAD pixel unit. After the calibration process is completed, the second enabling unit operates all SPAD pixel units to perform rapid gating. After the gating process is completed, if the SPAD pixel unit is calibrated and gated at the same time, the pixel unit is activated for detecting photons.

[0085] The gating subcircuit 400 provided in the embodiment of the present application can operate the SPAD pixel unit in two processes through the cooperation of two enabling units to realize the identification and determination of the activated SPAD pixel unit, thereby ensuring the accuracy of the activation of the SPAD pixel unit, reducing the activation and signal acquisition of erroneous pixels, and effectively reducing the signal-to-noise ratio.

[0086] Figure 5 FIG. 5 shows a circuit diagram of another gating subcircuit 500 provided in an embodiment of the present application. The gating subcircuit 500 may include, for example, Figure 4The structure of the gating subcircuit 400 is shown. The first enabling unit is used to calibrate the pixel unit, so it is also called a calibration enabling unit, and the second enabling unit is used to gating the pixel unit, so it is also called a gating enabling unit.

[0087] like Figure 5 As shown, the calibration enable unit includes a second AND gate and a synchronous trigger, also known as a D flip-flop (D filp-flop, DFF). The second AND gate is a three-input AND gate, that is, it is provided with three input terminals and one output terminal. The three input terminals respectively input a first enable signal (also known as a calibration enable signal spad_cb_en), a first selection signal (also known as a row selection signal spad_en_h) and a second selection signal (also known as a column selection signal spad_en_v). After the logic operation inside the AND gate, the signal is output to the synchronous trigger through the output terminal of the second AND gate. The synchronous trigger includes a clock input terminal (CLK terminal) connected to the output terminal of the second AND gate, a data input terminal (D terminal) inputting a high level signal (also called Logic_high), a reset terminal of the synchronous trigger inputting a clear reset signal (also called spad_cb_resetn), and an output terminal ("Q" terminal) outputting a first response signal of the calibration enable unit, the first response signal is also called a calibration response signal (also called spad_alive_en), and the first response signal of the first enable unit is obtained by signal coordination between the clock input terminal, the data input terminal and the reset terminal input signal. This application ignores the complementary output terminal ( terminal) output.

[0088] See also Figure 5 The gating enable unit includes a third AND gate, which is a three-input AND gate, that is, it is provided with three input terminals and one output terminal, and the three input terminals respectively input the second enable signal (also called the gating enable signal), the row gating signal and the column gating signal, and through the logical AND operation of the AND gate, the second response signal (also called the gating response signal, spad_fire_en) is output from the output terminal. The output circuit includes a first AND gate, which is a two-input AND gate, that is, it is provided with two input terminals and one output terminal, and the two input terminals respectively receive the calibration response signal and the gating response signal, and after obtaining the two response signals, the output signal of the gating subcircuit 500 is output from the output terminal through the logical operation of the AND gate, and the output signal is used to control the SPAD pixel unit in the SPAD pixel array, and is therefore also called a pixel activation signal (also called spad_en), and the SPAD pixel array can realize the closing or opening of the corresponding pixel unit according to the output signal.

[0089] Among them, the calibration enable signal and the selection enable signal are both issued by the pixel row and column control circuit to indicate the start of the calibration enable process and the selection enable process. The selection enable unit shares the row selection signal and the column selection signal with the calibration enable unit, that is, they use the same signal input terminal.

[0090] Combine the following Figure 6 The working process of the gating subcircuit is described in detail.

[0091] Figure 6 The working timing logic diagram of the gating subcircuit provided in the embodiment of the present application is shown. The gating subcircuit can be as follows Figure 4 or Figure 5 The gating sub-circuit 400 or the gating sub-circuit 500 is shown.

[0092] like Figure 6 As shown, the working timing logic diagram includes: a reset signal, a first enable signal, a second enable signal, a first selection signal, a second selection signal, a first response signal, a second response signal, and an output signal of the selection subcircuit. The selection process of the SPAD pixel unit includes a calibration enable process and a selection enable process in sequence. For ease of explanation, the low-level signal is recorded as a digital signal "0" and the high-level signal is recorded as a digital signal "1".

[0093] When the reset signal is at a low level, the existing signal in the pixel unit can be cleared. When it is at a high level, the pixel signal can be read in. In the calibration enable unit, the reset terminal in the D flip-flop receives the reset signal, and an input terminal of the second AND gate is connected to the calibration enable signal. When the calibration enable signal changes from a low level signal to a high level signal, it indicates that the selection subcircuit starts the calibration enable process. The other two input terminals of the second AND gate are respectively connected to the row selection signal and the column selection signal. When the low level signals of the two selection signals change to high level signals, it indicates that the SPAD pixel unit of the corresponding row and column of the signal is selected.

[0094] Specifically, see Figure 6In the calibration enabling process, when the calibration enabling signal changes from a low level signal to a high level signal, the calibration enabling process starts; at this time, starting with the row enabling signal, when the row enabling signal of the row where the SPAD pixel unit is located changes from a low level signal to a high level signal, the column enabling signal of each column of SPAD pixel units is obtained row by row, and when the column enabling signal of a column of SPAD pixel units on the row and the row enabling signal change from a low level signal to a high level signal at the same time, that is, when both are set to "1", a digital signal "1" is output from the output end through the logic AND operation of the second AND gate; after the digital signal "1" is input to the clock input end of the D flip-flop, the D flip-flop is triggered to sample and store the input of the signal of the data input end of the D flip-flop, that is, the high level signal is sampled as the output signal of the output end of the D flip-flop, and the calibration response signal of the currently selected SPAD pixel unit is set to a high level signal "1", indicating that the current SPAD pixel unit is configured as the calibration enabling state "1", that is, it is calibrated.

[0095] If any one of the row selection signal and the column selection signal is a low level signal, or the row selection signal and the column selection signal do not change from a low level signal to a high level signal at the same time, the output end of the second AND gate outputs a digital signal "0", and when the digital signal "0" is input to the clock input end of the D flip-flop, the D flip-flop maintains its current state and ignores the input of the digital signal "0", then the calibration response signal of the current SPAD pixel unit is set to "0", indicating that the current SPAD pixel unit is configured as the calibration enable state "0", that is, it is not calibrated. After the calibration process is completed, the calibration enable signal changes from a high level signal to a low level signal.

[0096] See also Figure 6 In the gating enable process, when the gating enable signal changes from a low level signal to a high level signal, the gating enable process starts; at this time, starting with the row gating signal, the row gating signal of the row where the SPAD pixel unit to be activated is located changes from a low level signal to a high level signal, and the column gating signal of each column of SPAD pixel units is obtained row by row; when the column gating signal of the SPAD pixel unit on the column and the row gating signal change from a low level signal to a high level signal at the same time, that is, when both are set to "1", the output end of the third AND gate outputs a digital signal "1", and the gating response signal of the currently selected SPAD pixel unit is set to a high level signal "1", indicating that the current SPAD pixel unit is configured as the gating enable state "1", that is, it is gating. If either the row selection signal or the column selection signal is a low level signal, or the row selection signal and the column selection signal do not change from a low level signal to a high level signal at the same time, the output end of the third AND gate outputs a digital signal "0", and the selection response signal of the currently selected SPAD pixel unit is set to a high level signal "0", indicating that the current SPAD pixel unit is configured as a selection enable state "0", that is, it is not selected.

[0097] When the calibration response signal and the strobe response signal are both high-level signals "1", that is, when the current SPAD pixel unit is calibrated and strobed at the same time, the two input terminal signals of the output circuit, i.e., the first AND gate, are both "1", and the output terminal output signal is a high-level signal "1", indicating that the SPAD pixel unit is strobed and activated. When either the calibration response signal or the strobe response signal is a low-level signal, or the calibration response signal and the strobe response signal are both low-level signals, the output terminal of the first AND gate outputs a low-level signal, indicating that the SPAD pixel unit is not strobed and activated.

[0098] Through the coordination of the calibration enabling process and the gating enabling process, the gating subcircuit can calibrate and gate all SPAD pixel units to accurately find the SPAD pixel units that need to be activated. This process can accurately locate a single SPAD pixel unit to achieve the on or off control of any single SPAD pixel unit, while ensuring the gating speed and improving the efficiency and accuracy of SPAD pixel unit activation.

[0099] Combine the following Figure 7 The gating process of the SPAD pixel unit is described in detail.

[0100] Figure 7 A schematic diagram of a SPAD pixel unit selection process provided by an embodiment of the present application is shown. Each intersection of rows and columns shown in the figure can represent a SPAD pixel unit, and the figure only shows a part of the SPAD pixel array.

[0101] like Figure 7As shown, the embodiment of the present application takes the activation of two SPAD pixel units as an example, and the coordinates of the two SPAD pixel units are (ik, j+1) and (ik+1, j), respectively, where i, j, and k are integers greater than or equal to 0, respectively. Starting with the row selection signal, the SPAD pixel units in each column are calibrated in turn. When the SPAD pixel units in the ikth row are calibrated, the row selection signal of the SPAD pixel units in the ikth row changes from a low level signal to a high level signal, and the column selection signals of the SPAD pixel units in each column of the ikth row are obtained column by column. When the row selection signal of the SPAD pixel unit in the jth column of the ikth row changes from a low level signal to a high level signal, or while maintaining a high level signal, its column selection signal changes from a low level signal to a high level signal, that is, it is calibrated simultaneously in the row and column, then the calibration response signal of the (ik, j+1) SPAD pixel unit is set to "1"; the column selection signals of the SPAD pixel units in the remaining columns are kept as low level signals when the row selection signal of the SPAD pixel unit in the ikth row changes from a low level signal to a high level signal, or while maintaining a high level signal, so that the calibration response signals of the SPAD pixel units in the ikth row except the j+1th column are set to "0".

[0102] When the calibration of the SPAD pixel units in the ikth row is completed, the SPAD pixel units in the ik+1th row are calibrated, and the process is the same as above, which will not be repeated here. The SPAD pixel units in the remaining rows and columns are analogous, starting with the row, traversing all SPAD pixel units row by row to write the calibration response signal row by row, and when the column-by-column traversal of a row of SPAD pixel units is completed, the row selection signal and column selection signal corresponding to the SPAD pixel unit in the current row and column are set to low-level signals, and the calibration of the next row is entered until the calibration of all SPAD pixel units is completed; when the calibration of all SPAD pixel units is completed, the calibration enable signal input to the second AND gate changes from a high-level signal to a low-level signal, indicating that the calibration enable process is completed, and the relevant information of the calibration response signal of each SPAD pixel unit is stored in the D flip-flop.

[0103] After completing the calibration and enabling process of all SPAD pixel units, the SPAD pixel array enters the gating and enabling process. In the gating and enabling unit, the gating and enabling signal changes from a low level signal to a high level signal, indicating the start of the gating and enabling process; the other two input terminals of the third AND gate input the row gating signal and the column gating signal of the current SPAD pixel unit, and both the row gating signal and the column gating signal change from a low level signal to a high level signal and are maintained, and the gating response signal is output through the output terminal of the third AND gate as a digital signal "1" to indicate the gating state "1", that is, the current SPAD pixel unit is gating. Among them, the input terminals of the third AND gate and the second AND gate share the row gating signal and the column gating signal.

[0104] After obtaining the calibration response signal and the gating response signal, the two input terminals of the first AND gate receive the calibration response signal and the gating response signal respectively, and the AND gate performs a logic operation. When the calibration response signal and the gating response signal are both digital signals "1", the output signal output by the output terminal of the first AND gate, i.e., the pixel activation signal, is a digital signal "1", thereby activating the corresponding pixel to open to collect photons; when either the calibration response signal or the gating response signal is a digital signal "0", the pixel activation signal output by the output terminal of the first AND gate is a digital signal "0", thereby keeping the corresponding SPAD pixel unit in a closed state, thereby realizing independent control of each SPAD pixel unit.

[0105] in, Figure 7 The row selection signal and column selection signal shown in the figure are variable in timing, and each SPAD pixel unit has a row selection signal and a column selection signal corresponding to its coordinates. In the calibration enabling process and the selection enabling process, the calibration is performed row by row and column by column. After the row selection signal of the row corresponding to the current SPAD pixel unit becomes high, the column selection signal on the row becomes high in turn. After the calibration of a single pixel is completed, the column selection signal becomes low in turn. After all SPAD pixel units on the row are calibrated, the row selection signal becomes low in turn, and the calibration of the next row of SPAD pixel units is performed. Optionally, the calibration enabling process can be started with a row selection signal or a column selection signal. In the embodiment of the present application, the row selection signal is used as an example.

[0106] The single SPAD pixel unit calibration and gating process provided in the embodiment of the present application can realize the activation of any SPAD pixel unit, and ensure the accuracy of the activation coordinates from the two processes, which can improve the flexibility of the SPAD pixel unit gating and activation, and effectively improve the work efficiency of SPAD pixel unit positioning and activation.

[0107] In addition to the above-mentioned gating activation of a single SPAD pixel unit, the gating subcircuit can also quickly gate a large array SPAD. Figure 8 The gating process of a large-array SPAD is described.

[0108] Figure 8 A schematic diagram of the gating process of the SPAD pixel array provided in an embodiment of the present application is shown.

[0109] like Figure 8 As shown, "0" and "1" in the SPAD pixel unit in the SPAD pixel array represent inactive and activated respectively, the SPAD pixel unit in the square area represents the part that is enabled by the enabling process, and the SPAD pixel unit in the circular area represents the activated part.

[0110] Specifically, the selection process is similar to Figure 7The gating process shown in is similar to that shown in . First, all SPAD pixel units are calibrated row by row, that is, the calibration enable state (calibration enable state "0" or calibration enable state "1") of each row is written row by row, and stored in the corresponding D flip-flop. Among them, when the transmitter of the distance measuring device emits a pulse light beam to the target object, the light source in the transmitter and the corresponding SPAD pixel array in the collector have a known corresponding relationship, that is, the corresponding relationship between the emission light beam channel and the receiving light beam channel, that is, when the light source at a position in the transmitter emits a light beam, the SPAD pixel array at the corresponding position in the collector can be activated through the above-mentioned gating process to collect photons to generate a histogram.

[0111] After completing the above calibration of all SPAD pixel units, the gating area of ​​the SPAD pixel array is selected by means of the rapidly changing row gating signal and column gating signal. The SPAD pixel units in the square area shown in the figure represent the gating area selected after both the row gating signal and the column gating signal are set to high level signals. It should be understood that the SPAD pixel units in the square area are the parts with the gating enable state of "1", and only the SPAD pixel units whose calibration enable state is also "1" are activated. At this time, as shown in the circular area, the pixels marked as "1" in the area are both calibrated and gating parts, that is, the SPAD pixel units that are finally activated.

[0112] Through the correspondence between the emitter light source and the SPAD pixel unit, the gating subcircuit can perform fast, preset calibration on the SAPD pixel array. Combined with fast row and column gating, it can activate only the SPAD pixel units that collect the reflected light beam, eliminate interfering pixels that only collect ambient light, and effectively improve the signal-to-noise ratio of detection.

[0113] For example, in addition to the above-mentioned situation where there are continuous SPAD pixel units in the large-array SPAD, there may be SPAD pixel units with poor performance in actual application scenarios. For example, the avalanche effect of the SPAD pixel unit is triggered when no photon is received, or the SPAD pixel unit cannot collect photon signals. Such SPAD pixel units are called bad pixels. Fig. 9 The selection process when a bad pixel exists in the SPAD pixel array is described.

[0114] Fig. 9 A schematic diagram of a selection process when a bad pixel exists in a SPAD pixel array provided in an embodiment of the present application is shown.

[0115] The calibration enabling process shown in the embodiment of the present application is similar to the aforementioned process, that is, it is performed row by row and column by column, and each SPAD pixel unit is independently set to a calibration enabling state of "0" or "1". It can be pre-calibrated before the collector in the distance measurement device works to find out the problematic SPAD pixel units and configure them to the calibration enabling state "0", such as Fig. 9 The SPAD pixel unit marked as "0" in the circular area in the middle. Figure 8 The selection process is similar to that shown in the figure. According to the row selection signal and the column selection signal, the rows and columns where the SPAD pixel units to be activated are quickly selected, so that the specific pixels can be turned on or off within nanoseconds, and the bad SPAD pixel units marked as the calibrated enable state "0" can be quickly eliminated.

[0116] By eliminating bad pixels during the calibration enable process, it can be combined with fast selection during the gating enable process to achieve efficient gating activation, which can accurately and effectively avoid bad SPAD pixel units and improve the flexibility and quality of signal acquisition.

[0117] Fig.10 A schematic structural diagram of a pixel row and column control circuit provided in an embodiment of the present application is shown.

[0118] like Fig.10 As shown, each individual square area represents a SPAD pixel unit, and the pixel row and column control circuit includes a first selection signal input terminal (i.e., a row selection signal input terminal, or a spad_en_h input terminal) and a second selection signal input terminal (i.e., a column selection signal input terminal, or a spad_en_v input terminal). The first selection signal input terminal and the second selection signal input terminal have pixel symmetry, that is, each row of pixels shares a row selection signal input terminal, and each column of pixels shares a column selection signal input terminal. When the row selection signal of the current row selection input terminal and the column selection signal of the column selection input terminal are both selected, i.e., set to "1", the corresponding SPAD pixel unit responds to activation.

[0119] Each row of pixels in the SPAD pixel array shares a row selection input terminal, and each column of pixels shares a column selection input terminal, and the arrangement of the row and column selection input terminals satisfies symmetry, that is, they are symmetrical about the diagonal of the pixel array. Therefore, the SPAD pixel unit can be quickly selected by sharing the row and column selection input terminals, avoiding the redundancy of each SPAD pixel unit having a row and column selection input terminal, thereby realizing the selection control of large-array SPADs.

[0120] The input signal in the pixel row and column control circuit has pixel symmetry, avoiding the redundancy of having a row and column selection input terminal for each SPAD pixel unit, enabling rapid activation control of the SPAD pixel unit, reducing the occupied area of ​​the pixel row and column control circuit, and facilitating the miniaturization of the photosensitive chip.

[0121] Fig.11 FIG. 6 is a schematic diagram showing the structure of a readout circuit 600 provided in an embodiment of the present application. The readout circuit may be as follows: Figure 2 Or the readout circuit shown in Figure 3.

[0122] like Fig.11 As shown, the readout circuit 600 includes a sampling subcircuit, a TDC subcircuit, a clock source, a histogram subcircuit, and a serial-to-parallel circuit. The sampling subcircuit of the readout circuit 600 includes a first shaping synchronization unit and a second shaping synchronization unit; the first shaping synchronization unit is connected to the SPAD pixel array, and the first shaping synchronization unit is used to shape and synchronize the pulse signal output by the SPAD pixel array; the second shaping synchronization unit is connected to the control and processor and the clock source, and the second shaping synchronization unit is used to shape and synchronize the instructions issued by the control and processor and the control signal output by the clock source. The SPAD pixel array can be as follows Figure 2 or Figure 3 For the SPAD pixel array in the photosensitive chip 200 or 300 shown in FIG. , the clock source may be as follows: Figure 3 The clock source shown in the figure can be the control and processor as follows Figure 1 The control and processor 130 of the system is shown.

[0123] The sampling subcircuit includes a first shaping synchronization unit and a second shaping synchronization unit. The plurality of first shaping synchronization units correspond to the plurality of SPAD pixel units one by one and are used to shape and synchronize the clock of the signal output by the corresponding SPAD pixel units. The second shaping synchronization unit is used to receive a control signal and shape and synchronize it. The control signal is sent by the control and processor and generated by the timing generation circuit. The second shaping synchronization unit outputs a synchronization reset signal. The synchronization reset signal is synchronized with the clock signal provided by the PLL and has a pulse width of 0.5 times the clock period.

[0124] The TDC subcircuit includes at least two TDC units, each of which includes a timer and a synchronous adder. The timer is used to count the time, and the synchronous adder is used to count the number of pulse signals at different times. Fig.11The output ends of the multiple first shaping and synchronization units in the sampling subcircuit are electrically connected to the synchronous adder of the TDC subcircuit, and the first shaping and synchronization units shape and synchronize the pulse signals generated when the SPAD pixel unit triggers the avalanche effect, and then transmit them to the synchronous adder in parallel for statistics. Among them, the synchronous reset signal output by the second shaping and synchronization unit in the sampling subcircuit is used to reset the timer.

[0125] In some possible implementations, in combination with the sampling subcircuit and the TDC subcircuit, when each SPAD pixel unit in the SPAD pixel array triggers an avalanche effect, a first pulse signal is generated via its corresponding pixel front-end circuit, and the first pulse signal is transmitted to the sampling subcircuit of the readout circuit 600. The first pulse signal is shaped and synchronized by the corresponding first shaping synchronization unit, so that a second pulse signal synchronized with the clock signal and having a fixed pulse width can be obtained. Subsequently, the second pulse signal is sent to a synchronous adder, which can count the number of second pulse signals received at the same time. The counting moment of the timer is synchronized with the clock signal, and counts from 0 to 1 in sequence, so that the count value of the timer represents time information, and the synchronization of the timer and the synchronous adder makes the statistical result the number of SPAD pixel units triggered in unit time.

[0126] Continue to see Fig.11 The histogram processing subcircuit of the readout circuit 600 is connected to the TDC subcircuit, and the histogram processing subcircuit is used to count the output of the TDC unit to integrate it into a histogram; wherein the horizontal axis of the histogram represents time information, and the vertical axis of the histogram represents the number of pulse signals per unit time. Under the shaping synchronization of the first shaping synchronization unit, the aforementioned synchronous adder counts the number of second pulse signals synchronized with the clock signal, and the counting moment of the timer is also synchronized with the clock signal under the control of the synchronous reset signal of the second shaping synchronization unit. Therefore, the statistical value of the synchronous adder and the time value of the timer are counted under the same clock signal, that is, the values ​​of the two have a synchronous relationship. Under the action of the first shaping synchronization unit and the second shaping synchronization unit, the numerical values ​​of the synchronous adder and the timer are input into the histogram processing circuit at the same time. The histogram processing circuit can count the numerical values ​​counted by the synchronous adder and the count value of the timer to obtain a real-time histogram, wherein the calculated value of the timer represents the time axis of the histogram, i.e. the horizontal axis, and the statistical value of the synchronous adder represents the quantity value of the pulse signal of the histogram, i.e. the vertical axis.

[0127] Optionally, in addition to the synchronous adder and the timer, the TDC subcircuit may also include a threshold control unit, which is arranged before the synchronous adder and is used to calculate the threshold of the number of photons / pulse intensity to identify and distinguish the ambient light and / or stray light from the reflected light beam. In actual application scenarios, the light beam reflected back to the distance measuring device will be received and collected in a very short time, and the number of photons that can be detected during this time is much larger than the number of photons in the ambient light or the pulse signal intensity formed by the reflected light beam is much higher than the pulse signal intensity formed by the ambient light. Based on this, the threshold control unit counts the pulse signal within a preset time. If the number of collected photons or the pulse signal intensity reaches a preset threshold, it means that most of the photons collected by the threshold control unit are photons in the light beam reflected back to the distance measuring device. At this time, a stop signal is sent to the quenching subcircuit of the SPAD pixel unit to reset the SPAD pixel array for the next operation.

[0128] Through the action of the threshold control unit, the reflected pulse light beam and background light signal can be distinguished in real time, which can effectively reduce the interference of background stray light or the false trigger signal caused by dark counting when no light beam is received, thereby improving the accuracy of photon detection.

[0129] Continue to see Fig.11 , the readout circuit 600 also includes a serial-to-parallel subcircuit, which is electrically connected to the histogram processing subcircuit. In the distance measurement device, the processing frequency of the control and processor is lower than the processing frequency of the histogram processing subcircuit in the readout circuit 600. In order to adaptively transmit the output histogram to the control and processor, the serial-to-parallel subcircuit is used to synchronize the histogram data, convert it into data under a low-frequency clock and convert it into parallel data, and output signals as TDC data and counting data, which are respectively used to represent time information and activation information of the SPAD pixel unit. Through the conversion of information by the serial-to-parallel subcircuit, the readout circuit 600 can transmit data to the control and processor, and ensure that it is transmitted at an appropriate frequency, thereby improving the performance and efficiency of data transmission and facilitating the circuit to perform more complex algorithm calculations.

[0130] The operation process of the TDC subcircuit in the readout circuit 600 is described below in conjunction with the operation timing diagram.

[0131] Fig.12 The working timing diagram of the readout circuit provided in the embodiment of the present application is shown. In practical applications, the SPAD pixel array may include, for example, 256 SPAD pixel units. For simplicity, the embodiment of the present application is described in detail by taking 3 SPAD pixel units as an example.

[0132] like Fig.12As shown, the working timing diagram of the readout circuit includes a PLL signal, a start signal, a first pulse signal <0> , the first pulse signal <1> , the first pulse signal <2> , the first pulse signal <3-255>, the second pulse signal corresponding to the first pulse signal <0> , the second pulse signal <1> , the second pulse signal <2> , the second pulse signal <3-255>, and the signal of the timer and the synchronous adder.

[0133] Exemplarily, the instruction issued by the control and processor generates a control signal, i.e., a start signal, through a timing generation circuit, and the signal is transmitted to the second shaping synchronization unit of the sampling subcircuit, and the second shaping synchronization unit performs shaping synchronization on it to obtain a synchronization reset signal. The synchronization reset signal is used to reset the timer and synchronize it with the clock signal, and make it count continuously from 0, and output continuous values ​​such as 0, 1, 2, 3, etc., which are used to represent time information, i.e., 0, 1Tclk, 2Tclk, 3Tclk, etc., where Tclk represents the time length of a clock cycle.

[0134] When the SPAD pixel unit triggers the avalanche effect, its corresponding pixel front-end circuit generates a first pulse signal (also called spad signal), which is recorded as the first pulse signal <0> , the first pulse signal <1> and the first pulse signal <2> Subsequently, the first pulse signal is input into the sampling subcircuit in the readout circuit, and is shaped and synchronized by the first shaping and synchronization unit in the sampling subcircuit to obtain a second pulse signal (also called spad_sync signal), which are respectively recorded as the second pulse signal <0> , the second pulse signal <1> and the second pulse signal <2> The second pulse signal is synchronized with the clock signal and has a fixed pulse width, and corresponds to the first pulse signal respectively.

[0135] from Fig.12 It can be seen that since the first pulse signal is triggered on the SPAD pixel array, and the second pulse signal is generated in the first shaping synchronization unit of the sampling subcircuit, there is a propagation delay between the two, and the interval time is 1Tclk, so the second pulse signal is delayed compared to the first pulse signal in the working timing diagram. In one clock cycle, the synchronous adder will count the number of second pulse signals at this time, that is, count the number of triggered SPAD pixel units.

[0136] For example, see Fig.12, the figure shows the changes of four groups of pulse signals. After the readout circuit receives the start signal, it instructs the timer to start working, and the timer signal begins to change with time, that is, it gradually increases from 0; the first pulse signal in the first group <0> and the first pulse signal <1> is triggered, that is, changes from low level to high level, the second pulse signal <0> and the second pulse signal <1> They are triggered at a time 1Tclk apart from the corresponding first pulse signal; referring to the signal of the synchronous adder in the figure, the number of second pulse signals counted by the synchronous adder is 2, which is D2 in the figure, indicating that a total of 2 SPAD pixel units are triggered per unit time. The first pulse signal is triggered in the second, third and fourth groups respectively, and the corresponding second pulse signal is also triggered at a time 1Tclk apart. The synchronous timer counts the second pulse signal triggered in each group at the same time. The process is similar to that of the first group, so I will not go into details here.

[0137] By clock synchronizing the activation signal of the SPAD pixel unit, the readout circuit can perform real-time statistics on photon detection events. Combined with the integration of pulse signals by the synchronous adder and timer with clock synchronization, it can ultimately obtain highly accurate and real-time statistical results, thereby improving the performance of signal acquisition.

[0138] Fig.13 A histogram schematic diagram provided in an embodiment of the present application is shown.

[0139] Combination Fig.12 Based on the clock signal provided by the PLL, the first shaping synchronization unit and the second shaping synchronization unit will respectively synchronize the first pulse signal and the second pulse signal, so that the values ​​of the synchronous adder and the timer have a synchronous relationship. Based on this synchronization, the histogram processing subcircuit integrates the output values ​​of the two, thereby obtaining a real-time histogram.

[0140] See also Fig.13 , the horizontal axis in the histogram represents time information, corresponding to the output of the timer, and the vertical axis represents the count of the pulse signal, corresponding to the output of the synchronous adder. The bar graph shown in the figure represents the number of triggers of the pulse signal in the corresponding unit time, that is, the number of excitations of the second pulse signal recorded by the synchronous adder in a time interval of the timer. The histogram processing subcircuit integrates it to generate a real-time histogram. By integrating and summarizing the output signals of the synchronous adder and the timer through the histogram processing subcircuit, the real-time output of the histogram can be realized, providing intuitive and efficient data analysis, and improving the efficiency of data output analysis.

[0141] Fig.14 A schematic diagram of the circuit structure of a shaping synchronization unit provided in an embodiment of the present application is shown.

[0142] like Fig.14As shown, the shaping synchronization unit at least includes a first synchronization trigger, a second synchronization trigger and a third synchronization trigger, and the first synchronization trigger, the second synchronization trigger and the third synchronization trigger cooperate to realize shaping synchronization of the signal input to the shaping synchronization unit; the complementary output end of the third synchronization trigger is connected to the reset end of the first synchronization trigger, the second synchronization trigger and the third synchronization trigger to activate the first synchronization trigger, the second synchronization trigger and the third synchronization trigger. Among them, the shaping synchronization unit can be as follows Fig.11 The first shaping synchronization unit and / or the second shaping synchronization unit in the readout circuit are shown.

[0143] See also Fig.14 , the three synchronization triggers are connected to each other. Specifically, the input end (D end) of the first synchronization trigger is connected to a high-level signal, the clock input end (CLK end) is used to receive a pulse signal or a control signal, and the output end (Q end) is connected to the data input end of the second synchronization trigger; wherein, when the shaping synchronization unit is the first shaping synchronization unit, it receives a pulse signal, and the pulse signal can be, for example, a pulse signal generated when the SPAD pixel unit is triggered, that is, Fig.11 The pulse signal output by the SPAD pixel array in the readout circuit shown in the figure; when the shaping synchronization unit is the second shaping synchronization unit, the control signal is received, and the control signal is a signal sent by the control and processor and generated by the timing generation circuit, that is, Fig.11 The second synchronous trigger has an input terminal for receiving the output signal of the first synchronous trigger, a clock input terminal for receiving the clock signal, and an output terminal of the second synchronous trigger is connected to a data input terminal of the third synchronous trigger; the clock input terminal of the third synchronous trigger also inputs the clock signal, and the output signal of the output terminal is a pulse signal synchronized with the clock signal and having a fixed pulse width.

[0144] The output signal of the complementary output terminal (Q-terminal) of the third synchronous flip-flop is connected to the reset terminal (CLR terminal) of the three synchronous flip-flops, and is used to input a reset signal for the three synchronous flip-flops. Specifically, when the output terminal of the third synchronous flip-flop outputs a pulse signal, the complementary output terminal is set to a low-level signal, so that the reset terminal of each synchronous flip-flop is activated to reset the synchronous flip-flop, that is, to perform a new round of shaping synchronization work.

[0145] In some possible embodiments, when a first pulse signal or a control signal is input to the clock input terminal of the first synchronous trigger, the first synchronous trigger generates a rising edge signal, that is, changes from a low-level signal to a high-level signal. The rising edge signal triggers the first synchronous trigger to sample and store its input signal, and the output terminal of the first synchronous trigger outputs a high-level signal. The high-level signal is used as the input signal of the input terminal of the second synchronous trigger. When the clock signal input to the clock input terminal of the second synchronous trigger changes from a low-level signal to a high-level signal, the second synchronous trigger generates a rising edge signal, which triggers the output terminal of the second synchronous trigger to output a high-level signal.

[0146] It should be understood that in the above process, when the clock signal changes from a low-level signal to a high-level signal, the second synchronization trigger samples and stores the input signal, and uses the high-level signal obtained by sampling as the output signal of the output end, so that the output signal is synchronized with the clock signal. When the clock signal changes from a high-level signal to a low-level signal, the state of the output end of the second synchronization trigger will change, and the input signal received by the input end will stop being sampled. When the clock signal changes from a high-level signal to a low-level signal, the output end of the second synchronization trigger stops sampling the input signal, and the pulse signal received at its input end is synchronized with the clock signal and has a fixed pulse width after being reshaped and synchronized by the second synchronization trigger. The shaping synchronization principle of the third synchronization trigger is similar to that of the second synchronization trigger, and the embodiments of the present application will not be described in detail here.

[0147] Exemplarily, the output signal of the third synchronization trigger can be, for example, the second pulse signal obtained by the first shaping synchronization unit. In this case, the output signal will be transmitted to the synchronization adder for numerical statistics. Alternatively, the output signal can also be the synchronization reset signal obtained by the second shaping synchronization unit. In this case, the output signal will be transmitted to the timer for resetting the signal.

[0148] In the embodiment of the present application, by cascading multiple synchronization triggers, it is possible to shape the input pulse signal and synchronize it with the clock signal, thereby improving the stability of the synchronization signal and reducing the occurrence of signal metastable states.

[0149] In such Figure 3In the photosensitive chip shown, the pixel front-end circuit includes a quenching sub-circuit, which is used to protect the SPAD pixel unit from being damaged by the rapidly changing avalanche current when entering the avalanche effect. However, in actual application scenarios, for SPAD pixel units exposed to strong light, the avalanche current triggered is higher than that under normal lighting. In this case, even if the SPAD pixel is not in Geiger mode, it will generate a large photocurrent. Relying solely on the quenching sub-circuit cannot completely avoid damage to the device. To solve this problem, the present application also proposes a protection circuit for the pixel front-end circuit. Fig.15 Provide explanation.

[0150] Fig.15 A schematic diagram of a pixel front-end circuit provided in an embodiment of the present application is shown.

[0151] like Fig.15 As shown, the pixel front-end circuit includes a SPAD pixel circuit corresponding to a plurality of SPAD pixel units one by one; the SPAD pixel circuit includes a protection circuit, the protection circuit is connected between the quenching circuit and the pixel diode, the protection circuit includes a current limiting resistor and a protection diode, and the protection circuit is used to protect the SPAD pixel unit under high voltage conditions.

[0152] See also Fig.15 , the quenching subcircuit includes a quenching resistor and is connected to the reference potential node Vex, the positive electrode of the pixel diode is connected to the reference high level node (Very-High-Voltage, VHV), and the negative electrode is connected to one end of the quenching resistor, which is denoted as VC. The protection circuit includes a diode and a current limiting resistor (also known as Rs), one end of the protection circuit is connected to the reference potential node VSS, which can be, for example, ground or a negative power supply voltage, and the other end of the protection circuit is connected to the node VC between the pixel diode and the quenching subcircuit. The pixel front-end circuit also includes an operational amplifier for amplifying the voltage drop generated by the quenching resistor and outputting a pulse signal to indicate the excitation of the SPAD pixel unit.

[0153] One end of the current limiting resistor in the protection circuit is connected to the reference voltage node VHV, and the other end is connected to the positive electrode of the diode. When the SPAD pixel unit collects a strong light beam, the pixel diode is triggered to produce an avalanche effect, and the avalanche current rises rapidly, causing the voltage difference between the node VC and the node VSS to be lower than the reverse conduction voltage. At this time, the node VC is a negative voltage relative to the node VSS, and the absolute value is greater than the forward conduction voltage of the diode. In this case, the positive electrode of the protection diode is negative relative to the negative electrode, so the protection diode is in a reverse biased state, that is, the protection diode is reversely broken down, so that the protection diode begins to conduct under reverse bias. At this time, the pixel diode will produce a clamping effect, thereby limiting the voltage of the node VC from further decreasing, protecting the SPAD pixel circuit and the SPAD pixel unit.

[0154] It should be understood that the forward conduction voltage of the diode can be, for example, 0.7V; the clamping effect is based on the principle of unidirectional conductivity of the diode, that is, the diode only allows current to flow in one direction, so the voltage can be limited by using a diode to prevent the voltage from exceeding a certain safety threshold, thereby protecting the circuit from damage.

[0155] Through the pixel front-end circuit provided by the embodiment of the present application, its protection circuit can protect the SPAD pixel unit and the readout circuit connected to the pixel front-end circuit in real time. When the SPAD pixel unit collects strong light, the protection circuit can maintain the voltage of the VC node to avoid excessive voltage difference from damaging the device; when the SPAD pixel unit collects normal light beams, the protection diode in the protection circuit is in a high-resistance state, that is, a non-conducting state, and will not affect the normal functions of other circuits. The protection circuit and the current-limiting resistor can make the clamping effect of the diode within a controllable range, thereby improving the protection effect of the protection circuit and enhancing the safety of the device. The structural design is simple and occupies a small layout area, which is convenient for manufacturing the process of integrated circuits and simplifying the integration of the readout circuit. Optionally, the process of the integrated circuit can be, for example, a complementary metal oxide semiconductor (CMOS) process.

[0156] Optionally, the protection circuit can also be used in high-voltage bias situations. The principle is similar to the aforementioned process. In normal lighting environments, the protection circuit is in a high-resistance state and will not affect the normal operation of the SPAD circuit. In strong light environments, the protection diode produces a clamping protection effect, and the current-limiting resistor is used to prevent the protection circuit itself from being damaged by excessive current.

[0157] The embodiment of the present application also protects a distance measuring device, including a transmitter, a collector, and a control and processor; the transmitter includes a light source, a transmitting optical element, and a driver, and the transmitter is used to transmit a light beam to an object; the collector includes a filtering unit, a receiving optical element, and a photosensitive chip, and the collector is used to collect the light beam reflected back by the object to output a histogram; the control and processor is used to calculate the distance between the object and the distance measuring device according to the histogram.

[0158] Optionally, the photosensitive chip can be Figure 2 or Figure 3 The photosensitive chip 200 or photosensitive chip 300, the transmitter, the collector, the control and processor and the components inside thereof can all be as follows: Figure 1 Components in the system 100 of the distance measuring device are shown. For detailed description, please refer to the above content, and no further details will be given here.

[0159] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0160] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0161] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0162] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0163] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0164] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A photosensitive chip, characterized in that: It includes a SPAD pixel array, a pixel row and column control circuit, and a readout circuit; The SPAD pixel array includes a plurality of SPAD pixel units, and the SPAD pixel units are used to collect photons to output pulse signals; The pixel row and column control circuit includes a plurality of gating subcircuits, the plurality of gating subcircuits correspond one-to-one to the plurality of SPAD pixel units, the gating subcircuits include a first enabling unit, a second enabling unit and an output circuit, the output circuit is connected to the first enabling unit and the second enabling unit, and is used to output a response signal to activate the SPAD pixel unit corresponding to the gating subcircuit; The readout circuit is used to receive the response signal to output a histogram, and the histogram is used to record the number of the pulse signals.

2. The photosensitive chip according to claim 1, characterized in that: The first enabling unit is used to calibrate the SPAD pixel unit; The second enabling unit is used to gate the SPAD pixel unit; The first enabling unit and the second enabling unit cooperate to enable activation of the SPAD pixel unit.

3. The photosensitive chip according to claim 2, characterized in that: The first enabling unit and the second enabling unit cooperate to realize activation of the SPAD pixel unit, including: When the SPAD pixel unit is calibrated by the first enabling unit and is enabled by the second enabling unit, the SPAD pixel unit is activated.

4. The photosensitive chip according to any one of claims 1 to 3, characterized in that: The first enabling unit is used to receive a first enabling signal, a first strobe signal, a second strobe signal, a reset signal and a high level signal, so as to output a first response signal through signal coordination between the signals; The second enabling unit is used to receive the first selection signal, the second selection signal and the second enabling signal, and output a second response signal through signal coordination between the signals; The output circuit is used to receive the first response signal and the second response signal, and output the output signal of the gating subcircuit in combination with the first response signal and the second response signal to activate the corresponding SPAD pixel unit to respond.

5. The photosensitive chip according to claim 4, characterized in that: The first enabling unit includes a second AND gate and a D flip-flop, the second AND gate includes three input terminals and an output terminal, the three input terminals are used to receive the first enabling signal, the first selection signal and the second selection signal respectively, and output the signal to the D flip-flop through the output terminal through the logic AND operation of the second AND gate; The D flip-flop includes a clock input terminal connected to the output terminal of the second AND gate, a data input terminal for inputting the high-level signal, a reset terminal for inputting the clear reset signal, and an output terminal for outputting the first response signal, so as to obtain the first response signal of the first enabling unit through the signal coordination between the clock input terminal, the data input terminal and the reset terminal input signal.

6. The photosensitive chip according to claim 4, characterized in that: The second enabling unit includes a third input AND gate, which includes three input terminals and one output terminal. The three input terminals are used to respectively input the second enabling signal, the first selection signal and the second selection signal, and output the second response signal via the output terminal of the third AND gate through a logic AND operation.

7. The photosensitive chip according to claim 4, characterized in that: The output circuit includes the first AND gate, which includes two input terminals and an output terminal, the two input terminals are used to receive the first response signal and the second response signal respectively, and output the pixel activation signal through the output terminal through a logic AND operation to control the SPAD pixel unit in the SPAD pixel array.

8. The photosensitive chip according to any one of claims 1 to 3, characterized in that: The pixel row and column control circuit comprises a first selection signal input terminal and a second selection signal input terminal, wherein the first selection signal input terminal and the second selection signal input terminal have pixel symmetry.

9. The photosensitive chip according to claim 8, characterized in that: The photosensitive chip further includes a pixel front-end circuit, and the pixel front-end circuit includes a SPAD pixel circuit corresponding to the multiple SPAD pixel units one by one; The SPAD pixel circuit includes a protection circuit, which is connected between the quenching sub-circuit and the pixel diode. The protection circuit includes a current limiting resistor and a protection diode. The protection circuit is used to protect the SPAD pixel unit under high voltage conditions.

10. The photosensitive chip according to any one of claims 1 to 3, characterized in that: The readout circuit includes a TDC subcircuit, the TDC subcircuit includes at least two TDC units, the TDC unit includes a timer and a synchronous adder, the timer is used to count moments, and the synchronous adder is used to count the number of pulse signals at different moments.

11. The photosensitive chip according to claim 10, characterized in that: The TDC subcircuit also includes a threshold control unit, which is used to calculate the threshold of the photon quantity and / or pulse intensity to distinguish and identify background light.

12. The photosensitive chip according to claim 11, characterized in that: The readout circuit further includes a histogram processing subcircuit, the histogram processing subcircuit is connected to the TDC subcircuit, and the histogram processing subcircuit is used to receive the count output by the TDC unit to integrate into the histogram; The horizontal axis of the histogram represents time information, and the vertical axis of the histogram represents the number of pulse signals per unit time.

13. The photosensitive chip according to claim 12, characterized in that: The readout circuit includes a sampling subcircuit, and the sampling subcircuit includes a first shaping synchronization unit and a second shaping synchronization unit; The first shaping synchronization unit is connected to the SPAD pixel array, and is used to perform shaping synchronization on the pulse signal output by the SPAD pixel array, so that the statistical value of the synchronous adder is represented as the vertical axis value of the histogram; The second shaping and synchronization unit is connected to the control and processor and the clock source, and is used to shape and synchronize the instructions issued by the control and processor and the control signal output by the clock source so that the count value of the timer is the horizontal axis value of the histogram.

14. The photosensitive chip according to claim 13, characterized in that: The first shaping synchronization unit and / or the second shaping synchronization unit at least comprises a first synchronization trigger, a second synchronization trigger and a third synchronization trigger, and the first synchronization trigger, the second synchronization trigger and the third synchronization trigger cooperate to realize shaping synchronization of the signal input to the shaping synchronization unit; The complementary output terminal of the third synchronous trigger is connected to the reset terminals of the first synchronous trigger, the second synchronous trigger and the third synchronous trigger to activate the first synchronous trigger, the second synchronous trigger and the third synchronous trigger.

15. A distance measuring device, characterized in that: Includes transmitter, collector, and control and processor; The emitter is used to emit a first light beam toward a target object; The collector comprises a photosensitive chip as claimed in any one of claims 1 to 14, and is used to collect the second light beam reflected by the target object to output a histogram; The control and processor are used to calculate the distance between the target object and the distance measuring device according to the histogram.

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