Method and signal generator for generating a high-speed rate waveform signal

Abstract

The present application relates to a kind of method and system of cyclic generation high-speed rate waveform signal: waveform cycle module is cyclicly spliced to waveform data;Control module transmits variable related to waveform length to waveform cycle module;Data storage module stores waveform data information;Waveform cycle module includes: address cycle module is responsible for data addressing, and output data address to data storage module;Data cycle module receives waveform data sent by data storage module, and sends to data transmission interface after completing cyclic splicing of data, and data transmission interface sends waveform cycle data to DAC.The present application can effectively reduce the length of waveform data, reduce the requirement to storage space;It is suitable for any high-speed DAC using JESD204 protocol interface, can run most FPGA models of Xilinx JESD204 IP;It can be adapted to BRAM, FPGA on-chip storage resource, also can adapt off-chip storage resource DDR and other devices;According to need, it can be realized that waveform is cyclic, both can complete waveform infinite cycle, also can complete the cycle of specific number.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal generator, and particularly relates to a method for cyclically generating high-speed waveform signals and a signal generator. BACKGROUND

[0002] A signal generator is a device capable of providing various frequency, waveform and output level electrical signals, such as an arbitrary waveform signal generator (AWG) or a vector signal generator (VSG). The signal generator is used as a test signal source or excitation source when measuring the amplitude characteristics, frequency characteristics, transmission characteristics and other electrical parameters of various telecommunication systems or telecommunication devices, and when measuring the characteristics and parameters of components and devices.

[0003] The signal generator includes a digital analog conversion chip (Digital to Analog Converter, DAC) and a field programmable gate array chip (Field Programmable Gate Array, FPGA). The FPGA chip realizes the generation and control of signals, and the DAC chip is a common electronic device in the radio frequency field, which is used to convert the digital signal controlled and generated by the FPGA chip into an analog signal. As a key device of the signal generator, the DAC chip is widely used in the fields of communication, radar, test and measurement, etc. At present, the data interface of most high-speed DAC chips adopts JESD204 protocol. When the high-speed DAC chip sends a specific waveform, the FPGA chip needs to send waveform data to the DAC chip using the JESD204 protocol to achieve the purpose of waveform playing.

[0004] In the Xilinx FPGA, the JESD204 IP transmits a packet of sample frame data to the DAC chip every clock cycle. Each packet of sample frame data has multiple bit widths, such as 256bit, 512bit or 1024bit, according to the actual situation. Taking an 8bit sampling precision DAC as an example, a packet of sample frame needs to transmit 32, 64 or 128 sample points. When the DAC chip cyclically plays a certain waveform, the number of waveform sample points needs to meet two conditions:

[0005] Condition (1): The number of waveform sample points needs to be a complete period or multiple complete periods;

[0006] Condition (2): The number of waveform sample points needs to be an integer multiple of the number of sample frame sample points.

[0007] When the number of waveform sampling points is small, conditions (1) and (2) are relatively easy to meet; however, when the number of waveform sampling points is large, especially in the current mainstream method, the period is directly repeated on the waveform data, that is, the sampling frame is repeated according to the number of sampling points, and the length of the final transmission waveform will reach a very large value. Taking an 8-bit sampling precision DAC chip and a 512-bit sampling frame as an example, assuming that the transmission waveform is a prbs7 signal, a single cycle prbs7 signal has 127 sampling points, and after period repetition, the waveform length needs to be multiplied by 64, becoming 8128 sampling points. As can be seen, the period repetition method, although simple in thought, will produce several times of storage redundancy, leading to insufficient storage space of the hardware, data overwriting or loss, incomplete wave cycle data transmission, unstable analog signal output of the DAC chip, waveform distortion and other situations, which seriously affect the performance index of the test measurement system. SUMMARY

[0008] The present application provides a method for cyclically generating a high-speed waveform signal, which is used for a signal generator to cyclically generate a high-speed waveform signal. The signal generator comprises an FPGA chip, a data storage module and a DAC chip. The FPGA chip comprises a control module, a waveform cycle module and a data transmission interface. The waveform cycle module comprises an address cycle module and a data cycle module. The method comprises the following steps:

[0009] The control module sends a variable related to the length of the waveform data to the address cycle module and the data cycle module, respectively;

[0010] The address cycle module sends a data address of the length of the sampling frame to the data storage module according to the variable related to the length of the waveform data;

[0011] The data storage module pre-stores waveform data, and the waveform data comprises a plurality of sampling frame waveform data. The sampling frame waveform data comprises residual frame data and N complete frame data. The complete frame data comprises A sampling points, and the number of sampling points of the residual frame data is M. The data storage module finds the corresponding sampling frame waveform data according to the received data address and sends the sampling frame waveform data to the data cycle module;

[0012] The data cycle module determines whether the received sampling frame waveform data is complete frame data or residual frame data according to a first preset rule. If it is complete frame data, the complete frame data is sent to the DAC chip through the data transmission interface. In this way, the N complete frame data in the first sampling frame waveform data are sent out, and the cycle number i is i+1.

[0013] If the residual frame data is received, the residual frame data is updated to be original residual frame data, the number of sample points in the residual frame data is compared with the number of sample points in the complete frame data, if the number of sample points in the residual frame data is less than the number of sample points in the complete frame data, the sample points in the residual frame data and part of the sample points in the next sample frame waveform data are spliced to be complete frame data, and the complete frame data is sent to the DAC chip through the data transmission interface, and another part of the sample points in the next sample frame data is stored for splicing with the next waveform data, and the process is repeated until the sending of N complete frame data is completed, the residual frame is updated to be the last 2*M sample points in the Nth sample frame waveform data spliced with the sample points in the original residual frame data, and the cycle number i is i+1.

[0014] The process is repeated until the sending of P waveform data is completed, wherein the length of the last residual frame data is exactly the length of a complete frame data, and P is equal to the least common multiple of M and A.

[0015] In some embodiments, if the number of sample points in the residual frame data is greater than the number of sample points in the complete frame data, the first A sample points of the residual frame data are sent out, and the remaining sample points of the current residual frame data are reserved as new residual frame data.

[0016] If the number of sample points in the residual frame data is equal to the number of sample points in the complete frame data, the current residual frame data is sent out.

[0017] In some embodiments, the first preset rule comprises judging whether the number of sample points of the received sample frame waveform data is equal to the number of sample points transmitted in each clock cycle of the data transmission interface, if yes, the sample frame waveform data is complete frame data, otherwise, the sample frame waveform data is residual frame data.

[0018] In some embodiments, the control module sends a cycle enable instruction to the address cycle module.

[0019] The address cycle module waits for the cycle enable instruction, if the cycle enable instruction is received, the address cycle module outputs an address valid flag and a residual frame data address to the data storage module.

[0020] If not, whether the cycle starts is judged according to a second preset rule, if the cycle starts, the address cycle module outputs an address valid flag and outputs a first complete frame data address to the data storage module, and continues to wait for the cycle enable instruction.

[0021] If not, the address cycle module judges whether the cycle is valid according to a third preset rule, if the cycle is valid, the address cycle count is calculated, the complement length is calculated, and the cycle number is calculated; if not, the address cycle module outputs the invalid address and the address to the data storage module, and continues to wait for the cycle enable instruction;

[0022] According to the complement length, it is judged whether the residual frame data address needs to be output, if yes, it is judged whether a cycle is completed according to the address number, if the cycle is completed, the first address is returned and the cycle enable instruction is continued to wait; if the cycle is not completed, the address is incremented, the residual frame data address is not output, and the cycle enable instruction is continued to wait.

[0023] In some embodiments, the waveform data length related variable includes a total waveform data length, a sampling frame waveform data length, a frame number, and a residual frame data length.

[0024] In some embodiments, the second preset rule includes that a rising edge of the cycle enable instruction is delayed for one beat as a cycle start judgment mark, if the mark is valid, the cycle starts, and the cycle start mark is set to 1; otherwise, the cycle does not start, and the cycle start mark is kept;

[0025] The third preset rule includes that when the cycle start mark is set to 1 and the data transmission interface receives the enable signal, the cycle is valid, and the cycle valid mark is set to 1; otherwise, the cycle is invalid, and the cycle valid mark is set to 0.

[0026] In some embodiments, the calculation of the address cycle count includes that if the address cycle count is greater than or equal to (the total waveform data length-the sampling frame waveform data length), the address cycle count at the next moment = the current address cycle count-(the total waveform data length-the sampling frame waveform data length); otherwise, the address cycle count at the next moment = the current address cycle count+the sampling frame waveform data length.

[0027] The calculation of the complement length includes that if the address cycle count is greater than or equal to (the total waveform data length-the sampling frame waveform data length), the complement length at the next moment = the current address cycle count-(the total waveform data length-the sampling frame waveform data length); otherwise, the complement length at the next moment = the current complement length.

[0028] The calculation of the cycle number includes that if the address cycle count is greater than or equal to (the total waveform data length-the sampling frame waveform data length), the cycle count at the next moment = the current cycle count+1; otherwise, the cycle count at the next moment = the current cycle count.

[0029] In some embodiments, if the residual frame data address does not need to be output, it is judged whether the cycle is completed according to whether the address number exceeds the frame number-1.

[0030] In some embodiments, the control module sends a sampling frame waveform data enable;

[0031] The data cycle module judges whether the received sampling frame waveform data enable is valid, and if the sampling frame waveform data enable is valid, judges whether the received residual frame data enable is valid;

[0032] If the received residual frame data enable is valid, the residual frame data is pre-stored, and if not, the data cycle number is calculated, the data cycle length count is calculated, the complement length is calculated, and the cycle number is calculated;

[0033] According to the current complement length, different data processing branches are entered, it is judged whether the cycle is completed, if the cycle is not completed, it is judged whether the current cycle needs to output residual frame data, if it needs, it is judged whether the current data number is equal to the frame number, if not, the data valid enable is output, the complete frame data length part in the residual frame data is output, the residual frame data is updated, and the data cycle module judges whether the received sampling frame waveform data enable is valid.

[0034] The application also provides a signal generator for cyclically generating a high-speed rate waveform signal, comprising an FPGA chip, a data storage module and a DAC chip, the FPGA chip comprising a control module, a waveform cycle module and a data transmission interface, the waveform cycle module comprising an address cycle module and a data cycle module, the signal generator being used for cyclically generating a high-speed rate waveform signal by using the method in any of the preceding embodiments.

[0035] The application has the following beneficial effects:

[0036] The method for cyclically generating a high-speed rate waveform signal provided by the application comprises that an address module sends a data address, a data storage module addresses and then sends corresponding sampling frame waveform data, and a data cycle module combines the information of address cycle, the cycle enable information sent by the control module, etc., to splice residual frame data, so that the waveform data is completely sent to the DAC chip within a limited number of cycles, the waveform cycle data length is effectively reduced, the requirement for the storage space in the data storage module is reduced, the incomplete waveform cycle data transmission, the unstable analog signal output of the DAC chip, the waveform distortion, etc., caused by insufficient storage space are avoided, and the performance of the signal generator and the test and measurement system is effectively improved. The application can adapt to the on-chip storage resource BRAM of the FPGA and can also adapt to the off-chip storage resource DDR and other devices. The waveform cycle can be realized according to the requirement, the waveform infinite cycle can be completed, and the cycle of a specific number of times can also be completed. BRIEF DESCRIPTION OF DRAWINGS

[0037] The specific embodiments of the application are further illustrated below with reference to the accompanying drawings.

[0038] Figure 1 A method step diagram for cyclically generating a high-speed waveform signal is provided for an embodiment of the present application.

[0039] Figure 2 A principle block diagram of a signal generator is provided for an embodiment of the present application.

[0040] Figure 3 A principle block diagram of a signal generator is provided for another embodiment of the present application.

[0041] Figure 4 A flowchart of waveform cycle splicing is provided for an embodiment of the present application.

[0042] Figure 5 A method flowchart of address cycle is provided for an embodiment of the present application.

[0043] Figure 6 A method flowchart of data cycle is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0044] A signal generator is an electronic instrument capable of generating various waveforms, adjustable frequency, amplitude and phase, used to provide stable waveform signals in the process of testing and measurement, including a circuit board, an FPGA chip and a DAC chip integrated on the circuit board, the FPGA chip is used to realize the generation and control of signals, and the DAC chip is used to convert the digital signal generated by the FPGA control into an analog signal.

[0045] In the signal generator, the sampling frame length (i.e. the sampling time length or the number of sampling points) in a waveform cycle means that more points of the signal are sampled, so that the details of the signal can be captured more finely. In the DAC signal processing, the increase of the number of sampling points can improve the fidelity of signal reconstruction, so that the reconstructed signal is closer to the original signal. However, longer sampling frame has higher requirement for the storage space of the system. EMBODIMENT

[0046] Generating a high-speed waveform signal often results in data overwrite or loss due to insufficient storage space (such as DDR) of hardware, so that the waveform signal data transmission is incomplete, and the DAC chip 200 may output unstable analog signal and distorted waveform.

[0047] Figure 1 A method step diagram for cyclically generating a high-speed waveform signal is provided for an embodiment of the present application.

[0048] As shown in Figure 1 , the present embodiment provides a method for cyclically generating a high-speed waveform signal, which is used for the signal generator to cyclically generate a high-speed waveform signal.

[0049] Figure 2 A principle block diagram of a signal generator provided for an embodiment of the present application is shown in the figure, Figure 4 A schematic diagram of waveform data is shown in the figure.

[0050] As shown in the figure, Figure 2 The signal generator comprises an FPGA chip 100, a data storage module 130 and a DAC chip 200, the FPGA chip 100 comprises a control module 110, a waveform cycle module 120 and a data transmission interface 140, the waveform cycle module 120 comprises an address cycle module 121 and a data cycle module 122, and the address cycle module 121 and the data cycle module 122 are connected to the control module 110 and the data transmission interface 140, respectively. Figure 1 The method for generating a high-speed waveform signal in cycles comprises the following steps:

[0051] Step S1, the control module 110 sends a variable related to the length of waveform data to the address cycle module 121 and the data cycle module 122, respectively;

[0052] Step S2, the address cycle module 121 sends a data address of a sampling frame length to the data storage module 130 according to the variable related to the length of waveform data;

[0053] Step S3, please refer to the figure Figure 4 The data storage module 130 pre-stores waveform data, the waveform data comprises a plurality of sampling frame waveform data, wherein the sampling frame waveform data comprises residual frame data and N complete frame data, the complete frame data comprises A sampling points, and the number of sampling points of the residual frame data is M, the data storage module 130 finds the corresponding sampling frame waveform data according to the received data address and sends the sampling frame waveform data to the data cycle module 122;

[0054] Step S4, the data cycle module 122 judges whether the received sampling frame waveform data is complete frame data or residual frame data according to a first preset rule, if it is complete frame data, the complete frame data is sent to the DAC chip 200 through the data transmission interface 140, and the same is repeated until the N complete frame data in the first sampling frame are sent out, and the cycle number i is i=i+1, the initial value of i is 0;

[0055] Step S5, if the residual frame data, update the residual frame data to the original residual frame data, compare the number of sample points in the residual frame data and the number of sample points in the complete frame data, if the number of sample points in the residual frame data is less than the number of sample points in the complete frame data, then the sample points in the residual frame data and part of the sample points in the next sampling frame waveform data are spliced into complete frame data and sent to the DAC chip 200 through the data transmission interface 140, and another part of the sample points in the next sampling frame data are stored for splicing with the next waveform data, and so on, until the sending of N complete frame data is completed, the residual frame is updated to the last 2*M sample points of the Nth sampling frame waveform data and the sample points of the original residual frame data are spliced, and the loop number is i=i+1.

[0056] Step S6, the cycle is completed, and the sending of the waveform data with P times of loop is completed, wherein the length of the last residual frame data is exactly the length of a complete frame data, and P is equal to the least common multiple of M and A.

[0057] Specifically, in the embodiment, the first preset rule includes judging whether the number of sample points of the received sampling frame waveform data is equal to the number of sample points transmitted by the data transmission interface 140 in each clock cycle, if yes, it is complete frame data, otherwise, it is residual frame data. The number of sample points that can be transmitted by the data transmission interface 140 in each clock cycle is determined by the sampling accuracy of the DAC and the bit width of the data transmission interface, for example, the DAC with 8 bit sampling accuracy and the data transmission interface 140 with 512 bit bit width, the number of sample points that can be transmitted in each clock cycle is 64.

[0058] Figure 3 The principle block diagram of the signal generator provided by another embodiment of the application is provided.

[0059] In the embodiment of the application, the data storage module 130 can be a BRAM storage area (as shown in Figure 2 in the FPGA chip 100, or a storage unit (as shown in Figure 3 outside the FPGA chip 100, for example, a DDR chip. The method for cyclically generating high-rate waveform signals provided by the embodiment of the application can save storage space. According to the needs, the method can be used without relying on the DDR chip, only using the storage area in the FPGA.

[0060] In the above description, only 8 bit sampling accuracy and 64 sample points of sampling frame length are described as the main body, but the application is also applicable to other sampling accuracies and other sampling frame lengths. In addition, the length of the waveform data can be specially specified to reduce the difficulty of FPGA implementation, while not greatly increasing the length of the waveform data.

[0061] The method for generating a high-speed rate waveform signal in cycles provided by the embodiment of the present application comprises: an address module sending data addresses; a data storage module 130 addressing and then sending corresponding sample frame waveform data; and a data cycle module 122 combining the information of address cycles, cycle enable information sent by a control module 110, and the like to splice residual frame data, so that the waveform data is completely sent out to a DAC chip 200 within a limited number of cycles, the length of the waveform cycle data is effectively reduced, the requirement for the storage space in the data storage module 130 is reduced, the incomplete transmission of the waveform cycle data, the unstable analog signal output of the DAC chip 200, waveform distortion, and the like caused by insufficient storage space are avoided, and the performance of a signal generator and a test and measurement system is effectively improved; the present application can adapt to on-chip storage resources BRAM and off-chip storage resources DDR and the like, and can realize the cycle of the waveform according to the requirement, that is, the waveform can be infinitely cycled or cycled for a specific number of times.

[0062] Further, the method further comprises:

[0063] In step S51, if the number of sample points in the residual frame data is greater than the number of sample points in the complete frame data, the first A sample points of the residual frame data are sent out, and the remaining sample points of the current residual frame data are reserved as new residual frame data.

[0064] In step S52, if the number of sample points in the residual frame data is equal to the number of sample points in the complete frame data, the current residual frame data is sent out.

[0065] In the cycle process, sometimes the number of sample points in the residual frame data is greater than the number of sample points in the complete frame data, and this method can effectively solve this situation, that is, the first A sample points of the residual frame data are sent out as a complete frame data, and the remaining sample points of the current residual frame data are reserved as new residual frame data. The case when the number of sample points is equal is the same. This method is flexible and convenient, can effectively cope with various situations, and makes the waveform data transmission accurate and stable.

[0066] In the embodiment, the variables related to the length of the waveform data include the total length of the waveform data, the length of the sample frame waveform data, the number of frames, and the length of the residual frame data, which facilitates the address cycle of the address cycle module 121 and the splicing of the waveform by the data cycle module 122.

[0067] In the embodiment, the data transmission interface 140 sends the waveform data to the DAC chip 200 by using the JESD204 protocol.

[0068] The application is based on the case that the logic device uses FPGA to transmit data to high-speed DAC through JESD204 IP, and proposes an implementation method of high-speed waveform signal cycle generation. The method can effectively reduce the requirement for device storage depth and complete complex waveform cycle output under the condition of limited storage depth for DAC and FPGA using JESD204 protocol. Embodiment

[0069] Figure 5 The flowchart of the method for cyclically generating high-speed waveform signals provided by another embodiment of the application is shown.

[0070] As shown in Figure 5 , the embodiment provides a method for cyclically generating high-speed waveform signals, and further comprises the following steps.

[0071] In step S10, the control module 110 sends a cycle enable instruction to the address cycle module 121.

[0072] In step S11, the address cycle module 121 waits for the cycle enable instruction. If the cycle enable instruction is received, the address cycle module 121 outputs an address valid flag and a residual frame data address to the data storage module 130.

[0073] In step S12, if not, it is determined whether the cycle starts according to a second preset rule. If the cycle starts, the address cycle module 121 outputs an address valid flag and the address of the first complete frame data to the data storage module 130, and continues to wait for the cycle enable instruction.

[0074] In step S13, if not, it is determined whether the cycle is valid according to a third preset rule. If the cycle is valid, the address cycle module 121 calculates the address cycle count, the length of the complement, and the cycle number. If not, the address cycle module 121 outputs an address invalid flag and an address retention flag to the data storage module 130, and continues to wait for the cycle enable instruction.

[0075] In step S14, it is determined whether the residual frame data address needs to be output according to the length of the complement. If yes, it is determined whether a cycle is completed according to the address number. If the cycle is completed, the first address is returned and the cycle enable instruction is continued to be waited for.

[0076] In step S15, if the cycle is not completed, the address is incremented, the residual frame data address is not output, and the cycle enable instruction is continued to be waited for.

[0077] The method for generating high-speed rate waveform signals in cycles provided by the embodiment can output residual frame addresses, so that the data storage module 130 can find waveforms according to the residual frame data addresses, and the cycle enabling instruction of the control module 110 is received through the address cycle module 121, so that the generation of the waveform signals is accurately controlled, the generation of the waveform signals is ensured to be performed according to the predetermined cycle, and the operation efficiency of the system is improved; the residual frame data addresses are output, so that the data storage module 130 can accurately find and process the residual frame data, the loss or repeated processing of the residual frame data is avoided, and the integrity and accuracy of the waveform data transmission are improved.

[0078] Specifically, in the embodiment, the second preset rule includes that a rising edge of the cycle enabling instruction is delayed by one beat to serve as a cycle start judgment mark, the cycle starts if the mark is valid, and the cycle start mark is set to 1; otherwise, the cycle does not start, and the cycle start mark remains.

[0079] Specifically, in the embodiment, the third preset rule includes that the cycle is valid when the cycle start mark is set to 1 and the enable received by the data transmission interface 140 is valid, and the cycle valid mark is set to 1; otherwise, the cycle is invalid, and the cycle valid mark is set to 0.

[0080] Specifically, in the embodiment, the calculation of the address cycle count includes that if the address cycle count is greater than or equal to (total length of waveform data-sample frame waveform data length), then the address cycle count at the next moment = current address cycle count-(total length of waveform data-sample frame waveform data length); otherwise, the address cycle count at the next moment = current address cycle count+sample frame waveform data length.

[0081] The calculation of the complement length includes that if the address cycle count is greater than or equal to (total length of waveform data-sample frame waveform data length), then the complement length at the next moment = current address cycle count-(total length of waveform data-sample frame waveform data length); otherwise, the complement length at the next moment = current complement length.

[0082] The calculation of the cycle count includes that if the address cycle count is greater than or equal to (total length of waveform data-sample frame waveform data length), then the cycle count at the next moment = current cycle count+1; otherwise, the cycle count at the next moment = current cycle count.

[0083] In the embodiment, the method further includes that if the residual frame data address is not needed to be output, whether the cycle is completed is determined according to whether the address number exceeds frame number-1. Embodiment

[0084] Figure 6 The method flowchart for data cycle provided by an embodiment of the application.

[0085] AsFigure 5 As shown, the method for generating a high-speed waveform signal through cycle provided in this embodiment further includes:

[0086] In step S20, the control module 110 sends a sample frame waveform data enablement.

[0087] In step S21, the data cycle module 122 determines whether the received sample frame waveform data enablement is valid. If the sample frame waveform data enablement is invalid, the sample frame data is maintained, and the residual frame data is maintained.

[0088] In step S22, if the sample frame waveform data enablement is valid, it is determined whether the received residual frame data enablement is valid. If the received residual frame data enablement is valid, the pre-stored residual frame data is determined. If it is invalid, the data cycle sequence number, the data cycle length count, the complement length, and the cycle number are calculated.

[0089] In step S23, according to the current complement length, different data processing branches are entered, it is determined whether the cycle is completed, and if the cycle is not completed, it is determined whether the current cycle needs to output residual frame data. If not, the data valid enablement is outputted, the complete frame data length part in the residual frame data is outputted, the residual frame data is updated, and the data cycle module 122 continues to determine whether the received sample frame waveform data enablement is valid.

[0090] In step S24, if it is needed, it is determined whether the current data sequence number is equal to the frame number. If it is equal, the data valid enablement is outputted, the residual frame data is outputted, and the residual frame data is updated.

[0091] In step S25, if it is not equal, the data valid enablement is outputted, the complete frame data length part in the residual frame data is outputted, the residual frame data is updated, and the data cycle module 122 continues to determine whether the received sample frame waveform data enablement is valid.

[0092] The method for generating a high-speed waveform signal through cycle provided in this embodiment can intelligently select pre-stored residual frame data or perform other data processing operations through the validity of the sample frame waveform data enablement and the residual frame data enablement, thereby improving the flexibility and efficiency of data processing. Through the calculation of the data cycle sequence number, the data cycle length count, the complement length, and the cycle number, the precise control of the cycle process is realized, and the storage resource utilization is optimized. When the cycle is not completed and the residual frame data needs to be outputted, the method can accurately determine the relationship between the current data sequence number and the frame number, thereby outputting the complete frame data length part and updating the residual frame data, avoiding the repeated processing or loss of waveform data, and improving the integrity and accuracy of waveform data transmission. Embodiment

[0093] The embodiment provides a signal generator for cyclically generating a high-speed rate waveform signal, comprising an FPGA chip 100, a data storage module 130 and a DAC chip 200, wherein the FPGA chip 100 comprises a control module 110, a waveform cycle module 120 and a data transmission interface 140, the waveform cycle module 120 comprises an address cycle module 121 and a data cycle module 122, and the signal generator is used for cyclically generating the high-speed rate waveform signal by using the method steps described in any of the above embodiments.

[0094] The method for cyclically generating the high-speed rate waveform signal comprises the following steps: the address module sends data addresses; the data storage module 130 addresses and then sends corresponding sample frame waveform data; the data cycle module 122 combines the information of address cycles, the cycle enable information sent by the control module 110 and the like to splice residual frame data, so that the waveform data is completely sent to the DAC chip 200 within a limited number of cycles, the length of the waveform cycle data is effectively reduced, the requirement for the storage space in the data storage module 130 is reduced, the incomplete transmission of the waveform cycle data, the unstable analog signal output of the DAC chip 200 and waveform distortion caused by insufficient storage space are avoided, and the performance of the signal generator and the test and measurement system is effectively improved; the application can adapt to the on-chip storage resource BRAM and the off-chip storage resource DDR and the like; the waveform cycle can be realized according to the requirement, the waveform infinite cycle can be completed, and the cycle of a specific number of times can be completed.

[0095] In the above description, many specific details are set forth in order to provide a thorough understanding of the present application. However, the above description is only preferred embodiments of the present application, and the present application can be implemented in many different ways from those described herein, therefore the present application is not limited to the specific implementations disclosed above. Meanwhile, any person skilled in the art can make many possible changes and modifications to the technical solutions disclosed above, or modify equivalent embodiments, without departing from the scope of the technical solutions of the present application. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the scope of the technical solutions of the present application, all still belong to the scope of protection of the technical solutions of the present application.

Claims

1. A method of cyclically generating a high rate waveform signal, characterized by, The application relates to a method for generating high-speed waveform signals in a signal generator cycle, wherein the signal generator comprises an FPGA chip, a data storage module and a DAC chip, the FPGA chip comprises a control module, a waveform cycle module and a data transmission interface, the waveform cycle module comprises an address cycle module and a data cycle module, and the method comprises the following steps: The control module sends a waveform data length-related variable to the address cycle module and the data cycle module respectively; The address cycle module sends a data address of a sampling frame length to the data storage module according to the waveform data length-related variable; The data storage module pre-stores waveform data, and the waveform data comprises a plurality of sampling frame waveform data, wherein the sampling frame waveform data comprises residual frame data and N complete frame data, the complete frame data comprises A sampling points, the number of sampling points of the residual frame data is M, the data storage module finds corresponding sampling frame waveform data according to the received data address and sends the sampling frame waveform data to the data cycle module; The data cycle module judges whether the received sampling frame waveform data is complete frame data or residual frame data according to a first preset rule, if the sampling frame waveform data is complete frame data, the complete frame data is sent to the DAC chip through the data transmission interface, and the same is repeated until N complete frame data in the first sampling frame waveform data is sent out, and the cycle number i is i+1; If the sampling frame waveform data is residual frame data, the residual frame data is updated to original residual frame data, the number of sampling points in the residual frame data is compared with the number of sampling points in the complete frame data, if the number of sampling points in the residual frame data is smaller than the number of sampling points in the complete frame data, the sampling points in the residual frame data and part of sampling points in the next sampling frame waveform data are spliced into complete frame data which is sent to the DAC chip through the data transmission interface, and the other part of sampling points in the next sampling frame waveform data is stored for next time waveform data splicing, and the same is repeated until N complete frame data is sent, the residual frame is updated to the splicing of the last 2*M sampling points of the Nth sampling frame waveform data and the sampling points of the original residual frame data, and the cycle number i is i+1; The cycle is repeated, and the sending of waveform data with a cycle number P is completed, wherein the length of the last residual frame data is exactly the length of one complete frame data, and P is the least common multiple of M and A.

2. The method of claim 1, wherein, The method further comprises: If the number of sampling points in the residual frame data is greater than the number of sampling points in the complete frame data, the first A sampling points of the residual frame data are sent out, and the remaining sampling points of the current residual frame data are reserved as new residual frame data; If the number of sampling points in the residual frame data is equal to the number of sampling points in the complete frame data, the current residual frame data is sent out.

3. The method of claim 1, wherein The first preset rule comprises judging whether the number of sampling points of the received sampling frame waveform data is equal to the number of sampling points transmitted in each clock cycle of the data transmission interface, if yes, the sampling frame waveform data is complete frame data; otherwise, the sampling frame waveform data is residual frame data.

4. The method of claim 1, wherein Also comprising: The control module sends a cycle enable instruction to the address cycle module; The address cycle module waits for the cycle enable instruction, if the cycle enable instruction is received, the address cycle module outputs the address valid flag and the residual frame data address to the data storage module; If not, according to the second preset rule, it is judged whether the cycle starts, if the cycle starts, the address cycle module outputs the address valid flag and the first complete frame data address to the data storage module, and continues to wait for the cycle enable instruction; If not, according to the third preset rule, it is judged whether the cycle is valid, if the cycle is valid, the address cycle count is calculated, the complement length is calculated, and the cycle number is calculated; If not, the address cycle module outputs the address invalid and the address retention to the data storage module, and continues to wait for the cycle enable instruction; According to the complement length, it is judged whether the residual frame data address needs to be output, if it needs, it is judged whether a cycle is completed according to the address number, if the cycle is completed, it returns to the first address and continues to wait for the cycle enable instruction; If the cycle is not completed, the address is incremented, the residual frame data address is not output, and the cycle enable instruction is continued to wait.

5. The method of claim 4, wherein the method further comprises: The waveform data length related variables include the total waveform data length, the sampling frame waveform data length, the frame number and the residual frame data length.

6. The method of claim 4, wherein, The second preset rule includes that the rising edge of the cycle enable instruction is delayed for one beat as the cycle start judgment mark, if the mark is valid, the cycle starts, and the cycle start mark is set to 1; Otherwise, the cycle does not start, and the cycle start mark remains; The third preset rule includes that when the cycle start mark is set to 1 and the data transmission interface receives the enable, the cycle is valid, and the cycle valid flag is set to 1; Otherwise, the cycle is invalid, and the cycle valid flag is set to 0.

7. The method of claim 4, wherein the method further comprises: The calculation of the address cycle count includes that if the address cycle count is greater than or equal to (the total waveform data length-the sampling frame waveform data length), the next time address cycle count = current address cycle count-(the total waveform data length-the sampling frame waveform data length); Otherwise, the next time address cycle count = current address cycle count + sampling frame waveform data length; The calculation of the complement length includes that if the address cycle count is greater than or equal to (the total waveform data length-the sampling frame waveform data length), the next time complement length = current address cycle count-(the total waveform data length-the sampling frame waveform data length); Otherwise, the next time complement length = current complement length; The calculation of the cycle number includes that if the address cycle count is greater than or equal to (the total waveform data length-the sampling frame waveform data length), the next time cycle count = current cycle count + 1; Otherwise, the next time cycle count = current cycle count.

8. The method of claim 4, wherein the method further comprises: If the residual frame data address does not need to be output, it is judged whether the cycle is completed according to whether the address number exceeds the frame number-1.

9. The method of claim 1, wherein Also comprising: The control module sends a sampling frame waveform data enable; The data cycle module judges whether the received sampling frame waveform data enable is valid, if the sampling frame waveform data enable is valid, it is judged whether the received residual frame data enable is valid; If the received residual frame data enable is valid, the residual frame data is prestored, if not, the data cycle number is calculated, the data cycle length count is calculated, the complement length is calculated and the cycle number is calculated; According to the current complement length, different data processing branches are entered to judge whether the cycle is completed, if not, whether the current cycle needs to output residual frame data is judged, if yes, whether the current data number is equal to the frame number is judged, if not, the data enable is outputted, the complete frame data length part in the residual frame data is outputted, the residual frame data is updated and the data cycle module is continued to judge whether the received sampling frame waveform data enable is valid.

10. A signal generator for cyclically generating a high rate waveform signal, characterized by The signal generator is used to generate the high-speed rate waveform signal in cycles by using the method in any one of claims 1 to 9. The signal generator is used to generate the high-speed rate waveform signal in cycles by using the method in any one of claims 1 to 9.

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