Data path system, method and device based on soft and hard fusion engine and medium

Abstract

The invention provides a data path system, method and device based on a software and hardware fusion engine and a medium, and belongs to the technical field of solid state disks. Comprising a command self-analysis module, a collaborative data transmission module, a self-adaptive flash memory block management module and an abnormal power-off collaborative processing module. The system is electrified and initialized; acquiring a host command, and checking the legality of the command by a command self-analysis module according to a set threshold value; the collaborative data transmission module calculates the data transmission quantity, automatically obtains a cache block, analyzes and obtains a PRP address entry, and starts dma transmission; the adaptive flash memory block management module provides space block and flash memory programming and updates a logic physical address mapping table; when abnormal power-off is detected, the abnormal power-off cooperative processing module cancels the command automatic takeover function and flashes the current cache content into the NAND; and updating the logic-physical mapping table, and outputting the current block information to control software to complete power-off. According to the invention, the data transmission process is more efficient, and the loss of data transmission in a path is reduced.

Description

Technical Field

[0001] The present invention relates to a data path system, method, device and medium based on a software-hardware fusion engine, belonging to the technical field of solid-state hard disks. Background Art

[0002] With the widespread application of new generation information technologies such as cloud computing, big data, artificial intelligence, and 5G communications, data is growing in massive and explosive quantities. Some application scenarios have more stringent requirements on the timeliness of data access, and upper-level businesses have put forward higher performance requirements for data center storage systems. As a core component of modern data center storage systems, the performance of solid-state drives (SSDs) is directly related to the access efficiency of upper-level applications to data and user experience. However, the latency of SSDs for read and write access requests has become an important technical indicator for improving the performance of flash storage master chips. This latency directly affects the data transmission speed and storage efficiency.

[0003] Traditional SSD master control design has many bottlenecks in command processing and data transmission, such as low command parsing efficiency, high data transmission latency, insufficient hardware resource utilization, etc. These problems limit the improvement of SSD performance. Therefore, the industry has conducted extensive research and exploration on how to reduce the command processing and data transmission latency inside the SSD master control and improve data transmission efficiency to meet the application requirements of high performance and high reliability. Summary of the invention

[0004] The purpose of the present invention is to provide a data path system, method, device and medium based on a software and hardware fusion engine, which can improve the resource allocation efficiency of the data transmission engine, realize automatic collaborative processing of commands, reduce the processing delay and processing time of commands, ensure service quality, and meet high-performance and high-reliability application requirements while meeting queue priorities.

[0005] In order to achieve the above object, the present invention is implemented through the following technical solutions: A data path system based on a software-hardware fusion engine, comprising: The command self-analysis module automatically parses the command format after reading the command back from the host, calculates the logical address according to the number of namespaces, and automatically checks each command code in the command according to the configured error checking conditions; The collaborative data transmission module is used to configure a resource pool during power-on initialization. When processing a write command, it automatically allocates a buffer in the resource pool to receive host data, and automatically synchronizes and updates a copy to the DDR cache of the corresponding offset after the host data transmission is completed; automatically obtains the prp address and starts DMA data transmission, and sends the completion message to the fifo that interacts with the NAND control module after the transmission is completed; dynamically allocates DMA according to the current load of each DMA engine; The adaptive flash block management module is used to provide free writable NAND flash blocks in real time, and to perform operations such as flash block recycling, erasing, and changing the logical-physical mapping table according to the free block threshold set by the software; and to process messages in the interactive fifo. When new data is written from the interactive fifo, it starts the write programming action to the NAND flash block, and updates the logical address-physical address mapping table after the write is completed; The abnormal power-off collaborative processing module is used to disable the automatic management function of the flash memory free blocks when an abnormal power-off interruption is sensed, and to promptly flush the data in the cache to the NAND flash memory and output the current block information.

[0006] Preferably, after reading back the command from the host, the command self-parsing module further automatically checks the command according to the error checking condition configured by the software, wherein the error checking condition is the legal value range of the field, including the legal range of the logical address.

[0007] Preferably, the resource pool in the collaborative data transmission module is configured during power-on initialization to store data to be processed, and improves data transmission efficiency by automatically allocating buffers and synchronously updating DDR caches.

[0008] Preferably, the adaptive flash memory block management module is further used to dynamically adjust the allocation of flash memory blocks according to a set free block threshold to optimize storage performance.

[0009] Preferably, the automatic parsing of the command format includes automatic acquisition, parsing and format checking of the command.

[0010] Preferably, the resource pool corresponds to multiple SRAM buffers, and the granularity of the buffer is 4224 bytes.

[0011] Preferably, the automatic allocation of the buffer in the resource pool to receive the host data is achieved by applying for cache from the resource pool. The cache application processing logic is as follows: the command request that needs to apply for cache is put into the first-in-first-out fifo. If the cache application for the current command fails, the processing request for this command is reinserted into the fifo and waits for the release of resources.

[0012] A method for using a data path system based on a software-hardware fusion engine, comprising: When the system is powered on, the initialization command checks the boundary value of the field and the threshold value of the number of free blocks; Get the host command, and the command self-analysis module will check the legitimacy of the command according to the set threshold; The collaborative data transfer module calculates the data transfer volume, automatically obtains cache blocks, parses and obtains PRP address entries, and starts DMA transfers; The adaptive flash block management module provides space blocks and flash programming, and updates the logical-physical address mapping table; When an abnormal power failure is detected, the abnormal power failure collaborative processing module cancels the command automatic takeover function and flushes the current cache content to NAND; Update the logical-physical mapping table, output the current block information to the control software, the software completes the log and mapping table saving, and completes the power-off.

[0013] A data path device based on a soft-hard fusion engine comprises a processor and a memory storing program instructions, wherein the processor is configured to execute the data path method based on the soft-hard fusion engine when running the program instructions.

[0014] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the data path method based on a soft-hard fusion engine.

[0015] The advantages of the present invention are: through the design of the soft-hard fusion engine, the present invention reduces the involvement of software functions as much as possible, making the data transmission process more efficient and reducing the loss of data transmission in the path. This improvement not only improves the data transmission speed, but also optimizes the resource utilization efficiency.

[0016] The abnormal power-off protection mechanism designed in the present invention can respond quickly when an abnormal power-off is sensed, automatically shut down the automatic management function of the flash memory free blocks, and promptly flush the data in the cache to the NAND flash memory, thereby minimizing the risk of data loss. This mechanism not only enhances the reliability of data, but also reduces the difficulty of designing the backup power circuit, making the overall system more stable and reliable.

[0017] The method of the present invention not only supports the traditional LBA access mode, but also can adapt to new access modes such as ZNS, showing strong flexibility and applicability. This design enables the present invention to better meet the needs of different application scenarios and improve its market competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0019] Figure 1 It is a schematic diagram of the process of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] Example 1 A data path system based on a software-hard fusion engine improves the resource allocation efficiency of the data transmission engine under the premise of meeting the queue priority through the software-hard fusion engine and scheduling algorithm design, realizes automatic collaborative processing of commands, reduces the processing delay and processing time of commands, ensures service quality, and meets high-performance and high-reliability application requirements. The system includes: a command self-parsing module, a collaborative data transmission module, an adaptive flash block management module, and an abnormal power-off collaborative processing module.

[0022] The command self-parsing module is coupled to the command acquisition unit. After reading the command back from the host, it automatically parses the command format, calculates the logical address according to the number of namespaces, and automatically checks each command code in the command according to the configured error checking conditions.

[0023] As a refinement of the above embodiment, this module is used to realize automatic acquisition, parsing and format checking of commands, and rearrange the command format of the original command sent by the host according to the requirements of the collaborative data transmission module, so as to facilitate the data transmission module to calculate the data transmission volume. The command format check needs to be judged according to the legal value range of the field configured by the software. When any one of the conditions is found to be unsatisfactory, the command processing is terminated and an error code is returned to the host.

[0024] The collaborative data transmission module is used to configure a resource pool during power-on initialization. When processing a write command, it automatically allocates a buffer in the resource pool to receive host data, and automatically synchronizes and updates a copy to the DDR cache of the corresponding offset after the host data transmission is completed; it automatically obtains the prp address and starts DMA data transmission, and sends the completion message to the fifo that interacts with the NAND control module after the transmission is completed; it dynamically allocates DMA according to the current load conditions of each DMA engine.

[0025] As a refinement of the above-mentioned embodiment, the data collaborative transmission module is the key to the design of the soft-hard collaborative transmission engine. The collaborative data transmission module will automatically calculate the data transmission volume according to the command format output by the command self-parsing module, and apply to occupy the corresponding cache from the resource pool configured by the software to receive the host data. The design logic for applying for cache is to design a first-in-first-out fifo, and put the command request that needs to apply for cache into the fifo. If the cache application of the current command fails, the processing request of this command will be reinserted into the fifo and wait for the release of resources. The second function of the collaborative data transmission module is to automatically obtain the prp address and start DMA data transmission. This process does not require software participation. After the Host data transmission is completed, it will automatically and synchronously update a copy to the corresponding offset DDR cache for use in data recovery. At the same time, the completion message will be sent to the fifo that interacts with the adaptive flash block management module. When scheduling the DMA engine for data transmission, it will coordinate the work pressure between each DMA according to the working status of the DMA engine to avoid the problem of DMA load imbalance. The resource pool corresponds to multiple SRAM buffers, and the granularity of the buffer is 4224 bytes.

[0026] Automatic allocation of the buffer in the resource pool to receive host data is achieved by applying for cache from the resource pool. The cache application processing logic is as follows: the command request that needs to apply for cache is put into the first-in-first-out fifo. If the cache application for the current command fails, the processing request for this command is reinserted into the fifo and waits for the release of resources.

[0027] The adaptive flash memory block management module is used to provide free writable NAND flash memory blocks in real time, and execute the operations of recycling, erasing and changing the logical-physical mapping table of flash memory blocks according to the free block threshold set by the software; and process the messages in the interactive fifo. When new data is written from the interactive fifo, the write programming action to the NAND flash memory block is started, and the logical address-physical address mapping table is updated after the write is completed.

[0028] As a refinement of the above-mentioned embodiment, this module is mainly responsible for writing the data in the previous-level data collaborative transmission cache into the flash memory, including the flash memory block automatic management algorithm and the cache automatic saving function. The flash memory block automatic management algorithm refers to providing free writable flash memory blocks in real time according to the free block threshold set by the software, and automatically recovering, erasing and changing the logical-physical mapping table of the flash memory blocks. The cache automatic saving function refers to sending a message according to the data collaborative transmission module. When new data is written from the interactive fifo, the write programming action to the flash memory block is started, and after the write is completed, the logical address-physical address mapping table is updated.

[0029] The abnormal power-off collaborative processing module is used to disable the automatic management function of the flash memory free blocks when an abnormal power-off interruption is sensed, and to promptly flush the data in the cache to the NAND flash memory and output the current block information.

[0030] As a refinement of the above embodiment, the abnormal power-off collaborative processing module can automatically turn off the automatic management function of the flash memory free blocks when it senses an abnormal power-off interruption, and at the same time, promptly flush the data in the cache to the NAND, update the mapping table, output the currently used physical block information, and hand it over to the software for management, and the software triggers functions such as log saving and mapping table flushing.

[0031] It should be noted that compared with the traditional design, this method reduces the involvement of software functions as much as possible, reduces the loss of data transmission in the path, and the designed abnormal power-off protection mechanism can minimize the time consumption and reduce the difficulty of designing the backup power circuit. At the same time, this method can support both traditional LBA access methods and new access methods such as ZNS, and the design is more flexible and has strong applicability.

[0032] like Figure 2 As shown in the figure, its complete function realization also needs to include the basic hardware units of SSD, including the main control chip (soc main control), NAND FLASH flash memory, DDR cache, sram, power chip, PCIe gold finger. The main control chip is the core of the SSD controller, which is composed of MCU, PCIe module, NVMe controller, NAND flash memory controller and other modules.

[0033] Example 2 like Figure 1 As shown, a method for using a data path system based on a software-hardware fusion engine includes: S1: The system is powered on, and the initialization command checks the boundary value of the field and the threshold of the number of free blocks; S2: Obtain the host command, and the command self-analysis module performs a command validity check based on the set threshold; S3: The collaborative data transmission module calculates the data transmission volume, automatically obtains the cache block, parses and obtains the PRP address entry, and starts the DMA transmission; S4: The adaptive flash block management module provides space blocks and flash programming, and updates the logical-physical address mapping table; S5: abnormal power failure is detected, and the abnormal power failure collaborative processing module cancels the command automatic takeover function and flushes the current cache content to NAND; S6: Update the logic-physical mapping table, output the current block information to the control software, the software completes the log and mapping table saving, and completes the power-off.

[0034] The disclosed embodiment also provides a data path device based on a soft-hard fusion engine, including a processor and a memory. Optionally, the device may also include a communication interface and a bus. The processor, the communication interface, and the memory may communicate with each other through the bus. The communication interface may be used for information transmission. The processor may call the logic instructions in the memory to execute the data path method based on the soft-hard fusion engine of the above embodiment.

[0035] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0036] The memory, as a computer-readable storage medium, can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor executes the functional application and data processing by running the program instructions / modules stored in the memory, that is, the data path method based on the software and hardware fusion engine in the above embodiment is implemented.

[0037] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory may include a high-speed random access memory and may also include a non-volatile memory.

[0038] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A data path system based on a software and hardware fusion engine, characterized in that: include: The command self-analysis module automatically parses the command format after reading the command from the host, calculates the logical address according to the number of namespaces, and automatically checks each command code in the command according to the configured error checking conditions; The collaborative data transmission module is used to configure a resource pool during power-on initialization. When processing a write command, it automatically allocates a buffer in the resource pool to receive host data, and automatically synchronizes and updates a copy to the DDR cache of the corresponding offset after the host data transmission is completed; automatically obtains the prp address and starts DMA data transmission, and sends the completion message to the fifo that interacts with the NAND control module after the transmission is completed; dynamically allocates DMA according to the current load of each DMA engine; The adaptive flash block management module is used to provide free writable NAND flash blocks in real time, and to perform operations such as flash block recycling, erasing, and changing the logical-physical mapping table according to the free block threshold set by the software; and to process messages in the interactive fifo. When new data is written from the interactive fifo, it starts the write programming action to the NAND flash block, and updates the logical address-physical address mapping table after the write is completed; The abnormal power-off collaborative processing module is used to disable the automatic management function of the flash memory free blocks when an abnormal power-off interruption is sensed, and to promptly flush the data in the cache to the NAND flash memory and output the current block information.

2. The data path system based on the software and hardware fusion engine according to claim 1 is characterized in that: After reading back the command from the host, the command self-analysis module further automatically checks the command according to the error checking condition configured by the software, wherein the error checking condition is the legal value interval of the field, including the legal range of the logical address.

3. The data path system based on the software and hardware fusion engine according to claim 1 is characterized in that: The resource pool in the collaborative data transmission module is configured during power-on initialization, and is used to store data to be processed, and improves data transmission efficiency by automatically allocating buffers and synchronously updating DDR caches.

4. The data path system based on the software and hardware fusion engine according to claim 1, characterized in that: The adaptive flash memory block management module is also used to dynamically adjust the allocation of flash memory blocks according to the set free block threshold to optimize storage performance.

5. The data path system based on the software and hardware fusion engine according to claim 1 is characterized in that: Automatic parsing of command formats includes automatic acquisition, parsing and format checking of commands.

6. The data path system based on the software and hardware fusion engine according to claim 1, characterized in that: The resource pool corresponds to multiple SRAM buffers, and the granularity of the buffer is 4224 bytes.

7. The data path system based on the software and hardware fusion engine according to claim 1 or 6, characterized in that: Automatic allocation of the buffer in the resource pool to receive host data is achieved by applying for cache from the resource pool. The cache application processing logic is as follows: the command request that needs to apply for cache is put into the first-in-first-out fifo. If the cache application for the current command fails, the processing request for this command is reinserted into the fifo and waits for the release of resources.

8. A method for using the system of any one of the requirements 1-7, characterized in that: include: When the system is powered on, the initialization command checks the boundary value of the field and the threshold value of the number of free blocks; Get the host command, and the command self-analysis module will check the legitimacy of the command according to the set threshold; The collaborative data transfer module calculates the data transfer volume, automatically obtains cache blocks, parses and obtains PRP address entries, and starts DMA transfers; The adaptive flash block management module provides space blocks and flash programming, and updates the logical-physical address mapping table; When an abnormal power failure is detected, the abnormal power failure collaborative processing module cancels the command automatic takeover function and flushes the current cache content to NAND; Update the logical-physical mapping table, output the current block information to the control software, the software completes the log and mapping table saving, and completes the power-off.

9. A data path device based on a software-hardware fusion engine, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the data path method based on the soft-hard fusion engine as claimed in claim 8 when running the program instructions.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the program is executed by a processor, the data path method based on the soft-hard fusion engine as described in claim 8 above is implemented.

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