Instruction processing method and device, processor, medium, program and computer device

Abstract

Embodiments of the present application provide an instruction processing method, device, processor, medium, program and computer device, wherein the method on the processor side comprises: obtaining an instruction of an application program; determining whether the instruction is a supported instruction of the processor; if the instruction is an unsupported instruction of the processor, determining the type of the instruction in the unsupported instruction; if the instruction is an extended instruction in the unsupported instruction, decoding the instruction to obtain decoding information of the instruction, and saving the decoding information of the instruction to a corresponding register; wherein the extended instruction is an instruction that can be decoded and recognized by the processor but cannot be executed; and based on the instruction being an unsupported instruction of the processor, triggering an illegal instruction exception, so that an exception processing function corresponding to the illegal instruction exception performs software simulation execution based on the decoded decoding information of the extended instruction. Embodiments of the present application can efficiently process unsupported instructions and control hardware costs.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of processor, and in particular, to an instruction processing method, device, processor, medium, program and computer device. BACKGROUND

[0002] As operation commands in a program, instructions can guide a processor to complete computation and data operation, so that the processor can read, parse and execute the instructions (i.e., the processor processes the instructions) to realize the function of the program.

[0003] As a set of instructions that the processor can understand and execute, the instruction set of the processor can be designed specifically according to a specific application scenario, for example, by simplifying or customizing the instruction set, so that the processor can optimize performance, power consumption and cost to adapt to different application scenarios. Therefore, the processor has supported instructions and unsupported instructions, such as based on a specific application scenario, the instruction set of the processor is designed to have supported instructions (i.e., supported instructions), and instructions not in the instruction set of the processor can be regarded as unsupported instructions (i.e., unsupported instructions).

[0004] However, the specific design of the above instruction set also brings compatibility problems, especially when the program uses the unsupported instructions of the processor, the processor faces the situation of processing the unsupported instructions, so how to provide an instruction processing scheme to improve the processing efficiency of the unsupported instructions and reduce the hardware cost of processing the unsupported instructions has become a technical problem that technicians in the field need to solve. SUMMARY

[0005] Therefore, embodiments of the present application provide an instruction processing method, device, processor, medium, program and computer device to improve the processing efficiency of the unsupported instructions and reduce the hardware cost of processing the unsupported instructions, to realize efficient processing of the unsupported instructions and control the hardware cost.

[0006] To achieve the above object, embodiments of the present application provide the following technical solutions.

[0007] In a first aspect, an embodiment of the present application provides an instruction processing method applied to a processor, the method comprising:

[0008] obtaining an instruction of an application program;

[0009] determining whether the instruction is a supported instruction of the processor;

[0010] if the instruction is an unsupported instruction of the processor, determining a type of the instruction in the unsupported instructions;

[0011] If the instruction is an extended instruction in the unsupported instructions, the instruction is decoded to obtain decoding information of the instruction, and the decoding information of the instruction is stored into a corresponding register; the extended instruction is an instruction that can be decoded and recognized by the processor but cannot be executed;

[0012] If the instruction is an extended instruction in the unsupported instructions, the instruction is decoded to obtain decoding information of the instruction, and the decoding information of the instruction is stored into a corresponding register; the extended instruction is an instruction that can be decoded and recognized by the processor but cannot be executed;

[0013] In a second aspect, an embodiment of the present application provides an instruction processing method, applied to system software, wherein a processor runs the system software through a kernel space; the method comprises:

[0014] If the instruction is an extended instruction in the unsupported instructions, the instruction is decoded to obtain decoding information of the instruction, and the decoding information of the instruction is stored into a corresponding register; the extended instruction is an instruction that can be decoded and recognized by the processor but cannot be executed;

[0015] If the instruction is an extended instruction in the unsupported instructions, the instruction is decoded to obtain decoding information of the instruction, and the decoding information of the instruction is stored into a corresponding register; the extended instruction is an instruction that can be decoded and recognized by the processor but cannot be executed;

[0016] If the instruction is an extended instruction in the unsupported instructions, the instruction is decoded to obtain decoding information of the instruction, and the decoding information of the instruction is stored into a corresponding register; the extended instruction is an instruction that can be decoded and recognized by the processor but cannot be executed.

[0017] In a third aspect, an embodiment of the present application provides an instruction processing apparatus, applied to a processor, comprising:

[0018] An instruction fetching module, configured to obtain an instruction of an application program;

[0019] A decoding module, configured to determine whether the instruction is a supported instruction of the processor; if the instruction is an unsupported instruction of the processor, determine a type of the instruction in the unsupported instructions; if the instruction is an extended instruction in the unsupported instructions, decode the instruction to obtain decoding information of the instruction, and store the decoding information of the instruction into a corresponding register; the extended instruction is an instruction that can be decoded and recognized by the processor but cannot be executed.

[0020] An exception processing unit, configured to trigger an illegal instruction exception based on the instruction being an unsupported instruction of the processor, so that an exception processing function corresponding to the illegal instruction exception performs software simulation execution based on the decoded decoding information of the extended instruction.

[0021] In a fourth aspect, an embodiment of the present application provides an instruction processing apparatus, applied to system software, wherein a processor runs system software through a kernel space; the instruction processing apparatus comprises:

[0022] an entry module, configured to call an exception handling function corresponding to an illegal instruction exception, the exception handling function being deployed in the system software, and the exception handling function being configured to handle the illegal instruction exception triggered by an instruction of an application program being an unsupported instruction of the processor;

[0023] an exception handling function module, configured to determine whether a register contains decoding information of the instruction; if the register contains the decoding information of the instruction, it is determined that the instruction is an extended instruction in the unsupported instruction, the instruction is executed through software simulation based on the decoding information of the instruction, and an execution result of the software simulation is obtained as an execution result of the instruction; wherein the extended instruction is an instruction that can be recognized by the processor through decoding but cannot be executed.

[0024] In a fifth aspect, an embodiment of the present application provides a processor, comprising the instruction processing apparatus in the third aspect.

[0025] In a sixth aspect, an embodiment of the present application provides a computer device, comprising a memory and a processor, the memory stores computer system instructions, and the processor calls the computer system instructions to execute the instruction processing method in the second aspect.

[0026] In a seventh aspect, an embodiment of the present application provides a storage medium, the storage medium stores computer system instructions, and the computer system instructions are executed to implement the instruction processing method in the second aspect.

[0027] In an eighth aspect, an embodiment of the present application provides a computer system program, comprising computer system instructions, and the computer system instructions are executed to implement the instruction processing method in the second aspect.

[0028] In a ninth aspect, an embodiment of the present application provides a computer device, comprising a processor and system software of the computer device; the processor is the processor in the fifth aspect, and the system software comprises the instruction processing apparatus in the fourth aspect.

[0029] It can be seen that, for the extension instruction, the processor internally decodes and analyzes the extension instruction in advance, so that the processor internally saves the decoding information of the extension instruction in advance; further, when the instruction is a non-supported instruction of the processor, triggering an illegal instruction exception, the exception processing function corresponding to the illegal instruction exception can reuse the decoded decoding information of the extension instruction that has been decoded internally by the processor to perform software simulation execution on the extension instruction, avoiding the process of reacquiring the instruction from the memory for software decoding and then software simulation execution, reducing the memory access and software decoding delay, that is, the exception processing function can directly perform software simulation execution based on the decoded decoding information of the extension instruction, thereby improving the processing efficiency of the extension instruction as a non-supported instruction of the processor. That is, if the processor does not internally save the decoding information of the extension instruction in advance, the exception processing function needs to reacquire the instruction from the memory for software decoding before performing software simulation execution on the extension instruction, and then performs software simulation execution based on the result of software decoding, so that the embodiment of the present application can reduce the memory access and software decoding delay of the exception processing function when processing the extension instruction, thereby improving the processing efficiency of the extension instruction as a non-supported instruction. At the same time, the embodiment of the present application can avoid adding a coprocessor to participate in the processing of the non-supported instruction, reducing the hardware complexity and hardware cost. Therefore, the embodiment of the present application can improve the processing efficiency of the extension instruction as a non-supported instruction, and reduce the hardware cost, realizing efficient processing of the non-supported instruction and controlling the hardware cost. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0031] Figure 1 A simplified example diagram of computer architecture.

[0032] Figure 2 An example diagram of stages of a pipeline.

[0033] Figure 3 An example diagram of parallel processing of multiple instructions.

[0034] Figure 4 An example diagram of a decoding stage.

[0035] Figure 5 A flowchart of an instruction processing method provided by the embodiment of the present application.

[0036] Figure 6 A flowchart for determining the type of the instruction in the non-supported instruction.

[0037] Figure 7 A processing example diagram of a decoding stage provided for an embodiment of the present application.

[0038] Figure 8 Another flowchart of an instruction processing method provided for an embodiment of the present application.

[0039] Figure 9A A block diagram of an instruction processing apparatus provided for an embodiment of the present application.

[0040] Figure 9B Another block diagram of an instruction processing apparatus provided for an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0042] For ease of understanding, Figure 1 An exemplary simplified example diagram of a computer architecture is shown, Figure 1 Mainly used to illustrate that the instructions processed by the processor come from the memory, such as Figure 1 As shown in the figure, the computer architecture can include a processor 100, a memory 200, and a computer bus 300 connecting the processor 100 and the memory 200.

[0043] Among them, the processor 100 is a hardware component responsible for executing instructions and processing data. The memory 200 is a hardware component for storing data and programs; based on factors such as data access speed, storage capacity, and persistence, the memory can have different types, including but not limited to cache, memory, hard disk, etc. The computer bus 300 can build a communication channel between computer components (such as between the processor, memory, hard disk, etc. Computer components between) for transmitting data, addresses and control information between the connected computer components, including but not limited to data bus, address bus, control bus, etc.

[0044] It should be noted that the processor can be a single-core processor or a multi-core processor, the single-core processor refers to that there is only one computing core (i.e., one processor core) in the processor, and the multi-core processor refers to that the processor internally contains multiple computing cores (i.e., multiple processor cores), each processor core can process instructions, so that multiple processor cores can process multiple tasks at the same time, thereby improving the processing capability of the processor. The processor processing instructions referred to in the embodiments of the present application can be the processor core processing instructions in the processor, and is not limited to the single-core processor or the multi-core processor.

[0045] The processor (specifically, the processor core in the processor) can obtain instructions from the memory, thereby parsing and executing the instructions to complete the computing task of the instructions. In order to improve the throughput and efficiency of the processor processing instructions, the processor can use pipeline technology to process instructions. Specifically, the pipeline divides the processing process of the instructions into multiple stages, one stage can be regarded as a subtask of processing instructions, so that multiple instructions can be in different stages at the same time to realize the parallel execution of multiple instructions. That is, the pipeline can stage and parallelize the process of the processor processing instructions, thereby improving the efficiency of the processor processing instructions. For example, taking a 5-stage pipeline as an example, Figure 2 An example of a stage of a pipeline is shown as follows, Figure 2 As shown in the figure, the stages of the pipeline can include:

[0046] The instruction fetch (IF) stage is used to read instructions from the memory (such as the memory or the cache);

[0047] The instruction decode (ID) stage is used to decode and analyze the instructions, identify the operation type and required operands of the instructions, and the like;

[0048] The execute (EX) stage is used to execute the operations defined by the instructions, such as addition, multiplication, or logical operation, and the like;

[0049] The memory access (MEM) stage is used to access the memory to read or write data;

[0050] The write back (WB) stage is used to write the calculation results back to the register or the memory.

[0051] It should be noted that the above is an example of a 5-stage pipeline of instruction fetching, decoding, execution, memory access, and write back, and the specific number of stages (i.e., the specific number of stages of the pipeline) and the specific architecture of the pipeline can be adjusted and designed according to different processor requirements, and is not limited to the form of a 5-stage pipeline. For example, a processor can use a different number and complexity of pipeline stages according to performance, power consumption, cost, and other goals, so the number of pipeline stages of the processor can be more than 5 or less than 5, depending on the design goals and application scenarios of the processor.

[0052] Based on the use of the pipeline, the instruction stream entering the pipeline (i.e., the plurality of instructions entering the pipeline) can be in different stages at the same time, thereby achieving parallel execution of the plurality of instructions, shortening the completion time of the instruction stream; for example, the jth stage of a subsequent instruction in the instruction stream can be executed at the same time as the j+1th stage of a previous instruction, i.e., adjacent stages of adjacent instructions can be executed at the same time, and the stage of the previous instruction is faster than the stage of the subsequent instruction in the adjacent instructions, so that the processor can process different stages of multiple instructions at the same time in the same clock cycle, improving the instruction processing performance of the processor.

[0053] For ease of understanding, Figure 3 An example diagram of parallel processing of multiple instructions is shown as follows: Figure 3 As shown, taking instructions i1, i2, i3, and i4 in the instruction stream as an example, in clock cycle 1, instruction i1 is in the IF (instruction fetching) stage; in clock cycle 2, instruction i1 is in the ID (decoding) stage, and instruction i2 enters the pipeline and is in the IF stage; in clock cycle 3, instruction i1 is in the EX (execution) stage, instruction i2 is in the ID stage, and instruction i3 enters the pipeline and is in the IF stage; in clock cycle 4, instruction i1 is in the MEM (memory access) stage, instruction i2 is in the EX stage, instruction i3 is in the ID stage, and instruction i4 enters the pipeline and is in the IF stage, and so on. As can be seen, the stage of a previous instruction in the pipeline is one stage faster than the stage of a subsequent instruction in the pipeline, so that instructions i1, i2, i3, and i4 are in different stages of the pipeline at the same clock cycle, and the processor can process different stages of instructions i1, i2, i3, and i4 at the same time in the same clock cycle, achieving parallel processing of instructions i1, i2, i3, and i4.

[0054] It should be noted that in the pipeline, the program counter (PC) is used to store the address of the next instruction to be processed, and is one of the control registers in the pipeline; for example, after each instruction fetch stage is completed, the program counter can be automatically updated to point to the address (e.g., memory address) of the next instruction, that is, the value of the program counter is automatically updated with each instruction fetch stage to provide an address for the next instruction, ensuring that the pipeline is continuously filled with new instructions. The pipeline register is used to pass information (such as data and state information) between instructions in the pipeline stages. Each stage of the pipeline can have a corresponding pipeline register to save the information passed from the previous stage; that is, the pipeline register can ensure that each stage can work in parallel and maintain intermediate results, and thus in the case of different instructions being in different stages of the pipeline at the same time, the pipeline register can save the intermediate data of these instructions to ensure that the parallel processing of different instructions in the pipeline can proceed smoothly.

[0055] If the processor finds that the instruction is a processor-unsupported instruction, that is, the instruction is not within the support range of the processor, during the process of processing the instruction, the processor-unsupported instruction can be regarded as an abnormal instruction, and an abnormal instruction processing mechanism different from the pipeline stage needs to be used to process the unsupported instruction.

[0056] It should be noted that the processor-unsupported instruction can be an instruction omitted in the design stage of the instruction set of the processor. For example, in the design of the instruction set of the processor running the AI (Artificial Intelligence) application program, such as the design of the instruction set of the GPGPU (General Purpose Graphics Processing Unit), the instruction set of the processor selectively omits instructions that most AI application programs will not use to improve performance, reduce power consumption and cost. For example, most AI application programs will not use 64-bit floating-point numbers for calculation, and the processor pays more attention to 16-bit and 32-bit floating-point operation instructions, so that the instruction set of the processor running the AI application program omits the 64-bit floating-point operation instruction in the design, such as omitting the 64-bit floating-point operation unit in the processor. The design of omitting the 64-bit floating-point operation unit is sufficient for most AI application programs, but it can cause incompatibility for a small part of AI application programs that require high-precision operations, such as some AI application programs and frameworks that use 64-bit floating-point numbers. At this time, the processor can still encounter 64-bit floating-point operation instructions when running the application program, thereby causing an instruction exception.

[0057] It is worth noting that the above is an example of a processor that does not support instructions for running AI applications, 64-bit floating-point operation instructions, and other forms of processor instructions that do not support instructions. Not limited to 64-bit floating-point operation instructions, the embodiments of the present application do not limit the form of the processor and the form of the processor instruction that does not support instructions.

[0058] The processor instruction that does not support instructions can be directly used as an illegal instruction (an illegal instruction is a form of an exception instruction), so that the illegal instruction processing mechanism (a form of an exception instruction processing mechanism) is used to process the instruction that does not support instructions.

[0059] One way of the illegal instruction processing mechanism is to use a coprocessor to simulate the running of the illegal instruction, obtain the simulation result and return it to the processor, so that the processor can continue to execute the subsequent instructions after obtaining the simulation result of the illegal instruction. The coprocessor is an auxiliary processing unit of the processor (such as CPU, GPGPU, etc.), which is used to provide additional functions and computing power for the processor, such as the coprocessor can perform specific types of operations (such as floating-point operations, graphics processing operations, etc.) or handle special instruction extensions.

[0060] Specifically, when the processor determines that the currently processed instruction is an unsupported instruction, it is considered an illegal instruction. At this time, the processor does not immediately terminate the program or trigger an exception, but sends the instruction to the coprocessor for processing. After the coprocessor receives the instruction, it simulates the execution of the instruction (i.e., the coprocessor simulates the execution process of the instruction through software or hardware), thereby obtaining the simulation result of the instruction, and the coprocessor feeds back the simulation result to the processor. After the processor obtains the simulation result of the instruction, it continues to normally execute the subsequent instructions.

[0061] The illegal instruction processing mechanism involving the coprocessor can make the processor not need to directly report an error or terminate the program, but instead hand over the illegal instruction to a dedicated coprocessor for processing, avoiding system crashes or abnormal exits. However, the illegal instruction processing mechanism involving the coprocessor requires an additional coprocessor to process the illegal instruction, which means that in addition to the processor, an additional coprocessor hardware needs to be added, resulting in additional hardware costs. In addition, in order to support the coprocessor, the design of the computer architecture needs to be greatly changed, such as the tasks originally handled by the processor now need to be handled by the coprocessor, which requires adjustments and changes to the design of the instruction set architecture, bus structure, data flow, etc. Hardware changes undoubtedly further increase hardware costs. Further, the coprocessor can only handle specific types of operations or special instruction extensions, and if new instructions or requirements are encountered, the coprocessor may need to be upgraded or replaced, so the flexibility of the coprocessor is limited.

[0062] It can be seen that the hardware cost of the illegal instruction processing mechanism based on the coprocessor participation is high, and the flexibility is low.

[0063] Another processing manner of the illegal instruction processing mechanism is to check whether the instruction belongs to the supported instructions of the processor in the decoding stage of the pipeline. If the instruction is an unsupported instruction of the processor, an illegal instruction exception is triggered, so that the illegal instruction exception can be reported to the operating system of the computer, and the operating system responds.

[0064] To facilitate understanding of the reporting of the illegal instruction exception, Figure 4 An example diagram of the decoding stage is shown as follows: Figure 4 As shown, the decoding stage can be implemented by a decoding module in the processor. The decoding module can be a decoder group formed by multiple decoders. The input of the decoding module is the instruction output by the instruction fetching stage. The output of the decoding module is the decoding information of the instruction, such as the operation code and the operand after the instruction is parsed, etc. The decoding information of the instruction is used in the subsequent execution stage. In the decoding stage, according to the types of the supported instructions of the processor, the decoding module decodes different types of supported instructions, so that the decoding module can set decoding units for multiple types of supported instructions, including but not limited to:

[0065] A memory access instruction decoding unit, the memory access instruction is an instruction that needs to access the memory, such as a load instruction and a store instruction. The memory access instruction decoding unit needs to parse the address corresponding to the memory access instruction and identify whether the memory access instruction is a load operation or a store operation.

[0066] A branch instruction decoding unit, the branch instruction is used for program flow control, such as a conditional branch instruction (such as a jump instruction) and an unconditional branch instruction, etc. The branch instruction decoding unit needs to determine whether the branch condition is met (such as whether the condition of executing a jump is met), and determine the branch target address.

[0067] A computing instruction decoding unit, the computing instruction is an instruction that performs an arithmetic operation or a logical operation, such as an addition, subtraction, and operation, or operation instruction, etc. The operand of the computing instruction can come from a register or an immediate number (i.e., a constant value given in the instruction). The computing instruction decoding unit needs to parse the source operand of the computing instruction and other information.

[0068] A vector instruction decoding unit, the vector instruction is an instruction for processing vector data, which is used for multi-data parallel computing and can operate multiple data elements at a time. The vector instruction decoding unit needs to parse the related information of the vector operation, such as the operand, the length of the vector, etc.

[0069] It should be noted that the type of instruction supported by the processor and the corresponding decoding unit described above is only an example, and the type of instruction supported by the processor and the corresponding decoding unit is not limited to the above description. It should be further pointed out that in the decoding stage, the processor needs to read and parse the operands corresponding to the instruction, which are stored in the register, so the decoding stage needs to store and transfer information through the register.

[0070] In combination Figure 4 As shown, if the instruction input in the decoding stage is an unsupported instruction, the decoding stage will trigger an illegal instruction exception. For example, the decoding module can pass the information of the unsupported instruction to the exception handling unit inside the processor, so as to report the illegal instruction exception through the exception handling unit.

[0071] Among them, the exception handling unit is a module component inside the processor, which is responsible for handling exceptions during the execution of the processor. For example, the exception handling unit can be an interrupt controller in the processor, which can respond to and manage exception or interrupt signals. Of course, the interrupt controller is only an example of the exception handling unit, and the exception handling unit can also have other forms.

[0072] The exception handling unit can report the illegal instruction exception to the operating system of the computer, so that the operating system can decide the response mechanism to handle the illegal instruction exception. The operating system can respond to the illegal instruction exception in two ways: through software implementation of instruction extension and ending the application program.

[0073] Through software implementation of instruction extension means that when the operating system receives the reported illegal instruction exception, it will not directly terminate the application program, but will extend the instruction through software, so that the processor can continue to execute. Specifically, for the instruction that reports the illegal instruction exception, the operating system can read the instruction from the memory according to the memory address of the instruction (for example, calculate the memory address of the instruction from the instruction pointer register, and then obtain the instruction from the memory address), and then parse the instruction through software decoding (i.e. understand the meaning of the instruction through software algorithm), and then based on the instruction information parsed by software decoding, implement the function of the instruction through software simulation. However, this way involves reacquiring the instruction from the memory, and then performing software decoding and simulation execution, which is relatively slow, resulting in low processing efficiency of unsupported instructions.

[0074] The ending application program refers to that the operating system directly terminates the application program corresponding to the instruction, for example, the operating system delivers the exception information of the instruction to the application program, so as to inform the application program that an illegal instruction is encountered, and then the application program is ended. After the application program is terminated, the user can perform subsequent processing according to needs, such as restarting the program, checking problems in the code, updating the processor or system configuration, and the like, to solve the problem caused by the illegal instruction. However, this way will cause the instruction function to be unable to be executed, and the application program will be unable to normally run because of encountering the illegal instruction, so that the reliability of the application program is reduced. If the user is required to handle the application program crash or stop situation by himself / herself, it may be necessary to restart the program, reload data or manually adjust the settings, which will increase the burden of the user, the operation threshold of the user is high and is not friendly to the user.

[0075] It can be seen that the processing efficiency of the illegal instruction processing mechanism of the instruction extension implemented by the operating system through software is low, and the illegal instruction processing mechanism of ending the application program has the problems of missing instruction function and low reliability of the application program.

[0076] Based on this, the improved instruction processing scheme provided in the embodiments of the present application supports processing of the unsupported instruction of the processor, and can improve the processing efficiency of the unsupported instruction and reduce the hardware cost of processing the unsupported instruction, to realize efficient processing of the unsupported instruction and control the hardware cost.

[0077] As an optional implementation, the instruction processing method provided in the embodiments of the present application can be executed by the processor and the system software interaction, so that the instruction processing method provided in the embodiments of the present application is divided into the flow of the processor side and the flow of the system software side. The system software is, for example, an operating system; it can be understood that the operating system is a system-level software for managing computer hardware and software resources, and is used for managing and coordinating the work of each hardware (such as CPU, memory, hard disk, peripheral device, and the like) of the computer; the processor is the hardware part of the computer, and is responsible for executing machine instructions and performing data processing; that is, the processor directly interacts with the hardware resources of the computer, and the operating system is responsible for managing the hardware resources of the computer, provides an abstraction layer to coordinate the execution of different tasks, and provides a running environment for the application program.

[0078] The flow of the processor side will be introduced first, as an optional implementation, Figure 5 An optional flowchart of the instruction processing method provided in the embodiments of the present application is exemplarily shown, as shown in Figure 5 As shown in the figure, the flow of the processor side can include the following steps.

[0079] Step S510, acquiring the instruction of the application program.

[0080] For example, the instructions of the application program, including but not limited to the instructions of the AI application, can be regarded as the instructions of the program in the user space, which are fetched from the memory such as the cache or the memory by the instruction fetching stage of the pipeline.

[0081] Step S511 determines whether the instruction is a supported instruction of the processor. If yes, step S512 is performed. If no, step S513 is performed.

[0082] Step S511 enters the decoding stage. In the decoding stage, the decoding module (for example, the decoder) of the processor can determine whether the instruction is a supported instruction of the processor before decoding the instruction. If the instruction is a supported instruction, the embodiment of the present application processes the instruction in the normal pipeline stage. If the instruction is an unsupported instruction, the illegal instruction processing mechanism provided by the embodiment of the present application is used for processing.

[0083] As an optional implementation, the instruction set of the processor defines the supported instructions of the processor. The embodiment of the present application can determine whether the instruction is a supported instruction by determining whether the instruction belongs to the instruction set of the processor. For example, if the instruction does not belong to the instruction set of the processor, it means that the instruction is an unsupported instruction. If the instruction belongs to the instruction set of the processor, it means that the instruction is a supported instruction. For example, the instruction set as a set of supported instructions of the processor can include the operation code and the function description of each supported instruction. The embodiment of the present application can compare the operation code of the instruction with the instruction set. If the operation code of the instruction is contained in the instruction set, the instruction is a supported instruction of the processor. If the operation code of the instruction is not contained in the instruction set, the instruction is an unsupported instruction of the processor.

[0084] Step S512 processes the instruction in the normal pipeline stage.

[0085] In an optional implementation, the normal pipeline stage includes the decoding of the supported instructions of the processor (for example, the decoding of the memory access instruction, the decoding of the branch instruction, the decoding of the calculation instruction, the decoding of the vector instruction, etc.), the subsequent execution stage, the memory access stage, the write-back stage, etc. For details, refer to the description of the pipeline process in the foregoing. Figure 4

[0086] Step S513 determines the type of the instruction in the unsupported instruction. The unsupported instruction type includes the extension instruction and the illegal instruction.

[0087] ​In the case that the instruction is determined to be a non-supported instruction (i.e., the instruction is determined to be not a supported instruction in step S511), the embodiment of the present application does not directly regard the non-supported instruction as an illegal instruction, but classifies the non-supported instruction into an extended instruction and an illegal instruction. That is, if the instruction is a non-supported instruction, the embodiment of the present application can determine the type of the instruction in the non-supported instruction, to determine whether the instruction is an extended instruction or an illegal instruction.

[0088] The extended instruction is an instruction which is not included in the instruction set when the processor is designed, but can be recognized by the decoding. That is, the format of the extended instruction is legal, and the processor can correctly parse the extended instruction (i.e., the extended instruction can be recognized by the decoding) in the decoding stage (e.g., the decoder), but the processor does not have an execution unit corresponding to the extended instruction to actually execute the extended instruction, because the extended instruction is not included in the instruction set. It can be understood that the execution unit corresponds to the execution stage of the pipeline, and the extended instruction does not have a corresponding execution unit in the processor, so the extended instruction cannot be executed in the execution stage. For example, the extended instruction such as a 64-bit floating-point operation instruction can be recognized by the decoding stage (e.g., the decoder), but the processor does not have a corresponding execution unit.

[0089] The illegal instruction is an instruction which cannot be recognized by the decoding and cannot be executed. That is, the instruction which cannot be recognized by the decoding and cannot be executed by the processor is an illegal instruction. For example, the illegal instruction can be an instruction which cannot be recognized by the decoding and cannot be executed by the processor due to an incorrect instruction format, not belonging to any supported instruction set, and the like.

[0090] As an optional implementation, Figure 6 An optional flowchart for determining the type of the instruction in the non-supported instruction is shown, with reference to Figure 6 The method flowchart can include the following steps.

[0091] In step S610, the opcode of the instruction is determined.

[0092] In step S611, the opcode of the instruction is compared with the instruction set extension information of the processor.

[0093] When the instruction does not belong to the instruction set of the processor (e.g., the opcode of the instruction is not included in the instruction set of the processor), the instruction is not a standard instruction defined by the instruction set of the processor, i.e., the instruction is a non-supported instruction. In an optional implementation, for the non-supported instruction, the embodiment of the present application can further compare the opcode of the non-supported instruction with the instruction set extension information of the processor, to determine whether the non-supported instruction is an extended instruction.

[0094] The instruction set extension information of the processor, for example, an instruction set extension table, can define additional extended instructions of the processor, for example, record the operation code, format, instruction function, and tag information of the additional extended instructions of the processor; for example, in the instruction set extension table, instructions have tags to indicate whether the instructions have corresponding execution units, if the tag of the instruction in the corresponding entry of the instruction set extension table indicates that the instruction does not have a corresponding execution unit, it means that the instruction can be recognized by decoding, but there is no corresponding execution unit for subsequent execution. Therefore, by comparing the operation code of the unsupported instruction with the instruction set extension information, and checking the tag of the unsupported instruction in the entry of the instruction set extension information, it can be judged whether the unsupported instruction is an extended instruction.

[0095] It should be noted that the instruction set of the processor (i.e., the standard instruction set of the processor, also referred to as the basic instruction set) is a set of instructions supported by the processor, and the instruction set extension information (for example, the instruction set extension table) is an additional extended instruction defined on the basis of the instruction set of the processor.

[0096] In step S612, if the operation code of the instruction is recorded in the instruction set extension information, and the tag of the instruction set extension information indicates that the instruction does not have a corresponding execution unit, it is confirmed that the instruction is an extended instruction.

[0097] For the instruction belonging to the unsupported instruction, after comparing the operation code of the instruction with the instruction set extension information, if it is found that the operation code of the instruction is recorded in the instruction set extension information, it can be confirmed that the instruction is a legal instruction, that is, the instruction is not a standard supported instruction defined by the instruction set of the processor, but an additional extended instruction of the instruction set extension information; in this case, if the tag of the instruction in the corresponding entry of the instruction set extension information also indicates that the instruction does not have a corresponding execution unit, it is confirmed that the instruction is an extended instruction in the unsupported instruction.

[0098] In step S613, if the operation code of the instruction is not recorded in the instruction set extension information, it is confirmed that the instruction is an illegal instruction.

[0099] For the instruction belonging to the unsupported instruction, after comparing the operation code of the instruction with the instruction set extension information, if it is found that the operation code of the instruction is not recorded in the instruction set extension information, it is confirmed that the instruction is an illegal instruction in the unsupported instruction, that is, the instruction is neither a standard supported instruction defined by the instruction set of the processor, nor an additional extended instruction of the instruction set extension information, at this time the instruction cannot be recognized by decoding and cannot be executed, corresponding to the illegal instruction.

[0100] It should be noted that, Figure 6The optional way of classifying the instruction as an extension instruction and an illegal instruction only when the instruction is a non-supported instruction, any way of determining that the instruction can be recognized by the decoding and has no corresponding execution unit, can be regarded as the way of classifying the instruction as an extension instruction by the embodiment of the application, and any way of determining that the instruction cannot be recognized by the decoding and cannot be processed, can be regarded as the way of classifying the instruction as an illegal instruction by the embodiment of the application. For example, when it is determined that the instruction does not belong to the instruction set of the processor, that is, it is confirmed that the instruction is a non-supported instruction, the embodiment of the application can further perform a legality check on the instruction format of the instruction, and if the format of the instruction is illegal, the instruction is regarded as an illegal instruction.

[0101] Returning to Figure 5 As shown in FIG. 14, if the instruction is an extension instruction, the instruction is decoded to obtain the decoding information of the instruction, and the decoding information of the instruction is stored in the corresponding register in step S514.

[0102] If it is determined that the instruction is a non-supported instruction and is an extension instruction in the non-supported instruction, the instruction can be recognized by the decoding, so that the processor can decode and analyze the instruction in the decoding stage (for example, the decoder in the processor can decode and analyze the extension instruction), to obtain the decoding information of the instruction, that is, the decoding result of the instruction.

[0103] In an optional implementation, the processor can set an extension instruction decoding unit in the decoding stage to support the decoding and analysis of the extension instruction. As an optional implementation, Figure 7 An exemplary diagram of the processing in the decoding stage provided by the embodiment of the application is shown, in combination with Figure 4 and Figure 7 As shown in FIG. 15, the decoding module of the processor is provided with an extension instruction decoding unit in addition to the decoding units of multiple types of supported instructions such as the memory instruction decoding unit, the branch instruction decoding unit, the calculation instruction decoding unit and the vector instruction decoding unit, to support the decoding and analysis of the extension instruction. The extension instruction decoding unit can be regarded as a logic unit set by the processor in the decoding stage (for example, the decoding module) to analyze and recognize the extension instruction. That is, in the decoding stage, if the decoding module checks that the instruction is an extension instruction, the instruction is handed over to the extension instruction decoding unit for further decoding and analysis.

[0104] After decoding the instruction belonging to the extension instruction, the embodiment of the application can obtain the decoding information of the instruction, that is, the specific information converted by the instruction in the decoding and analysis process and understood by the processor, including but not limited to:

[0105] Machine code, binary representation of instructions, is the encoding that can be directly understood and executed by the processor, including operation code (operation part of the instruction, which defines the operation type of the instruction), operand (i.e. the operand required for the operation of the instruction), etc.

[0106] Destination operand, storage location of the execution result of the instruction, the execution result of the instruction can be stored in the register or the memory;

[0107] Source operand, input data required when the instruction is executed;

[0108] Modifier, additional information of the instruction, used to control the execution mode, such as for floating point operation instruction, the modifier is used to specify the precision of the floating point number, the rounding mode, the overflow mode, etc.

[0109] Further, the decoding information of the instruction can be saved to the corresponding register, and different types of decoding information can be saved to different types of registers, such as the instruction can get different types of decoding information such as machine code, destination operand, source operand, modifier after decoding, and these different types of decoding information can be saved to different types of registers respectively; for example, in combination with Figure 7 As shown in the figure, the registers of the decoding module include but are not limited to:

[0110] Machine code register, used to save the machine code of the instruction;

[0111] Destination operand register, used to save the destination operand of the instruction;

[0112] Source operand register, used to save the source operand of the instruction; wherein, the source operand register can be in the form of register group, the number of source operand register groups can be determined based on the maximum number of source operands of the extended instruction, for example, different instructions can require different number of source operands, and the embodiment of the present application can determine the size of the source operand register group based on the maximum number of source operands of the extended instruction; that is, how many source operand register groups are set corresponding to how many source operands are required by the extended instruction;

[0113] Modifier register, used to save the modifier of the instruction; wherein, different instructions can require different modifiers, or some instructions do not require modifiers, so the embodiment of the present application can increase or decrease the modifier register based on the requirements of the extended instruction, or even not set the modifier register.

[0114] It should be noted that the content of the decoding information of the above-mentioned instructions and the corresponding registers are only used as an example. The embodiment of the present application can also support other content in the decoding information of the instruction, which is correspondingly saved in other registers of the decoding module. The embodiment of the present application does not limit the specific content form of the decoding information of the instruction and the corresponding register form.

[0115] Step S515: If the instruction is an illegal instruction, clear the corresponding register.

[0116] If the instruction is determined to be an unsupported instruction and an illegal instruction among the unsupported instructions, the instruction cannot be decoded and recognized and cannot be executed. Therefore, for the illegal instruction, the processor can clear the relevant registers to ensure that no invalid or erroneous information will affect subsequent processing. In an optional implementation, for the illegal instruction, the embodiment of the present application can clear the machine code register, destination operand register, source operand register, modifier register and other related registers.

[0117] Step S516: Generate an illegal instruction exception signal.

[0118] In an embodiment of the present application, if the instruction is judged to be an unsupported instruction, regardless of whether the instruction is an extended instruction among the unsupported instructions or an illegal instruction, it is reported to the system software (such as the operating system) through an illegal instruction exception, so that the system software can respond and process it; that is, if the embodiment of the present application judges that the instruction is an unsupported instruction, an illegal instruction exception can be triggered based on the fact that the instruction is an unsupported instruction of the processor. It should be noted that the difference between extended instructions and illegal instructions in triggering illegal instruction exceptions is that: extended instructions can be decoded and identified but cannot be executed, so the register stores the decoding information of the extended instruction, that is, there is a value in the register; and illegal instructions cannot be decoded and identified and cannot be executed, so the register is cleared, that is, there is no value in the register. Therefore, when the system software is subsequently processed, the system software can distinguish whether the current instruction is an extended instruction among the unsupported instructions or an illegal instruction among the unsupported instructions by whether there is a value in the register, such as whether there is a machine code value in the machine code register.

[0119] As an optional implementation, the decoding module of the processor can generate an illegal instruction exception signal. Furthermore, based on the illegal instruction exception report being performed by the exception handling unit in the processor, the illegal instruction exception signal generated by the decoding module can be transmitted to the exception handling unit in the processor, thereby triggering an illegal instruction exception, that is, the decoding module notifies the exception handling unit of the illegal instruction exception signal, so that the exception handling unit triggers an illegal instruction exception, such as triggering an illegal instruction interrupt. For example, in combination with Figure 7As shown, for the extension instruction, after the decoding module decodes and analyzes the extension instruction and saves the decoding information to the corresponding register, the decoding module can deliver an illegal instruction exception signal to the exception handling unit so as to trigger the illegal instruction exception; for the illegal instruction, after the decoding module empties the corresponding register, the decoding module can deliver an illegal instruction exception signal to the exception handling unit so as to trigger the illegal instruction exception.

[0120] In an optional implementation, Figure 5 The steps S511 to S516 shown can be performed by a decoding module in the processor that implements the decoding stage, Figure 5 The subsequent steps S517 to S518 of the flow shown can be performed by an exception handling unit (for example, an interrupt controller) in the processor.

[0121] Step S517, save the return address of the processor.

[0122] Step S518, based on the illegal instruction exception signal, jump to the exception handling function corresponding to the illegal instruction exception.

[0123] Based on the instruction being an unsupported instruction of the processor, the exception handling unit can obtain the illegal instruction exception signal, for example, the exception handling unit can receive the illegal instruction exception signal delivered by the decoding module to obtain the illegal instruction exception signal. After obtaining the illegal instruction exception signal, the exception handling unit can analyze the illegal instruction exception signal and save the return address of the processor; and based on the illegal instruction exception signal, jump to the exception handling function corresponding to the illegal instruction exception, wherein the exception handling function is deployed in the system software, so that the subsequent flow can be processed by the system software.

[0124] As an optional implementation, based on the processor exception type corresponding to the illegal instruction exception signal being the illegal instruction exception, the exception handling unit jumps to the exception handling function corresponding to the illegal instruction exception pre-defined by the system software, that is, jumps to the exception handling function corresponding to the illegal instruction exception.

[0125] The processor exception type is a classification of an exception event of the processor, including but not limited to an illegal instruction exception, a memory access exception, an arithmetic error exception, a hardware failure exception, and the like. In an optional implementation, the processor encountering an unsupported instruction (not limited to the extension instruction or the illegal instruction referred to in the embodiments of the present application) can belong to the processor exception type of the illegal instruction exception; that is, the extension instruction and the illegal instruction of the embodiments of the present application use the processor exception type of the illegal instruction exception uniformly, that is, the extension instruction and the illegal instruction share the illegal instruction exception signal, so as to indicate that the processor exception type is the illegal instruction exception, and thus the illegal instruction exception signal can not distinguish between the illegal instruction exception caused by the extension instruction or the illegal instruction exception caused by the illegal instruction. As described above, the system software side can distinguish between the unsupported instruction being the extension instruction or the illegal instruction by whether there is a value in the register (for example, whether there is a value of the machine code in the machine code register).

[0126] In other possible implementations, the embodiments of the present application can also support distinguishing between the illegal instruction exception caused by the extension instruction or the illegal instruction exception caused by the illegal instruction through the illegal instruction exception signal, for example, carrying information of the extension instruction or information of the illegal instruction in the illegal instruction exception signal to distinguish between them. Of course, this is only an optional implementation.

[0127] In further optional implementations, different processor exception types can be identified by different exception vector numbers, and correspondingly, the processor exception type of the illegal instruction exception can be identified by an illegal instruction exception vector number (referred to as an illegal instruction exception vector number for short). Thus, after receiving the illegal instruction exception signal, the exception handling unit can determine the illegal instruction exception vector number corresponding to the illegal instruction exception by analyzing the illegal instruction exception signal, for example, through the format and signal information of the illegal instruction exception signal, to confirm the illegal instruction exception vector number corresponding to the illegal instruction exception of the processor exception type pre-associated with the illegal instruction exception signal by the processor. Further, based on the illegal instruction exception vector number, the entry address of the exception handling function of the illegal instruction exception processor exception type is determined, and based on the entry address, the exception handling function of the illegal instruction exception is jumped to, that is, the exception handling function corresponding to the illegal instruction exception is jumped to.

[0128] That is, various processor exception types are respectively pre-defined with corresponding exception vector numbers (for example, numerical numbers) for uniquely identifying the processor exception types and corresponding to the entry addresses of the exception handling functions of the processor exception types. Thus, for the processor exception type of the illegal instruction exception, the exception handling unit can determine the entry address of the exception handling function corresponding to the illegal instruction exception through the illegal instruction exception vector number, so as to jump to the exception handling function corresponding to the illegal instruction exception to continue subsequent processing.

[0129] In a further optional implementation, the processor can set an interrupt vector data structure (e.g., an interrupt vector table) to record the correspondence between the exception vector number of each processor exception type and the entry address of the exception handling function, so that after receiving the illegal instruction exception signal, the exception handling unit can determine the illegal instruction exception vector number, and in the interrupt vector data structure (e.g., the interrupt vector table), find the entry address of the corresponding exception handling function based on the illegal instruction exception vector number, i.e., find the entry address of the exception handling function of the illegal instruction exception, and then jump to the exception handling function of the illegal instruction exception based on the found entry address of the exception handling function.

[0130] In a further optional implementation, when the computer system is initialized, the operating system or the processor can associate and bind the entry address of the exception handling function of each processor exception type with the exception vector number corresponding to the processor exception type, and record it in the interrupt vector data structure (e.g., the interrupt vector table); when the processor occurs a certain processor exception type, the exception processor unit can find the entry address of the corresponding exception handling function through the exception vector number of the processor exception type, so as to jump to the corresponding exception handling program for execution based on the entry address.

[0131] In a further optional implementation, the exception vector number of each processor exception type can be predefined by the processor, and the exception handling function of each processor exception type (including the exception handling function of the illegal instruction exception) can be pre-written in the system software, so as to be predefined in the system software.

[0132] In order to facilitate the processor to continue subsequent execution after the execution of the exception handling function of the illegal instruction exception is completed, the exception handling unit can also save the return address of the processor after receiving the illegal instruction exception signal, which is the address of the processor to return to continue execution after the illegal instruction exception is processed by the corresponding exception handling function. In an optional implementation, the exception handling unit can save the return address of the processor by reading the program counter (PC) and saving the value of the program counter.

[0133] Further, in the optional implementation of jumping to the exception handling function of the illegal instruction exception based on the entry address of the exception handling function of the illegal instruction exception, the exception handling unit can set the program counter (PC) to the entry address of the exception handling function of the illegal instruction exception, so as to realize the jump of the processor to the exception handling function of the illegal instruction exception for execution.

[0134] After jumping to the exception handling function corresponding to the illegal instruction exception, based on the fact that the exception handling function belongs to the function component in the system software, the flow can jump to the system software side for execution. It can be understood that the exception handling function is part of the system software (for example, the operating system) and belongs to the code of the system software (for example, the operating system); the exception handling function, although belonging to the code of the operating system, is still executed by the processor because the final execution depends on the processor hardware. Specifically, the instructions in the exception handling function belong to the code of the operating system and are responsible for handling the exception events of the processor, and the instructions in the exception handling function are different from the instructions of the application program (for example, the AI application program) in the flow shown in the figure, that is, the application program can be understood as a user space program, and the instructions of the application program interact with the hardware through the interface provided by the operating system, while the exception handling function runs in the kernel space of the operating system and is mainly used to respond to hardware events, such as handling the exception events of the processor. Figure 5 The flow shown in the figure can be understood as the flow of the pipeline architecture of the processor in processing the instructions of the application program in the user space; while the flow on the system software side can be understood as the flow of the processor in the kernel space of the operating system, executing the exception handling function, that is, the processor runs the system software through the kernel space, so that the execution of the exception handling function in the system software can be regarded as a process of handling the illegal instruction exception in the kernel space.

[0135] That is, Figure 5 The flow shown in the figure can be understood as the flow of the pipeline architecture of the processor in processing the instructions of the application program in the user space; while the flow on the system software side can be understood as the flow of the processor in the kernel space of the operating system, executing the exception handling function, that is, the processor runs the system software through the kernel space, so that the execution of the exception handling function in the system software can be regarded as a process of handling the illegal instruction exception in the kernel space.

[0136] The following will introduce the subsequent process from the flow on the system software side, which is an optional implementation. Figure 8 An exemplary flowchart of the instruction processing method provided by the embodiments of the present application is shown in the figure. Figure 8 As shown in the figure, the flow on the system software side can include the following steps.

[0137] Step S810: An exception handling function corresponding to the illegal instruction exception is called, and the exception handling function is used to handle the illegal instruction exception triggered by the unsupported instruction of the processor for the instructions of the application program.

[0138] As described above, the unsupported instruction (not limited to the extended instruction or the illegal instruction) of the processor will cause an illegal instruction exception signal in the decoding stage and be transmitted to the exception handling unit, thereby triggering the illegal instruction exception, and the exception handling unit jumps to the exception handling function corresponding to the illegal instruction exception for processing. When the control flow jumps to the exception handling function corresponding to the illegal instruction exception (for example, jumps to the exception handling function corresponding to the illegal instruction exception based on the corresponding entry address), the processor enters the kernel mode, at which time the processor can access the code and resources of the operating system kernel to call the exception handling function corresponding to the illegal instruction exception to handle the illegal instruction exception triggered by the unsupported instruction of the processor for the instructions of the application program.

[0139] Step S811, saving the state of the registers related to the illegal instruction exception by using the exception handling function.

[0140] After the exception handling function is invoked, the state of the registers related to the illegal instruction exception can be saved, so that the processor can be restored to the normal execution state after the exception handling function handles the illegal instruction exception; this process can be regarded as the exception handling function protecting the context. That is, protecting the context refers to saving the current state of the registers, which can correspond to the execution state of the application program, so that the execution of the application program can be restored after the exception handling function handles the illegal instruction exception.

[0141] In an optional implementation, the processing procedure of the exception handling function does not modify all the registers, so the exception handling function can only protect the registers used by the exception handling function when protecting the context, that is, the exception handling function can save the state of the registers related to the illegal instruction exception, instead of saving the state of all the registers. For example, the exception handling function can use the machine code register, the program counter, the state register, etc., and other registers can not be affected in the exception handling process. Therefore, the exception handling function only needs to protect the machine code register, the program counter, the state register, etc., which will be modified by the exception handling function, so as to save and back up the state of the machine code register, the program counter, the state register, etc., to reduce the overhead of saving and restoring the context.

[0142] In an optional implementation, the exception handling function can push the state of the registers related to the illegal instruction exception into the stack or save it to a specific memory area, to save the state of the related registers.

[0143] Step S812, determining whether the register contains the decoding information of the instruction by using the exception handling function, if yes, executing step S813, and if no, executing step S815.

[0144] As described above, when the instruction belongs to the extended instruction, the instruction can be recognized by decoding in the decoding stage, and the decoding information of the instruction can exist in the register; when the instruction belongs to the illegal instruction, the register can be emptied, so that the decoding information of the instruction does not exist in the register; therefore, the embodiment of the present application can determine whether the register contains the decoding information of the instruction by using the exception handling function, to confirm whether the unsupported instruction triggering the illegal instruction exception encountered by the processor is the extended instruction or the illegal instruction.

[0145] As an optional implementation, the operation code in the machine code can define the operation type of the instruction, so as to indicate the implementation manner of the instruction, and then the embodiment of the present application can determine whether the machine code register has a value by using the exception handling function, so as to determine whether the register has the decoding information of the instruction.

[0146] In step S813, it is determined that the instruction is an extended instruction in the unsupported instruction, and the instruction is executed by software simulation based on the decoding information of the instruction, so as to obtain the execution result of the software simulation as the execution result of the instruction.

[0147] If it is determined that the decoding information of the instruction exists in the register (for example, it is determined that the machine code register has a value, that is, it is determined that the machine code register has valid machine code), the exception handling function can determine that the unsupported instruction triggering the illegal instruction exception is an extended instruction; for the extended instruction, the exception handling function can execute the instruction by software simulation based on the decoding information of the instruction decoded and recognized by the processor in the decoding stage, so as to obtain the execution result of the software simulation of the instruction as the execution result of the instruction.

[0148] That is, in the case of the extended instruction, the decoding information of the instruction has already existed in the register, such as that the machine code of the instruction has been saved in the machine code register, the destination operand of the instruction has been saved in the destination operand register, the source operand of the instruction has been saved in the source operand register, and the modifier of the instruction has been saved in the modifier register. The decoding information of the instruction saved in these registers can be reused by the exception handling function, so as to execute the instruction by software simulation to obtain the execution result of the software simulation, and then the execution result of the software simulation can be used as the execution result of the instruction.

[0149] In an optional implementation, the software simulation referred to by the embodiment of the present application refers to simulating the operation of the instruction by combining the basic instructions, that is, for the extended instruction, the operation of the extended instruction can be implemented by combining multiple basic instructions. Specifically, the extended instruction cannot be directly executed by the processor because the processor does not have a corresponding execution unit for the extended instruction, but the operation of the extended instruction can be implemented by combining the existing basic instructions (such as multiplication, addition, shift, integer operation, etc.) through software simulation, that is, in the case that the hardware of the processor does not support the extended instruction, the conversion processing mode of software simulation is adopted.

[0150] For example, a MAD (Multiply Add) instruction, which can be a combination of multiplication and addition, can be implemented by software emulating the underlying multiplication and addition instructions if the processor can decode the MAD instruction but does not have an execution unit to support the MAD instruction (e.g., the processor does not have a dedicated MAD unit). For example, a floating point arithmetic operation (addition, subtraction, multiplication, division) can be emulated by conversion to integer arithmetic if the processor can decode the floating point arithmetic operation instruction but does not have a corresponding execution unit. For example, a floating point addition can be emulated using a combination of integer addition instructions and shift, rounding, etc. instructions, which can handle the mantissa and exponent portions of the floating point number.

[0151] In an optional implementation, an embodiment of the present application can determine the operation type of the instruction based on the decoding information of the instruction, and determine the instruction implementation program according to the operation type of the instruction, which can include a combination of underlying instructions corresponding to the operation type of the instruction, so as to implement a software emulated process by the instruction implementation program. The specific description and examples of the combination of underlying instructions of the instruction implementation program can refer to the foregoing description, which will not be expanded here. Further, the operation information of the instruction is executed based on the combination of underlying instructions included in the instruction implementation program and the operation information of the instruction in the decoding information of the instruction, to obtain a software emulated execution result as the execution result of the instruction.

[0152] Specifically, the operation type of the instruction can be indicated by the operation code of the instruction, which can be regarded as a part of the machine code, so that the operation code of the instruction can be read from the machine code register. The operation information of the instruction can include the source operand, modifier, etc. of the instruction, wherein the source operand of the instruction can be read from the source operand register, and the modifier of the instruction can be read from the modifier register. Thus, when the machine code register is confirmed to have a value by the exception handling function, the operation code of the instruction in the machine code register can be read, and the instruction implementation program corresponding to the operation type indicated by the operation code is selected based on the operation code of the instruction. Further, the source operand register of the instruction is read by the instruction implementation program to obtain the source operand of the instruction, and the modifier register of the instruction is read by the instruction implementation program to obtain the modifier of the instruction. The operation information of the instruction, such as the source operand and the modifier, is executed by the combination of underlying instructions included in the instruction implementation program to obtain a software emulated execution result. Further, the destination operand register of the instruction is read by the instruction implementation program to obtain the destination operand of the instruction, and the software emulated execution result is written into the destination operand to implement the software emulated execution result as the execution result of the instruction.

[0153] Step S814, the saved state of the register related to the illegal instruction exception is recovered, and the exception handling function is exited.

[0154] After the extended instruction is processed in the software simulation mode and the execution result of the instruction is obtained, the embodiment of the present application can restore the scene by using the exception handling function, that is, the state of the register saved in step S811 is recovered, so that the processor can return to the state at the time when the illegal instruction exception occurs. In an optional implementation, the exception handling function can restore the value of the register, the value of the program counter and the state of the register, so that the processor can continue to execute the application program from the position where the exception occurs, instead of executing the next instruction in the exception handling program.

[0155] That is, the protection scene saves the register state of the application program corresponding to the time when the illegal instruction exception occurs, and the recovery scene restores the register state to the register, so as to ensure the continuous execution of the application program, for example, after the exception handling function is exited, the processor (specifically, the processor core in the processor) can continue to perform the pipeline stages such as instruction fetching, decoding and execution on the next instruction of the application program.

[0156] Further, after the scene is restored by using the exception handling function, the exception handling function can be exited, so that the processor jumps back to the code position at the time when the exception occurs to continue execution, for example, after the value of the program counter is restored, the value of the program counter restored is the instruction address (that is, the return address) of the processor at the time when the illegal instruction exception occurs, so that the value of the program counter can jump back to the instruction address of the processor at the time when the illegal instruction exception occurs to continue the execution of the application program.

[0157] It can be seen that for the extended instruction, the processor internally decodes and analyzes the extended instruction in advance, for example, the decoding stage can set the extended instruction decoding unit to decode and analyze the extended instruction, so that the processor internally saves the decoding information of the extended instruction; further, the exception handling function can reuse the decoding information of the extended instruction which has been saved in the processor internally, to implement the software simulation of the extended instruction, so that the software simulation can avoid the process of reacquiring the instruction from the memory and performing software decoding, thereby reducing the memory access and software decoding delay and improving the processing efficiency of the extended instruction as an unsupported instruction of the processor. It should be noted that if the decoding information of the extended instruction is not saved in the processor in advance, the exception handling function also needs to reacquire the instruction from the memory and perform software decoding before performing software simulation execution on the extended instruction, and then the software simulation execution is performed based on the result of software decoding, so that the embodiment of the present application can reduce the memory access and software decoding delay of the exception handling function when processing the extended instruction.

[0158] That is, if the instruction is an illegal instruction in the unsupported instruction, the processor can decode the instruction to obtain the decoding information of the instruction, and save the decoding information of the instruction to the corresponding register; and then trigger an illegal instruction exception, so that the exception processing function corresponding to the illegal instruction exception performs software simulation based on the decoding information of the instruction to obtain the execution result of the instruction. That is, the embodiment of the present application optimizes the processing mode of the extension instruction as an unsupported instruction by combining the software simulation of the exception processing function with the early decoding of the extension instruction by the processor hardware, which can improve the processing efficiency of the extension instruction as an unsupported instruction; at the same time, the co-processor is avoided to participate in the processing of the unsupported instruction, which reduces the hardware complexity and hardware cost; therefore, the embodiment of the present application can improve the processing efficiency of the extension instruction as an unsupported instruction, and reduce the hardware cost, and realize efficient processing of the unsupported instruction and control of the hardware cost.

[0159] In step S815, it is determined that the instruction is an illegal instruction in the unsupported instruction, an illegal instruction exception is reported to the application program, or the instruction is read from the memory, software decoding is performed on the instruction, and then software simulation is performed.

[0160] If it is determined that the decoding information of the instruction does not exist in the register (for example, it is determined that the value does not exist in the machine code register), the embodiment of the present application can determine that the unsupported instruction triggering the illegal instruction exception is an illegal instruction, that is, the current instruction of the processor is an illegal instruction in the unsupported instruction. For the case that the instruction is an illegal instruction, the exception processing function can have two processing modes:

[0161] I. report the illegal instruction exception to the application program, so that the user performs subsequent processing;

[0162] II. read the instruction from the memory, perform software decoding on the instruction, and then perform software simulation; for example, the exception processing function can obtain the address of the instruction (which is an illegal instruction at this time) from the instruction pointer register, read the instruction from the memory based on the address of the instruction, and then parse the operation code and the operand of the instruction by the basic operation instruction in the software decoding mode; thereby, according to the operation code of the instruction, select an instruction implementation program corresponding to the operation type indicated by the operation code, execute the operation on the operation information (such as the source operand) of the instruction by using the combination of the basic instructions included in the instruction implementation program, and obtain the execution result of the software simulation as the execution result of the instruction.

[0163] That is, the second processing mode in the above illegal instruction case has the process of re-reading the instruction from the memory and software decoding compared with the extension instruction case, because the register of the illegal instruction needs to be emptied.

[0164] It should be noted that the decoding of the processor in the decoding stage (for example, the decoding of the decoder) refers to the decoding process at the hardware level, such as the decoder parsing the meaning of the instruction through the operation code and operand of the instruction, and then generating the corresponding control signal to drive the hardware to execute. The software decoding refers to the decoding and parsing of the instruction by using the software program when the processor hardware cannot directly identify the illegal instruction, instead of relying on the special decoding unit of the hardware; specifically, the software decoding can extract the key information (such as the operation code and the operand) in the instruction by executing some basic operation instructions (such as addition, bit shift, etc.), without modifying the hardware structure or adding a special hardware decoding unit.

[0165] Further, the second processing mode in the above illegal instruction case needs to restore the saved state of the register related to the illegal instruction exception after processing, and exit the exception handling function, so that the processor returns to the instruction address when the illegal instruction exception occurs, and continues the execution of the application program.

[0166] The embodiment of the application optimizes the processing of the case where the instruction is an extended instruction, and avoids the process of obtaining the instruction from the memory and software decoding by the processor hardware decoding the extended instruction in advance, so that the processing process of the extended instruction in the exception handling function is accelerated, not only reducing the memory access, but also improving the efficiency of the processor processing the extended instruction and reducing the delay. At the same time, compared with increasing a special coprocessor, the embodiment of the application uses the flexible implementation of the processor hardware decoding (i.e., decoding) of the extended instruction and the software simulation of the exception handling function to avoid the problems of high cost, high hardware complexity and low flexibility in processing the unsupported instruction. Therefore, the embodiment of the application combines the processor hardware and the system software (specifically, the exception handling function in the system software) to ensure flexibility, improve the processing efficiency of the extended instruction as the unsupported instruction, reduce the hardware cost and complexity, and adapt to different architectures and instruction sets.

[0167] The instruction processing device provided by the embodiment of the application is introduced below, and the description below can be mutually corresponding with the description above.

[0168] As an optional implementation, the embodiment of the application provides an instruction processing device from the perspective of the processor hardware. Figure 9A An example of the instruction processing device provided by the embodiment of the application is shown in a block diagram, which can be applied to the processor and can be regarded as a hardware logic device in the processor. Referring to Figure 9A The instruction processing device can include:

[0169] The instruction fetching module 910 is configured to obtain the instruction of the application program.

[0170] The decoding module 911 is configured to determine whether the instruction is a supported instruction of the processor; if the instruction is an unsupported instruction of the processor, determine a type of the instruction in the unsupported instruction; and if the instruction is an extended instruction in the unsupported instruction, decode the instruction to obtain decoding information of the instruction, and save the decoding information of the instruction to a corresponding register; the extended instruction is an instruction that can be decoded and recognized by the processor but cannot be executed.

[0171] The exception processing unit 912 is configured to trigger an illegal instruction exception based on the instruction being an unsupported instruction of the processor, so that an exception processing function corresponding to the illegal instruction exception performs software simulation execution based on the decoded decoding information of the extended instruction.

[0172] In an optional implementation, the decoding module 911 is further configured to:

[0173] If the instruction is an illegal instruction in the unsupported instruction, the corresponding register is emptied; the illegal instruction is an instruction that cannot be decoded and recognized by the processor and cannot be executed.

[0174] In an optional implementation, as shown in Figure 9A The decoding module 911 can be provided with an extended instruction decoding unit 9111, which is a logic unit provided by the decoding module for parsing and recognizing the extended instruction; the extended instruction decoding unit 9111 is specifically configured to decode the instruction to obtain the decoding information of the instruction if the instruction is an extended instruction in the unsupported instruction.

[0175] In an optional implementation, the decoding module 911 is further configured to generate an illegal instruction exception signal based on the instruction being an unsupported instruction of the processor, and deliver the illegal instruction exception signal to the exception processing unit 912.

[0176] The exception processing unit 912 is configured to trigger an illegal instruction exception based on the instruction being an unsupported instruction of the processor, and the triggering of the illegal instruction exception includes:

[0177] Obtaining an illegal instruction exception signal;

[0178] Based on the illegal instruction exception signal, jumping to an exception processing function corresponding to the illegal instruction exception.

[0179] In an optional implementation, the extended instruction and the illegal instruction can share the illegal instruction exception signal to indicate that the processor exception type is an illegal instruction exception.

[0180] In an optional implementation, the exception processing unit 912 is configured to jump to an exception processing function corresponding to the illegal instruction exception based on the illegal instruction exception signal, and the jumping to the exception processing function corresponding to the illegal instruction exception includes:

[0181] The illegal instruction exception signal is analyzed, and an illegal instruction exception vector number is determined, the illegal instruction exception vector number being used to uniquely identify that the processor exception type is an illegal instruction exception;

[0182] Based on the illegal instruction exception vector number, an entry address of an exception handling function corresponding to the illegal instruction exception is determined;

[0183] Based on the entry address, the illegal instruction exception corresponding exception handling function is jumped to.

[0184] In an optional implementation, the exception handling unit 912 is configured to determine, based on the illegal instruction exception vector number, an entry address of an exception handling function corresponding to the illegal instruction exception, including:

[0185] In the interrupt vector data structure, the entry address of the corresponding exception handling function is found based on the illegal instruction exception vector number; wherein the interrupt vector data structure records the corresponding relationship between the exception vector number of various processor exception types and the entry address of the exception handling function, and the illegal instruction exception belongs to a processor exception type.

[0186] In an optional implementation, the exception handling unit 912 is further configured to, before jumping, based on the illegal instruction exception signal, to the illegal instruction exception corresponding exception handling function, save a return address of the processor, the return address being an address at which the processor returns to continue execution after the illegal instruction exception is processed by the exception handling function.

[0187] In an optional implementation, the decoding module 911 is configured to determine whether the instruction is a supported instruction of the processor, including: determining whether the instruction belongs to an instruction set of the processor, if yes, the instruction is a supported instruction of the processor, and if no, the instruction is an unsupported instruction of the processor, the instruction set defining the supported instructions of the processor.

[0188] In an optional implementation, the decoding module 911 is configured to determine the type of the instruction in the unsupported instruction, including: comparing an operation code of the instruction with instruction set extension information of the processor, wherein the instruction set extension information defines additional instructions extended by the processor; if the operation code of the instruction is recorded in the instruction set extension information, and a flag of the instruction set extension information indicates that the instruction has no corresponding execution unit, it is determined that the instruction is an extended instruction; if the operation code of the instruction is not recorded in the instruction set extension information, or the format of the instruction is checked to be illegal, it is determined that the instruction is an illegal instruction.

[0189] In an optional implementation, the decoding information of the instruction includes: machine code, destination operand, source operand, and modifier of the instruction; and the decoding module 911 is configured to save the decoding information of the instruction to the corresponding register, including:

[0190] saving the machine code of the instruction to a machine code register, saving the destination operand to a destination operand register, saving the source operand to a source operand register, and saving the modifier to a modifier register.

[0191] Further, the embodiment of the present application further provides a processor comprising the instruction processing apparatus provided by the embodiment of the present application.

[0192] As an optional implementation, the embodiment of the present application provides an instruction processing apparatus from the perspective of system software. Figure 9B An exemplary block diagram of another instruction processing apparatus provided by the embodiment of the present application is shown, which can be applied to system software and can be regarded as a software functional apparatus in system software.

[0193] With reference to Figure 9B The instruction processing apparatus can comprise:

[0194] The calling entry module 920 is configured to call an exception handling function corresponding to an illegal instruction exception, the exception handling function is deployed in the system software, and the exception handling function is configured to handle the illegal instruction exception triggered by the instruction of the application program being an unsupported instruction of the processor.

[0195] The exception handling function module 921 is configured to determine whether the register contains the decoding information of the instruction; if the register contains the decoding information of the instruction, it is determined that the instruction is an extended instruction in the unsupported instruction, the instruction is executed by software simulation based on the decoding information of the instruction, and an execution result of the software simulation is obtained as an execution result of the instruction; wherein the extended instruction is an instruction that can be decoded and recognized by the processor but cannot be executed.

[0196] In an optional implementation, the software simulation simulates the instruction operation through a combination of basic instructions; the exception handling function module 921 is configured to execute the instruction by software simulation based on the decoding information of the instruction, and obtain an execution result of the software simulation as an execution result of the instruction, comprising:

[0197] determining an operation type of the instruction based on the decoding information of the instruction;

[0198] determining an instruction implementation program according to the operation type of the instruction, the instruction implementation program comprising a combination of basic instructions corresponding to the operation type of the instruction;

[0199] performing an operation on the operation information of the instruction based on the combination of basic instructions included in the instruction implementation program and the operation information of the instruction in the decoding information of the instruction, to obtain an execution result of the software simulation as the execution result of the instruction.

[0200] In an optional implementation, the exception handling function module 921 is configured to determine the operation type of the instruction based on the decoding information of the instruction by reading the operation code of the instruction in the machine code register.

[0201] The exception handling function module 921 is configured to determine the instruction implementation program according to the operation type of the instruction by selecting the instruction implementation program corresponding to the operation type indicated by the operation code of the instruction based on the operation code of the instruction.

[0202] The exception handling function module 921 is configured to execute the operation on the operation information of the instruction based on the combination of the basic instructions included in the instruction implementation program and the operation information of the instruction in the decoding information of the instruction to obtain the execution result of the software simulation as the execution result of the instruction, including: reading the source operand of the instruction in the source operand register and the modifier of the instruction in the modifier register by using the instruction implementation program; and executing the operation on the source operand of the instruction and the modifier by using the combination of the basic instructions included in the instruction implementation program to obtain the execution result of the software simulation as the execution result of the instruction.

[0203] In an optional implementation, the exception handling function module 921 is further configured to read the destination operand of the instruction in the destination operand register by using the instruction implementation program; and the execution result of the software simulation is written into the destination operand as the execution result of the instruction.

[0204] In an optional implementation, the exception handling function module 921 is further configured to save the state of the register related to the illegal instruction exception by using the exception handling function before determining whether the register exists the decoding information of the instruction; and after obtaining the execution result of the software simulation as the execution result of the instruction, the saved state of the register related to the illegal instruction exception is restored, and the exception handling function is exited so that the processor returns to the state at the time when the illegal instruction exception occurs.

[0205] In an optional implementation, the exception handling function module 921 is further configured to determine that the instruction is an illegal instruction in the unsupported instruction if the register does not exist the decoding information of the instruction, report the illegal instruction exception to the application program, or read the instruction from the memory, perform software decoding on the instruction, and then perform software simulation execution; wherein the illegal instruction is an instruction that cannot be decoded and recognized by the processor and cannot be executed.

[0206] In an optional implementation, the exception handling function module 921 is configured to determine whether the register exists the decoding information of the instruction by determining whether the machine code register exists the value.

[0207] Further, the embodiment of the present application further provides a computer device, such as a terminal device or a server device, comprising a memory and a processor, the memory stores computer system instructions (such as instructions in system software), and the processor invokes the computer system instructions to execute the instruction processing method on the system software side provided by the embodiment of the present application.

[0208] Further, the embodiment of the present application further provides a storage medium, which stores computer system instructions (such as instructions in system software), and the computer system instructions, when executed (such as executed by a processor), implement the instruction processing method on the system software side provided by the embodiment of the present application.

[0209] Further, the embodiment of the present application further provides a computer system program, which comprises computer system instructions (such as instructions in system software), and the computer system instructions, when executed (such as executed by a processor), implement the instruction processing method on the system software side provided by the embodiment of the present application.

[0210] Further, the embodiment of the present application further provides a computer device, such as a terminal device or a server device, comprising a processor and system software of the computer device, the processor is the processor provided by the embodiment of the present application, and the system software of the computer device comprises the instruction processing apparatus on the system software side provided by the embodiment of the present application.

[0211] The above describes the multiple embodiment schemes provided by the embodiment of the present application, and each optional mode introduced by each embodiment scheme can be combined, cross-referenced in the case of no conflict, thereby extending multiple possible embodiment schemes, which can be considered as the embodiment schemes disclosed and published by the embodiment of the present application.

[0212] Although the embodiment of the present application discloses as above, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be limited by the scope defined by the claims.

Claims

1. A method for processing an instruction, characterized in that: Applied to a processor, the method includes: Get instructions for the application; Determining whether the instruction is a supported instruction of the processor; If the instruction is an unsupported instruction of the processor, determining a type of the instruction among the unsupported instructions; If the instruction is an extended instruction among the unsupported instructions, the instruction is decoded to obtain decoding information of the instruction, and the decoding information of the instruction is saved in a corresponding register; wherein the extended instruction is an instruction that the processor can decode and recognize but cannot execute; Furthermore, based on the fact that the instruction is an unsupported instruction of the processor, an illegal instruction exception is triggered, so that an exception handling function corresponding to the illegal instruction exception performs software simulation execution based on the decoded decoding information of the extended instruction.

2. The method according to claim 1, characterized in that The method further comprises: If the instruction is an illegal instruction among the unsupported instructions, the corresponding register is cleared; wherein the illegal instruction is an instruction that the processor cannot decode, identify, and execute.

3. The method according to claim 1, characterized in that If the instruction is an extended instruction among the unsupported instructions, decoding the instruction to obtain decoding information of the instruction includes: If the instruction is an extended instruction among the unsupported instructions, the instruction is decoded using an extended instruction decoding unit set in the decoding module of the processor to obtain decoding information of the instruction; wherein, the extended instruction decoding unit is a logic unit set in the decoding module of the processor for parsing and identifying extended instructions.

4. The method according to claim 2, characterized in that The triggering of the illegal instruction exception based on the instruction being an unsupported instruction by the processor includes: Based on the fact that the instruction is an unsupported instruction by the processor, an illegal instruction exception signal is obtained; wherein the extended instruction and the illegal instruction share the illegal instruction exception signal to indicate that the processor exception type is an illegal instruction exception; Based on the illegal instruction exception signal, jump to the exception handling function corresponding to the illegal instruction exception.

5. The method according to claim 4, characterized in that The step of jumping to an exception handling function corresponding to the illegal instruction exception based on the illegal instruction exception signal includes: Parsing the illegal instruction exception signal to determine an illegal instruction exception vector number, wherein the illegal instruction exception vector number is used to uniquely identify the processor exception type as an illegal instruction exception; Based on the illegal instruction exception vector number, determining an entry address of an exception handling function corresponding to the illegal instruction exception; Based on the entry address, jump to the exception handling function corresponding to the illegal instruction exception.

6. The method according to claim 5, characterized in that Determining the entry address of the exception handling function corresponding to the illegal instruction exception based on the illegal instruction exception vector number includes: In an interrupt vector data structure, an entry address of a corresponding exception handling function is searched based on an illegal instruction exception vector number; wherein the interrupt vector data structure records the correspondence between the exception vector numbers of various processor exception types and the entry addresses of the exception handling functions, and the illegal instruction exception belongs to a processor exception type.

7. The method according to claim 4, characterized in that Before jumping to an exception handling function corresponding to the illegal instruction exception based on the illegal instruction exception signal, the method further includes: The return address of the processor is saved, where the return address is the address to which the processor returns to continue execution after the illegal instruction exception is processed by the exception handling function.

8. The method according to claim 2, characterized in that Determining whether the instruction is a supported instruction of the processor includes: Determining whether the instruction belongs to an instruction set of the processor; if so, the instruction is a supported instruction of the processor; if not, the instruction is an unsupported instruction of the processor, and the instruction set defines supported instructions of the processor; Determining the type of the instruction among the unsupported instructions includes: Comparing the operation code of the instruction with instruction set extension information of the processor, wherein the instruction set extension information defines additional extended instructions of the processor; If the operation code of the instruction is recorded in the instruction set extension information, and the tag of the instruction in the instruction set extension information indicates that the instruction has no corresponding execution unit, then determining that the instruction is an extended instruction; If the operation code of the instruction is not recorded in the instruction set extension information, or if the format of the instruction is found to be illegal, the instruction is determined to be an illegal instruction.

9. The method according to claim 1, characterized in that The decoding information of the instruction includes: the machine code, destination operand, source operand and modifier of the instruction; Saving the decoding information of the instruction to the corresponding register includes: The machine code of the instruction is saved in a machine code register, the destination operand is saved in a destination operand register, the source operand is saved in a source operand register, and the modifier is saved in a modifier register.

10. A method for processing an instruction, characterized in that: Applied to system software, wherein a processor runs the system software through kernel space; the method includes: Calling an exception handling function corresponding to an illegal instruction exception, wherein the exception handling function is deployed in the system software and is used to handle an illegal instruction exception triggered by an instruction of the application program being an instruction not supported by the processor; Using the exception handling function to determine whether the register contains the decoding information of the instruction; If the register contains decoding information of the instruction, it is determined that the instruction is an extended instruction among the unsupported instructions. Based on the decoding information of the instruction, the instruction is executed by software simulation to obtain an execution result of the software simulation as the execution result of the instruction; wherein, the extended instruction is an instruction that the processor can decode and identify but cannot execute.

11. The method according to claim 10, characterized in that The software simulation simulates instruction operations by combining basic instructions; the software simulation executes the instructions based on the decoding information of the instructions to obtain the execution results of the software simulation, which include: determining an operation type of the instruction based on decoding information of the instruction; determining an instruction implementation program according to the operation type of the instruction, wherein the instruction implementation program includes a combination of basic instructions corresponding to the operation type of the instruction; Based on the combination of basic instructions included in the instruction implementation program and the operation information of the instruction in the decoding information of the instruction, an operation is performed on the operation information of the instruction to obtain a software simulated execution result as the execution result of the instruction.

12. The method according to claim 11, characterized in that Determining the operation type of the instruction based on the decoding information of the instruction includes: Read the opcode of the instruction in the machine code register; Determining the instruction implementation program according to the operation type of the instruction includes: Based on the operation code of the instruction, selecting an instruction implementation program corresponding to the operation type indicated by the operation code; The combination of basic instructions included in the instruction implementation program and the operation information of the instruction in the decoding information of the instruction are performed on the operation information of the instruction to obtain the execution result of the software simulation, which includes: Using the instruction to implement the program to read the source operand of the instruction in the source operand register and the modifier of the instruction in the modifier register; The instruction implementation program includes a combination of basic instructions, performs operations on the source operands and modifiers of the instructions, and obtains a software-simulated execution result as the execution result of the instruction.

13. The method according to claim 12, characterized in that Also includes: Using the instruction to implement the program to read the destination operand of the instruction in the destination operand register; The execution result of the software simulation is written into the destination operand as the execution result of the instruction.

14. The method according to claim 10, characterized in that Before using the exception handling function to determine whether the register contains the decoding information of the instruction, the method further includes: Use the exception handling function to save the state of registers related to the illegal instruction exception; After obtaining the execution result of the software simulation as the execution result of the instruction, the method further includes: The saved state of the registers related to the illegal instruction exception is restored, and the exception handling function is exited so that the processor returns to the state when the illegal instruction exception occurs.

15. The method according to claim 10, characterized in that The method further comprises: If the register does not contain decoding information of the instruction, the instruction is determined to be an illegal instruction among the unsupported instructions, and the illegal instruction exception is reported to the application, or the instruction is read from the memory, software-decoded and then executed in software simulation; wherein the illegal instruction is an instruction that the processor cannot decode, identify and execute.

16. An instruction processing device, characterized in that: Applied to a processor, the instruction processing device includes: Instruction fetch module, used to obtain instructions from application programs; a decoding module, configured to determine whether the instruction is a supported instruction of the processor; if the instruction is an unsupported instruction of the processor, determine the type of the instruction among the unsupported instructions; if the instruction is an extended instruction among the unsupported instructions, decode the instruction to obtain decoding information of the instruction, and save the decoding information of the instruction to a corresponding register; wherein the extended instruction is an instruction that the processor can decode and recognize but cannot execute; The exception handling unit is used to trigger an illegal instruction exception based on the fact that the instruction is an unsupported instruction of the processor, so that the exception handling function corresponding to the illegal instruction exception performs software simulation execution based on the decoded decoding information of the extended instruction.

17. An instruction processing device, characterized in that: Applied to system software, wherein the processor runs the system software through kernel space; the instruction processing device includes: A calling entry module is used to call an exception handling function corresponding to an illegal instruction exception, wherein the exception handling function is deployed in the system software and is used to handle an illegal instruction exception triggered by an instruction of the application program being an instruction not supported by the processor; An exception handling function module is used to determine whether the register contains decoding information for the instruction; if the register contains decoding information for the instruction, the instruction is determined to be an extended instruction among unsupported instructions, and based on the decoding information for the instruction, the instruction is software simulated and executed to obtain a software simulated execution result as the execution result of the instruction; wherein the extended instruction is an instruction that the processor can decode and identify but cannot execute.

18. A processor, characterized in that: The apparatus comprises the instruction processing device as claimed in claim 16.

19. A computer device, characterized in that: The system comprises a memory and a processor, wherein the memory stores computer system instructions, and the processor calls the computer system instructions to execute the instruction processing method according to any one of claims 10 to 15.

20. A storage medium, characterized in that The storage medium stores computer system instructions, and when the computer system instructions are executed, the instruction processing method according to any one of claims 10 to 15 is implemented.

21. A computer system program, characterized in that The method comprises computer system instructions, which, when executed, implement the instruction processing method according to any one of claims 10 to 15.

22. A computer device, characterized in that: A system software comprising a processor and a computer device; the processor is the processor as claimed in claim 18, and the system software comprises the instruction processing device as claimed in claim 17.

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