A network chip instruction processing method, network chip, electronic equipment and device

Abstract

The embodiment of the present application provides a network chip instruction processing method, a network chip, an electronic device and a device, which relates to the field of chip technology and is applied to a network chip. The method includes: obtaining an instruction, the operation type indicated by the instruction is: the first type, the second type or the third type, the first type indicates: performing data calculation on the operand, the second type indicates: moving the storage location of the operand, the third type indicates: jumping the memory access location according to the value of the operand, and the instruction contains the identifier of the register where the operand is located, the source address of the operand in the register, and the main operation code indicating the operation type indicated by the instruction; parsing the instruction, reading the operand from the register; processing the operand through the data processing unit of the network chip to obtain the target processing result. The scheme provided by the embodiment of the present application can control the network chip to process the message through the instructions in the expanded instruction set.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a network chip instruction processing method, a network chip, an electronic device and a device. Background Art

[0002] With the development of information technology, people's requirements for high performance and low power consumption of chips are becoming increasingly stringent. The core of the chip is the instruction set.

[0003] Instruction sets can be divided into CISC (Complex Instruction Set Computing) and RISC (Reduced Instruction Set Computing). RISC implements CISC's complex instructions using a combination of simple instructions, and achieves more complex functions through a combination of software and hardware, reducing the difficulty of the circuit and thus reducing chip power consumption and area.

[0004] The key indicator of network chip performance is the message processing capability, which is mainly divided into three planes: control plane, data plane, and monitoring plane. In the data plane, the processing of messages is controlled by instructions, and the instructions need to carry enough information for calculation to realize complex business processes. However, the existing RISC instruction sets are represented by ARM. Although they have relatively mature functions, they are all closed-source instruction sets. The RISC-V instruction set is an open-source instruction set that can solve the closed-source problem of the RISC instruction set. However, the functions that the RISC-V instruction set can realize are relatively simple and are not fully adapted to network chips. The existing RISC-V instruction set cannot control the data plane in the network chip to perform a series of complex operations on the message, which seriously limits the performance of the network chip. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a network chip instruction processing method, a network chip, an electronic device and a device, so as to control the network chip to process messages through instructions in an extended instruction set. The specific technical solution is as follows:

[0006] In a first aspect, an embodiment of the present application provides a network chip instruction processing method, which is applied to a network chip, and the method includes:

[0007] Obtain an instruction, wherein the operation type indicated by the instruction is: a first type, a second type, or a third type, the first type indicates: performing data calculation on an operand, the second type indicates: moving a storage location of an operand, and the third type indicates: jumping a memory access location according to a value of the operand, and the instruction includes an identifier of a register where the operand is located, a source address of the operand in the register, and a primary operation code indicating the operation type indicated by the instruction;

[0008] Parsing the instruction, reading an operand from a source address in a register indicated by the instruction, and determining a target operation type indicated by the instruction according to an operation code included in the instruction;

[0009] The operand is processed by a data processing unit corresponding to the target operation type in the network chip to obtain a target processing result.

[0010] In one embodiment of the present application, the instruction indicating the first type includes: a first main operation code, a first sub-operation code, a second sub-operation code, an operand length, a first source address of the first operand, a second source address of the second operand, an identifier of the first register, and an identifier of the second register;

[0011] The first major operation code indicates that the operation type indicated by the instruction is the first type;

[0012] The first sub-operation code indicates that the data calculation performed on the operand is a logic calculation, a shift calculation or an addition or subtraction calculation;

[0013] In the case where the first sub-operation code indicates performing a logic calculation on an operand, the second sub-operation code indicates performing one of AND, OR, NOT, and XOR calculations;

[0014] In the case where the first sub-operation code indicates that a shift calculation is performed on an operand, the second sub-operation code indicates that a logical left shift, a logical right shift or a circular shift is performed;

[0015] In the case where the first sub-operation code indicates performing addition or subtraction calculations on operands, the second sub-operation code indicates performing addition or subtraction calculations;

[0016] The first register is a register where the first operand is located and a register where the calculated result is to be stored, and the second register is a register where the second operand is located.

[0017] In one embodiment of the present application, the instruction indicating the second type includes: a second main opcode, a third sub-opcode, a source address where the operand was originally located, a destination address to which the operand is to be moved, an identifier of a source register where the operand was originally located, and an identifier of a destination register to which the operand is to be moved, wherein the third sub-opcode indicates: a discrete bit number of the operand to be moved;

[0018] The second major operation code indicates that the operation type indicated by the instruction is the second type.

[0019] In one embodiment of the present application, when the operation type indicated by the instruction is the second type and the total number of discrete bits of the operand to be moved is greater than 1 bit, the instruction includes a first instruction indicating reading the operand and a second instruction indicating writing the operand;

[0020] The first instruction includes: an identifier of a source register where each operand originally resides, a source address of each operand in the source register, a third sub-operation code, and a second main operation code;

[0021] The second instruction includes: an identifier of a destination register to which each operand is to be moved, a destination address in the destination register to which each operand is to be moved, a third sub-operation code, and a second main operation code;

[0022] The second major operation code indicates that the operation type indicated by the instruction is the second type.

[0023] In one embodiment of the present application, the third type of instruction is indicated to include: a source address of an operand, an identifier of a source register where the operand is located, an offset of an access location to be jumped to in a memory, a fourth sub-operation code, and a third main operation code;

[0024] The fourth sub-operation code is used to indicate a target value, and when the value of the operand is the target value, a memory access position is jumped;

[0025] The third major operation code indicates that the operation type indicated by the instruction is the third type.

[0026] In one embodiment of the present application, the data processing unit corresponding to the first type includes an adder subunit for performing addition calculation, a logic subunit for performing logic calculation, a shift subunit for performing shift processing, a mask subunit for calculating a mask, and an alignment subunit for performing data alignment;

[0027] The data processing unit corresponding to the second type includes a mask subunit and a shift subunit;

[0028] The data processing units corresponding to the third type include logic subunits and mask subunits.

[0029] In a second aspect, an embodiment of the present application provides a network chip, wherein the network chip performs the following steps:

[0030] Obtain an instruction, wherein the operation type indicated by the instruction is: a first type, a second type, or a third type, the first type indicates: performing data calculation on an operand, the second type indicates: moving a storage location of an operand, and the third type indicates: jumping a memory access location according to a value of the operand, and the instruction includes an identifier of a register where the operand is located, a source address of the operand in the register, and a primary operation code indicating the operation type indicated by the instruction;

[0031] Parsing the instruction, reading an operand from a source address in a register indicated by the instruction, and determining a target operation type indicated by the instruction according to an operation code included in the instruction;

[0032] The operand is processed by a data processing unit corresponding to the target operation type in the network chip to obtain a target processing result.

[0033] In one embodiment of the present application, the instruction indicating the first type includes: a first main operation code, a first sub-operation code, a second sub-operation code, an operand length, a first source address of the first operand, a second source address of the second operand, an identifier of the first register, and an identifier of the second register;

[0034] The first major operation code indicates that the operation type indicated by the instruction is the first type;

[0035] The first sub-operation code indicates that the data calculation performed on the operand is a logic calculation, a shift calculation or an addition or subtraction calculation;

[0036] In the case where the first sub-operation code indicates performing a logic calculation on an operand, the second sub-operation code indicates performing one of AND, OR, NOT, and XOR calculations;

[0037] In the case where the first sub-operation code indicates that a shift calculation is performed on an operand, the second sub-operation code indicates that a logical left shift, a logical right shift or a circular shift is performed;

[0038] In the case where the first sub-operation code indicates performing addition or subtraction calculations on operands, the second sub-operation code indicates performing addition or subtraction calculations;

[0039] The first register is a register where the first operand is located and a register where the calculated result is to be stored, and the second register is a register where the second operand is located.

[0040] In one embodiment of the present application, the instruction indicating the second type includes: a second main opcode, a third sub-opcode, a source address where the operand was originally located, a destination address to which the operand is to be moved, an identifier of a source register where the operand was originally located, and an identifier of a destination register to which the operand is to be moved, wherein the third sub-opcode indicates: a discrete bit number of the operand to be moved;

[0041] The second major operation code indicates that the operation type indicated by the instruction is the second type.

[0042] In one embodiment of the present application, when the operation type indicated by the instruction is the second type and the total number of discrete bits of each operand to be moved is greater than 1 bit, the instruction includes a first instruction indicating reading an operand and a second instruction indicating writing an operand;

[0043] The first instruction includes: an identifier of a source register where each operand originally resides, a source address of each operand in the source register, a third sub-operation code, and a second main operation code;

[0044] The second instruction includes: an identifier of a destination register to which each operand is to be moved, a destination address in the destination register to which each operand is to be moved, a third sub-operation code, and a second main operation code;

[0045] The second major operation code indicates that the operation type indicated by the instruction is the second type.

[0046] In one embodiment of the present application, the third type of instruction is indicated to include: a source address of an operand, an identifier of a source register where the operand is located, an offset of an access location to be jumped to in a memory, a fourth sub-operation code, and a third main operation code;

[0047] The fourth sub-operation code is used to indicate a target value, and when the value of the operand is the target value, a memory access position is jumped;

[0048] The third major operation code indicates that the operation type indicated by the instruction is the third type.

[0049] In one embodiment of the present application, the data processing unit corresponding to the first type includes an adder subunit for performing addition calculation, a logic subunit for performing logic calculation, a shift subunit for performing shift processing, a mask subunit for calculating a mask, and an alignment subunit for performing data alignment;

[0050] The data processing unit corresponding to the second type includes a mask subunit and a shift subunit;

[0051] The data processing units corresponding to the third type include logic subunits and mask subunits.

[0052] In a third aspect, an embodiment of the present application provides an electronic device, including a network chip, a communication interface, a memory, and a communication bus, wherein the network chip, the communication interface, and the memory communicate with each other through the communication bus;

[0053] Memory, used to store computer programs;

[0054] The network chip is used to implement any method step described in the first aspect when executing a program stored in a memory.

[0055] In a fourth aspect, an embodiment of the present application provides a network chip instruction processing device, which is applied to a network chip, and the device includes:

[0056] An instruction acquisition module is used to acquire instructions, wherein the operation type indicated by the instruction is: a first type, a second type or a third type, the first type indicates: performing data calculation on the operand, the second type indicates: moving the storage location of the operand, and the third type indicates: jumping the memory access location according to the value of the operand, and the instruction includes an identifier of the register where the operand is located, a source address of the operand in the register, and a main operation code indicating the operation type indicated by the instruction;

[0057] An instruction parsing module, used to parse the instruction, read an operand from a source address in a register indicated by the instruction, and determine a target operation type indicated by the instruction according to an operation code contained in the instruction;

[0058] The data processing module is used to process the operands through a data processing unit corresponding to the target operation type in the network chip to obtain a target processing result.

[0059] In one embodiment of the present application, the instruction indicating the first type includes: a first main operation code, a first sub-operation code, a second sub-operation code, an operand length, a first source address of the first operand, a second source address of the second operand, an identifier of the first register, and an identifier of the second register;

[0060] The first major operation code indicates that the operation type indicated by the instruction is the first type;

[0061] The first sub-operation code indicates that the data calculation performed on the operand is a logic calculation, a shift calculation or an addition or subtraction calculation;

[0062] In the case where the first sub-operation code indicates performing a logic calculation on an operand, the second sub-operation code indicates performing one of AND, OR, NOT, and XOR calculations;

[0063] In the case where the first sub-operation code indicates that a shift calculation is performed on an operand, the second sub-operation code indicates that a logical left shift, a logical right shift or a circular shift is performed;

[0064] In the case where the first sub-operation code indicates performing addition or subtraction calculations on operands, the second sub-operation code indicates performing addition or subtraction calculations;

[0065] The first register is a register where the first operand is located and a register where the calculated result is to be stored, and the second register is a register where the second operand is located.

[0066] In one embodiment of the present application, the instruction indicating the second type includes: a second main opcode, a third sub-opcode, a source address where the operand was originally located, a destination address to which the operand is to be moved, an identifier of a source register where the operand was originally located, and an identifier of a destination register to which the operand is to be moved, wherein the third sub-opcode indicates: a discrete bit number of the operand to be moved;

[0067] The second major operation code indicates that the operation type indicated by the instruction is the second type.

[0068] In one embodiment of the present application, when the operation type indicated by the instruction is the second type and the total number of discrete bits of each operand to be moved is greater than 1 bit, the instruction includes a first instruction indicating reading an operand and a second instruction indicating writing an operand;

[0069] The first instruction includes: an identifier of a source register where each operand originally resides, a source address of each operand in the source register, a third sub-operation code, and a second main operation code;

[0070] The second instruction includes: an identifier of a destination register to which each operand is to be moved, a destination address in the destination register to which each operand is to be moved, a third sub-operation code, and a second main operation code;

[0071] The second major operation code indicates that the operation type indicated by the instruction is the second type.

[0072] In one embodiment of the present application, the third type of instruction is indicated to include: a source address of an operand, an identifier of a source register where the operand is located, an offset of an access location to be jumped to in a memory, a fourth sub-operation code, and a third main operation code;

[0073] The fourth sub-operation code is used to indicate a target value, and when the value of the operand is the target value, a memory access position is jumped;

[0074] The third major operation code indicates that the operation type indicated by the instruction is the third type.

[0075] In one embodiment of the present application, the data processing unit corresponding to the first type includes an adder subunit for performing addition calculation, a logic subunit for performing logic calculation, a shift subunit for performing shift processing, a mask subunit for calculating a mask, and an alignment subunit for performing data alignment;

[0076] The data processing unit corresponding to the second type includes a mask subunit and a shift subunit;

[0077] The data processing units corresponding to the third type include logic subunits and mask subunits.

[0078] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a network chip, any method step described in the first aspect is implemented.

[0079] In a sixth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the above-mentioned network chip instruction processing methods.

[0080] Beneficial effects of the embodiments of the present application:

[0081] The network chip instruction processing method provided in the embodiment of the present application defines a new indicated operation type as a first type, a second type and a third type of instruction, and the three instructions can respectively indicate data calculation, moving operands and jumping to memory access locations according to the values ​​of operands. The above three types of instructions are instructions that are not included in the existing instruction set in the relevant technology, and are adapted to the process of the network chip processing the message. In addition, the instruction in the embodiment of the present application contains the source address of the operand in the register, rather than the value of the operand in the relevant technology, so the scheme provided by the embodiment of the present application can read the operand from the register based on the source address, which will not hinder the acquisition of the operand. And the length of the source address is less than the length of the value of the operand, and the source address occupies fewer bits in the instruction, so the other bits in the instruction can be used to record more other information, so that the information carried in the instruction is richer, and then it can indicate the operation of complex network information. Therefore, through the above three types of instructions, the data plane in the network chip can be controlled to perform the above three complex operations on the message, thereby improving the performance of the network chip. The encoded instruction segment domain is rich in information, which can be flexibly scheduled by the software, optimize program performance, and reduce program running time. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0083] Figure 1 A schematic diagram of an instruction format in a RISC-V open source standard instruction set in the related art;

[0084] Figure 2 An instruction template provided for an embodiment of the present application;

[0085] Figure 3 A flowchart of a network chip processing method provided in an embodiment of the present application;

[0086] Figure 4 A schematic diagram of instructions defined in an embodiment of the present application;

[0087] Figure 5 A schematic diagram of an optimized MOV instruction provided in an embodiment of the present application;

[0088] Figure 6 A schematic diagram of the principle of a Kogge-Stone structure provided in an embodiment of the present application;

[0089] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0090] Figure 8 A schematic diagram of the structure of a network chip instruction processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0091] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0092] In order to reflect the difference between the embodiments of the present application and the related art, RISC in the related art is first described.

[0093] The RISC-V open source standard instruction set is the fifth generation of RISC and has the following characteristics:

[0094] 1. Open source: free and open architecture, developers do not need to worry about being restricted;

[0095] 2. The architecture is simple, which reduces the difficulty of decoding and makes hardware implementation relatively easy;

[0096] 3. Modular design: developers can choose the required instruction set according to their needs;

[0097] 4. Highly scalable.

[0098] The instructions defined in the RISC-V open source standard instruction set have a consistent length, the position of each field is fixed, and the functions that can be implemented are relatively simple. However, for network chips, a series of complex operations need to be performed on the message on the data plane, and the instructions defined in the current RISC-V open source standard instruction set do not support complex operations. Therefore, in order to implement the above operations, it may be necessary to combine multiple instructions to implement a complex operation, or even if multiple instructions are combined, complex operations cannot be implemented. In addition, if multiple instructions are used to implement a complex operation, additional instruction space will be occupied. In the case of tight resources, the additional occupation of instruction space will become a critical path that limits the implementation of network chips.

[0099] Therefore, the current RISC-V open source standard instruction set is not fully suitable for network chips and needs to be expanded.

[0100] See also Figure 1 , which is a schematic diagram of the instruction format in a RISC-V open source standard instruction set in the related technology.

[0101] The figure shows the fields contained in some instructions in the RISC-V open source standard instruction set in the related art. The numbers 0, 6, 7, 11, 12, 14, 15, 19, 20, 24, 25, 31 at the top represent the bit numbers. Each rectangular box represents a field, and each row corresponds to an instruction. It can be seen from the figure that the data length of each instruction is 32 bits.

[0102] In addition, opcode represents a 7-bit operation code, which is used as the main operation code to distinguish different instructions. func3 represents a 3-bit function code, and funct7 represents a 7-bit function code, both of which are sub-operation codes, and they can help distinguish different types of instructions.

[0103] Rs1 and rs2 represent two 5-bit source registers, and the two source registers are used to store operands to be processed.

[0104] rd is a 5-bit destination register, and the result of the operation on the operand is stored in rd.

[0105] Each imm represents an immediate value of different length and can be used directly as an operand.

[0106] The R-type instructions in the first row of the figure are the most commonly used arithmetic instructions, which are all integer arithmetic instructions that do not contain immediate values, and generally represent register-register operations.

[0107] The I-type instruction in the second line has two register addresses and an immediate value, which is equivalent to changing an operand in the R-type instruction format to an immediate value. It generally represents instructions for short immediate values ​​and memory access load operations.

[0108] The S-type instruction in the third line contains a 12-bit immediate value consisting of imm[11:5] and imm[4:0], which generally indicates a memory access Store operation instruction.

[0109] The B-type instructions on the fourth line generally represent conditional jump operation instructions, such as equal, unequal, greater than or equal to, and less than jump instructions.

[0110] The U-type instruction in the fifth row has a 20-bit immediate value, which generally indicates a long immediate value operation instruction.

[0111] The J-type instruction on the sixth line generally indicates an unconditional jump instruction.

[0112] The above instructions are all instructions defined in the existing RISC-V open source standard instruction set. Their specific meanings can be found in the specific definition of the RISC-V open source standard instruction set, and will not be repeated here.

[0113] In addition, different operations corresponding to different values ​​of the opcode field are described.

[0114] See Table 1, which is a table of correspondence between opcode field values ​​and operations in the related art.

[0115] Table 1

[0116] Among them, the values ​​of bit 0 and bit 1 of the opcode field of all instructions are 1. The 000-111 in the first row of the table represent the different values ​​of bit 4 to bit 2 in the opcode field, and the 00-11 in the first column represent the different values ​​of bit 6 and bit 5 in the opcode field.

[0117] According to the value combination of each bit in the above table, a complete opcode can be obtained. For example, the opcode value 00000011 corresponds to the operation LOAD, the opcode value 0100011 corresponds to the operation STORE, etc. By analogy, the correspondence between the opcode and the operation shown in the above table is defined by the existing RISC-V open source standard instruction set, and will not be repeated here.

[0118] In addition, custom-0, custom-1, custom-2, and custom-3 in the above table are four user-defined opcodes reserved in the RISC-V open source standard instruction set. Users can use the above opcodes to define new instructions according to their needs. The RISC-V open source standard instruction set uses two instruction extension methods: greenfield and brownfield. Greenfield extension means that the extended instruction uses a new opcode, and brownfield extension means that the opcode used by the extended instruction is embedded in the opcode space that has been used. The same greenfield extension code can contain multiple brownfield extension codes, depending on the instruction function.

[0119] On this basis, in order to solve the problems existing in the related technology, the embodiment of the present application provides a network chip instruction processing method, a network chip, an electronic device and a device.

[0120] Since the newly defined instructions in this application are quite different from the existing instructions in the current RISC-V open source standard instruction set, a combination of greenfield expansion and brownfield expansion can be adopted in this application.

[0121] As shown above, the location of the opcode field in the RISC-V open source standard instruction set is located at bit 0 to bit 6 in the defined instructions. In one embodiment of the present application, the above definition can be followed to continue to record the main opcode at bit 0 to bit 6 in the instruction.

[0122] See also Figure 2 , which is an instruction template provided in an embodiment of the present application.

[0123] The 0th bit to the 6th bit in the template is the main operation code field, and the other bits are the encoding segment field which can be defined according to the actual requirements of each instruction.

[0124] The encoding segment field can be divided into three parts: sub-operation code segment field, register segment field and function segment field.

[0125] The sub-opcode segment field records the sub-opcode. The register segment field is used to record the identifiers of the source register and / or the destination register, and the specific number of the identifiers of the source register and / or the destination register recorded can be limited according to the actual situation. The function segment field is used to record the information required to implement the function indicated by the instruction according to the actual needs.

[0126] Alternatively, in other embodiments, the main operation code may also be defined at other locations in the instruction, which is not limited in the embodiments of the present application.

[0127] See also Figure 3 , is a flow chart of a network chip processing method provided in an embodiment of the present application, which is applied to a network chip. The method includes the following steps S301-S303.

[0128] S301: Get instructions.

[0129] Among them, the operation type indicated by the above instruction is: the first type, the second type or the third type, the above first type means: performing data calculation on the operand, the above second type means: moving the operand, and the above third type means: jumping the memory access location according to the value of the operand. The above instruction contains the identifier of the register where the operand is located, the source address of the operand in the register, and the main operation code indicating the operation type indicated by the above instruction.

[0130] The newly added instructions in this application are ALUB (Arithmetic and Logic Unit) class instructions that instruct data calculation on operands, MOV (Move) class instructions that instruct the storage location of moving operands, and BIS2 (Branch if set 2 bit) class instructions that instruct the jump of memory access locations according to the values ​​of operands.

[0131] S302: Parse the instruction, read an operand from a source address in a register indicated by the instruction, and determine a target operation type indicated by the instruction according to an operation code included in the instruction.

[0132] In one embodiment of the present application, the source address of the operand is recorded in the above instruction, so the operand can be read from the register according to the source address.

[0133] In addition, the operation code contained in the above instruction includes a main operation code and a sub-operation code. The operation specifically indicated by the instruction can be determined based on the main operation code and the sub-operation code, and an execution function code can be generated based on the above main operation code and the sub-operation code.

[0134] The execution function code contains multiple bits and is divided into two parts. The first part is used to indicate the operation type, and the second part further distinguishes the specific data processing method corresponding to the final target processing result.

[0135] S303: Process the operands through a data processing unit corresponding to the target operation type in the network chip to obtain a target processing result.

[0136] In one embodiment of the present application, the network chip is configured with data processing units corresponding to different operation types. After receiving the instruction, the network chip can use the data processing units corresponding to different operation types in parallel to perform data processing respectively, obtain three different processing results, and then select the processing result corresponding to the target operation type. This can reduce the complexity of the network chip hardware design. This application adopts this method when describing the data processing process in detail below.

[0137] Alternatively, before performing data processing, the data processing unit corresponding to the target operation type can be determined and only the data processing unit can be enabled. Only the enabled data processing unit can perform data processing. In this case, the processing result obtained is the target processing result.

[0138] As can be seen from the above, the network chip instruction processing method provided in the embodiment of the present application defines a new indicated operation type as a first type, a second type and a third type of instruction, and the three instructions can respectively indicate data calculation, moving operands and jumping to memory access locations according to the values ​​of operands. The above three types of instructions are instructions that are not included in the existing instruction set in the relevant technology, and are adapted to the process of the network chip processing the message. In addition, the instruction in the embodiment of the present application contains the source address of the operand in the register, rather than the value of the operand in the relevant technology, so the scheme provided by the embodiment of the present application can read the operand from the register based on the source address, which will not hinder the acquisition of the operand. And the length of the source address is less than the length of the value of the operand, and the source address occupies fewer bits in the instruction, so the other bits in the instruction can be used to record more other information, so that the information carried in the instruction is richer, and then it can indicate the operation of complex network information. Therefore, through the above three types of instructions, the data plane in the network chip can be controlled to perform the above three complex operations on the message, thereby improving the performance of the network chip. The encoded instruction segment domain is rich in information, which can be flexibly scheduled by the software, optimize program performance, and reduce program running time.

[0139] The specific data processing process can be found below and will not be described in detail here.

[0140] The following is a detailed description of the newly defined instructions in the embodiments of the present application:

[0141] In one embodiment of the present application, an instruction indicating a first type (ALUB class) includes: a first main operation code, a first sub-operation code, a second sub-operation code, an operand length, a first source address of the first operand, a second source address of the second operand, an identifier of a first register, and an identifier of a second register.

[0142] The first main operation code is represented by opcode, which means that the operation type indicated by the instruction is the first type.

[0143] The first sub-opcode is represented by func3, which has a length of 3 bits and indicates that the data calculation performed on the operand is a logical calculation, a shift calculation, or an addition or subtraction calculation. Different values ​​of func3 respectively indicate that the data calculation performed on the operand is a logical calculation, a shift calculation, or an addition or subtraction calculation. For example, a func3 value of 000 indicates a logical calculation, a func3 value of 001 indicates a shift calculation, and a func3 value of 010 indicates an addition or subtraction calculation. The above example is only a possible case. The embodiment of the present application does not limit the specific values ​​of func3 in different cases, as long as the values ​​of func3 corresponding to different calculations are different.

[0144] The second sub-operation code is represented by func2 and has a length of 2 bits.

[0145] In the case where the first sub-operation code indicates that a logic calculation is performed on an operand, the second sub-operation code indicates that one of AND, OR, NOT, and XOR calculations is performed. Different values ​​of func2 correspond to AND, OR, NOT, and XOR calculations, respectively. In this case, the first operand and the second operand are two data for performing a logic calculation.

[0146] In the case where the first sub-operation code indicates that the operand is shifted, the second sub-operation code indicates that a logical left shift, a logical right shift, or a circular shift is performed. Different values ​​of func2 correspond to logical left shift, logical right shift, or circular shift, respectively. In this case, the first operand is the data to be shifted, and the second operand is the number of bits to be shifted.

[0147] In the case where the first sub-operation code indicates that the operands are to be added or subtracted, the second sub-operation code indicates that addition or subtraction is to be performed. Different values ​​of func2 correspond to addition or subtraction, respectively. In this case, the first operand and the second operand are two data to be added or subtracted. In fact, the subtraction of the first operand and the second operand is equivalent to the addition of the complement of the second operand and the first operand. Therefore, the addition and subtraction can be realized by addition in hardware implementation.

[0148] The first register is the register where the first operand is located and the register where the calculated result is to be stored, and the second register is the register where the second operand is located.

[0149] In another embodiment of the present application, an instruction indicating the second type (MOV type) includes: a second main opcode, a third sub-opcode, a source address where the operand was originally located, a destination address to which the operand is to be moved, an identifier of the source register where the operand was originally located, and an identifier of the destination register to which the operand is to be moved.

[0150] The above-mentioned second main operation code indicates that the operation type indicated by the instruction is the second type.

[0151] The third sub-opcode can be represented by func3, and the third sub-opcode indicates the number of discrete bits of the operand to be moved. For example, the value of the third sub-opcode can be 001, 010, and 011, which respectively indicate that the number of discrete bits of the operand to be moved is 1 bit, 2 bits, and 3 bits. When the number of discrete bits of the operand to be moved is 1 bit, the movement of the bit data can be completed by an instruction indicating the second type. When the number of discrete bits of the operand to be moved is 2 bits or 3 bits, please refer to the description of the first instruction and the second instruction below, which will not be described in detail here.

[0152] In another embodiment of the present application, the third type (BIS2 type) instruction is indicated to include: the source address of the operand, the identifier of the source register where the operand is located, the offset of the access location to be jumped to in the memory, the fourth sub-opcode, and the third main opcode.

[0153] The fourth sub-opcode is used to indicate a target value. When the operand value is the target value, a jump is performed to the memory access location. The operand indicated by the third type of instruction is a 1-bit number in two registers, a total of 2 bits. The target value can be 00, 01, 10 or 11, which respectively indicates a jump when the operand is 00, a jump when it is 01, a jump when it is 10 or a jump when it is 11.

[0154] The third major operation code mentioned above indicates that the operation type indicated by the instruction is the third type.

[0155] In this case, refer to Table 2, which is a table of correspondence between opcode field values ​​and operations provided in an embodiment of the present application.

[0156] Table 2

[0157] Compared with the embodiment shown in the aforementioned Table 1, in the embodiment of the present application, the reserved custom-0 opcode space is used for the opcode of the ALUB instruction, the custom-1 opcode space is used for the opcode of the MOV instruction, and the reserved custom-2 opcode space is used for the opcode of the BIS2 instruction, and the other parts remain unchanged. That is, in this case, the value of the first main opcode is 0001011, the value of the second main opcode is 0101011, and the value of the third main opcode is 1011011.

[0158] Of course, the above opcode allocation method is only an example. The opcodes of different types of instructions can also be allocated in other ways. For example, the custom-1 opcode space is used for the opcodes of ALUB instructions, the reserved custom-0 opcode space is used for the opcodes of MOV instructions, the reserved custom-2 opcode space is used for the opcodes of BIS2 instructions, etc. The embodiments of the present application do not limit this.

[0159] See also Figure 4 , which is a schematic diagram of the instructions defined in the embodiments of the present application.

[0160] The figure contains three types of instructions. From top to bottom, the three rows are ALUB-TYPE (ALUB type), MOV-TYPE (MOV type), and BIS2-TYPE (BRANCH type).

[0161] Among them, func2 in the ALUB class instructions is the second sub-opcode, SIZE (size) is the operand length, rs2 is the identifier of the second register, rs1 / rd is the identifier of the first register, func3 is the first sub-opcode, R is the 2-bit reserved segment field, SRC2_POS is the second source address, SRC1_POS is the first source address, SRC2_POS and SRC1_POS are in BYTE granularity, and opcode is the first main opcode.

[0162] In MOV instructions, R is a 2-bit reserved segment field, SRC_POS1 is the source address, DST_POS1 is the destination address, rs1 is the source register identifier, func3 is the third sub-operation code, rs2 / rd is the destination register identifier, and opcode is the second main operation code.

[0163] The offset[8|5] and offset[4:2|7:6] in the BIS2 class instruction are combined to get offset[8:2], which is the offset of the access location to be jumped to in the memory. SRC_POS2 and SRC_POS1 are the source addresses of the two operands, rs1 is the identifier of the source register, func3 is the fourth sub-opcode, and opcode is the third main opcode.

[0164] In another embodiment of the present application, if there is a need to move a multi-bit operand, if the MOV class instruction defined above is used to move the operand, it is necessary to call the same number of MOV class instructions as the number of operand bits, and each MOV class instruction can move a 1-bit operand. This will take up a lot of instruction space. In order to solve the above problem, in the embodiment of the present application, the method of binding implicit registers can be used to save instruction space, thereby optimizing instruction entries.

[0165] Specifically, in one embodiment of the present application, when the operation type indicated by the above instruction is the second type and the total number of discrete bits of each operand to be moved is greater than 1 bit, the above instruction includes a first instruction indicating a read operand and a second instruction indicating a write operand.

[0166] The first instruction includes: an identifier of a source register where each operand originally resides, a source address of each operand in the source register, a third sub-operation code, and a second main operation code.

[0167] The second instruction includes: an identifier of a destination register to which each operand is to be moved, a destination address in the destination register to which each operand is to be moved, a third sub-operation code, and a second main operation code.

[0168] The above-mentioned second main operation code indicates that the operation type indicated by the instruction is the second type.

[0169] The first instruction and the second instruction may be referred to as optimized MOV instructions.

[0170] That is, the aforementioned first instruction is used to centrally read discrete multi-bit operands from the source register, and the second instruction is used to centrally move the read discrete multi-bit operands to the destination register. Limited by the current instruction length of 32 bits, theoretically, it contains at most the addresses corresponding to 2 discrete operands. Therefore, in order to enable an instruction in the present application to schedule 3 discrete operands, the shaddow register is used to save 5 bits of encoding space in the instruction, so the address of the discrete 3-bit operand can be stored in the instruction in the present application. That is, a maximum of 3 bits of operands are scheduled through one instruction, so the solution provided by the embodiment of the present application only requires 2 instructions when moving a 3-bit operand, but if the MOV-type instruction shown in the above text is directly used for moving, 3 instructions are required. Therefore, the solution provided by the embodiment of the present application can save instruction space and optimize instruction entries.

[0171] See also Figure 5 , is a schematic diagram of an optimized MOV-type instruction provided in an embodiment of the present application.

[0172] The first line in the figure is the second instruction (shad2reg), and the second line is the first instruction (reg2shad). Both the first and second instructions use the shaddow register to save encoding space in the instruction, so that the address of the 3-bit operand can be recorded. The encoding space saved in shad2reg is located at [19:15] bits, and the encoding space saved in reg2shad is located at [11:7] bits.

[0173] DST_POS3, DST_POS2, and DST_POS1 contained in the second instruction are three destination addresses respectively, func3 is the third sub-operation code, rs2 / rd is the identifier of the destination register, and opcode is the second main operation code.

[0174] SRC_POS3, SRC_POS2, and SRC_POS1 contained in the first instruction are three source addresses, func3 is the third sub-operation code, rs1 is the identifier of the source register, and opcode is the second main operation code.

[0175] The R in the figure is a reserved segment field with a length of 2 bits.

[0176] It should be noted that the first instruction and the second instruction may also carry only two addresses for moving a 2-bit operand, but in this case the number of instructions required to move the 2-bit operand is the same as the number of instructions required to directly use the aforementioned MOV-type instructions to move the operand.

[0177] The specific process of data processing is described below.

[0178] In one embodiment of the present application, the data processing unit corresponding to the above-mentioned first type includes an adder subunit for performing addition calculations, a logic subunit for performing logical calculations, a shift subunit for performing shift processing, a mask subunit for calculating masks, and an alignment subunit for performing data alignment.

[0179] The data processing unit corresponding to the second type mentioned above includes a mask subunit and a shift subunit.

[0180] The data processing unit corresponding to the third type mentioned above includes a logic sub-unit and a mask sub-unit.

[0181] For example, when the logic subunit and the mask subunit implement the data processing indicated by the third type of instruction: assuming that the value of the fourth sub-operation in the instruction is 000, it means that the jump will only be made when the bits at the two source addresses recorded in the instruction are both 00. The specific process is:

[0182] (1) Use the mask subunit to generate two one-hot masks, namely one-hot mask 1 and one-hot mask 2.

[0183] (2) Input one-hot mask 1, one-hot mask 2, and two operands into the logic subunit to perform AND logic calculation.

[0184] (3) Finally, the logical calculation results are self-ORed and inverted. If both are 1, it means jump.

[0185] If the operand is originally 1 and is still 1 after masking, then it will be 0 after negation; if the operand is originally 0, then the final value is 1, so if both values ​​are 1, it means that the expectation is met.

[0186] The following is a description of each subunit:

[0187] (i) The adder subunit performs addition calculations as an adder. The adder is the core of data processing in the network chip and directly affects the performance of the network chip and the overall performance of the system. The parallel prefix algorithm is widely used in adders due to its advantage of fast operation speed. The parallel prefix algorithm is represented by the Sklansy structure, the Brent-Kung structure and the Kogge-Stone structure. The adder subunit can be generated by selecting a suitable hardware structure according to actual needs, including but not limited to the Sklansy structure, the Brent-Kung structure and the Kogge-Stone structure mentioned above for implementing the parallel prefix algorithm. In the embodiments of the present application, the adder subunit can also be implemented by other structures of other algorithms.

[0188] Preferably, since the Kogge-Stone structure has the advantages of low fan-out, regular structure, low implementation difficulty, easy expansion and low delay compared to other structures, in one embodiment of the present application, the Kogge-Stone structure can be selected to calculate the carry status of each bit when two operands are added.

[0189] The advantage of the Kogge-Stone structure is that it does not need to calculate the carry of each bit in order from low to high, but can calculate the carry of each bit in parallel. For example, if the number of bits of both operands is 32, if the same bit in the two operands is added from low to high to calculate the carry, 32 rounds of calculation are required, but if the Kogge-Stone structure is used, only log232=5 rounds are needed to complete the carry calculation of each bit. The level of the Kogge-Stone structure = log2size, where size is equal to the number of bits contained in the operand.

[0190] See also Figure 6 , which is a schematic diagram of the principle of a Kogge-Stone structure provided in an embodiment of the present application. When both operands to be added are 32-bit numbers, Q(1,1)-Q(32,32) in the figure are respectively the carry after adding the two numbers located at bit0 of the two operands - the carry after adding the two numbers located at bit31, and are represented by g(1)-g(32) respectively. In addition, the result obtained by performing an XOR calculation on the two numbers located at bit0 of the two operands - the result obtained by performing an XOR calculation on the two numbers located at bit31 are represented by p(1)-p(32).

[0191] The 0-5 on the left side of the figure are the levels of the Kogge-Stone structure.

[0192] The dotted and solid arrows between two adjacent levels in the figure indicate that a round of calculations has been performed between the two adjacent levels. The white circle in the figure indicates that this value has not changed in this round of calculations and is equal to the value of the previous level connected to the dotted line of this value. The black circle indicates that this value is obtained by carrying the value corresponding to the tail of the arrow pointing to the black circle and the value of the previous level connected to the dotted line of the black circle.

[0193] According to mathematical principles, when performing addition calculations, the final carry of each digit is not only related to the carry after adding the two numbers in that position in the two operands, but also to the carry after adding all the numbers with a digit lower than that position.

[0194] In the figure, Q(32,31) refers to the total carry calculated from bit31-bit30 of the two operands, Q(32,29) refers to the total carry calculated from bit31-bit28 of the two operands, and so on. Finally, we get Q(1,1)-Q(32,1), which is the carry corresponding to bit0-bit31 of the calculation result after adding the two operands.

[0195] After the carry is calculated, the carry corresponding to biti is added to p(i+1) to obtain the value of biti in the calculation result.

[0196] The adder subunit can be realized using the above principles.

[0197] When processing ALUB instructions, the adder subunit can implement the addition or subtraction calculation indicated by the ALUB instructions.

[0198] (ii) The logic subunit executes the following steps a1 to a4.

[0199] Step a1: Generate logic_sel according to the main operation code and sub-operation code in the instruction. Different values ​​of logic_sel represent AND calculation, OR calculation, NOT calculation, and XOR calculation respectively.

[0200] Step a2: configure the same bits in the two operands to perform four calculations, namely AND, OR, NOT, XOR, and obtain four results, namely tmp_res0, tmp_res1, tmp_res2 and tmp_res3.

[0201] Step a3: Set the initial value of j to 0, and select one from tmp_res0, tmp_res1, tmp_res2 and tmp_res3 corresponding to the j-th bit according to logic_sel as the final result of the logical calculation of the j-th bit, as res[j].

[0202] Specifically, if logic_sel indicates to perform an AND calculation, tmp_res0 is selected; if logic_sel indicates to perform an OR calculation, tmp_res1 is selected; if logic_sel indicates to perform a NOT calculation, tmp_res2 is selected; if logic_sel indicates to perform an XOR calculation, tmp_res3 is selected.

[0203] Step a4: add j+1 and return to step 3 until j=the number of bits n of the operand, and obtain the final result res[n] as the final calculation result.

[0204] When processing ALUB instructions, the logic subunit can implement the logic calculation indicated by the ALUB instructions. When processing BIS2 instructions, the logic subunit can determine whether the operand and the target value are equal. If they are equal, the memory access location can be jumped.

[0205] (iii) The translocation subunit performs the following steps b1 to b5.

[0206] Step b1: Determine the level sh_lv of the shift tree structure according to the number of bits of the operand.

[0207] sh_lv = log2size, where size is the number of bits of the operand.

[0208] Step b2: Determine the shift type sh_sel, fill value sh_fill according to the major opcode and sub opcode in the instruction, and read the number of shifted bits.

[0209] Different values ​​of sh_sel represent left shift, right shift or circular shift, and different values ​​of sh_fill represent logical shift or arithmetic shift.

[0210] Step b3: When calculating the i-th level shift value, compare whether the i-th bit in the shift amount is 1. If it is 1, concatenate 2 to the current high bit. i sh_fill to get the new shift value; if it is not 1, concatenate 2 to the low bit of the current shift value i 0.

[0211] Among them, the initial value of i is 0, for logical shift, sh_fill is 0, for arithmetic shift, sh_fill is the sign bit.

[0212] Step b4: add i+1 and return to step b3 until i=sh_lv.

[0213] In one embodiment of the present application, a 63-bit shift vector is finally obtained.

[0214] Step b5: Select the final 32-bit shift result from the shift vector according to sh_sel.

[0215] If sh_sel indicates left shift, 31-bit data is selected from the low order of the shift vector, and 1'b0 is added to the low order to obtain a 32-bit shift result.

[0216] If sh_sel indicates right shift, the 32-bit shift result is selected from the high bit of the shift vector.

[0217] When processing ALUB instructions, the shift calculation indicated by the ALUB instructions can be implemented through the shift subunit. When processing MOV instructions, when writing an operand into a destination register, the operand needs to be shifted according to the offset of the destination address in the destination register.

[0218] (iv) The mask subunit performs the following steps c1 to c4.

[0219] Step c1: Determine the level msk_lv of the mask tree structure according to the number of bits of the operand.

[0220] msk_lv=log2size, where size is the number of bits of the operand.

[0221] Step c2: Generate a mask type msk_sel according to the major operation code and the sub-operation code in the instruction.

[0222] Different values ​​of msk_sel represent one-hot mask and variable-length mask respectively.

[0223] Step c3: When calculating the i-th level mask, compare whether the i-th bit in size[i] is 1. If it is 1, concatenate 2 to the lower bit of the current mask. i mask bits to get a new mask; if it is not 1, concatenate 2 bits to the high bit of the current mask. i mask bits.

[0224] The initial value of i is 0, the mask bit is 0 for one-hot masking, and the mask bit is 1 for variable-length masking.

[0225] Step c4: add i+1 and return to step c3 until i=msk_lv to obtain the final mask result.

[0226] When processing ALUB instructions and MOV instructions, data needs to be written to the register. At this time, the data to be written needs to be compared with the data currently stored in the register to determine the bit in the register that needs to be updated. In this process, a mask needs to be used, so the mask needs to be calculated by the mask subunit. When processing BIS2 instructions, the instruction value needs to be compared. In this process, the mask subunit and the logic subunit are used for calculation.

[0227] (V) An alignment subunit is used for processing and shifting data with a granularity of BYTE, and the execution steps include the following steps d1 to d4.

[0228] Step d1: Generate a 4-bit one-hot mask as byte_sel according to the major opcode and sub-opcode in the instruction.

[0229] Step d2: configure the operand starting point to start from 0B, 1B, 2B, and 3B. The four alignment results obtained in the four cases are respectively recorded as in0, in1, in2, and in3.

[0230] Step d3: Calculate byte_sel and ini to obtain resi.

[0231] The values ​​of i are 0-3, so the calculated results are res0-res3.

[0232] Step d4: Perform a logical OR operation on res0, res1, res2 and res3 to obtain res.

[0233] When implementing ALUB instructions and using the alignment subunit to process operands, first read the first operand and the second operand from the register according to the first source address and the second source address recorded in the instruction, align the two operands to the LSB, and perform calculations. Perform mask merge on the calculation result and the data originally stored in the register.

[0234] From the above, it can be seen that there are some common sub-units between different types of data processing units in the embodiments of the present application, and there are some common data processing processes between different sub-units. Therefore, the common parts can be combined and reused in the hardware implementation of the network chip, thereby reducing the difficulty of developing the network chip and reducing the chip area.

[0235] Corresponding to the aforementioned network chip instruction processing method, an embodiment of the present application also provides a network chip.

[0236] An embodiment of the present application provides a network chip, wherein the network chip performs the following steps:

[0237] Obtain an instruction, wherein the operation type indicated by the instruction is: a first type, a second type, or a third type, the first type indicates: performing data calculation on an operand, the second type indicates: moving a storage location of an operand, and the third type indicates: jumping a memory access location according to a value of the operand, and the instruction includes an identifier of a register where the operand is located, a source address of the operand in the register, and a primary operation code indicating the operation type indicated by the instruction;

[0238] Parsing the instruction, reading an operand from a source address in a register indicated by the instruction, and determining a target operation type indicated by the instruction according to an operation code included in the instruction;

[0239] The operand is processed by a data processing unit corresponding to the target operation type in the network chip to obtain a target processing result.

[0240] As can be seen from the above, the network chip instruction processing method provided in the embodiment of the present application defines a new indicated operation type as a first type, a second type and a third type of instruction, and the three instructions can respectively indicate data calculation, moving operands and jumping to memory access locations according to the values ​​of operands. The above three types of instructions are instructions that are not included in the existing instruction set in the relevant technology, and are adapted to the process of the network chip processing the message. In addition, the instruction in the embodiment of the present application contains the source address of the operand in the register, rather than the value of the operand in the relevant technology, so the scheme provided by the embodiment of the present application can read the operand from the register based on the source address, which will not hinder the acquisition of the operand. And the length of the source address is less than the length of the value of the operand, and the source address occupies fewer bits in the instruction, so the other bits in the instruction can be used to record more other information, so that the information carried in the instruction is richer, and then it can indicate the operation of complex network information. Therefore, through the above three types of instructions, the data plane in the network chip can be controlled to perform the above three complex operations on the message, thereby improving the performance of the network chip. The encoded instruction segment domain is rich in information, which can be flexibly scheduled by the software, optimize program performance, and reduce program running time.

[0241] In one embodiment of the present application, the instruction indicating the first type includes: a first main operation code, a first sub-operation code, a second sub-operation code, an operand length, a first source address of the first operand, a second source address of the second operand, an identifier of the first register, and an identifier of the second register;

[0242] The first major operation code indicates that the operation type indicated by the instruction is the first type;

[0243] The first sub-operation code indicates that the data calculation performed on the operand is a logic calculation, a shift calculation or an addition or subtraction calculation;

[0244] In the case where the first sub-operation code indicates performing a logic calculation on an operand, the second sub-operation code indicates performing one of AND, OR, NOT, and XOR calculations;

[0245] In the case where the first sub-operation code indicates that a shift calculation is performed on an operand, the second sub-operation code indicates that a logical left shift, a logical right shift or a circular shift is performed;

[0246] In the case where the first sub-operation code indicates performing addition or subtraction calculations on operands, the second sub-operation code indicates performing addition or subtraction calculations;

[0247] The first register is a register where the first operand is located and a register where the calculated result is to be stored, and the second register is a register where the second operand is located.

[0248] In one embodiment of the present application, the instruction indicating the second type includes: a second main opcode, a third sub-opcode, a source address where the operand was originally located, a destination address to which the operand is to be moved, an identifier of a source register where the operand was originally located, and an identifier of a destination register to which the operand is to be moved, wherein the third sub-opcode indicates: a discrete bit number of the operand to be moved;

[0249] The second major operation code indicates that the operation type indicated by the instruction is the second type.

[0250] In one embodiment of the present application, when the operation type indicated by the instruction is the second type and the total number of discrete bits of each operand to be moved is greater than 1 bit, the instruction includes a first instruction indicating reading an operand and a second instruction indicating writing an operand;

[0251] The first instruction includes: an identifier of a source register where each operand originally resides, a source address of each operand in the source register, a third sub-operation code, and a second main operation code;

[0252] The second instruction includes: an identifier of a destination register to which each operand is to be moved, a destination address in the destination register to which each operand is to be moved, a third sub-operation code, and a second main operation code;

[0253] The second major operation code indicates that the operation type indicated by the instruction is the second type.

[0254] It can be seen from the above that the solution provided by the embodiment of the present application can save instruction space, optimize instruction entries, and save encoding space.

[0255] In one embodiment of the present application, the third type of instruction is indicated to include: a source address of an operand, an identifier of a source register where the operand is located, an offset of an access location to be jumped to in a memory, a fourth sub-operation code, and a third main operation code;

[0256] The fourth sub-operation code is used to indicate a target value, and when the value of the operand is the target value, a memory access position is jumped;

[0257] The third major operation code indicates that the operation type indicated by the instruction is the third type.

[0258] In one embodiment of the present application, the data processing unit corresponding to the first type includes an adder subunit for performing addition calculation, a logic subunit for performing logic calculation, a shift subunit for performing shift processing, a mask subunit for calculating a mask, and an alignment subunit for performing data alignment;

[0259] The data processing unit corresponding to the second type includes a mask subunit and a shift subunit;

[0260] The data processing units corresponding to the third type include logic subunits and mask subunits.

[0261] From the above, it can be seen that there are some common sub-units between different types of data processing units in the embodiments of the present application, and there are some common data processing processes between different sub-units. Therefore, the common parts can be combined and reused in the hardware implementation of the network chip, thereby reducing the difficulty of developing the network chip and reducing the chip area.

[0262] Corresponding to the aforementioned network chip instruction processing method, see Figure 7 , is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. This application also provides an electronic device, the electronic device comprising:

[0263] Network chip 701;

[0264] transceiver 704;

[0265] A machine-readable storage medium 702 stores machine-executable instructions that can be executed by the network chip 701; the machine-executable instructions prompt the network chip 701 to execute a network chip instruction processing method.

[0266] like Figure 7 As shown, the network device may further include a communication bus 703. The network chip 701, the machine-readable storage medium 702 and the transceiver 704 communicate with each other through the communication bus 703. The communication bus 703 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus 703 may be divided into an address bus, a data bus, a control bus and the like.

[0267] The transceiver 704 may be a wireless communication module. Under the control of the network chip 701 , the transceiver 704 performs data exchange with other devices.

[0268] The machine-readable storage medium 702 may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk storage. In addition, the machine-readable storage medium 702 may also be at least one storage device located away from the aforementioned network chip.

[0269] The network chip 701 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0270] As can be seen from the above, the network chip instruction processing method provided in the embodiment of the present application defines a new indicated operation type as a first type, a second type and a third type of instruction, and the three instructions can respectively indicate data calculation, moving operands and jumping to memory access locations according to the values ​​of operands. The above three types of instructions are instructions that are not included in the existing instruction set in the relevant technology, and are adapted to the process of the network chip processing the message. In addition, the instruction in the embodiment of the present application contains the source address of the operand in the register, rather than the value of the operand in the relevant technology, so the scheme provided by the embodiment of the present application can read the operand from the register based on the source address, which will not hinder the acquisition of the operand. And the length of the source address is less than the length of the value of the operand, and the source address occupies fewer bits in the instruction, so the other bits in the instruction can be used to record more other information, so that the information carried in the instruction is richer, and then it can indicate the operation of complex network information. Therefore, through the above three types of instructions, the data plane in the network chip can be controlled to perform the above three complex operations on the message, thereby improving the performance of the network chip. The encoded instruction segment domain is rich in information, which can be flexibly scheduled by the software, optimize program performance, and reduce program running time.

[0271] See also Figure 8 , is a schematic diagram of the structure of a network chip instruction processing device provided in an embodiment of the present application, which is applied to a network chip, and the device includes:

[0272] The instruction acquisition module 801 is used to acquire instructions, wherein the operation type indicated by the instruction is: the first type, the second type or the third type, the first type indicates: performing data calculation on the operand, the second type indicates: moving the storage location of the operand, and the third type indicates: jumping the memory access location according to the value of the operand, and the instruction includes an identifier of the register where the operand is located, a source address of the operand in the register, and a main operation code indicating the operation type indicated by the instruction;

[0273] The instruction parsing module 802 is used to parse the instruction, read the operand from the source address in the register indicated by the instruction, and determine the target operation type indicated by the instruction according to the operation code contained in the instruction;

[0274] The data processing module 803 is used to process the operands through a data processing unit corresponding to the target operation type in the network chip to obtain a target processing result.

[0275] As can be seen from the above, the network chip instruction processing method provided in the embodiment of the present application defines a new indicated operation type as a first type, a second type and a third type of instruction, and the three instructions can respectively indicate data calculation, moving operands and jumping to memory access locations according to the values ​​of operands. The above three types of instructions are instructions that are not included in the existing instruction set in the relevant technology, and are adapted to the process of the network chip processing the message. In addition, the instruction in the embodiment of the present application contains the source address of the operand in the register, rather than the value of the operand in the relevant technology, so the scheme provided by the embodiment of the present application can read the operand from the register based on the source address, which will not hinder the acquisition of the operand. And the length of the source address is less than the length of the value of the operand, and the source address occupies fewer bits in the instruction, so the other bits in the instruction can be used to record more other information, so that the information carried in the instruction is richer, and then it can indicate the operation of complex network information. Therefore, through the above three types of instructions, the data plane in the network chip can be controlled to perform the above three complex operations on the message, thereby improving the performance of the network chip. The encoded instruction segment domain is rich in information, which can be flexibly scheduled by the software, optimize program performance, and reduce program running time.

[0276] In one embodiment of the present application, the instruction indicating the first type includes: a first main operation code, a first sub-operation code, a second sub-operation code, an operand length, a first source address of the first operand, a second source address of the second operand, an identifier of the first register, and an identifier of the second register;

[0277] The first major operation code indicates that the operation type indicated by the instruction is the first type;

[0278] The first sub-operation code indicates that the data calculation performed on the operand is a logic calculation, a shift calculation or an addition or subtraction calculation;

[0279] In the case where the first sub-operation code indicates performing a logic calculation on an operand, the second sub-operation code indicates performing one of AND, OR, NOT, and XOR calculations;

[0280] In the case where the first sub-operation code indicates that a shift calculation is performed on an operand, the second sub-operation code indicates that a logical left shift, a logical right shift or a circular shift is performed;

[0281] In the case where the first sub-operation code indicates performing addition or subtraction calculations on operands, the second sub-operation code indicates performing addition or subtraction calculations;

[0282] The first register is a register where the first operand is located and a register where the calculated result is to be stored, and the second register is a register where the second operand is located.

[0283] In one embodiment of the present application, the instruction indicating the second type includes: a second main opcode, a third sub-opcode, a source address where the operand was originally located, a destination address to which the operand is to be moved, an identifier of a source register where the operand was originally located, and an identifier of a destination register to which the operand is to be moved, wherein the third sub-opcode indicates: a discrete bit number of the operand to be moved;

[0284] The second major operation code indicates that the operation type indicated by the instruction is the second type.

[0285] In one embodiment of the present application, when the operation type indicated by the instruction is the second type and the total number of discrete bits of each operand to be moved is greater than 1 bit, the instruction includes a first instruction indicating reading an operand and a second instruction indicating writing an operand;

[0286] The first instruction includes: an identifier of a source register where each operand originally resides, a source address where each operand resides in the source register, a third sub-operation code, and a second main operation code;

[0287] The second instruction includes: an identifier of a destination register to which each operand is to be moved, a destination address in the destination register to which each operand is to be moved, a third sub-operation code, and a second main operation code;

[0288] The second major operation code indicates that the operation type indicated by the instruction is the second type.

[0289] It can be seen from the above that the solution provided by the embodiment of the present application can save instruction space, optimize instruction entries, and save encoding space.

[0290] In one embodiment of the present application, the third type of instruction is indicated to include: a source address of an operand, an identifier of a source register where the operand is located, an offset of an access location to be jumped to in a memory, a fourth sub-operation code, and a third main operation code;

[0291] The fourth sub-operation code is used to indicate a target value, and when the value of the operand is the target value, a memory access position is jumped;

[0292] The third major operation code indicates that the operation type indicated by the instruction is the third type.

[0293] In one embodiment of the present application, the data processing unit corresponding to the first type includes an adder subunit for performing addition calculation, a logic subunit for performing logic calculation, a shift subunit for performing shift processing, a mask subunit for calculating a mask, and an alignment subunit for performing data alignment;

[0294] The data processing unit corresponding to the second type includes a mask subunit and a shift subunit;

[0295] The data processing units corresponding to the third type include logic subunits and mask subunits.

[0296] From the above, it can be seen that there are some common sub-units between different types of data processing units in the embodiments of the present application, and there are some common data processing processes between different sub-units. Therefore, the common parts can be combined and reused in the hardware implementation of the network chip, thereby reducing the difficulty of developing the network chip and reducing the chip area.

[0297] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by the network chip, the steps of any of the above-mentioned network chip instruction processing methods are implemented.

[0298] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any network chip instruction processing method in the above embodiments.

[0299] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0300] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0301] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the network chip, electronic device, device, and computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0302] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A network chip instruction processing method, characterized in that: Applied to a network chip, the method comprises: Obtain an instruction, wherein the operation type indicated by the instruction is: a first type, a second type, or a third type, the first type indicates: performing data calculation on an operand, the second type indicates: moving a storage location of an operand, and the third type indicates: jumping a memory access location according to a value of the operand, and the instruction includes an identifier of a register where the operand is located, a source address of the operand in the register, and a primary operation code indicating the operation type indicated by the instruction; Parsing the instruction, reading an operand from a source address in a register indicated by the instruction, and determining a target operation type indicated by the instruction according to an operation code included in the instruction; The operand is processed by a data processing unit corresponding to the target operation type in the network chip to obtain a target processing result.

2. The method according to claim 1, characterized in that Indicating that the instruction of the first type includes: a first major operation code, a first sub-operation code, a second sub-operation code, an operand length, a first source address of the first operand, a second source address of the second operand, an identifier of the first register, and an identifier of the second register; The first major operation code indicates that the operation type indicated by the instruction is the first type; The first sub-operation code indicates that the data calculation performed on the operand is a logic calculation, a shift calculation or an addition or subtraction calculation; In the case where the first sub-operation code indicates performing a logic calculation on an operand, the second sub-operation code indicates performing one of AND, OR, NOT, and XOR calculations; In the case where the first sub-operation code indicates that a shift calculation is performed on an operand, the second sub-operation code indicates that a logical left shift, a logical right shift or a circular shift is performed; In the case where the first sub-operation code indicates performing addition or subtraction calculations on operands, the second sub-operation code indicates performing addition or subtraction calculations; The first register is a register where the first operand is located and a register where the calculated result is to be stored, and the second register is a register where the second operand is located.

3. The method according to claim 1, characterized in that The instruction indicating the second type includes: a second major opcode, a third sub-opcode, a source address where the operand was originally located, a destination address to which the operand is to be moved, an identifier of a source register where the operand was originally located, and an identifier of a destination register to which the operand is to be moved, wherein the third sub-opcode indicates: a discrete bit number of the operand to be moved; The second major operation code indicates that the operation type indicated by the instruction is the second type.

4. The method according to claim 1, characterized in that: When the operation type indicated by the instruction is the second type and the total number of discrete bits of the operands to be moved is greater than 1 bit, the instruction includes a first instruction indicating reading the operand and a second instruction indicating writing the operand; The first instruction includes: an identifier of a source register where each operand originally resides, a source address of each operand in the source register, a third sub-operation code, and a second main operation code; The second instruction includes: an identifier of a destination register to which each operand is to be moved, a destination address in the destination register to which each operand is to be moved, a third sub-operation code, and a second main operation code; The second major operation code indicates that the operation type indicated by the instruction is the second type.

5. The method according to claim 1, characterized in that: Indicating that the third type of instruction includes: a source address of an operand, an identifier of a source register where the operand is located, an offset of an access location to be jumped to in a memory, a fourth sub-operation code, and a third main operation code; The fourth sub-operation code is used to indicate a target value, and when the value of the operand is the target value, a memory access position is jumped; The third major operation code indicates that the operation type indicated by the instruction is the third type.

6. The method according to any one of claims 1 to 5, characterized in that The data processing unit corresponding to the first type includes an adder subunit for performing addition calculation, a logic subunit for performing logic calculation, a shift subunit for performing shift processing, a mask subunit for calculating a mask, and an alignment subunit for performing data alignment; The data processing unit corresponding to the second type includes a mask subunit and a shift subunit; The data processing units corresponding to the third type include logic subunits and mask subunits.

7. A network chip, characterized in that: The network chip performs the following steps: Obtain an instruction, wherein the operation type indicated by the instruction is: a first type, a second type, or a third type, the first type indicates: performing data calculation on an operand, the second type indicates: moving a storage location of an operand, and the third type indicates: jumping a memory access location according to a value of the operand, and the instruction includes an identifier of a register where the operand is located, a source address of the operand in the register, and a primary operation code indicating the operation type indicated by the instruction; Parsing the instruction, reading an operand from a source address in a register indicated by the instruction, and determining a target operation type indicated by the instruction according to an operation code included in the instruction; The operand is processed by a data processing unit corresponding to the target operation type in the network chip to obtain a target processing result.

8. The network chip according to claim 7, characterized in that: Indicating that the instruction of the first type includes: a first major operation code, a first sub-operation code, a second sub-operation code, an operand length, a first source address of the first operand, a second source address of the second operand, an identifier of the first register, and an identifier of the second register; The first major operation code indicates that the operation type indicated by the instruction is the first type; The first sub-operation code indicates that the data calculation performed on the operand is a logic calculation, a shift calculation or an addition or subtraction calculation; In the case where the first sub-operation code indicates performing a logical calculation on an operand, the second sub-operation code indicates performing one of AND, OR, NOT, and XOR calculations; In the case where the first sub-operation code indicates that a shift calculation is performed on an operand, the second sub-operation code indicates that a logical left shift, a logical right shift or a circular shift is performed; In the case where the first sub-operation code indicates performing addition or subtraction calculations on operands, the second sub-operation code indicates performing addition or subtraction calculations; The first register is a register where the first operand is located and a register where the calculated result is to be stored, and the second register is a register where the second operand is located.

9. The network chip according to claim 7, characterized in that: The instruction indicating the second type includes: a second major opcode, a third sub-opcode, a source address where the operand was originally located, a destination address to which the operand is to be moved, an identifier of a source register where the operand was originally located, and an identifier of a destination register to which the operand is to be moved, wherein the third sub-opcode indicates: a discrete bit number of the operand to be moved; The second major operation code indicates that the operation type indicated by the instruction is the second type.

10. The network chip according to claim 7, characterized in that: When the operation type indicated by the instruction is the second type and the total number of discrete bits of the operands to be moved is greater than 1 bit, the instruction includes a first instruction indicating reading the operand and a second instruction indicating writing the operand; The first instruction includes: an identifier of a source register where each operand originally resides, a source address of each operand in the source register, a third sub-operation code, and a second main operation code; The second instruction includes: an identifier of a destination register to which each operand is to be moved, a destination address in the destination register to which each operand is to be moved, a third sub-operation code, and a second main operation code; The second major operation code indicates that the operation type indicated by the instruction is the second type.

11. The network chip according to claim 7, characterized in that: Indicating that the third type of instruction includes: a source address of an operand, an identifier of a source register where the operand is located, an offset of an access location to be jumped to in a memory, a fourth sub-operation code, and a third main operation code; The fourth sub-operation code is used to indicate a target value, and when the value of the operand is the target value, a memory access position is jumped; The third major operation code indicates that the operation type indicated by the instruction is the third type.

12. The network chip according to any one of claims 7 to 11, characterized in that: The data processing unit corresponding to the first type includes an adder subunit for performing addition calculation, a logic subunit for performing logic calculation, a shift subunit for performing shift processing, a mask subunit for calculating a mask, and an alignment subunit for performing data alignment; The data processing unit corresponding to the second type includes a mask subunit and a shift subunit; The data processing units corresponding to the third type include logic subunits and mask subunits.

13. An electronic device, characterized in that: The electronic device comprises: Network chips; Transceiver; A machine-readable storage medium storing machine-executable instructions that can be executed by the network chip; the machine-executable instructions prompt the network chip to execute the method steps described in any one of claims 1-6.

14. A network chip instruction processing device, characterized in that: Applied to a network chip, the device comprises: An instruction acquisition module is used to acquire instructions, wherein the operation type indicated by the instruction is: a first type, a second type or a third type, the first type indicates: performing data calculation on the operand, the second type indicates: moving the storage location of the operand, and the third type indicates: jumping the memory access location according to the value of the operand, and the instruction includes an identifier of the register where the operand is located, a source address of the operand in the register, and a main operation code indicating the operation type indicated by the instruction; An instruction parsing module, used to parse the instruction, read an operand from a source address in a register indicated by the instruction, and determine a target operation type indicated by the instruction according to an operation code contained in the instruction; The data processing module is used to process the operands through a data processing unit corresponding to the target operation type in the network chip to obtain a target processing result.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the network chip, the method steps described in any one of claims 1 to 6 are implemented.

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