Instruction generation method and device, electronic equipment and storage medium

Abstract

The invention provides an instruction generation method and device, electronic equipment and a storage medium. The instruction generation method comprises the steps of obtaining an instruction generation rule; generating a corresponding instruction based on the generation rule and a pre-generated instruction generator; wherein the instruction generator comprises a configuration information unit, an instruction library unit, an instruction generation unit and an instruction visualization unit; the configuration information unit is obtained based on preset operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted to the main control chip and the type of an instruction sent in the NFC; the instruction generation unit selects a corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit to perform instantiation processing to generate an instruction, sends the instruction to the DUT and stores the instruction to a TXT file to obtain the instruction; the instruction visualization unit is obtained by analyzing instruction information in the TXT file and conducting visualization processing through a preset program. The verification efficiency is improved by automatically generating an instruction generator for internal commands of different NAND particles and different NFCs.

Description

Technical Field

[0001] The present invention relates to the technical field of instruction generation, and in particular to an instruction generation method, device, electronic equipment and storage medium. Background Art

[0002] During the verification process of NFC (NAND Flash Controller), a series of technical challenges are faced. These challenges mainly come from the characteristics of NAND flash memory particles themselves and the need for NFC to interact with these particles efficiently and accurately. However, there are significant differences between NAND particles of different brands and models, including but not limited to page size, block size, read and write speed, erase count limit, etc. In addition, NFC also contains a large number of instructions, including but not limited to sending NAND addresses, NAND commands and other operations. This large number of instructions requires NFC to perform massive tests during verification to ensure the completeness of the verification. Summary of the invention

[0003] In view of this, the purpose of the present invention is to provide an instruction generation method, device, electronic device and storage medium, which can reduce manual intervention and improve verification efficiency by automatically generating an instruction generator for internal commands of different NAND particles and different NFCs.

[0004] In the first aspect, an embodiment of the present invention provides an instruction generation method, the method comprising: obtaining instruction generation rules; generating corresponding instructions based on the generation rules and a pre-generated instruction generator; the instruction generator comprises a configuration information unit, an instruction library unit, an instruction generation unit and an instruction visualization unit; wherein the configuration information unit is obtained based on pre-set operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted by the main control chip, and the type of instruction sent inside the NFC; the instruction generation unit selects a corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates the generated instruction, sends it to the DUT and stores it in a TXT file; the instruction visualization unit is obtained by parsing the instruction information in the TXT file and visualizing it through a pre-set program.

[0005] In a preferred embodiment of the present invention, the configuration information unit is obtained based on pre-set operation settings and parameters, including: configuration of operation settings corresponding to the test case; the operation settings include: reset and erase, and include: direct memory access write, direct memory access read at least one;

[0006] The parameters corresponding to the operation settings are configured; if the parameters corresponding to the operation settings are not configured, the parameters corresponding to the operation settings are determined to be default values.

[0007] In a preferred embodiment of the present invention, the instruction library unit is obtained based on the particle type and operation adapted by the main control chip, and the type of instruction sent inside the NFC, including: determining the corresponding target particle type and the instruction corresponding to the operation based on the particle type adapted by the main control chip, and designing an instruction generator corresponding to the manipulation of the particles; determining the type of instruction sent inside the NFC, and designing an instruction generator corresponding to the NFC.

[0008] In a preferred embodiment of the present invention, the above-mentioned determination of the corresponding target particle type and the instruction corresponding to the operation based on the particle type adapted by the main control chip, and designing the instruction generator corresponding to the manipulation particle include: defining the NAND instruction sequence as the NAND designated instruction in the designated instruction library of the NAND flash memory; the NAND designated instruction includes at least the following first operations: erase, program, read, write back, cache read, cache write, set function, get function, multi-plane read / write, multi-plane cache read / write, multi-plane write back and reset; obtaining the target instruction of each first operation in the ONFI protocol; the target instruction includes the instruction sent from the NFC to the NAND flash memory; based on the sending mode of the instruction sent from the NFC to the NAND flash memory, determining the operation instruction of each first operation; the sending mode includes sending commands and sending addresses; setting the address in the operation instruction to a random value, and setting other values ​​in the operation instruction except the address to a fixed value, and using macros as the distinction between different manipulation particles to complete the establishment of the class of each first operation.

[0009] In a preferred embodiment of the present invention, the instruction sequence defined in the NFC includes: pull ce, send address, send particle command and at least one second operation of reading and writing, determining the type of instruction sent in the NFC, and designing the instruction generator corresponding to the NFC, including: establishing a class for each second operation; wherein all values ​​in the operation instruction corresponding to the second operation are random values.

[0010] In a preferred embodiment of the present invention, the above-mentioned instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit for instantiation processing, generates instructions, sends them to the DUT and stores them in a TXT file, including: selecting the corresponding class from the instruction library unit for instantiation processing based on the configuration information provided by the configuration information unit; after the instantiation processing, sending the transmitted information to the DUT and storing it in the TXT file, so that the TXT file can be used to debug whether the DUT signal is the expected instruction.

[0011] In a preferred embodiment of the present invention, the instruction visualization unit is obtained by parsing the instruction information in the TXT file and performing visualization processing through a preset program, including: traversing the TXT file corresponding to the test case, parsing the instruction information according to the information in different instructions in NFC, and saving the parsed instructions into a list dictionary; normalizing all values ​​in the list dictionary through a preset library; and drawing a scatter plot based on the number of occurrences of the normalized values ​​to achieve visualization.

[0012] In the second aspect, an embodiment of the present invention also provides an instruction generation device, including: an instruction generation rule acquisition module, used to acquire instruction generation rules; an instruction generation module, used to generate corresponding instructions based on the generation rules and a pre-generated instruction generator; the instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit and an instruction visualization unit; wherein the configuration information unit is obtained based on pre-set operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted by the main control chip, and the type of instruction sent inside the NFC; the instruction generation unit selects an instruction template from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates it, and stores it in a TXT file; the instruction visualization unit is obtained by parsing the instruction information in the TXT file and visualizing it through a pre-set program.

[0013] In a third aspect, an embodiment of the present invention further provides an electronic device, including a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the instruction generation method of the first aspect above.

[0014] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the instruction generation method of the first aspect mentioned above.

[0015] The embodiments of the present invention bring the following beneficial effects:

[0016] The embodiment of the present invention provides an instruction generation method, device, electronic device and storage medium, which obtains instruction generation rules, generates corresponding instructions based on the generation rules and a pre-generated instruction generator; the instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit and an instruction visualization unit; wherein the configuration information unit is obtained based on pre-set operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted by the main control chip, and the type of instruction sent internally by the NFC; the instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates and generates instructions to send to the DUT and stores them in a TXT file; the instruction visualization unit is obtained by parsing the instruction information in the TXT file and visualizing it through a pre-set program. In this method, by automatically generating an instruction generator for internal commands of different NAND particles and different NFCs, manual intervention is reduced and verification efficiency is improved.

[0017] Other features and advantages of the present disclosure will be set forth in the following description, or some features and advantages may be inferred or unambiguously determined from the description, or may be learned by implementing the above-mentioned technology of the present disclosure.

[0018] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A flowchart of an instruction generation method provided by an embodiment of the present invention;

[0021] Figure 2 A flowchart of another instruction generation method provided by an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of the structure of an instruction generation device provided by an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] During the verification process of NFC (NAND Flash Controller), a series of technical challenges are faced. These challenges mainly come from the characteristics of NAND flash memory particles themselves and the need for NFC to interact with these particles efficiently and accurately. However, there are significant differences between NAND particles of different brands and models, including but not limited to page size, block size, read and write speed, erase count limit, etc. In addition, NFC also contains a large number of instructions, including but not limited to sending NAND addresses, NAND commands and other operations. This large number of instructions requires NFC to perform massive tests during verification to ensure the completeness of the verification.

[0026] Based on this, an instruction generation method, device, electronic device and storage medium provided by an embodiment of the present invention can generate corresponding instructions based on the generation rules and a pre-generated instruction generator by acquiring instruction generation rules; the instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit and an instruction visualization unit; wherein the configuration information unit is obtained based on the preset operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted by the main control chip, and the type of instruction sent internally by NFC; the instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit to instantiate and generate instructions to send to the DUT and store them in a TXT file; the instruction visualization unit is obtained by parsing the instruction information in the TXT file and visualizing it through a pre-set program. In this way, by automatically generating an instruction generator for internal commands for different NAND particles and different NFCs, manual intervention is reduced and verification efficiency is improved.

[0027] Specifically, at present, most NFC IC verification work relies on manually writing test instructions for specified NAND particles. This method is not only time-consuming and labor-intensive, but also prone to errors. With the increase in the types of NAND particles and the development of technology, the method of manually writing test instructions is increasingly difficult to meet the needs of rapid iteration. In the process of manually writing test instructions, it is often difficult to achieve random processing of parameters. This means that during the verification process, the performance of NFC in extreme conditions or abnormal situations may not be fully tested, thus affecting the stability and reliability of the final product. Due to time and resource constraints, the method of manually writing test instructions is difficult to cover all possible situations within a limited time.

[0028] For ease of understanding, the meanings of the terms / abbreviations in this application are explained below:

[0029] NFC (NAND Flash Controller): A controller that complies with the Open NAND Flash Interface (ONFI) standard.

[0030] OCB (on chip buffer): on-chip cache.

[0031] DLM (Data Local Memory): Data local memory.

[0032] UVM (Universal Verification Methodology): Unified Verification Methodology.

[0033] AGENT: functional unit.

[0034] DEBUG: Debug.

[0035] To facilitate understanding of this embodiment, a method for generating instructions disclosed in an embodiment of the present invention is first introduced in detail.

[0036] Example 1

[0037] The embodiment of the present invention provides a method for generating an instruction. Figure 1 A flowchart of an instruction generation method provided by an embodiment of the present invention. Figure 1 As shown, the instruction generation method may include the following steps:

[0038] Step S101, obtaining instruction generation rules.

[0039] Among them, the generation rules are set according to requirements.

[0040] The instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit and an instruction visualization unit.

[0041] Among them, the configuration information unit is obtained based on the preset operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted by the main control chip, and the type of instructions sent inside the NFC; the instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates the generated instruction, sends it to the DUT and stores it in a TXT file; the instruction visualization unit is obtained by parsing the instruction information in the TXT file and visualizing it through a preset program.

[0042] Among them, config is configuration information, which is the information that the user needs to send to the instruction generator; it corresponds to the configuration information unit.

[0043] Among them, instruction_lib is a collection of NAND and NFC custom instructions, which is essentially a database; it corresponds to the instruction library unit.

[0044] Among them, instr_gen determines which classes in instruction_lib to instantiate based on the configuration information, and is composed of instance_instruction_lib, pack_data_to_queue, output_data_to_file, and statistics_coverage. The main functions are: to instantiate the corresponding class from the instruction library based on the user's configuration information, and to process the instruction data into a format that can be directly input into the NFC verification platform; corresponding to the instruction generation unit.

[0045] Among them, a python script is used to read the internal information of TXT, visualize the instructions according to the TXT file, and determine the coverage of NAND instructions and NFC commands; corresponding to the visualization unit.

[0046] Specifically, the configuration information unit is obtained based on pre-set operation settings and parameters, and may include the following steps: configuring the operation settings corresponding to the test case; the operation settings include: reset and erase, and include: at least one of direct memory access write and direct memory access read; configuring the corresponding parameters for the operation settings; if the corresponding parameters for the operation settings are not configured, determining that the parameters corresponding to the operation settings are default values.

[0047] Among them, the user configures the operations that need to be done in the test case, such as sending erase, program, dma_w, and dma_r based on particles. When no settings are made, the default values ​​are used.

[0048] Among them, users can optionally configure internal parameters for operations such as erase, program, and NFC's internal dma_w. When randomness is not required, the corresponding random_parameter is set to zero, and the parameters with the prefix usr are set to a fixed value. When no setting is made, the default value is used.

[0049] Specifically, the instruction generation unit selects a corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, performs instantiation processing, and stores the instantiation processing in a TXT file, which may include steps B1 to B3:

[0050] Step B1: Select a corresponding class from the instruction library unit for instantiation based on the configuration information provided by the configuration information unit.

[0051] Among them, instance_instruction_lib selects a class from instruction_lib and instantiates the corresponding class according to the config information provided by the user. Here, the factory mechanism in UVM is used to create a class according to a string - create_object_by_name. The corresponding task is called and the instantiation of the corresponding class can be realized by passing in the parameter instr_class_name.

[0052] Step B2: After instantiation processing, the transmitted information is sent to the DUT and stored in a TXT file, so that the TXT file can be used to debug whether the DUT signal is the expected instruction.

[0053] The built-in functions pre_randomize and post_randomize in the class call the tasks in the class. For example, suppose the user passes the following information through the config information: cfg.instruction_queue.push_back("erase_slc_instruction_nand");

[0054] cfg.instruction_queue.push_back("program_slc_normal_nand");

[0055] cfg.instruction_queue.push_back("dmaw4k_list_nfc");

[0056] cfg.instruction_queue.push_back("read_slc_normal_nand");

[0057] cfg.instruction_queue.push_back("dmar4k_list_nfc").

[0058] The create_object_by_name can complete the instantiation of nand and nfc related classes in the instrction_lib database.

[0059] After instantiation, taking the erase operation as an example, pre_randomize() determines whether the information passed is the expected information (erase cfg related information), and post_randomize() calls random taskerase_piece_random_addr_instruction() or directed erase_piece_usr_addr_instruction() according to whether the cfg information is random; whether it is a directed or random task, its internal logic is to assign values, pass the configuration information to erase_slc_instruction, and then call print_parameter() to print the information, and finally through taskpush_instr_to_queue(), store it in the queue in the form of instructions required by DUT. Repeat the above operations according to the cfg information to complete the storage of all instructions.

[0060] push_data_to_dut, on the one hand, sends the above-generated instructions to the DUT, and on the other hand, adds the information to the relevant instructions to explain them, and then saves them to a TXT file to facilitate subsequent operations and debugging of subsequent test cases.

[0061] Specifically, the instruction visualization unit is obtained by parsing the instruction information in the TXT file and performing visualization processing through a preset program, which may include: traversing the TXT file corresponding to the test case, parsing the instruction information according to the information in different instructions in NFC, and saving the parsed instructions into a list dictionary; normalizing all values ​​in the list dictionary through a preset library; and drawing a scatter plot based on the number of occurrences of the normalized values ​​to achieve visualization.

[0062] Among them, all TXT information of the regression test case is traversed, and the instructions are parsed according to all the information in different instructions in NFC, and each instruction is saved in a list dictionary. Through the python library matplotlib, all values ​​in the list dictionary are normalized, and a scatter plot is drawn according to the number of times the values ​​appear in the list.

[0063] Step S102: Generate corresponding instructions based on the generation rules and the pre-generated instruction generator.

[0064] Among them, by inputting the generation rules into the instruction generator, the corresponding instructions can be generated.

[0065] In practical applications, the specification data of different types of NAND particles and NFC-related instructions can be systematized to form a professional database. This management method is not only convenient for subsequent query and maintenance, but also can quickly adapt to the emergence of new particles and technological changes.

[0066] In actual applications, users can flexibly configure test cases through config files, supporting the generation of directional and randomized instructions. This feature enables users to quickly generate required instructions according to specified test requirements, avoiding the inefficiency and error risks caused by manual processing, and improving the convenience and flexibility of operation.

[0067] In practical applications, by automatically generating instructions, the present invention effectively reduces the reliance on manual writing, avoids time-consuming manual processes, and reduces related human resource costs, especially when there are many types of NAND particles, saving a lot of time and energy.

[0068] In practical applications, the test results can be visualized through Python scripts to help users intuitively understand the instruction coverage. This not only helps users to conduct subsequent analysis and decision-making, but also improves the transparency of the verification process and makes the verification of NFC complete.

[0069] The instruction generation method provided by the embodiment of the present invention can obtain instruction generation rules, generate corresponding instructions based on the generation rules and a pre-generated instruction generator; the instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit and an instruction visualization unit; wherein the configuration information unit is obtained based on the preset operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted by the main control chip, and the type of instruction sent internally by the NFC; the instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit to instantiate and generate instructions to send to the DUT and store them in a TXT file; the instruction visualization unit is obtained by parsing the instruction information in the TXT file and visualizing it through a pre-set program. In this way, by automatically generating an instruction generator for internal commands of different NAND particles and different NFCs, manual intervention is reduced and verification efficiency is improved.

[0070] Example 2

[0071] The embodiment of the present invention also provides another instruction generation method; this method is implemented on the basis of the method in the above embodiment; this method focuses on describing the specific implementation method obtained by the instruction library unit based on the particle type and operation adapted by the main control chip, and the type of instructions sent inside the NFC.

[0072] Figure 2 A flowchart of another instruction generation method provided by an embodiment of the present invention, such as Figure 2 As shown, the instruction library unit is obtained based on the particle type and operation adapted by the main control chip and the type of instructions sent inside the NFC, and may include the following steps:

[0073] Step S201, based on the particle type adapted by the main control chip, the corresponding target particle type and the corresponding operation instruction are determined, and the instruction generator corresponding to the operation particle is designed.

[0074] Specifically, based on the particle type adapted by the main control chip, the corresponding target particle type and the corresponding operation instruction are determined, and the instruction generator corresponding to the operation particle is designed, which may include the following steps A1-A4:

[0075] Step A1, define a NAND instruction sequence as a NAND designated instruction in a designated instruction library of a NAND flash memory; the NAND designated instruction includes at least the following first operations: erase, program, read, write back, cache read, cache write, set function, get function, multi-plane read / write, multi-plane cache read / write, multi-plane write back and reset.

[0076] Among them, the command sequence defined in nand_spec_instruction_lib is mainly the command of nand_spec, including operations such as erase, program, read, set_feature, get_feature, copyback and reset.

[0077] Step A2, obtaining a target instruction of each first operation in the ONFI protocol; the target instruction includes an instruction sent from the NFC to the NAND flash memory.

[0078] Step A3, determining the operation instruction of each first operation based on the sending mode of the instruction sent from the NFC to the NAND flash memory; the sending mode includes sending a command and sending an address;

[0079] Step A4, setting the address in the operation instruction to a random value, setting other values ​​in the operation instruction except the address to a fixed value, and using macros as a distinction between different manipulation particles to complete the establishment of each first operation class.

[0080] Among them, these operations are respectively established into a class. Take the erase operation as an example. In the ONFI (Open NAND Flash Interface) protocol, its instruction is 06h-addr (NAND address)-d0h, where 00h and 60h are the instructions sent by NFC to NAND. Assume that the instruction for sending the command in NFC is 3xh, and the instruction for sending the address is 4xh (where x represents the length of the sent instruction plus one). Therefore, the NFC operation completes the erase operation on the NAND particle. The actual instruction that needs to be obtained from the DLM is 30h-60h-42h-addr*3-30h-d0h. Here, the address is set to rand bit (random value), and the others are set to fixed values. In fact, the length of the NAND address, as well as the block address, lun address, and page address are defined differently by different brands. Here, macros are used to distinguish different particles. For example, assuming that the row address of a particle is 3, its corresponding page address is {addr address1[5:0], addr address0[7:0]}, its block address is {addr address2[5:0], addr address1[7:6]}, and its lun address is addr address2[7:6]. The address is assigned within the class; repeat similar operations from step A1 to step A4 to complete the establishment of other classes respectively.

[0081] Step S202, determine the type of command sent inside NFC and design a command generator corresponding to NFC.

[0082] Among them, the instruction sequence defined inside NFC includes: pulling ce, sending address, sending particle command and at least one second operation of reading and writing. Determining the type of instructions sent inside NFC and designing the instruction generator corresponding to NFC may include: establishing a class for each second operation; wherein all values ​​in the operation instruction corresponding to the second operation are random values.

[0083] Among them, the command sequence defined by NFC mainly includes operations such as pulling ce, sending address, sending particle command, reading and writing. A class is established in the way of step A1-step A4. Here, take the write instruction as an example. The internal information of a write instruction includes information about scrambling and descrambling, ldpc, and reading back several 4k. Different from the previous particle-related operations, all the information here may be random.

[0084] The instruction generation method provided by the embodiment of the present invention effectively reduces the reliance on manual writing, avoids the time-consuming manual process, and reduces the related human resource costs, especially when there are many types of NAND particles, saving a lot of time and energy.

[0085] Example 3

[0086] Corresponding to the above method embodiment, the embodiment of the present invention provides an instruction generating device, Figure 3 A schematic diagram of the structure of an instruction generation device provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the instruction generating device may include:

[0087] The instruction generation rule acquisition module 301 is used to acquire instruction generation rules.

[0088] The instruction generation module 302 is used to generate corresponding instructions based on generation rules and a pre-generated instruction generator; the instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit and an instruction visualization unit.

[0089] Among them, the configuration information unit is obtained based on the preset operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted by the main control chip, and the type of instructions sent inside NFC; the instruction generation unit selects an instruction template from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates it, and stores it in a TXT file; the instruction visualization unit is obtained by parsing the instruction information in the TXT file and visualizing it through a preset program.

[0090] The instruction generation device provided by the embodiment of the present invention can obtain instruction generation rules, generate corresponding instructions based on the generation rules and a pre-generated instruction generator; the instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit and an instruction visualization unit; wherein the configuration information unit is obtained based on pre-set operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted by the main control chip, and the type of instruction sent internally by NFC; the instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit to instantiate and generate instructions to send to DUT and store them in a TXT file; the instruction visualization unit is obtained by parsing the instruction information in the TXT file and visualizing it through a pre-set program. In this way, by automatically generating an instruction generator for internal commands of different NAND particles and different NFCs, manual intervention is reduced and verification efficiency is improved.

[0091] In some embodiments, the instruction generation module is also used to configure the operation settings corresponding to the test case; the operation settings include: reset and erase, and include: at least one of direct memory access write and direct memory access read;; the parameters corresponding to the operation settings are configured; if the parameters corresponding to the operation settings are not configured, the parameters corresponding to the operation settings are determined to be default values.

[0092] In some embodiments, the instruction generation module is also used to determine the corresponding target particle type and the corresponding operation instructions based on the particle type adapted by the main control chip, and design the instruction generator corresponding to the operation particles; determine the type of instructions sent inside NFC, and design the corresponding instruction generator for NFC.

[0093] In some embodiments, the instruction generation module is further used to define NAND specified instructions in the specified instruction library of the NAND flash memory, including at least the following first operations: erase, program, read, write back, cache read, cache write, set function, get function, multi-plane read / write, multi-plane cache read / write, multi-plane write back and reset; obtain the target instruction of each first operation in the ONFI protocol; the target instruction includes the instruction sent from the NFC to the NAND flash memory; based on the sending method of the instruction sent from the NFC to the NAND flash memory, determine the operation instruction of each first operation; the sending method includes sending a command and sending an address; set the address in the operation instruction to a random value, set other values ​​in the operation instruction except the address to a fixed value, and use macros as a distinction between different manipulation particles to complete the establishment of a class for each first operation.

[0094] In some embodiments, the instruction sequence defined within NFC includes: pull ce, send address, send particle command and at least one second operation of reading and writing, and the instruction generation module is also used to establish a class for each second operation; wherein all values ​​in the operation instruction corresponding to the second operation are random values.

[0095] In some embodiments, the instruction generation module is also used to select a corresponding class from the instruction library unit for instantiation processing based on the configuration information provided by the configuration information unit; after the instantiation processing, the transmitted information is sent to the DUT and stored in a TXT file, so that the TXT file can be used to debug whether the DUT signal is the expected instruction.

[0096] In some embodiments, the instruction generation module is also used to traverse the TXT file corresponding to the test case, parse the instruction information according to the information in different instructions in NFC, and save the parsed instructions into a list dictionary; normalize all values ​​in the list dictionary through a pre-set library; and draw a scatter plot based on the number of occurrences of the normalized values ​​to achieve visualization.

[0097] The device provided in the embodiment of the present invention has the same implementation principle and technical effects as those of the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0098] Example 4

[0099] The embodiment of the present invention also provides an electronic device for executing the above instruction generation method; see Figure 4 A structural diagram of an electronic device is shown, the electronic device includes a memory 400 and a processor 401, wherein the memory 400 is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor 401 to implement the above-mentioned instruction generation method.

[0100] Further, Figure 4 The electronic device shown further includes a bus 402 and a communication interface 403 , and the processor 401 , the communication interface 403 and the memory 400 are connected via the bus 402 .

[0101] The memory 400 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk storage. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 403 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used. The bus 402 may be an ISA bus, a PCI bus, or an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0102] The processor 401 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 401. The above processor 401 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present invention can be directly embodied as a hardware decoding processor for execution, or a combination of hardware and software modules in the decoding processor for execution. The software module may be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 400, and the processor 401 reads the information in the memory 400 and completes the steps of the method of the above embodiment in combination with its hardware.

[0103] An embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the above-mentioned instruction generation method. The specific implementation can be found in the method embodiment, which will not be repeated here.

[0104] The computer program product for performing the instruction generation method provided in the embodiment of the present invention includes a computer-readable storage medium storing a non-volatile program code executable by a processor. The instructions included in the program code can be used to execute the method described in the previous method embodiment. The specific implementation can be found in the method embodiment and will not be repeated here.

[0105] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0106] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0107] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0108] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0109] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0110] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for generating an instruction, characterized in that: The method comprises: Get instruction generation rules; Generate corresponding instructions based on the generation rules and the pre-generated instruction generator; the instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit and an instruction visualization unit; Among them, the configuration information unit is obtained based on preset operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted by the main control chip, and the type of instructions sent inside NFC; the instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates the generated instruction, sends it to the DUT and stores it in a TXT file; the instruction visualization unit is obtained by parsing the instruction information in the TXT file and visualizing it through a preset program.

2. The method according to claim 1, characterized in that The configuration information unit is obtained based on pre-set operation settings and parameters, including: Configure operation settings corresponding to the test case; the operation settings include: reset and erase, and include: at least one of direct memory access write and direct memory access read; Setting parameters corresponding to the operation configuration; If the parameters corresponding to the operation settings are not configured, the parameters corresponding to the operation settings are determined to be default values.

3. The method according to claim 1, characterized in that The instruction library unit is obtained based on the particle type and operation adapted by the main control chip and the type of instructions sent inside the NFC, including: Determine the corresponding target particle type and the instruction corresponding to the operation based on the particle type adapted by the main control chip, and design an instruction generator corresponding to the operation particle; Determine the type of command sent inside the NFC and design a command generator corresponding to the NFC.

4. The method according to claim 3, characterized in that The step of determining the corresponding target particle type and the instruction corresponding to the operation based on the particle type adapted by the main control chip, and designing the instruction generator corresponding to the operation particle includes: A NAND instruction sequence is defined as a NAND designated instruction in a designated instruction library of a NAND flash memory; the NAND designated instruction includes at least the following first operations: erase, program, read, write back, cache read, cache write, set function, get function, multi-plane read / write, multi-plane cache read / write, multi-plane write back and reset; Obtaining a target instruction of each of the first operations in the ONFI protocol; the target instruction includes an instruction sent from the NFC internal to the NAND flash memory; Determine the operation instruction of each of the first operations based on the sending mode of the instruction sent from the NFC to the NAND flash memory; the sending mode includes sending a command and sending an address; The address in the operation instruction is set to a random value, and other values ​​in the operation instruction except the address are set to fixed values. Macros are used as a distinction between different operation particles to complete the establishment of each class of the first operation.

5. The method according to claim 4, characterized in that The instruction sequence defined in the NFC includes: pull ce, send address, send particle command and at least one second operation of reading and writing, and the determining the type of the instruction sent in the NFC and designing the instruction generator corresponding to the NFC includes: A class is established for each of the second operations; wherein all values ​​in the operation instructions corresponding to the second operations are random values.

6. The method according to claim 1, characterized in that The instruction generation unit selects a corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, performs instantiation processing, generates instructions, sends them to the DUT, and stores them in a TXT file, including: Selecting a corresponding class from the instruction library unit for instantiation processing based on the configuration information provided by the configuration information unit; After instantiation processing, the transmitted information is sent to the DUT and stored in a TXT file, so that the TXT file can be used to debug whether the DUT signal is the expected instruction.

7. The method according to claim 6, characterized in that The instruction visualization unit is obtained by parsing the instruction information in the TXT file and performing visualization processing through a preset program, including: Traverse the TXT files corresponding to the test cases, parse the instruction information according to the information in different instructions in NFC, and save the parsed instructions into a list dictionary; Normalizing all values ​​in the list dictionary using a preset library; Draw a scatter plot based on the number of times the normalized values ​​occur for visualization.

8. An instruction generating device, characterized in that: The device comprises: An instruction generation rule acquisition module, used to acquire instruction generation rules; An instruction generation module, used to generate corresponding instructions based on the generation rules and a pre-generated instruction generator; the instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit and an instruction visualization unit; Among them, the configuration information unit is obtained based on preset operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted by the main control chip, and the type of instructions sent inside NFC; the instruction generation unit selects an instruction template from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates the generated instruction, sends it to the DUT and stores it in a TXT file; the instruction visualization unit is obtained by parsing the instruction information in the TXT file and visualizing it through a preset program.

9. An electronic device, characterized in that: The invention comprises a processor and a memory, wherein the memory stores computer executable instructions that can be executed by the processor, and the processor executes the computer executable instructions to implement the instruction generation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the instruction generation method according to any one of claims 1 to 7.

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