Instruction generation method and apparatus, electronic device, and storage medium

Abstract

The application provides an instruction generation method and device, electronic equipment and a storage medium, comprising: obtaining an instruction generation rule; generating a corresponding instruction based on the generation rule and a pre-generated instruction generator; wherein the instruction generator comprises a configuration information unit, an instruction library unit, an instruction generation unit and an instruction visualization unit; the configuration information unit is obtained based on pre-set operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted to the master control chip and the type of internal instruction sending of the NFC; the instruction generation unit generates an instruction by selecting a corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, instantiating the class, sending the instruction to the DUT and storing the instruction to a TXT file; and the instruction visualization unit obtains the visualization processing by analyzing the instruction information in the TXT file and through a pre-set program. The instruction generator for the internal commands of different NAND particles and different NFCs is automatically generated, and the verification efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of instruction generation technology, and in particular to an instruction generation method, apparatus, electronic device, and storage medium. Background Technology

[0002] The verification process for NFC (NAND Flash Controller) faces a series of technical challenges. These challenges primarily stem from the characteristics of NAND flash memory chips themselves and the need for NFC to interact with these chips efficiently and accurately. However, there are significant differences between NAND chips of different brands and models, including but not limited to page size, block size, read / write speed, and erase cycle limits. Furthermore, NFC contains a large number of instructions, including but not limited to sending NAND addresses and NAND commands. This large number of instructions necessitates extensive testing during NFC verification to ensure its completeness. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide an instruction generation method, apparatus, electronic device and storage medium, which reduces manual intervention and improves verification efficiency by automatically generating an instruction generator for internal commands of different NAND chips and different NFCs.

[0004] In a first aspect, embodiments of the present invention provide an instruction generation method, the method comprising: acquiring instruction generation rules; generating corresponding instructions based on the generation rules and a pre-generated instruction generator; the instruction generator comprising a configuration information unit, an instruction library unit, an instruction generation unit, and an instruction visualization unit; wherein, the configuration information unit is obtained based on pre-set operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted to the main control chip, as well as the types of internal NFC transmission instructions; the instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, performs instantiation processing to generate instructions, sends them to the DUT, and stores them in a TXT file; the instruction visualization unit obtains the instructions by parsing the instruction information in the TXT file and performing visualization processing through a pre-set program.

[0005] In a preferred embodiment of the present invention, the above-mentioned configuration information unit is obtained based on pre-set operation settings and parameters, including: operation settings corresponding to the configuration test cases; the operation settings include: reset and erase, and include at least one of: direct memory access write and direct memory access read;

[0006] Configure the corresponding parameters for the operation settings; if no corresponding parameters are configured for the operation settings, then the parameters for the operation settings will be set to their default values.

[0007] In a preferred embodiment of the present invention, the above-mentioned instruction library unit is obtained based on the particle type and operation adapted to the main control chip, as well as the types of internal NFC transmission instructions, including: determining the corresponding target particle type and the corresponding instructions for the operation based on the particle type adapted to the main control chip, and designing an instruction generator corresponding to the manipulated particle; determining the types of internal NFC transmission instructions, and designing an instruction generator corresponding to NFC.

[0008] In a preferred embodiment of the present invention, the above-mentioned determination of the corresponding target particle type and operation instructions based on the particle type adapted to the main control chip, and the design of the instruction generator corresponding to the manipulated particle, includes: defining NAND instruction sequences as NAND specified instructions in a specified instruction library of NAND flash memory; the NAND specified instructions include at least the following first operations: erase, program, read, write back, cache read, cache write, set function, get function, multi-plane read / write, multi-plane cache read / write, multi-plane write back, and reset; obtaining the target instruction of each first operation in the ONFI protocol; the target instruction includes the instruction sent from the NFC internal to the NAND flash memory; determining the operation instruction of each first operation based on the transmission method of the instruction sent from the NFC internal to the NAND flash memory; the transmission method includes sending a command and sending an address; setting the address in the operation instruction to a random value, setting other values ​​in the operation instruction besides the address to a fixed value, and using macros to distinguish different manipulated particles to complete the establishment of the class of each first operation.

[0009] In a preferred embodiment of the present invention, the instruction sequence defined internally by the NFC includes at least one second operation among: pull ce, send address, send granular command, and read / write. The type of internal NFC transmission instruction is determined, and an instruction generator corresponding to the NFC is designed, including: establishing a class for each second operation; wherein all values ​​in the operation instruction corresponding to the second operation are random values.

[0010] In a preferred embodiment of the present invention, the instruction generation unit selects a corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, performs instantiation processing to generate instructions, sends them to the DUT, and stores them in a TXT file. This includes: selecting a corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit and performing instantiation processing; after instantiation processing, sending the transmitted information to the DUT and storing it in a TXT file, so that the TXT file can be used to debug whether the DUT signal is the expected instruction.

[0011] In a preferred embodiment of the present invention, the instruction visualization unit obtains the instruction information by parsing the instruction information in the TXT file and performing visualization processing through a pre-set program, including: traversing the TXT file corresponding to the test case, parsing the instruction information according to the information in different instructions in NFC, and saving the parsed instructions to a list dictionary; normalizing all values ​​in the list dictionary through a pre-set library; and drawing a scatter plot based on the frequency of occurrence of the normalized values ​​to achieve visualization.

[0012] Secondly, embodiments of the present invention also provide an instruction generation device, comprising: an instruction generation rule acquisition module for acquiring instruction generation rules; an instruction generation module for generating corresponding instructions based on the generation rules and a pre-generated instruction generator; the instruction generator comprising a configuration information unit, an instruction library unit, an instruction generation unit, and an instruction visualization unit; wherein, the configuration information unit is obtained based on pre-set operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted to the main control chip, as well as the types of NFC internal transmission instructions; the instruction generation unit selects an instruction template from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates it, and stores it in a TXT file; the instruction visualization unit obtains the instruction by parsing the instruction information in the TXT file and performing visualization processing through a pre-set program.

[0013] Thirdly, embodiments of the present invention also provide an electronic device, including a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the instruction generation method of the first aspect described above.

[0014] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are invoked and executed by a processor, the computer-executable instructions cause the processor to implement the instruction generation method of the first aspect described above.

[0015] The embodiments of the present invention bring the following beneficial effects:

[0016] This invention provides an instruction generation method, apparatus, electronic device, and storage medium. The method involves acquiring instruction generation rules and generating corresponding instructions based on these rules and a pre-generated instruction generator. The instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit, and an instruction visualization unit. The configuration information unit is based on pre-set operation settings and parameters. The instruction library unit is based on the type of NAND flash memory and its operation, as well as the types of internal NFC transmission instructions. The instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates the generated instruction, sends it to the DUT (Distributed Under Test) and stores it in a TXT file. The instruction visualization unit parses the instruction information in the TXT file and performs visualization processing using a pre-set program. This method automatically generates instruction generators for different NAND flash memory chips and different NFC internal commands, reducing manual intervention and improving verification efficiency.

[0017] Other features and advantages of this disclosure will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0018] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 A flowchart of an instruction generation method provided in an embodiment of the present invention;

[0021] Figure 2 A flowchart of another instruction generation method provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the structure of an instruction generation device provided in an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] The verification process for NFC (NAND Flash Controller) faces a series of technical challenges. These challenges primarily stem from the characteristics of NAND flash memory chips themselves and the need for NFC to interact with these chips efficiently and accurately. However, there are significant differences between NAND chips of different brands and models, including but not limited to page size, block size, read / write speed, and erase cycle limits. Furthermore, NFC contains a large number of instructions, including but not limited to sending NAND addresses and NAND commands. This large number of instructions necessitates extensive testing during NFC verification to ensure its completeness.

[0026] Based on this, the present invention provides an instruction generation method, apparatus, electronic device, and storage medium that can generate corresponding instructions by acquiring instruction generation rules and generating corresponding instructions based on the generation rules and a pre-generated instruction generator. The instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit, and an instruction visualization unit. The configuration information unit is obtained based on pre-set operation settings and parameters; the instruction library unit is obtained based on the type of NAND flash memory and operation adapted to the main control chip, as well as the types of internal NFC transmission instructions; the instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, performs instantiation processing to generate instructions, sends them to the DUT, and stores them in a TXT file; the instruction visualization unit parses the instruction information in the TXT file and performs visualization processing through a pre-set program. In this method, by automatically generating instruction generators for different NAND flash memory chips and different NFC internal commands, manual intervention is reduced and verification efficiency is improved.

[0027] Specifically, currently, most NFC IC verification work relies on manually writing test instructions for specific NAND flash memory chips. This method is not only time-consuming and labor-intensive, but also prone to errors. With the increasing variety of NAND flash memory chips and technological advancements, manually writing test instructions is becoming increasingly difficult to meet the demands of rapid iteration. Furthermore, it is often difficult to randomize parameters during the manual writing of test instructions. This means that the performance of NFC under extreme or abnormal conditions may not be fully tested during verification, thus affecting the stability and reliability of the final product. Due to time and resource constraints, manually writing test instructions makes it difficult to cover all possible scenarios within a limited timeframe.

[0028] For ease of understanding, the meanings of the terms / abbreviations used in this application are explained as follows:

[0029] NFC (NAND Flash Controller): A controller that conforms to the Open NAND Flash Interface (ONFI) standard.

[0030] OCB (on-chip buffer): On-chip buffer.

[0031] DLM (Data Local Memory): Data local storage.

[0032] UVM (Universal Verification Methodology): A unified verification methodology.

[0033] AGENT: Functional Unit.

[0034] DEBUG: Debugging.

[0035] To facilitate understanding of this embodiment, a method for generating instructions disclosed in this embodiment of the invention will first be described in detail.

[0036] Example 1

[0037] This invention provides an instruction generation method. Figure 1 This is a flowchart illustrating an instruction generation method provided in an embodiment of the present invention. Figure 1 As shown, the instruction generation method may include the following steps:

[0038] Step S101: Obtain the instruction generation rules.

[0039] The generation rules are set according to requirements.

[0040] The instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit, and an instruction visualization unit.

[0041] The configuration information unit is based on pre-set operation settings and parameters; the instruction library unit is based on the particle type and operation adapted to the main control chip, as well as the types of internal NFC transmission instructions; the instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, performs instantiation processing to generate instructions, sends them to the DUT, and stores them in a TXT file; the instruction visualization unit obtains the instruction information by parsing the instruction information in the TXT file and performing visualization processing through a pre-set program.

[0042] Here, config is the configuration information, which is the information that the user needs to send to the instruction generator; it corresponds to the configuration information unit.

[0043] Among them, instruction_lib is a collection of custom instructions for NAND and NFC, which is essentially a database; it corresponds to the instruction library unit.

[0044] The `instr_gen` function determines which classes in `instruction_lib` to instantiate based on configuration information. It consists of `instance_instruction_lib`, `pack_data_to_queue`, `output_data_to_file`, and `statistics_coverage`. Its main functions are: instantiating the corresponding classes from the instruction library based on the user's configuration information, and processing the instruction data into a format that can be directly input into the NFC verification platform; this corresponds to the instruction generation unit.

[0045] The system uses a Python script to read the internal information of a TXT file, visualizes the instructions based on the TXT file, and determines the coverage of NAND instructions and NFC commands; corresponding to the visualization unit.

[0046] Specifically, the configuration information unit is obtained based on pre-set operation settings and parameters, and may include the following steps: configuring the operation settings corresponding to the test case; the operation settings include: reset and erase, and include at least one of: direct memory access write and direct memory access read; configuring the corresponding parameters for the operation settings; if no corresponding parameters are configured for the operation settings, the parameters corresponding to the operation settings are determined to be default values.

[0047] Among them, the operations that users need to perform when configuring test cases, such as sending erase, program, dma_w, and dma_r based on granularity, will use the default values ​​when not set.

[0048] Users can optionally configure internal parameters for operations such as erase, program, and dma_w within NFC. When randomness is not required, the corresponding random_parameter is set to zero, parameters prefixed with usr are set to fixed values, and default values ​​are used when no settings are made.

[0049] Specifically, the instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates it, and stores it in a TXT file. This process may include steps B1-B3.

[0050] Step B1: Based on the configuration information provided by the configuration information unit, select the corresponding class from the instruction library unit for instantiation.

[0051] The `instance_instruction_lib` function selects and instantiates a class from the `instruction_lib` based on the user-provided configuration information. It uses the UVM factory mechanism, specifically `create_object_by_name`, to create a class based on a string. The corresponding task is then invoked, and the instantiation of the class is achieved by passing the `instr_class_name` parameter.

[0052] Step B2: After instantiation, the transmitted information is sent to the DUT and stored in a TXT file, which is used to debug whether the DUT signals are the expected instructions.

[0053] The built-in functions `pre_randomize` and `post_randomize` within the class call the tasks within that class. For example, suppose a user passes the following information via configuration: `cfg.instruction_queue.push_back(“erase_slc_instruction_nand”);`

[0054] cfg.instruction_queue.push_back("program_slc_normal_nand");

[0055] cfg.instruction_queue.push_back("dmaw4k_list_nfc");

[0056] cfg.instruction_queue.push_back("read_slc_normal_nand");

[0057] cfg.instruction_queue.push_back("dmar4k_list_nfc").

[0058] The `create_object_by_name` function can instantiate NAND and NFC-related classes in the `instruction_lib` database.

[0059] After instantiation, taking the erase operation as an example, `pre_randomize()` determines whether the passed information is the expected information (related to the erase cfg). `post_randomize()` determines whether the cfg information randomly calls either `random_task_piece_random_addr_instruction()` or a directed `task_piece_usr_addr_instruction()`. Regardless of whether it's a directed or random task, the internal logic is to assign values, passing the configuration information to `erase_slc_instruction`, then calling `print_parameter()` to print the information, and finally using `taskpush_instr_to_queue()` to store the instructions required by the DUT in the queue. The above operations are repeated based on the cfg information to complete the storage of all instructions.

[0060] The push_data_to_dut command sends the generated instructions to the DUT and adds information to the instr_mean command to explain the relevant instructions. The data is then saved to a TXT file for later use and for debugging test cases.

[0061] Specifically, the instruction visualization unit obtains the instruction information by parsing the instruction information in the TXT file and performing visualization processing through a pre-set program. This may include: traversing the TXT file corresponding to the test case, parsing the instruction information according to the information in different instructions in NFC, and saving the parsed instructions to a list dictionary; normalizing all values ​​in the list dictionary through a pre-set library; and drawing a scatter plot based on the frequency of occurrence of the normalized values ​​to achieve visualization.

[0062] The process involves iterating through all the TXT information of the regression test cases, parsing the instructions based on all the information in the different instructions in the NFC, saving each instruction into a list dictionary, normalizing all the values ​​in the list dictionary using the Python library matplotlib, and plotting a scatter plot based on the frequency of the values ​​in the list.

[0063] Step S102: Generate corresponding instructions based on the generation rules and the pre-generated instruction generator.

[0064] By inputting the generation rules into the instruction generator, corresponding instructions can be generated.

[0065] In practical applications, the specifications and data of different types of NAND flash memory chips and NFC-related instructions can be systematically organized into a professional database. This management approach not only facilitates subsequent queries and maintenance but also allows for rapid adaptation to the emergence of new types of chips and technological changes.

[0066] In practical applications, users can flexibly configure test cases through config files, supporting the generation of targeted and randomized instructions. This feature enables users to quickly generate the required instructions according to specified test requirements, avoiding the inefficiency and error risks caused by manual processing, and improving the convenience and flexibility of operation.

[0067] In practical applications, by automatically generating instructions, this invention effectively reduces reliance on manual programming, avoids time-consuming manual processes, and reduces related human resource costs. Especially when there are many types of NAND flash memory chips, it saves a lot of time and effort.

[0068] In practical applications, test results can be visualized using Python scripts, helping users to intuitively understand the instruction coverage. This not only helps users with subsequent analysis and decision-making but also improves the transparency of the verification process, making NFC verification complete.

[0069] The instruction generation method provided in this invention can generate corresponding instructions by acquiring instruction generation rules and generating corresponding instructions based on the rules and a pre-generated instruction generator. The instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit, and an instruction visualization unit. The configuration information unit is based on pre-set operation settings and parameters. The instruction library unit is based on the type of NAND flash memory and operation adapted to the main control chip, as well as the types of internal NFC transmission instructions. The instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates it, generates instructions, sends them to the DUT, and stores them in a TXT file. The instruction visualization unit parses the instruction information in the TXT file and performs visualization processing through a pre-set program. This method automatically generates instruction generators for different NAND flash memory chips and different NFC internal commands, reducing manual intervention and improving verification efficiency.

[0070] Example 2

[0071] This invention also provides another instruction generation method; this method is implemented based on the method of the above embodiments; this method focuses on describing the specific implementation of the instruction library unit based on the particle type and operation adapted to the main control chip, as well as the types of instructions sent internally by NFC.

[0072] Figure 2 A flowchart of another instruction generation method provided in an embodiment of the present invention is shown below. Figure 2 As shown, this instruction library unit is derived based on the type of granular material and operation adapted to the main control chip, as well as the types of internal NFC transmission instructions, and may include the following steps:

[0073] Step S201: Based on the type of particle that the main control chip is compatible with, determine the corresponding target particle type and the corresponding operation instructions, and design the instruction generator corresponding to the manipulation particle.

[0074] Specifically, based on the type of particle that the main control chip is compatible with, the corresponding target particle type and the corresponding operation instructions are determined, and the instruction generator corresponding to the manipulation particle is designed, which may include the following steps A1-A4:

[0075] Step A1: Define NAND instruction sequences as NAND specified instructions in the specified instruction library of NAND flash memory; NAND specified instructions include at least the following first operations: erase, program, read, write back, cache read, cache write, set function, get function, multi-plane read / write, multi-plane cache read / write, multi-plane write back and reset.

[0076] The command sequence defined in nand_spec_instruction_lib is mainly the command of nand_spec, which includes operations such as erase, program, read, set_feature, get_feature, copyback and reset.

[0077] Step A2: Obtain the target instruction for each first operation in the ONFI protocol; the target instruction includes the instruction sent from within the NFC to the NAND flash memory.

[0078] Step A3: Based on the transmission method of the instructions sent from the NFC internally to the NAND flash memory, determine the operation instructions for each first operation; the transmission method includes sending commands and sending addresses;

[0079] Step A4: Set the address in the operation instruction to a random value, and set other values ​​in the operation instruction other than the address to fixed values. Use macros to distinguish different manipulation particles to complete the establishment of the class for each first operation.

[0080] These operations are divided into separate classes. Taking the erase operation as an example, in the ONFI (Open NAND Flash Interface) protocol, the instruction is 06h-addr (NAND address)-d0h, where 00h and 60h are the instructions sent from NFC to the NAND. Assuming the instruction to send a command in NFC is 3xh, and the instruction to send an address is 4xh (where x represents the length of the instruction plus one), the actual instruction needed to obtain from the DLM to complete the erase operation on the NAND chip via NFC is 30h-60h-42h-addr*3-30h-d0h. Here, the address is set to a rand bit (random value), and the others are set to fixed values. In reality, the length of the NAND address, as well as the block address, LUN address, and page address, have different definitions for different brands; here, macros are used to distinguish different chips. For example, suppose a particle has a row address of 3, its corresponding page address is {addr address1[5:0], addr address0[7:0]}, its block address is {addr address2[5:0], addr address1[7:6]}, and its LUN address is addr address2[7:6]. The address assignment is completed inside the class. Repeat similar operations from steps A1 to A4 to complete the creation of other classes.

[0081] Step S202: Determine the types of internal NFC transmission commands and design the corresponding NFC command generator.

[0082] The instruction sequence defined internally by NFC includes at least one second operation among: pull CE, send address, send granular command, and read / write. The types of internal NFC transmission instructions are determined, and the corresponding instruction generator for NFC is designed, which may include: establishing a class for each second operation; wherein all values ​​in the operation instruction corresponding to the second operation are random values.

[0083] The NFC-defined command sequence mainly includes operations such as pulling the CE, sending the address, sending the granular command, and reading / writing. Each of these operations is set up as a class in the manner of steps A1-A4. Taking the write command as an example, the internal information of a write command includes information about scrambling / descrambling, LDPC, and how many 4Ks to read back. Unlike the granular-related operations mentioned earlier, all the information here may be random.

[0084] The instruction generation method provided in this invention effectively reduces reliance on manual programming, avoids time-consuming manual processes, and reduces related human resource costs. Especially when there are many types of NAND chips, it saves a lot of time and effort.

[0085] Example 3

[0086] Corresponding to the above method embodiments, this invention provides an instruction generation apparatus. Figure 3 This is a schematic diagram of the structure of an instruction generation device provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the instruction generation apparatus may include:

[0087] The instruction generation rule acquisition module 301 is used to acquire instruction generation rules.

[0088] The instruction generation module 302 is used to generate corresponding instructions based on generation rules and a pre-generated instruction generator; the instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit, and an instruction visualization unit.

[0089] The configuration information unit is based on pre-set operation settings and parameters; the instruction library unit is based on the particle type and operation adapted to the main control chip, as well as the types of internal NFC transmission instructions; the instruction generation unit selects an instruction template from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates it, and stores it in a TXT file; and the instruction visualization unit parses the instruction information in the TXT file and performs visualization processing through a pre-set program.

[0090] The instruction generation device provided in this embodiment of the invention can generate corresponding instructions by acquiring instruction generation rules and based on the generation rules and a pre-generated instruction generator. The instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit, and an instruction visualization unit. The configuration information unit is obtained based on pre-set operation settings and parameters. The instruction library unit is obtained based on the type of NAND flash memory and operation adapted to the main control chip, as well as the types of internal NFC transmission instructions. The instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, performs instantiation processing to generate instructions, sends them to the DUT, and stores them in a TXT file. The instruction visualization unit parses the instruction information in the TXT file and performs visualization processing through a pre-set program. This method automatically generates instruction generators for different NAND flash memory chips and different NFC internal commands, reducing manual intervention and improving verification efficiency.

[0091] In some embodiments, the instruction generation module is further configured to configure operation settings corresponding to test cases; the operation settings include: reset and erase, and include at least one of: direct memory access write and direct memory access read; configure corresponding parameters for the operation settings; if no corresponding parameters are configured for the operation settings, the parameters corresponding to the operation settings are determined to be default values.

[0092] In some embodiments, the instruction generation module is further configured to determine the corresponding target particle type and operation instructions based on the particle type adapted to the main control chip, and design an instruction generator for manipulating the particle; determine the types of internal NFC transmission instructions, and design an instruction generator for NFC.

[0093] In some embodiments, the instruction generation module is further configured to define specified NAND instructions in a specified instruction library of the NAND flash memory, including at least the following first operations: erase, program, read, write back, cache read, cache write, set function, get function, multi-plane read / write, multi-plane cache read / write, multi-plane write back, and reset; obtain the target instruction for each first operation in the ONFI protocol; the target instruction includes instructions sent from within the NFC to the NAND flash memory; determine the respective operation instruction for each first operation based on the transmission method of the instructions sent from within the NFC to the NAND flash memory; the transmission method includes sending commands and sending addresses; set the address in the operation instruction to a random value, set other values ​​in the operation instruction besides the address to fixed values, and use macros to distinguish different manipulation particles to complete the establishment of the class for each first operation.

[0094] In some embodiments, the instruction sequence defined internally by NFC includes at least one second operation among: pull CE, send address, send granular command, and read / write. The instruction generation module is further configured to establish a class for each second operation; wherein all values ​​in the operation instruction corresponding to the second operation are random values.

[0095] In some embodiments, the instruction generation module is further configured to select a corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit for instantiation processing; after instantiation processing, the transmitted information is sent to the DUT and stored in a TXT file, so that the TXT file can be used to debug whether the DUT signal is the expected instruction.

[0096] In some embodiments, the instruction generation module is further configured to traverse the TXT files corresponding to the test cases, parse the instruction information according to the information in different instructions in NFC, save the parsed instructions to a list dictionary, normalize all values ​​in the list dictionary using a pre-set library, and draw a scatter plot based on the frequency of occurrence of the normalized values ​​for visualization.

[0097] The device provided in this embodiment of the invention has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0098] Example 4

[0099] This invention also provides an electronic device for running the above-described instruction generation method; see [link to previous document]. Figure 4 The diagram shows the structure of an electronic device, which includes a memory 400 and a processor 401. The memory 400 is used to store one or more computer instructions, which are executed by the processor 401 to implement the instruction generation method described above.

[0100] Furthermore, Figure 4 The electronic device shown also includes a bus 402 and a communication interface 403. The processor 401, the communication interface 403 and the memory 400 are connected via the bus 402.

[0101] The memory 400 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 403 (which can be wired or wireless), such as the Internet, wide area network, local area network, or metropolitan area network. The bus 402 may be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 4 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0102] Processor 401 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 401 or by instructions in software form. Processor 401 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a readily available storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 400, and processor 401 reads information from memory 400 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0103] This invention also provides a computer-readable storage medium storing computer-executable instructions. When these computer-executable instructions are called and executed by a processor, they cause the processor to implement the above-described instruction generation method. For specific implementation details, please refer to the method embodiments, which will not be repeated here.

[0104] The computer program product for the instruction generation method provided in this embodiment of the invention includes a computer-readable storage medium storing non-volatile program code executable by a processor. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementation details, please refer to the method embodiments, which will not be repeated here.

[0105] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0106] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0107] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0108] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0109] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0110] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for generating instructions, characterized in that, The method includes: Obtain the command generation rules; Based on the aforementioned generation rules and a pre-generated instruction generator, corresponding instructions are generated; the instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit, and an instruction visualization unit; The configuration information unit is obtained based on pre-set operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted to the main control chip, as well as the types of internal NFC transmission instructions; the instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, performs instantiation processing to generate instructions, sends them to the DUT, and stores them in a TXT file; the instruction visualization unit obtains the instruction information by parsing the instruction information in the TXT file and performing visualization processing through a pre-set program. The instruction library unit is derived based on the granular type and operation adapted to the main control chip, as well as the types of internal NFC transmission instructions, and includes: Based on the particle type adapted to the main control chip, the corresponding target particle type and the corresponding instruction for the operation are determined, and an instruction generator for manipulating the particle is designed. Determine the types of internal transmission commands of the NFC and design the corresponding command generator for the NFC; The step of determining the corresponding target particle type and the corresponding instruction for the operation based on the particle type adapted to the main control chip, and designing an instruction generator for manipulating the particle, includes: In the designated instruction library of NAND flash memory, NAND instruction sequences are defined as NAND designated instructions; the NAND designated instructions include at least the following first operations: erase, program, read, write back, cache read, cache write, set function, get function, multi-plane read / write, multi-plane cache read / write, multi-plane write back, and reset; Obtain the target instruction for each of the first operations in the ONFI protocol; the target instruction includes the instruction sent from within the NFC to the NAND flash memory; Based on the transmission method of the instructions sent from the NFC internally to the NAND flash memory, the operation instructions for each of the first operations are determined; the transmission method includes sending commands and sending addresses; The address in the operation instruction is set to a random value, and other values ​​in the operation instruction other than the address are set to fixed values. Macros are used to distinguish different manipulation particles to complete the establishment of the class of each first operation. The instruction sequence defined internally by the NFC includes at least one second operation among: pull CE, send address, send granular command, and read / write. Determining the types of internal NFC transmission instructions and designing the corresponding NFC instruction generator includes: A class is created for each of the second operations; wherein all values ​​in the operation instruction corresponding to the second operation are random values.

2. The method according to claim 1, characterized in that, The configuration information unit is obtained based on pre-set operation settings and parameters, including: Configure the operation settings corresponding to the test cases; the operation settings include: reset and erase, and include at least one of: direct memory access write and direct memory access read; Configure the corresponding parameters for the operation; If no corresponding parameters are configured for the operation settings, then the parameters corresponding to the operation settings are determined to be default values.

3. The method according to claim 1, characterized in that, The instruction generation unit selects the corresponding class from the instruction library unit based on the configuration information provided by the configuration information unit, instantiates the class, generates instructions, sends them to the DUT, and stores them in a TXT file, including: Based on the configuration information provided by the configuration information unit, the corresponding class is selected from the instruction library unit for instantiation. After instantiation, the transmitted information is sent to the DUT and stored in a TXT file, which is then used to debug whether the DUT signals are the expected instructions.

4. The method according to claim 3, characterized in that, The instruction visualization unit obtains the instruction information by parsing the instruction information in the TXT file and performing visualization processing through a pre-set program, including: Traverse the TXT files corresponding to the test cases, parse the instruction information according to the information in different instructions in NFC, and save the parsed instructions to a list dictionary; The list dictionary is normalized using a pre-set library; A scatter plot is drawn based on the frequency of occurrence of the normalized values ​​to achieve visualization.

5. An instruction generation apparatus, characterized in that, The apparatus for implementing the instruction generation method according to any one of claims 1 to 4, the apparatus comprising: The instruction generation rule acquisition module is used to acquire instruction generation rules; The instruction generation module is used to generate corresponding instructions based on the generation rules and a pre-generated instruction generator; the instruction generator includes a configuration information unit, an instruction library unit, an instruction generation unit, and an instruction visualization unit; The configuration information unit is obtained based on pre-set operation settings and parameters; the instruction library unit is obtained based on the particle type and operation adapted to the main control chip, as well as the types of internal NFC transmission instructions; the instruction generation unit selects an instruction template from the instruction library unit based on the configuration information provided by the configuration information unit, performs instantiation processing to generate instructions, sends them to the DUT, and stores them in a TXT file; the instruction visualization unit obtains the instruction information by parsing the instruction information in the TXT file and performing visualization processing through a pre-set program.

6. An electronic device, characterized in that, The method includes a processor and a memory, the memory storing computer-executable instructions that can be executed by the processor, the processor executing the computer-executable instructions to implement the instruction generation method according to any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the instruction generation method according to any one of claims 1 to 4.

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