A RISC-V DSP chip test program script optimization method, system and storage medium

Abstract

The present invention provides a RISC‑V DSP chip test program script optimization method, system and storage medium. Firstly, functions to be tested are grouped according to first numerical information, so that functions to be tested with higher abnormality rates are arranged in a front group, thereby reducing the test time of abnormal chips; then, functions to be tested are grouped according to first configuration module information, and the same configuration module information is allocated to the same group, thereby reducing the time for module switching or reconfiguration; finally, functions to be tested are sorted according to the first functional module information, and the time for output interface switching and output parameter configuration is reduced, thereby improving the efficiency of chip function-level testing.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and more specifically, to a RISC-V DSP chip test program script optimization method, system and storage medium. Background Art

[0002] When the RISC-V DSP chip is tested at the functional level ATE (Automatic Test Equipment), a specific test program is usually required for each function that needs to be tested. The test program is simulated in the RTL simulation environment to generate a test waveform passing through the JTAG / CJTAG pin of the chip. This waveform completes the function of loading the current test program into the RAM of the chip under test and controlling the chip to run this test program.

[0003] In the chip production and testing process, it is often necessary to conduct full inspection or random inspection on each batch of chips, and the chip inspection requires test waveform verification of each functional module. Therefore, the number of chips that need to be inspected and the number of test waveforms that need to be verified are large. Due to the large amount of testing, a RISC-V DSP chip test program script optimization technology that can improve the test efficiency is urgently needed. Summary of the invention

[0004] In view of the above problems, the purpose of the present invention is to provide a RISC-V DSP chip test program script optimization method, system and storage medium. First, the functions with higher test exception rates are ranked in the front for testing, thereby reducing the test time of abnormal chips; then, the modules and module configuration parameters involved in the chip function test are grouped and sorted, thereby reducing the time for module initialization or reconfiguration and improving detection efficiency.

[0005] A first aspect of the present invention provides a RISC-V DSP chip test program script optimization method, the method comprising: obtaining first count information;

[0006] According to the first number information, the functions to be tested are grouped to obtain first grouping information;

[0007] Obtaining first configuration module information in the first group information;

[0008] Grouping the functions to be tested according to the first configuration module information to obtain second grouping information;

[0009] Obtaining first functional module information in second group information;

[0010] Sort the functions to be tested according to the first functional module information to obtain a first functional sequence;

[0011] According to the first functional sequence, the script list is adjusted.

[0012] In this solution, the functions to be tested are grouped according to the first configuration module information to obtain the second grouping information, specifically:

[0013] According to the first configuration module information and a preset module classification strategy, a second configuration module and a third configuration module are obtained;

[0014] Obtaining a first configuration parameter of a second configuration module;

[0015] Grouping the functions to be tested in the first grouping information according to the first configuration parameter to obtain third grouping information;

[0016] Acquire first quantity information of a third configuration module;

[0017] The functions to be tested in the third group are grouped and sorted according to the quantity information to obtain second group information.

[0018] In this solution, the functions to be tested are sorted according to the first functional module information to obtain a first functional sequence, which is specifically:

[0019] Obtain output interface information of the first functional module information;

[0020] Grouping the functions to be tested in the second grouping information according to the output interface information to obtain fourth grouping information;

[0021] A second configuration parameter of the first functional module information;

[0022] The functions to be tested in the fourth grouping information are sorted according to the second configuration parameter to obtain a first function sequence.

[0023] This plan also includes:

[0024] Obtaining first verification information;

[0025] Determining whether the function to be tested passes verification according to the first verification information;

[0026] If not, obtain the number of retests;

[0027] Determine whether the retest number information is lower than a set first number threshold;

[0028] If not, sending the first control instruction information;

[0029] Get the first-hand information;

[0030] Determining whether the first time information exceeds a first time threshold;

[0031] If yes, stop testing the current chip.

[0032] This plan also includes:

[0033] Obtaining first waveform data according to the first verification information;

[0034] Acquire second waveform data;

[0035] Calculate an exclusive OR value of the first waveform data and the second waveform data to obtain first verification data;

[0036] Determine whether the first verification data is 0;

[0037] If yes, the verification passes;

[0038] If not, the verification fails.

[0039] This plan also includes:

[0040] Obtaining second time information according to the first verification information;

[0041] Determining whether the second time information is lower than a set second time threshold;

[0042] If yes, the verification passes;

[0043] If not, the verification fails.

[0044] A second aspect of the present invention provides a RISC-V DSP chip test program script optimization system, including a RISC-V DSP chip test program script optimization method program, wherein the RISC-V DSP chip test program script optimization method program implements the following steps when executed by the processor:

[0045] Get the first count information;

[0046] According to the first number information, the functions to be tested are grouped to obtain first grouping information;

[0047] Obtaining first configuration module information in the first group information;

[0048] Grouping the functions to be tested according to the first configuration module information to obtain second grouping information;

[0049] Obtaining first functional module information in second group information;

[0050] Sort the functions to be tested according to the first functional module information to obtain a first functional sequence;

[0051] According to the first functional sequence, the script list is adjusted.

[0052] In this solution, the functions to be tested are grouped according to the first configuration module information to obtain the second grouping information, specifically:

[0053] According to the first configuration module information and a preset module classification strategy, a second configuration module and a third configuration module are obtained;

[0054] Obtaining a first configuration parameter of a second configuration module;

[0055] Grouping the functions to be tested in the first grouping information according to the first configuration parameter to obtain third grouping information;

[0056] Acquire first quantity information of a third configuration module;

[0057] The functions to be tested in the third group are grouped and sorted according to the quantity information to obtain second group information.

[0058] In this solution, the functions to be tested are sorted according to the first functional module information to obtain a first functional sequence, which is specifically:

[0059] Obtain output interface information of the first functional module information;

[0060] Grouping the functions to be tested in the second grouping information according to the output interface information to obtain fourth grouping information;

[0061] A second configuration parameter of the first functional module information;

[0062] The functions to be tested in the fourth grouping information are sorted according to the second configuration parameter to obtain a first function sequence.

[0063] A third aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a RISC-V DSP chip test program script optimization method program. When the RISC-V DSP chip test program script optimization method program is executed by a processor, the steps of the RISC-V DSP chip test program script optimization method as described in any one of the above items are implemented.

[0064] The present invention provides a RISC-V DSP chip test program script optimization method, system and storage medium. Firstly, functions to be tested are grouped according to first numerical information, so that functions to be tested with higher abnormality rates are arranged in a front group, thereby reducing the test time of abnormal chips; then, functions to be tested are grouped according to first configuration module information, and the same configuration module information is allocated to the same group, thereby reducing the time for module switching or reconfiguration; finally, functions to be tested are sorted according to the first functional module information, so as to reduce the time for output interface switching and output parameter configuration, thereby improving the efficiency of chip function-level testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope.

[0066] Figure 1 A flow chart of a RISC-V DSP chip test program script optimization method of the present invention is shown;

[0067] Figure 2 A flowchart of grouping first configuration module information provided by an embodiment of the present invention is shown;

[0068] Figure 3 A flowchart of sorting the first configuration module information provided by an embodiment of the present invention is shown;

[0069] Figure 4 A block diagram of a RISC-V DSP chip test program script optimization system of the present invention is shown. DETAILED DESCRIPTION

[0070] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present invention have the same meanings as commonly understood by those of ordinary skill in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless the embodiments of the present invention are clearly defined in this way.

[0072] The words "first", "second" and similar words used in the embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one", "an" or "the" and similar words do not indicate a quantity limitation, but indicate the existence of at least one. Similarly, words such as "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The steps before or after the method of the embodiment of the present invention are not necessarily carried out in precise order. On the contrary, various steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or more steps can be removed from these processes.

[0073] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0074] Figure 1 A flow chart of a RISC-V DSP chip test program script optimization method of the present invention is shown.

[0075] like Figure 1 As shown, the first aspect of the present invention discloses a RISC-V DSP chip test program script optimization method, the method comprising:

[0076] S102, obtaining first number information;

[0077] S104, grouping the functions to be tested according to the first number information to obtain first grouping information;

[0078] S106, obtaining first configuration module information in the first group information;

[0079] S108, grouping the functions to be tested according to the first configuration module information to obtain second grouping information;

[0080] S110, obtaining first functional module information in second group information;

[0081] S112, sorting the functions to be tested according to the first functional module information to obtain a first functional sequence;

[0082] S114: Adjust the script list according to the first function sequence.

[0083] It should be noted that the first number information is the number of times that each function to be tested of the tested chip has failed the verification; the first grouping information is obtained by grouping according to the value of the first number information, that is, the first number information of the functions to be tested in the same group is the same or shows a similar trend; the first configuration module information includes but is not limited to the number of configuration modules, configuration module numbers and configuration parameters; the second grouping information is obtained by grouping according to the first configuration module information for the functions to be tested in each group of the first grouping information, that is, the number, module number and configuration parameters of the first configuration module information of the functions to be tested in the same group show the same trend; the first function module information is the function output module of the function to be tested, including but not limited to the output interface and configuration parameters; the first function sequence is the test order sequence of the function to be tested in the second grouping information.

[0084] In this embodiment, first, the functions to be tested are grouped according to the first number information of each function to be tested. In practical applications, the functions to be tested whose first number information is lower than the preset number threshold are usually grouped into one group, and the remaining functions to be tested are grouped according to the actual number. In addition, the group with the higher first number is placed in front, that is, the higher the first number information of the function to be tested, the higher the test order, that is, the higher the test priority. Then, for the functions to be tested in the same first group information, the configuration module information of the function to be tested is obtained. First, according to the type of the configuration module, the first configuration parameter of the core configuration module is determined, and the functions to be tested are grouped again according to the first configuration parameter to obtain the third group information, so that the functions to be tested with the same first configuration parameter are in the same group. Then, according to the type of the configuration module, the first quantity information of the secondary configuration module is obtained, and the functions to be tested in the third group information are grouped according to the first quantity information to obtain the second group information; and the second group information is sorted according to the first quantity information in a preset ascending or descending manner. Finally, for the functions to be tested within the same second grouping information, they are first grouped according to the output interface of the functions to be tested to obtain the fourth grouping information; then they are sorted according to the configuration parameters of the functional modules of the functions to be tested to obtain the first functional sequence, which is used to adjust the script list and achieve the purpose of adjusting the test order. Through the above-mentioned script optimization technology, first, the functions to be tested with a higher test abnormality rate are tested first. If the test fails, it can be determined that the current chip function test fails, shortening the time for other functional tests; then, they are grouped and sorted according to the type, number and parameters of the configuration modules, reducing the waiting time caused by operations such as adjusting or switching the configuration module parameters, and improving the speed of chip testing; finally, they are grouped and sorted according to the output interface and configuration parameters of the functional modules, reducing the machine operation time required for output interface switching and output parameter adjustment, and improving the chip detection efficiency.

[0085] Figure 2A flow chart of grouping the first configuration module information provided by an embodiment of the present invention is shown.

[0086] According to an embodiment of the present invention, Figure 2 As shown, the functions to be tested are grouped according to the first configuration module information to obtain second grouping information, which is specifically:

[0087] S202, obtaining a second configuration module and a third configuration module according to the first configuration module information and a preset module classification strategy;

[0088] S204, obtaining a first configuration parameter of a second configuration module;

[0089] S206, grouping the functions to be tested in the first grouping information according to the first configuration parameter to obtain third grouping information;

[0090] S208, obtaining first quantity information of a third configuration module;

[0091] S210: Group and sort the functions to be tested in the third group according to the quantity information to obtain second group information.

[0092] It should be noted that the second configuration module is a core configuration module, that is, modifying the configuration parameters of the second configuration module requires operations such as resetting or restarting the chip, which require a long wait; the third configuration module is a secondary configuration module, that is, the operation of the configuration module can be directly adjusted after modifying the configuration parameters of the third configuration module. In this embodiment, first, the functions to be tested in the first group are grouped according to the first configuration parameters of the second configuration module to obtain the third grouping information; the second configuration modules of the functions to be tested in the third grouping information have the same first configuration parameters, and when the functions to be tested in the same group are tested, the parameters of the second configuration module do not need to be configured. Then, the third configuration modules are grouped according to the first number, and the configuration modules of the same number are arranged in the same group; and the first number information is sorted in ascending or descending order to obtain the second grouping information. As can be seen from the above, the functions to be tested in the second grouping information have second configuration modules with the same configuration parameters, and the same number of third configuration modules.

[0093] Figure 3 A flowchart of sorting the first configuration module information provided by an embodiment of the present invention is shown.

[0094] According to an embodiment of the present invention, Figure 3 As shown, the functions to be tested are sorted according to the first functional module information to obtain a first functional sequence, which is specifically:

[0095] S302, obtaining output interface information of the first functional module information;

[0096] S304, grouping the functions to be tested in the second grouping information according to the output interface information to obtain fourth grouping information;

[0097] S306, second configuration parameter of the first functional module information;

[0098] S308: Sort the functions to be tested in the fourth grouping information according to the second configuration parameter to obtain a first function sequence.

[0099] It should be noted that the first functional module is an output control module of the function to be tested. In this embodiment, for the modules to be tested in the same second grouping information, first, according to the output interface information of the first functional module, the functions to be tested in the second grouping information are grouped to obtain fourth grouping information, that is, the functions to be tested in the same group have the same output interface, thereby reducing the machine operation time required for output interface switching. Then, according to the second configuration parameter of the first functional module information, the functions to be tested in the fourth grouping information are sorted to obtain a first function sequence.

[0100] According to an embodiment of the present invention, it also includes:

[0101] Obtaining first verification information;

[0102] Determining whether the function to be tested passes verification according to the first verification information;

[0103] If not, obtain the number of retests;

[0104] Determine whether the retest number information is lower than a set first number threshold;

[0105] If not, sending the first control instruction information;

[0106] Get the first-hand information;

[0107] Determining whether the first time information exceeds a first time threshold;

[0108] If yes, stop testing the current chip.

[0109] It should be noted that the first verification information is the verification result of the output waveform of the function to be tested; the first time information is the time for waiting for the operation feedback instruction. When the first verification information indicates that it has not passed, it is determined whether the number of retests of the current function is lower than the preset number threshold. If not, it means that the current function has been retested too many times and has exceeded the set number limit. At this time, the first control instruction information is sent to the test machine to wait for the operation feedback instruction. When the first time information exceeds the preset first time threshold, it means that there is no operation feedback instruction, which means that the current function test has not passed and no special operation is required. When there is no operation feedback instruction, the test of the current chip is stopped at this time, that is, the subsequent function test is not performed at present, and it is marked as an abnormal chip.

[0110] According to an embodiment of the present invention, it also includes:

[0111] Obtaining first waveform data according to the first verification information;

[0112] Acquire second waveform data;

[0113] Calculate an exclusive OR value of the first waveform data and the second waveform data to obtain first verification data;

[0114] Determine whether the first verification data is 0;

[0115] If yes, the verification passes;

[0116] If not, the verification fails.

[0117] It should be noted that the first waveform data is a binary data value obtained by the chip output waveform according to a preset waveform extraction method; the second waveform data is a binary data value extracted from the output reference waveform prepared by the test machine. The first waveform data and the second waveform data are XORed to obtain the first verification data. From the XOR logic operation, it can be seen that when the operation result is 0, it means that the data on both sides are the same. Therefore, when the first verification data is 0, it means that the first waveform data is the same as the second waveform data, that is, the verification is passed; if the first verification data is not 0, it means that the first waveform data is different from the second waveform data, that is, the verification is not passed.

[0118] According to an embodiment of the present invention, it also includes:

[0119] Obtaining second time information according to the first verification information;

[0120] Determining whether the second time information is lower than a set second time threshold;

[0121] If yes, the verification passes;

[0122] If not, the verification fails.

[0123] It should be noted that the second time information is the time when the chip outputs the waveform during the function test. In this embodiment, each function to be tested is set with a waveform output duration, that is, a second time threshold. When the second time information exceeds the set second time threshold, it means that the waveform output of the current function is abnormal and the verification fails; otherwise, it means that the waveform output is normal and the verification passes.

[0124] It is worth mentioning that it also includes:

[0125] Obtaining first feedback instruction information;

[0126] Acquire operation code information according to the first feedback instruction information;

[0127] When it is determined that the operation code information is a continued test operation, the current function is continued to be tested;

[0128] When it is determined that the operation code information is a skip operation, the test of the current function is skipped;

[0129] When it is determined that the operation code information is a stop operation, the test of the current chip is stopped.

[0130] It should be noted that after receiving the first control instruction, the test machine returns the first feedback instruction information to the test chip according to the tester's operation. The operation code information of the first feedback instruction information includes at least a continue test operation, a skip operation and a stop operation. When the operation code information is a continue test operation, it means to continue testing the current function. When the operation code information is a skip operation, it means to skip the current function test and perform the subsequent function test. When the operation code information is a stop operation, it means that the chip function is abnormal and the current chip test is stopped. Through feedback instructions, the flexibility of functional testing when abnormalities occur is improved.

[0131] It is worth mentioning that it also includes:

[0132] When it is determined that the operation code information is a continued test operation;

[0133] Obtaining first verification information;

[0134] Determining whether the function to be tested has passed the verification according to the verification information;

[0135] If so, the first count threshold is adjusted upward.

[0136] It should be noted that when the function test passes after the continued test operation, the first times threshold of the current function is adjusted upward to improve the fault tolerance of the test. By automatically adjusting the times threshold, the chip test misjudgment caused by excessively high audit requirements can be avoided.

[0137] Figure 4A block diagram of a RISC-V DSP chip test program script optimization system of the present invention is shown.

[0138] like Figure 4 As shown, the second aspect of the present invention discloses a RISC-V DSP chip test program script optimization system 4, comprising a memory 41 and a processor 42, wherein the memory comprises a RISC-V DSP chip test program script optimization method program, and when the RISC-V DSP chip test program script optimization method program is executed by the processor, the following steps are implemented:

[0139] Get the first count information;

[0140] According to the first number information, the functions to be tested are grouped to obtain first grouping information;

[0141] Obtaining first configuration module information in the first group information;

[0142] Grouping the functions to be tested according to the first configuration module information to obtain second grouping information;

[0143] Obtaining first functional module information in second group information;

[0144] Sort the functions to be tested according to the first functional module information to obtain a first functional sequence;

[0145] According to the first functional sequence, the script list is adjusted.

[0146] It should be noted that the first number information is the number of times that each function to be tested of the tested chip has failed the verification; the first grouping information is obtained by grouping according to the value of the first number information, that is, the first number information of the functions to be tested in the same group is the same or shows a similar trend; the first configuration module information includes but is not limited to the number of configuration modules, configuration module numbers and configuration parameters; the second grouping information is obtained by grouping according to the first configuration module information for the functions to be tested in each group of the first grouping information, that is, the number, module number and configuration parameters of the first configuration module information of the functions to be tested in the same group show the same trend; the first function module information is the function output module of the function to be tested, including but not limited to the output interface and configuration parameters; the first function sequence is the test order sequence of the function to be tested in the second grouping information.

[0147] In this embodiment, first, the functions to be tested are grouped according to the first number information of each function to be tested. In practical applications, the functions to be tested whose first number information is lower than the preset number threshold are usually grouped into one group, and the remaining functions to be tested are grouped according to the actual number. In addition, the group with the higher first number is placed in front, that is, the higher the first number information of the function to be tested, the higher the test order, that is, the higher the test priority. Then, for the functions to be tested in the same first group information, the configuration module information of the function to be tested is obtained. First, according to the type of the configuration module, the first configuration parameter of the core configuration module is determined, and the functions to be tested are grouped again according to the first configuration parameter to obtain the third group information, so that the functions to be tested with the same first configuration parameter are in the same group. Then, according to the type of the configuration module, the first quantity information of the secondary configuration module is obtained, and the functions to be tested in the third group information are grouped according to the first quantity information to obtain the second group information; and the second group information is sorted according to the first quantity information in a preset ascending or descending manner. Finally, for the functions to be tested within the same second grouping information, they are first grouped according to the output interface of the functions to be tested to obtain the fourth grouping information; then they are sorted according to the configuration parameters of the functional modules of the functions to be tested to obtain the first functional sequence, which is used to adjust the script list and achieve the purpose of adjusting the test order. Through the above-mentioned script optimization technology, first, the functions to be tested with a higher test abnormality rate are tested first. If the test fails, it can be determined that the current chip function test fails, shortening the time for other functional tests; then, they are grouped and sorted according to the type, number and parameters of the configuration modules, reducing the waiting time caused by operations such as adjusting or switching the configuration module parameters, and improving the speed of chip testing; finally, they are grouped and sorted according to the output interface and configuration parameters of the functional modules, reducing the machine operation time required for output interface switching and output parameter adjustment, and improving the chip detection efficiency.

[0148] According to an embodiment of the present invention, grouping the functions to be tested according to the first configuration module information to obtain the second grouping information is specifically:

[0149] According to the first configuration module information and a preset module classification strategy, a second configuration module and a third configuration module are obtained;

[0150] Obtaining a first configuration parameter of a second configuration module;

[0151] Grouping the functions to be tested in the first grouping information according to the first configuration parameter to obtain third grouping information;

[0152] Acquire first quantity information of a third configuration module;

[0153] The functions to be tested in the third group are grouped and sorted according to the quantity information to obtain second group information.

[0154] It should be noted that the second configuration module is a core configuration module, that is, modifying the configuration parameters of the second configuration module requires operations such as resetting or restarting the chip, which require a long wait; the third configuration module is a secondary configuration module, that is, the operation of the configuration module can be directly adjusted after modifying the configuration parameters of the third configuration module. In this embodiment, first, the functions to be tested in the first group are grouped according to the first configuration parameters of the second configuration module to obtain the third grouping information; the second configuration modules of the functions to be tested in the third grouping information have the same first configuration parameters, and when the functions to be tested in the same group are tested, the parameters of the second configuration module do not need to be configured. Then, the third configuration modules are grouped according to the first number, and the configuration modules of the same number are arranged in the same group; and the first number information is sorted in ascending or descending order to obtain the second grouping information. As can be seen from the above, the functions to be tested in the second grouping information have second configuration modules with the same configuration parameters, and the same number of third configuration modules.

[0155] According to an embodiment of the present invention, the functions to be tested are sorted according to the first functional module information to obtain a first functional sequence, specifically:

[0156] Obtain output interface information of the first functional module information;

[0157] Grouping the functions to be tested in the second grouping information according to the output interface information to obtain fourth grouping information;

[0158] A second configuration parameter of the first functional module information;

[0159] The functions to be tested in the fourth grouping information are sorted according to the second configuration parameter to obtain a first function sequence.

[0160] It should be noted that the first functional module is an output control module of the function to be tested. In this embodiment, for the modules to be tested in the same second grouping information, first, according to the output interface information of the first functional module, the functions to be tested in the second grouping information are grouped to obtain fourth grouping information, that is, the functions to be tested in the same group have the same output interface, thereby reducing the machine operation time required for output interface switching. Then, according to the second configuration parameter of the first functional module information, the functions to be tested in the fourth grouping information are sorted to obtain a first function sequence.

[0161] According to an embodiment of the present invention, it also includes:

[0162] Obtaining first verification information;

[0163] Determining whether the function to be tested passes verification according to the first verification information;

[0164] If not, obtain the number of retests;

[0165] Determine whether the retest number information is lower than a set first number threshold;

[0166] If not, sending the first control instruction information;

[0167] Get the first-hand information;

[0168] Determining whether the first time information exceeds a first time threshold;

[0169] If yes, stop testing the current chip.

[0170] It should be noted that the first verification information is the verification result of the output waveform of the function to be tested; the first time information is the time for waiting for the operation feedback instruction. When the first verification information indicates that it has not passed, it is determined whether the number of retests of the current function is lower than the preset number threshold. If not, it means that the current function has been retested too many times and has exceeded the set number limit. At this time, the first control instruction information is sent to the test machine to wait for the operation feedback instruction. When the first time information exceeds the preset first time threshold, it means that there is no operation feedback instruction, which means that the current function test has not passed and no special operation is required. When there is no operation feedback instruction, the test of the current chip is stopped at this time, that is, the subsequent function test is not performed at present, and it is marked as an abnormal chip.

[0171] According to an embodiment of the present invention, it also includes:

[0172] Obtaining first waveform data according to the first verification information;

[0173] Acquire second waveform data;

[0174] Calculate an exclusive OR value of the first waveform data and the second waveform data to obtain first verification data;

[0175] Determine whether the first verification data is 0;

[0176] If yes, the verification passes;

[0177] If not, the verification fails.

[0178] It should be noted that the first waveform data is a binary data value obtained by the chip output waveform according to a preset waveform extraction method; the second waveform data is a binary data value extracted from the output reference waveform prepared by the test machine. The first waveform data and the second waveform data are XORed to obtain the first verification data. From the XOR logic operation, it can be seen that when the operation result is 0, it means that the data on both sides are the same. Therefore, when the first verification data is 0, it means that the first waveform data is the same as the second waveform data, that is, the verification is passed; if the first verification data is not 0, it means that the first waveform data is different from the second waveform data, that is, the verification is not passed.

[0179] According to an embodiment of the present invention, it also includes:

[0180] Obtaining second time information according to the first verification information;

[0181] Determining whether the second time information is lower than a set second time threshold;

[0182] If yes, the verification passes;

[0183] If not, the verification fails.

[0184] It should be noted that the second time information is the time when the chip outputs the waveform during the function test. In this embodiment, each function to be tested is set with a waveform output duration, that is, a second time threshold. When the second time information exceeds the set second time threshold, it means that the waveform output of the current function is abnormal and the verification fails; otherwise, it means that the waveform output is normal and the verification passes.

[0185] It is worth mentioning that it also includes:

[0186] Obtaining first feedback instruction information;

[0187] Acquire operation code information according to the first feedback instruction information;

[0188] When it is determined that the operation code information is a continued test operation, the current function is continued to be tested;

[0189] When it is determined that the operation code information is a skip operation, the test of the current function is skipped;

[0190] When it is determined that the operation code information is a stop operation, the test of the current chip is stopped.

[0191] It should be noted that after receiving the first control instruction, the test machine returns the first feedback instruction information to the test chip according to the tester's operation. The operation code information of the first feedback instruction information includes at least a continue test operation, a skip operation and a stop operation. When the operation code information is a continue test operation, it means to continue testing the current function. When the operation code information is a skip operation, it means to skip the current function test and perform the subsequent function test. When the operation code information is a stop operation, it means that the chip function is abnormal and the current chip test is stopped. Through feedback instructions, the flexibility of functional testing when abnormalities occur is improved.

[0192] It is worth mentioning that it also includes:

[0193] When it is determined that the operation code information is a continued test operation;

[0194] Obtaining first verification information;

[0195] Determining whether the function to be tested has passed the verification according to the verification information;

[0196] If so, the first count threshold is adjusted upward.

[0197] It should be noted that when the function test passes after the continued test operation, the first times threshold of the current function is adjusted upward to improve the fault tolerance of the test. By automatically adjusting the times threshold, the chip test misjudgment caused by excessively high audit requirements can be avoided.

[0198] A third aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a RISC-V DSP chip test program script optimization method program. When the RISC-V DSP chip test program script optimization method program is executed by a processor, the steps of the RISC-V DSP chip test program script optimization method as described in any one of the above items are implemented.

[0199] The present invention provides a RISC-V DSP chip test program script optimization method, system and storage medium. Firstly, functions to be tested are grouped according to first numerical information, so that functions to be tested with higher abnormality rates are arranged in a front group, thereby reducing the test time of abnormal chips; then, functions to be tested are grouped according to first configuration module information, and the same configuration module information is allocated to the same group, thereby reducing the time for module switching or reconfiguration; finally, functions to be tested are sorted according to the first functional module information, so as to reduce the time for output interface switching and output parameter configuration, thereby improving the efficiency of chip function-level testing.

[0200] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0201] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A RISC-V DSP chip test program script optimization method, characterized in that: The method comprises: Get the first count information; According to the first number information, the functions to be tested are grouped to obtain first grouping information; Obtaining first configuration module information in the first group information; Grouping the functions to be tested according to the first configuration module information to obtain second grouping information; Obtaining first functional module information in second group information; Sort the functions to be tested according to the first functional module information to obtain a first functional sequence; According to the first functional sequence, the script list is adjusted.

2. A RISC-V DSP chip test program script optimization method according to claim 1, characterized in that: The grouping of the functions to be tested according to the first configuration module information to obtain the second grouping information is specifically: According to the first configuration module information and a preset module classification strategy, a second configuration module and a third configuration module are obtained; Obtaining a first configuration parameter of a second configuration module; Grouping the functions to be tested in the first grouping information according to the first configuration parameter to obtain third grouping information; Acquire first quantity information of a third configuration module; The functions to be tested in the third group are grouped and sorted according to the quantity information to obtain second group information.

3. A RISC-V DSP chip test program script optimization method according to claim 1, characterized in that: The first function sequence is obtained by sorting the functions to be tested according to the first function module information, specifically: Obtain output interface information of the first functional module information; Grouping the functions to be tested in the second grouping information according to the output interface information to obtain fourth grouping information; A second configuration parameter of the first functional module information; The functions to be tested in the fourth grouping information are sorted according to the second configuration parameter to obtain a first function sequence.

4. A RISC-V DSP chip test program script optimization method according to claim 1, characterized in that: Also includes: Obtaining first verification information; Determining whether the function to be tested passes verification according to the first verification information; If not, obtain the number of retests; Determine whether the retest number information is lower than a set first number threshold; If not, sending the first control instruction information; Get the first-hand information; Determining whether the first time information exceeds a first time threshold; If yes, stop testing the current chip.

5. A RISC-V DSP chip test program script optimization method according to claim 4, characterized in that: Also includes: Obtaining first waveform data according to the first verification information; Acquire second waveform data; Calculate an exclusive OR value of the first waveform data and the second waveform data to obtain first verification data; Determine whether the first verification data is 0; If yes, the verification passes; If not, the verification fails.

6. A RISC-V DSP chip test program script optimization method according to claim 4, characterized in that: Also includes: Obtaining second time information according to the first verification information; Determining whether the second time information is lower than a set second time threshold; If yes, the verification passes; If not, the verification fails.

7. A RISC-V DSP chip test program script optimization system, characterized in that: The system includes a memory and a processor, wherein the memory includes a RISC-V DSP chip test program script optimization method program, and when the RISC-V DSP chip test program script optimization method program is executed by the processor, the following steps are implemented: Get the first count information; According to the first number information, the functions to be tested are grouped to obtain first grouping information; Obtaining first configuration module information in the first group information; Grouping the functions to be tested according to the first configuration module information to obtain second grouping information; Obtaining first functional module information in second group information; Sort the functions to be tested according to the first functional module information to obtain a first functional sequence; According to the first functional sequence, the script list is adjusted.

8. A RISC-V DSP chip test program script optimization system according to claim 7, characterized in that: The grouping of the functions to be tested according to the first configuration module information to obtain the second grouping information is specifically: According to the first configuration module information and a preset module classification strategy, a second configuration module and a third configuration module are obtained; Obtaining a first configuration parameter of a second configuration module; Grouping the functions to be tested in the first grouping information according to the first configuration parameter to obtain third grouping information; Acquire first quantity information of a third configuration module; The functions to be tested in the third group are grouped and sorted according to the quantity information to obtain second group information.

9. A RISC-V DSP chip test program script optimization system according to claim 7, characterized in that: The first function sequence is obtained by sorting the functions to be tested according to the first function module information, specifically: Obtain output interface information of the first functional module information; Grouping the functions to be tested in the second grouping information according to the output interface information to obtain fourth grouping information; A second configuration parameter of the first functional module information; The functions to be tested in the fourth grouping information are sorted according to the second configuration parameter to obtain a first function sequence.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer-readable storage medium includes a RISC-V DSP chip test program script optimization method program. When the RISC-V DSP chip test program script optimization method program is executed by a processor, the steps of the RISC-V DSP chip test program script optimization method as described in any one of claims 1 to 6 are implemented.

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