Non-intrusive real-time monitoring debugger for DSP (Digital Signal Processor)

Abstract

The invention belongs to the technical field of digital signal processors, and particularly relates to a non-intrusive real-time monitoring debugger for a DSP (digital signal processor). The real-time monitoring debugger comprises a bus monitoring module and a tracking buffer module, and the bus monitoring module and the tracking buffer module jointly complete debugging and obtain real-time operation information. The bus monitoring module is used for monitoring the memory access operation of the DSP, and meanwhile, the tracking buffer module is used for recording execution tracks of a program before and after an event, so that comprehensive and accurate debugging information is provided for a system, and problems occurring in the running process of the DSP can be quickly positioned and solved, and the debugging efficiency is improved; in addition, by arranging a special register, high configurability is achieved, so that monitoring and recording strategies can be flexibly adjusted according to different debugging requirements, and the debugging process is more targeted and efficient.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital signal processors, and particularly relates to a non-intrusive real-time monitoring debugger for DSP processors. Background Art

[0002] Digital Signal Processors (DSPs) are widely used in many key fields such as communication, audio processing, image processing, and industrial control. With the continuous expansion and deepening of application scenarios, in order to meet the requirements for the real-time performance and stability of the processor, during the development and application process, it is necessary to monitor its operating state with higher real-time performance and accuracy through a debugging system.

[0003] Currently, the common DSP debugging methods mainly include software breakpoint debugging, hardware breakpoint debugging, and emulator debugging, and also involve the joint debugging of software and hardware. Software breakpoint debugging is to insert breakpoint instructions in the program code, and when the program executes to this instruction, it pauses. In the software and hardware co-debugging, first, set breakpoints through software instruction breakpoint debugging, run the program, trigger the breakpoint, and then send it to the hardware side via the developer setting the command line or the visual tool IDE through GDB and the debugging proxy software. After the hardware side receives the corresponding information, it can execute the debugging command, and thus the current variable values and register status can be viewed. However, this way of jointly setting breakpoints in software and hardware belongs to intrusive debugging, and some debugging commands will change the execution flow of the program, thus affecting the real-time operating state of the processor.

[0004] Due to the requirement of the DSP application field for system real-time performance, intrusive debugging through connecting a debugger has limitations. In actual development, the detection point and path buffer module can monitor specific memory addresses or variable changes and trigger interrupts, and record the program execution instruction sequence path, so as to break away from the debugger and independently implement the setting, monitoring of breakpoints, and retaining the program execution path, thereby meeting the requirements during the real-time operation of the DSP. Therefore, the present invention proposes a non-intrusive debugger for monitoring and recording the real-time operating state of DSP processors. Summary of the Invention

[0005] The purpose of the present invention is to propose a non-intrusive real-time monitoring debugger for DSP processors to achieve high real-time performance and high-accuracy monitoring and regulation.

[0006] The non-intrusive real-time monitoring debugger for DSP processors provided by the present invention has a system architecture as Figure 1As shown in the figure. By directly configuring the dedicated control special register group inside it and setting up hardware breakpoints, developers can establish a complex breakpoint triggering mechanism independent of the debugger and debugging agent software while maintaining the integrity of the program source code, introducing a "non-intrusive" debugging mechanism that does not interfere with the kernel. When a preset event is detected, the context program counter (PC) information is stored in an independent buffer area through the module with dedicated tracing function, and at the same time, the kernel can continue to execute task instructions at full speed.

[0007] The non-intrusive real-time monitoring debugger includes a bus monitoring module and a trace buffer module, which jointly complete debugging and obtain real-time running information. The bus monitoring module monitors the memory access operations of the DSP processor, and at the same time, the trace buffer module records the execution trajectory of the program before and after the event, providing comprehensive and accurate debugging information for the system to quickly locate and solve problems that occur during the operation of the DSP processor, so as to improve the debugging efficiency.

[0008] In this real-time monitoring debugger, high configurability is achieved by setting read-write special registers. Specifically, for the bus monitoring module, different bus monitoring methods are realized by reading and writing special registers to modify configuration information such as illegal address ranges and enable bits. For the trace buffer module, different cache working modes are selected by reading and writing special registers. This configurability enables it to flexibly adjust monitoring and recording strategies according to different debugging requirements, making the debugging process more targeted and efficient. In addition, the real-time monitoring debugger needs to ensure the stability of the debugging process. For this reason, after detecting an illegal memory access, the bus monitoring module automatically suspends the continuous monitoring function to avoid system instability caused by continuous exceptions. During exception handling, the trace buffer module is reasonably controlled according to the on or off states of the cache and the system operation to ensure the stability of data recording and reading. After the system problem or fault is handled, the monitoring and recording functions can be restarted by rewriting the special registers again.

[0009] The definition of "special register" is introduced in the specific implementation part.

[0010] The following further specifically describes the specific composition, as well as the functions and roles of the bus monitoring module and the trace buffer module.

[0011] (1) Bus monitoring module

[0012] The bus monitoring module is used to monitor the access operations of the DSP processor to the instruction memory and data memory during operation. The module architecture is as Figure 2 . Specifically, it includes an address data range register module, a control logic module, and a violation detection module; among them:

[0013] The data range register module stores the illegal address ranges and enable configurations preset by the developer through a special register interface, including two independent address ranges for the instruction memory and the data memory, denoted as A and B. Each group contains two programmable address ranges and separates the enable bits for controlling data read / write operations.

[0014] The control logic module is responsible for scheduling the monitoring process. According to the priority order of "instruction access > data write operation > data read operation", it sequentially selects the monitoring targets in each clock cycle, synchronously updates the configuration information in the data range register, and automatically pauses the monitoring function when an anomaly is detected to maintain system stability.

[0015] The violation detection module continuously receives the bus address signal. According to the monitoring mode selected by the control logic, it uses a hardware comparator to match the current instruction address or data read / write address with the preset illegal address range. If the address falls within the enabled illegal range, it immediately triggers an anomaly signal, records the violating address, and notifies the trace buffer module to save the context information. At the same time, it forces the control logic to enter a paused state and waits for developer intervention.

[0016] When the three work together, the developer first configures the illegal address and enable bits through special registers. After global enabling, the control logic schedules the detection process step by step according to the priority. The violation detection module dynamically compares the addresses and triggers anomalies. Finally, through the pause mechanism and linkage with the trace buffer, non-intrusive real-time monitoring is achieved to ensure the efficient debugging and stable operation of the DSP processor.

[0017] (2) Trace buffer module

[0018] The trace buffer module is mainly used for tracking the DSP system processing program. The module architecture is as Figure 3 . Specifically, it includes two parts: a control enable / disable logic and a FIFO module. Among them:

[0019] The control enable / disable logic is responsible for dynamically controlling the write enable, pause, or termination operations of the FIFO according to the trigger signal of the bus monitoring module, the system interrupt / anomaly status, and the working mode configured by the special register. For example, in mode 3, writing is only allowed when triggered by a bus monitoring anomaly, and in mode 2, writing is paused during interrupt handling. At the same time, it triggers the anomaly handling process by monitoring the empty / full status of the FIFO cache, and decides whether to resume recording according to the register configuration after the processing is completed.

[0020] The FIFO module consists of two parts: status control and read / write control. The status control monitors the empty / full status of the FIFO buffer in real time and feeds it back to the control logic through the status register. For example, when the FIFO is full, the interrupt signal is raised and the write operation is locked. The read / write control, based on the enable signal of the control logic, writes the program PC value into the FIFO according to the first-in-first-out rule under the clock drive. The write operation is restricted by the working mode, system status, and FIFO capacity, or reads out the data in sequence in response to the read instruction.

[0021] The two work together. The control logic generates the FIFO enable signal according to the configuration mode and system events (such as bus exceptions and interrupts). The status control feeds back the FIFO buffer capacity in real time, and the read / write control performs data access accordingly, forming a closed loop. For example, when continuously writing in Mode 1, if the FIFO is about to be full, the status control triggers an interrupt, the control logic pauses the write operation and starts exception handling, and resumes writing after the data is read, thus achieving reliable recording and efficient backtracking of the program trace under non-intrusive debugging.

[0022] The trace buffer module has three different working modes to meet different debugging requirements. The diverse recording modes provide developers with rich program execution trace information, which helps to comprehensively understand the running state of the program.

[0023] Working Mode 1 is used for continuous tracking. When the trace buffer is not full and the system is not currently in the interrupt or exception handling state, the program PC value is cyclically written into the buffer. The write operation is controlled by judging the buffer status and system status. When the buffer is full, an interrupt signal is generated and the trace buffer module exception handler is entered. After the processing is completed, if the trace buffer module function is not turned off through the write register, the PC value continues to be cyclically written into the buffer.

[0024] Working Mode 2 is used for peripheral interrupt context recording and controls the start and stop of the write operation by monitoring the interrupt and exception signals. When the system is not in the interrupt or exception handling state, the PC value is continuously cyclically written into the buffer; when an interrupt or exception occurs, the write operation stops and the corresponding interrupt or exception handler is entered; after exiting the interrupt or exception handling, if the trace buffer module function is not turned off, the PC value continues to be cyclically written into the buffer.

[0025] Working mode 3, triggered by the bus monitoring module. Enter this mode when the bus monitoring module detects illegal access and issues a response signal; when the buffer is not full and the system is not in an interrupt or exception handling state, write the PC value into the buffer. After the buffer is full, enter the exception handler of the trace buffer module. Developers can read out the data in the buffer by reading instructions. After reading the data, close the function of the trace buffer module by writing to the register. It is realized through the signal transmission and mode switching logic between the bus monitoring module and the trace buffer module, achieving efficient collaborative debugging of the real-time monitor debugger. This tight collaboration enables non-intrusive debugging while detecting illegal memory access problems and obtaining the program running state information before and after the event.

[0026] Description of the technical features and performance advantages of the present invention:

[0027] A non-intrusive real-time monitor debugger system is proposed for the real-time debugging requirements of DSP processors. The debugger works in collaboration with the bus monitoring module and the trace buffer module, and adopts a hardware-level monitoring mechanism to achieve zero-interference debugging. The bus monitoring module is based on the address data range register module, the control logic module, and the violation detection module. It flexibly configures the illegal address range and operation enable bits through special registers, adopts a priority scheduling strategy to achieve parallel monitoring of instruction access and data read / write operations, and uses a hardware comparator to match the bus address signal in real time, accurately triggering exception events and linking the trace buffer module to record the context PC information. The trace buffer module adopts a configurable FIFO architecture, supports three working modes: continuous tracking, interrupt context recording, and bus trigger recording, combines control logic to dynamically manage the cache writing strategy, and ensures data integrity through a status feedback mechanism and an exception handling process. The system achieves high configurability through special registers, supports dynamic reset of the illegal address range, adjustment of monitoring priorities, and cache mode switching, enabling the debugging strategy to be flexibly adapted to different scenarios.

[0028] The performance advantages of this debugger are reflected in:

[0029] (1) The non-intrusive design ensures the full-speed operation of the DSP and avoids the interference of traditional breakpoint debugging on real-time performance;

[0030] (2) The hardware-level parallel monitoring mechanism realizes high-precision violation detection and supports independent analysis of instruction and data access;

[0031] (3) The trace buffer module provides a complete program execution trajectory before and after the event, and effectively improves the debugging information capture ability through the loop writing and exception handling cooperation mechanism;

[0032] (4) The pause mechanism and status self-check function enhance system stability, and the exception handling process ensures the reliability and controllability of the debugging process. This debugger significantly improves the efficiency and accuracy of real-time debugging of DSP processors through modular design and hardware cooperation mechanisms. Description of the Drawings

[0033] Figure 1 This is the structural block diagram of the non-invasive real-time monitoring debugger based on the DSP processor of the present invention.

[0034] Figure 2 This is the structural block diagram of the bus monitoring module in the real-time monitoring debugger.

[0035] Figure 3 This is the structural block diagram of the trace buffer module in the real-time monitoring debugger. Detailed Implementation Manner

[0036] (1) Definition of the special control special register group:

[0037] ① Control enable register:

[0038] Top-level control enable of the bus monitoring module:

[0039] [7]: Controls whether to issue an interrupt request when an illegal address access is detected;

[0040] [6]: Controls whether to output to the trace buffer module when an illegal address access is detected;

[0041] [5:4]: Controls whether to detect the instruction PC values in areas A and B;

[0042] [3:2]: Controls whether to detect the data RAM write (store) addresses in areas A and B;

[0043] [1:0]: Controls whether to detect the data RAM read (load) addresses in areas A and B;

[0044] ② Readable illegal address register:

[0045] The illegal addresses detected by the bus monitoring module are output and readable;

[0046] ③ Address data range register A:

[0047] Sets the start and end addresses of the data RAM detection area A of the bus monitoring module;

[0048] ④ Address data range register B:

[0049] Sets the start and end addresses of the data RAM detection area B of the bus monitoring module;

[0050] ⑤ Instruction PC register A:

[0051] Set the control instruction PC of the bus monitoring module to detect the start and end addresses of area A;

[0052] ⑥ Instruction PC register B:

[0053] Set the control instruction PC of the bus monitoring module to detect the start and end addresses of area B;

[0054] ⑦ Module status register:

[0055] The tracking buffer module status register saves the working mode;

[0056] ⑧ Tracking buffer module read register:

[0057] The tracking buffer module read enable register saves the PC value read from the FIFO;

[0058] ⑨ FIFO buffer:

[0059] It is used for the tracking buffer module to store and read the program PC value and jump address, and realizes the writing and reading of data through the read-write enable control signal, and the depth is configurable.

[0060] (2) Bus monitoring module

[0061] By default, the bus monitoring module is in an unmonitored state. Enable the module by writing the control enable register, and set the monitoring address through the address data range register or the instruction PC register (both have two types, A and B). The bus monitoring point will start to monitor the instruction execution address and the read-write address of the data memory in real time according to the configured enable bit and the illegal address range.

[0062] Judge the memory access address and the valid signal in each clock cycle, and compare them with the set illegal address range. Once it is detected that the access address is within the set illegal address range, the bus monitoring module will react, immediately issue an exception signal according to the set register control enable register, or output a corresponding signal to the tracking buffer module, and at the same time record the illegal address that triggers the problem. This illegal address can be read out through the readable illegal address register. At this time, the bus monitoring module pauses to continue monitoring. If you need to continue monitoring, you need to rewrite the control enable register to enable the module again.

[0063] (3) Tracking buffer module

[0064] To meet different debugging requirements, this tracking buffer module sets three different working modes, which are selected by configuring the module status register in actual use. Specifically:

[0065] ① The module status register is configured as 2’b01, enabling the trace buffer module to enter working mode 1. At this time:

[0066] When the FIFO in the module is not full and the processor is not in the state of peripheral interrupt response or kernel exception handling, the program PC value is cyclically written into the FIFO.

[0067] When the FIFO is full, the trace buffer module sends an interrupt signal to the peripheral interrupt source, and the processor responds and enters the interrupt handling program. At this time, the data in the FIFO can be read out through the corresponding read instruction.

[0068] After the interrupt handling program responds, continue to cyclically write the PC value into the FIFO, or the write function of the trace buffer module can be closed by writing the module status register.

[0069] ② The module status register is configured as 2’b10, enabling the trace buffer module to enter working mode 2. This mode controls the start and stop of the FIFO write operation by monitoring interrupt and exception signals:

[0070] When the processor does not enter the peripheral interrupt response or kernel exception handling, continuously cyclically write the PC value into the FIFO.

[0071] When the peripheral interrupt response or kernel exception handling starts, stop writing the PC value into the FIFO.

[0072] After entering the peripheral interrupt response or kernel exception handling program, read the value in the FIFO through the read instruction.

[0073] After the peripheral interrupt response or kernel exception handling program finishes execution, continue to cyclically write the PC value into the FIFO, or the write function of the trace buffer module can be closed by writing the module status register.

[0074] ③ Working mode 3 is used in cooperation with the bus monitoring module. The write and exception handling logics in this mode are implemented by judging the bus monitoring point signal and the trace buffer status:

[0075] Only when the bus monitoring module detects an illegal access and sends a response signal to the trace buffer module, the module status register is configured as 2’b11, and the trace buffer module enters this mode. The working mechanism after entering this mode refers to working mode 1.

[0076] (4) Cooperative debugging process

[0077] Start debugging: Initialize the registers of the two modules through the reset signal, perform the initialization configuration of the register parameters for the bus monitoring module and the trace buffer module respectively, select the appropriate working mode, and make both in the ready working state.

[0078] Running program: Start the program running of the DSP processor. In each clock cycle, the bus monitoring module performs real-time monitoring of memory access operations, and the trace buffer module records the real-time execution trajectory of program instructions according to the selected working mode.

[0079] Exception triggering and collaborative recording: When the bus monitoring module detects an illegal memory access operation, it sets the corresponding signal flag and sends a response signal to the trace buffer module. The trace buffer module enters working mode 3 according to this signal and starts recording the relevant program execution trajectory.

[0080] Data analysis and problem location: Developers comprehensively analyze by reading the register that saves the illegal address information provided by the bus monitoring module and the program execution trajectory recorded by the trace buffer module to find the root causes of problems in the program, such as code logic errors, memory management problems, etc.

[0081] Problem repair and verification: Repair and optimize the program according to the analysis results, run the program again, repeat the above debugging process, observe the outputs of the bus monitoring module and the trace buffer module, and verify whether the problem is solved until the program meets the expected performance and stability requirements.

[0082] (5) Simulation test

[0083] Verify the collaborative working function of the two major modules of the real-time running state monitor through simulation waveforms, and test the main function points of the bus monitoring module and the trace buffer module respectively.

[0084] The main function points of the bus monitoring module include: monitoring each bus channel, verifying the monitoring functions of the instruction PC, write data, and read data bus channels respectively, and two sections of illegal addresses can be set for each bus, and data comparison is made with the preset reference value in the register; bus monitoring priority test, the instruction PC, write data, and read data bus channels are configured in the register at the same time, and the monitoring priority of the module is divided according to instruction PC access > data memory write > data memory read; verification of the illegal monitoring output rule, when an illegal bus address / data is detected, the module outputs an interrupt exception signal, for example, when the trace buffer module responds to the illegal address in working mode 3, the writable register of the readable illegal address register is written.

[0085] The main functional points of the trace buffer module include: verification of the FIFO read and write data functions, calculation of read and write pointers, enable judgment, control conditions for empty and full judgments, and timing alignment processing; verification of three working modes of the trace buffer, triggering of register configuration / illegal detection of the bus monitoring module, circular writing / generation of interrupt requests when the FIFO in the cache is full, suspension / non - impact on the FIFO cache writing when an external interrupt signal is written, and saving the working mode in the status register; output of the FIFO cache, reading of the trace buffer module registers, and generation of interrupt requests when the PC value written to the readable cache FIFO is full in Mode 1 and Mode 3 configurations; triggering of the cooperative working mechanism of the trace buffer module in Working Mode 3 by the bus monitoring module.

[0086] During the actual working and debugging process, the bus monitoring module provides an illegal address register for debugging information, while the trace buffer module provides a record of the program execution trajectory to achieve non - intrusive debugging. While the system program is running normally, various system operation information can be obtained through non - intrusive debugging. By obtaining the above - mentioned debugging information, targeted analysis can be carried out for problems such as logical code errors in the program, the root cause of the problems in the program can be found, and the real - time system can be controlled according to the actual application requirements. Through non - intrusive real - time monitoring, analysis, and diagnosis, the debugging and performance optimization of the real - time control system can be realized, which can significantly improve the debugging efficiency and operation reliability of the real - time control system, and achieve the cooperation between the DSP architecture hardware resources and the diagnostic tools.

Claims

1. A non-invasive real-time monitoring debugger for a DSP processor, characterized in that, By directly configuring the dedicated control special register group inside it, setting up hardware breakpoints, developers can establish a complex breakpoint triggering mechanism independent of the debugger and debugging proxy software while maintaining the integrity of the program source code, introducing a "non-intrusive" debugging mechanism that does not interfere with the kernel. When a preset event is detected, the context program counter (PC) information is stored in an independent buffer area through a module with dedicated tracing function, and at the same time, the kernel can continue to execute task instructions at full speed; specifically: The real-time monitoring debugger includes a bus monitoring module and a trace buffer module, which jointly complete debugging and obtain real-time running information; the bus monitoring module monitors the memory access operations of the DSP processor, and at the same time, the trace buffer module records the execution traces of the program before and after the event, providing comprehensive and accurate debugging information for the system to quickly locate and solve problems that occur during the operation of the DSP processor, so as to improve the debugging efficiency; Highly configurable through setting special registers; for the bus monitoring module, different bus monitoring methods are implemented by reading and writing special registers to modify the illegal address range and enable bit configuration information; for the trace buffer module, different cache working modes are selected by reading and writing special registers; this configurability enables it to flexibly adjust the monitoring and recording strategies according to different debugging requirements, making the debugging process more targeted and efficient; In addition: After the bus monitoring module detects an illegal memory access, it automatically pauses the continuous monitoring function to avoid system instability caused by continuous exceptions; during exception handling, the trace buffer module is reasonably controlled according to the on / off status of the cache and the system operation to ensure the stability of data recording and reading. After the system problem or fault is handled, the monitoring and recording function is restarted by rewriting the special register again.

2. The non-invasive real-time monitoring debugger according to claim 1, characterized in that The bus monitoring module is used to monitor the access operations of the DSP processor to the instruction memory and data memory during operation, specifically including an address data range register module, a control logic module, and a violation detection module; among them: The data range register module stores the illegal address range and enable configuration preset by the developer through a special register interface, including two independent address intervals for the instruction memory and data memory respectively, denoted as A and B, each group contains two programmable address ranges, and the enable bits for separating the control of data read / write operations; The control logic module is responsible for scheduling the monitoring process, selecting the monitoring target in turn in each clock cycle according to the priority order of "instruction access > data write operation > data read operation", synchronously updating the configuration information in the data range register, and automatically pausing the monitoring function when an exception is detected to maintain system stability; The violation detection module receives the bus address signal in real time, and according to the monitoring mode selected by the control logic, uses a hardware comparator to match the current instruction address or data read / write address with the preset illegal address range. If the address falls into the enabled illegal interval, an exception signal is immediately triggered, the violation address is recorded and the trace buffer module is notified to save the context information, and at the same time, the control logic is forced to enter a paused state waiting for developer intervention; When the three work together, the developer first configures the illegal address and the enable bit through special registers. After the global enable, the control logic schedules the detection process step by step according to the priority. The violation detection module dynamically compares the addresses and triggers an exception. Finally, through the pause mechanism and the tracking buffer linkage, non-intrusive real-time monitoring is achieved to ensure the efficient debugging and stable operation of the DSP processor.

3. The non-invasive real-time monitoring debugger according to claim 2, wherein The tracking buffer module mainly performs the tracking of the DSP system processing program, specifically including two parts: the control enable / disable logic and the FIFO module; among them: The control enable / disable logic is responsible for dynamically controlling the write enable, pause or termination operations of the FIFO according to the trigger signal of the bus monitoring module, the system interrupt / exception status, and the working mode configured by the special register; at the same time, it triggers the exception handling process by monitoring the empty / full status of the FIFO cache, and decides whether to resume recording according to the register configuration after the processing is completed; The FIFO module includes two parts: status control and read / write control: the status control monitors the empty / full status of the FIFO cache in real time and feeds it back to the control logic through the status register; the read / write control writes the program PC value into the FIFO according to the first-in-first-out rule based on the enable signal of the control logic under the clock drive. The write operation is restricted by the working mode, system status, and FIFO capacity, or reads the data out in sequence in response to the read instruction; The two cooperate to work. The control logic generates the FIFO enable signal according to the configuration mode and system events. The status control feeds back the FIFO cache capacity in real time, and the read / write control performs data access accordingly to form a closed loop.

4. The non-invasive real-time monitoring debugger according to claim 3, characterized in that The tracking buffer module has three different working modes to meet different debugging requirements: Working mode 1 is used for continuous tracking; when the tracking buffer is not full and the system is not currently in the interrupt or exception handling state, the program PC value is cyclically written into the buffer, and the write operation is controlled by judging the buffer status and the system status; when the buffer is full, an interrupt signal is generated and enters the exception handling program of the tracking buffer module. After the processing is completed, if the tracking buffer module function is not turned off through the write register, the PC value continues to be cyclically written into the buffer; Working mode 2 is used for peripheral interrupt context recording, and the start and stop of the write operation are controlled by monitoring the interrupt and exception signals; When the system is not performing interrupt or exception handling, the PC value is continuously cyclically written into the buffer; when an interrupt or exception occurs, the write operation stops and enters the corresponding interrupt or exception handling program; After exiting the interrupt or exception handling, if the tracking buffer module function is not turned off, the PC value continues to be cyclically written into the buffer; Working mode 3, triggered by the bus monitoring module. When the bus monitoring module detects illegal access and issues a response signal, it enters this mode; when the buffer is not full and the system is not in the interrupt or exception handling state, it writes the PC value into the buffer; after the buffer is full, it enters the exception handler of the trace buffer module. Developers can read out the data in the buffer by reading instructions. After reading out the data, the function of the trace buffer module is turned off by writing to the register; through the signal transmission and mode switching logic between the bus monitoring module and the trace buffer module, the efficient collaborative debugging of the real-time monitoring debugger is realized. This close collaboration enables the acquisition of the program running state information before and after the event while detecting illegal memory access problems, for non-intrusive debugging.

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