Data processing method, device and equipment for electrically erasable memory

Abstract

The present application relates to the technical field of electrically erasable memory, and specifically to a data processing method, device and equipment of an electrically erasable memory. A data processing method for simulating an electrically erasable memory, the method comprising: in response to an access request, when the access request is a write request, writing the first data information carried by the write request into a first memory area according to the address information of the first memory address carried by the write request, and writing the address information of the first memory address and the first data information as an update record into a flash memory area; determining whether there is a first valid data record corresponding to the update record in the flash memory area through the address record information stored in the second memory area; when it is determined that the first valid data record exists in the flash memory area, setting the first valid data record to invalid, and updating the address record information in the second memory area.

Description

Technical Field

[0001] The present application relates to the technical field of electrically erasable memory, and in particular to a data processing method, device and equipment of an electrically erasable memory. Background Art

[0002] Analog electrically erasable memory usually includes volatile random access memory, such as random access memory (RAM, or ERAM) and non-volatile memory, such as electrically erasable non-volatile memory (such as FLASH or EFLASH), wherein the storage capacity of non-volatile memory is much larger than that of random access memory. Compared with conventional non-volatile memory, analog electrically erasable memory has higher durability and flexibility, therefore, it is suitable for automotive applications where data needs to be frequently updated and must be stored in a non-volatile manner.

[0003] In an analog electrically erasable memory system, when performing a write operation on an address of a non-volatile memory, the previous valid record of the corresponding address needs to be set to an invalid state. Generally, a polling method is used to query the previous valid data record of the corresponding address, which will cause the query time to be not a constant value, and the query time will increase with the increase of the non-volatile memory capacity, thus causing the entire write operation time to be longer. It is very meaningful to design an analog electrically erasable memory system that can quickly query valid data records. Summary of the invention

[0004] The embodiments of the present invention provide a data processing method, device and equipment for an electrically erasable memory, which are used to solve the problem in the prior art that the time for querying valid data records in a non-volatile memory is not a constant value, resulting in a longer write operation time.

[0005] In a first aspect, an embodiment of the present invention provides a data processing method for simulating an electrically erasable memory, the method comprising:

[0006] In response to an access request, when the access request is a write request, writing first data information carried by the write request into a first memory area according to address information of a first memory address carried by the write request, and writing the address information of the first memory address and the first data information into a flash memory area as an update record;

[0007] Determine whether there is a first valid data record corresponding to the update record in the flash memory area through the address record information stored in the second memory area;

[0008] When it is determined that the first valid data record exists in the flash memory area, the first valid data record is set to be invalid, and the address record information is updated in the second memory area.

[0009] Optionally, the address record information is each offset address of valid data records stored in the flash memory area;

[0010] The valid data record is a plurality of groups of address information and data information written in the flash memory area and not overwritten before the update record is written into the flash memory area, the address record information is respectively stored in each memory address of the second memory area, the memory address of the first memory area and the memory address of the second memory area are both physical addresses, and the memory address of the first memory area corresponds to the memory address of the second memory area one by one;

[0011] Determining whether there is a first valid data record corresponding to the update record in the flash memory area through the address record information stored in the second memory area includes:

[0012] Determine, by using the address information of the first memory address, whether an offset address of the flash memory area is stored in a corresponding second memory address in the second memory area;

[0013] When the offset address is stored in the second memory address, it is determined that a first history record corresponding to the update record exists in the flash memory area.

[0014] Optionally, setting the first valid data record to invalid includes:

[0015] Determining the first valid data record stored in the flash memory area by using the address record information;

[0016] The flag information in the first valid data record is changed to flag information indicating that the first valid data record is an invalid record.

[0017] Optionally, updating the address record information in the second memory area includes:

[0018] The address information stored in the second memory address is changed to the offset address of the flash memory area storing the update record.

[0019] Optionally, before writing the address information of the first memory address and the first data information into the flash memory area as an update record, the step includes:

[0020] Determining whether there is an active sector in the sectors of the flash memory area;

[0021] When there is an active sector, writing the update record into an empty address of the active sector;

[0022] When the active sector does not exist, determining the active sector from the empty sectors, and determining whether the number of the empty sectors in the flash memory area is less than a preset first threshold when the number of the empty sectors changes;

[0023] When the number of empty sectors in the flash memory area is less than a preset first threshold, determining a compressed sector from the full sectors in the flash memory area;

[0024] Determining whether the number of empty sectors in the flash memory area is less than a preset second threshold;

[0025] When the number of empty sectors in the flash memory area is not less than the second threshold, compressing a first number of valid data records in the compressed sector;

[0026] When the number of empty sectors in the flash memory area is less than the second threshold, compressing a second number of valid data records in the compressed sector;

[0027] The second threshold is lower than the first threshold, and the second number is smaller than the first number.

[0028] Optionally, determining a compressed sector from a full sector of the flash memory area includes:

[0029] Determining the full sector with the least number of erases among all the full sectors as the compressed sector;

[0030] When there are at least two full sectors with the least number of erase times, the full sector with the least number of valid data records is determined as the compressed sector.

[0031] In a second aspect, an embodiment of the present invention provides an analog electrically erasable memory, comprising: a memory controller, a first memory area, a second memory area, and a flash memory area;

[0032] The memory controller is configured to receive an access request sent by a processor, and when the access request is a write request, write the first data information carried by the write request into a first memory area according to the address information of the first memory address carried by the write request, and write the address information of the first memory address and the first data information into a flash memory area as an update record;

[0033] Determine whether there is a first valid data record corresponding to the update record in the flash memory area through the address record information stored in the second memory area;

[0034] When it is determined that the first valid data record exists in the flash memory area, the first valid data record is set to be invalid, and the address record information is updated in the second memory area.

[0035] Optionally, the address record information is each offset address of valid data records stored in the flash memory area;

[0036] The valid data record is a plurality of sets of address information and data information written in the flash memory area before the update record is written into the flash memory area, the address record information is respectively stored in each memory address of the second memory area, the memory address of the first memory area and the memory address of the second memory area are both physical addresses, and the memory address of the first memory area corresponds to the memory address of the second memory area one by one;

[0037] Determining whether there is a first valid data record corresponding to the update record in the flash memory area through the address record information stored in the second memory area includes:

[0038] Determine, by using the address information of the first memory address, whether an offset address of the flash memory area is stored in a corresponding second memory address in the second memory area;

[0039] When the offset address is stored in the second memory address, it is determined that a first valid data record corresponding to the update record exists in the flash memory area.

[0040] Optionally, setting the first valid data record to invalid includes:

[0041] Determining the first valid data record stored in the flash memory area by using the address record information;

[0042] The flag information in the first valid data record is changed to flag information indicating that the first valid data record is an invalid record.

[0043] Optionally, updating the address record information in the second memory area includes:

[0044] The address information stored in the second memory address is changed to the offset address of the flash memory area storing the update record.

[0045] Optionally, it also includes: a valid record number storage;

[0046] The valid record number memory is used to count the number of valid data records in each sector of the flash memory area according to the control instruction of the memory controller.

[0047] Optionally, before the memory controller writes the address information of the first memory address and the first data information into the flash memory area as an update record, the process includes:

[0048] Determining whether there is an active sector in the sectors of the flash memory area;

[0049] When there is an active sector, writing the update record into an empty address of the active sector;

[0050] When the active sector does not exist, determining the active sector from the empty sectors, and determining whether the number of the empty sectors in the flash memory area is less than a preset first threshold when the number of the empty sectors changes;

[0051] When the number of empty sectors in the flash memory area is less than a preset first threshold, determining a compressed sector from the full sectors in the flash memory area;

[0052] Determining whether the number of empty sectors in the flash memory area is less than a preset second threshold;

[0053] When the number of empty sectors in the flash memory area is not less than the second threshold, compressing a first number of valid data records in the compressed sector;

[0054] When the number of empty sectors in the flash memory area is less than the second threshold, compressing a second number of valid data records in the compressed sector;

[0055] The second threshold is lower than the first threshold, and the second number is smaller than the first number.

[0056] Optionally, determining a compressed sector from a full sector of the flash memory area includes:

[0057] Determining the full sector with the least number of erases among all the full sectors as the compressed sector;

[0058] When there are at least two full sectors with the least number of erase times, the full sector with the least number of valid records is determined as the compressed sector.

[0059] Optionally, the first memory area is a volatile random access memory ERAM, the second memory area is a volatile address random access memory ARAM, and the flash memory area is a non-volatile memory EFLASH.

[0060] In a third aspect, an embodiment of the present invention provides a microprocessor chip, including a processor and the analog electrically erasable memory described in any one of the first aspects;

[0061] The microprocessor chip is used to send access requests to the memory controller in the analog electrically erasable memory through the processor, and the access requests include read requests and write requests.

[0062] In an embodiment of the present invention, a second memory area is set and address record information is stored therein to enable a quick query of a first valid data record that needs to be overwritten, without the need to poll the flash memory area to query the first valid record, thereby reducing the time for the analog electrically erasable memory to execute a write request. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0064] Figure 1 Shown is a schematic diagram of a microprocessor chip provided in an embodiment of the present application;

[0065] Figure 2 The figure is a flow chart of a data processing method of an electrically erasable memory provided by an embodiment of the present application;

[0066] Figure 3 Shown is a schematic diagram of an analog electrically erasable memory provided by an embodiment of the present application;

[0067] Figure 4 Shown is a schematic diagram of an analog electrically erasable memory provided by an embodiment of the present application;

[0068] Figure 5 Shown is a schematic diagram of an analog electrically erasable memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0070] It should be clear that the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0071] like Figure 1 As shown in FIG. 1 , a microprocessor chip is provided in an embodiment of the present invention. Figure 1The microprocessor chip includes: a processor 110, an analog electrically erasable memory 120, and may also include other modules 130. The analog electrically erasable memory 120 specifically includes a memory controller 121, a first memory area 122, a flash memory area 123, a second memory area 124, and a valid record number memory 125. The processor 110, the analog electrically erasable memory 120 and the other modules 130 are bidirectionally coupled through a system bus.

[0072] The processor may be any type of processor, such as a microprocessor, a digital signal processor, or any other type of interconnected host controller that can access the analog electrically erasable memory. The first memory area may be a volatile random access memory ERAM for simulating EEPROM, the flash memory area may be a non-volatile memory EFLASH for backing up EEPROM data, and the second memory area may be a volatile memory ERAM for recording addresses in EFLASH corresponding to valid data of ERAM data.

[0073] Among them, ERAM is a volatile random access memory with fast read and write speed; EFLASH is a non-volatile random access memory with slower read and write speed than ERAM. ARAM has various organizational forms. It can share a memory with ERAM or be an independent memory. The valid record number memory is used to count the valid data records in each sector under the control of the memory controller to store the number of valid data records in each sector.

[0074] There are also many forms of the effective record number memory, which can be an independent memory independent of the flash memory area 123, or a region of the flash memory area 123 can be divided as the effective record number memory 124. The present invention preferably uses the effective record number memory 124 as an independent memory, so that the original division structure and method of the flash memory area 123 do not need to be changed, making the control more concise. The reset signal is used to reset the processor, the effective record number memory and the memory controller.

[0075] The processor 110 is used to send an access request to the memory controller in the analog electrically erasable memory 120. The access request may be a read request or a write request. When the access request is a read request, the read request sent needs to include the corresponding access address; when the access request is a write request, the write request sent needs to carry the first data information to be written to the first memory address, and the address information of the first memory address.

[0076] The memory controller 121 is used to determine the type of access request after receiving the access request. In the case where the access request is a read access, the memory controller accesses the first memory area and transmits the data of the corresponding address back to the processor. In the case where the access request is a write access, the memory controller will first detect whether the first memory area needs to be updated. If the data needs to be written to the first memory address corresponding to the first memory area, the first data information and the first memory address will be written to the next available address in the flash memory area, and the number of valid data records of the current sector will be updated. If the data of the write request is consistent with the data of the corresponding address of the first memory area, there is no need to update the first memory area. When the data of the write request is different from the data of the corresponding address, the first memory area needs to be updated and written to the flash memory area. This can save time for the entire write process, improve the write speed, and there is no need to occupy additional space in the flash memory area, thereby increasing the period for the flash memory area to be written, and the number of times invalid data is erased and the number of times valid data is transferred is reduced in the later stage, thereby improving durability.

[0077] When writing the data record into the flash memory area, the first data information and the address information of the first memory address need to be written into the active sector of the flash memory area and stored in the form of data record.

[0078] The flash memory area is used to store data records, and the data records can be divided into valid data records and invalid data records according to the flag bit information therein.

[0079] After writing the address information of the first memory address and the first data as an update record into the flash memory area, it is necessary to determine whether there is a first valid data record corresponding to the update record in the valid data records stored in the flash memory area, that is, to determine whether there is a data record previously written to the first memory area in the flash memory area. If it exists, it is necessary to modify the flag bit information of the first valid data record to an invalid state to achieve overwriting of the first valid data record and make it invalid data.

[0080] Generally, the first valid data record can be queried in the flash memory area by polling, that is, the previous valid data record corresponding to the first memory address can be queried. However, this method will cause the query time to be not a constant value, and the query time will increase with the increase of the capacity of the analog electrically erasable memory, resulting in a longer write operation time.

[0081] In the embodiment of the present invention, a second memory area is provided in the memory controller 120. The second memory area is used to store address record information to achieve fast query of the first valid data record.

[0082] After each update record is written into the flash memory area, the memory controller will store the offset address of the flash memory area for storing the update record into the corresponding address of the second memory area according to the corresponding relationship with the first memory area. Therefore, after the update record is written into the flash memory area, it is no longer necessary to locate the first valid data record corresponding to the update record by polling all valid data records in the flash memory area, but it can be determined by only querying the address record information stored in the second memory area.

[0083] like Figure 2 As shown, a data processing method for simulating an electrically erasable memory is provided in an embodiment of the present invention. This method is applied to Figure 1 The memory controller shown in Figure 2 The specific steps of the method include:

[0084] S201, in response to an access request, when the access request is a write request, first data information carried by the write request is written into a first memory area according to address information of a first memory address carried by the write request, and the address information of the first memory address and the first data information are written into a flash memory area as an update record. The update record is a data record that is most recently written into the flash memory area.

[0085] Specifically, the memory controller in the simulated electrically erasable memory responds to the access request issued by the processor and determines the type of the access request. When the access request is a read request, the corresponding access address is accessed, and the corresponding data is read and transmitted back to the processor, without performing a write operation in the first memory area, the flash memory area, and the second memory area. When the access request is a write request, the first data information carried by the write request is written into the first memory address of the first memory area according to the address information of the first memory address carried by the write request, and the address information of the first memory address and the first data information are written into the flash memory area as an update record.

[0086] Furthermore, in the case of a write request, the memory controller will first detect whether the first memory area needs to be updated. If the first data information carried by the write request is consistent with the data stored in the first memory area, there is no need to update the first memory area. When the first data information of the write request is inconsistent with the data stored in the first memory area, it is necessary to update the first memory area and write the update record to the flash memory area. This can save time for the entire write process, increase the write speed, and there is no need to occupy additional space in the flash memory area, thereby increasing the period for the flash memory area to be available for writing, and later on, it also reduces the number of invalid data erasures and the number of valid data transfers, thereby improving durability.

[0087] S202: Determine whether there is a first valid data record corresponding to the update record in the flash memory area through the address record information stored in the second memory area.

[0088] Specifically, the second memory area stores address record information. The address record information is the offset address of each valid data record stored in the flash memory area. The valid data record is a plurality of sets of address information and data information written in the flash memory area and not overwritten before executing S201 to write the update record into the flash memory area.

[0089] The address record information is stored in each memory address of the second memory area. The memory address of the first memory area and the memory address of the second memory area are both physical addresses, and the memory address of the first memory area corresponds to the memory address of the second memory area. The memory address of the first memory area can be quickly indexed to the corresponding memory address of the first memory area through the memory address of the second memory area.

[0090] In an embodiment of the present invention, when determining whether there is a first valid data record in the flash memory area through the address record information stored in the second memory area, it is determined whether the offset address of the flash memory area is stored in the corresponding second memory address in the second memory area through the address information of the first memory address. When the offset address of the flash memory area is not stored in the second memory address of the second memory area, it can be determined that there is no first historical record in the flash memory area; when the offset address of the flash memory area is stored in the second address of the second memory area, it can be determined that there is a first historical record in the flash memory area, and the offset address stored in the second address is the address of the second memory area for storing the first historical record.

[0091] like Figure 3 FIG. 1 is a schematic diagram of a second memory area provided by an embodiment of the present invention. Figure 3 , the second memory area contains 256 rows, each row is used to store an address record information. Since the memory address of the second memory area corresponds to the memory address of the first memory area, when writing data to the first memory address, the offset address of the flash memory area storing data is written into the corresponding second memory address.

[0092] like Figure 3 As shown, in the first row of the second memory area, the physical address of the second memory area is 0x000, and the data stored therein is 0x3FE, which means that in the first memory area, the address 0x000 and the data information therein are stored as valid data records in the address 0x3FE of the flash memory area.

[0093] In the second row of the second memory area, the physical address of the second memory area is 0x001, and no data information is stored therein, which means that in the first memory area, the data at the address 0x001 is empty, and 0x001 and the data therein are not recorded as valid data in the flash memory area for storage.

[0094] In the third row of the second memory area, the physical address of the second memory area is 0x002, and the data stored therein is 0x303, which means that in the first memory area, the address 0x002 and the data information therein are stored as valid data records in the address 0x303 of the flash memory area.

[0095] The meanings represented by the subsequent rows are similar, and are all the address information corresponding to the first memory area and the address where the data information therein is written into the flash memory area as valid data records, which will not be repeated again.

[0096] S203: When it is determined that there is a first valid data record in the flash memory area, the first valid data record is set to be invalid, and the address record information is updated in the second memory area.

[0097] Specifically, when setting the first valid data record to invalid, it is necessary to determine the first valid data record stored in the flash memory area through the address record information of the second memory area, that is, determine the first valid data record from the flash memory area through the offset address stored under the corresponding memory address in the second memory area. After determining the first valid data record, the flag information in the first valid data record is changed to the flag information indicating that the first valid data record is an invalid record.

[0098] Among them, each data record stored in the flash memory area, in addition to the address information included in the first memory area and the data information in the corresponding address information, also includes a flag information used to characterize whether the data record is valid. When the flag information is recorded as valid, it means that the data record is a valid data record; when the flag information is recorded as invalid, it means that the data record is an invalid data record. Generally, when the data record is written into the flash memory area, the flag information is recorded as valid, that is, the data record is a valid data record; when the data in the corresponding address of the first memory area is updated, and the new data information is updated and written into the flash memory area, the flag information is modified to invalid, that is, the data record is an invalid data record.

[0099] When the address record information is updated in the second memory area, the address record information is updated by changing the address information stored in the second memory address to the offset address of the update record stored in the flash memory area.

[0100] like Figure 4FIG. 1 is a schematic diagram of a flash memory area provided by an embodiment of the present invention. Figure 4 The first line is the sector information, which is used to record the sector status and the number of times the sector has been erased. The second to last lines are stored data records, and each line is used to store one data record.

[0101] In each data record, the first column is flag information, which is used to record whether the data record is a valid data record or an invalid data record; the second column is address information, which is used to store the memory address of the corresponding first memory area; the third column is data information, which is used to actually store the written data, that is, the data information in the memory address in the first memory area. In addition, the dotted box indicates the offset address of each data record stored in the flash memory area.

[0102] See also Figure 4 , multiple data records are stored in the flash memory area. In the first row of the flash memory area, the data record stored at the address 0x300 is: data 0x1111 in the address 0x000 in the first memory area, and the flag information indicates that the data record is an invalid data record. In the second row of the flash memory area, the data record stored at the address 0x301 is: data 0x2222 in the address 0x000 in the first memory area, and the flag information indicates that the data record is an invalid data record. In the third row of the flash memory area, the data record stored at the address 0x303 is: data 0x3333 in the address 0x002 in the first memory area, and the flag information indicates that the data record is a valid data record. In the fourth row of the flash memory area, the data record stored at the address 0x304 is: data 0x1111 in the address 0x003 in the first memory area, and the flag information indicates that the data record is a valid data record. The data record stored in the fifth row of the flash memory area, that is, at address 0x305, is: data 0x4444 at address 0x1FE in the first memory area, and the flag information indicates that the data record is a valid data record.

[0103] In an embodiment of the present invention, a second memory area is set and address record information is stored therein to enable a quick query of a first valid data record that needs to be overwritten, without the need to poll the flash memory area to query the first valid data record, thereby reducing the time for the analog electrically erasable memory to execute a write request.

[0104] The following is a specific embodiment provided by the present application, which is used to illustrate the process when the memory controller performs a write operation. Figure 5The figure shows a specific analog electrically erasable memory provided by an embodiment of the present invention, and specifically shows the corresponding relationship between the first memory area, the second memory area and the flash memory area, wherein the first memory area is specifically ERAM, the second memory area is specifically ARAM, and the flash memory area is specifically EFLASH.

[0105] See also Figure 5 , the memory controller receives the access request sent by the processor, determines that the access request is a write request, and determines from the write request that the first memory address is 0x000 and the first data information is 0x1111, and stores the first record. Write 0x1111 to the ERAM address 0x000, write the address information 0x000 and the data information 0x1111 to the first row of the active sector of the EFLASH as an update record, and set its flag information to valid.

[0106] Determine whether there is a first valid data record in EFLASH through ARAM. Access the 0x000 address in ARAM. Since the 0x000 address in ARAM contains the initial data, that is, it is empty, it can be determined that there is no first valid data record corresponding to the 0x000 address in ERAM in EFLASH, that is, there is no valid data record of the 0x000 address previously written in EFLASH. Write the offset address 0x301 of the update record written in EFLASH into ARAM and the corresponding address 0x000 to update the address record information, completing a write operation.

[0107] Further, the memory controller receives the access request sent by the processor, determines that the access request is a write request, and determines from the write request that the first memory address is 0x000 and the first data information is 0x2222, and stores the second record. 0x2222 is written to the ERAM address 0x000, and the address information 0x000 and the data information 0x2222 are written to the next row of the active sector of the EFLASH as an update record, and its flag information is set to be valid.

[0108] Determine whether there is a first valid data record in EFLASH through ARAM. Access the 0x000 address in ARAM. Since the 0x000 address in ARAM is 0x301, it can be determined that there is a first valid data record corresponding to the 0x000 address in ERAM in EFLASH, and the address storing the first valid data record is 0x301. Based on this, access the 0x301 address of EFLASH, modify the flag information of the first valid data record to invalid, and re-write the offset address 0x302 of the update record in EFLASH into ARAM and the corresponding address 0x000 to update the address record information, completing a write operation.

[0109] Further, the memory controller receives the access request sent by the processor, determines that the access request is a write request, and determines from the write request that the first memory address is 0x002 and the first data information is 0x3333, and stores the third record. 0x3333 is written to the ERAM address 0x002, and the address information 0x002 and the data information 0x3333 are written to the next row of the active sector of the EFLASH as an update record, and its flag information is set to be valid.

[0110] Determine whether there is a first valid data record in EFLASH through ARAM. Access address 0x002 in ARAM. Since address 0x002 in ARAM contains initial data, that is, it is empty, it can be determined that there is no first valid data record corresponding to address 0x002 in ERAM in EFLASH, that is, there is no valid data record of address 0x000 previously written in EFLASH. Write the offset address 0x303 of the update record written in EFLASH into ARAM and the corresponding address 0x002 to update the address record information, completing a write operation.

[0111] Further, the memory controller receives the access request sent by the processor, determines that the access request is a write request, and determines from the write request that the first memory address is 0x000, the first data information is 0x5555, and stores the 255th record. 0x5555 is written to the ERAM address 0x000, and the address information 0x000 and the data information 0x5555 are written to the next row of the active sector of the EFLASH as an update record, and its flag information is set to be valid.

[0112] Determine whether there is a first valid data record in EFLASH through ARAM. Access the 0x000 address in ARAM. Since the 0x000 address of ARAM is 0x302, it can be determined that there is a first valid data record corresponding to the 0x000 address of ERAM in EFLASH, and the address storing the first valid data record is 0x302. Based on this, access the 0x302 address of EFLASH, modify the flag information of the first valid data record to invalid, and re-write the offset address 0x3FE of the update record of EFLASH into ARAM and the corresponding address 0x000 to update the address record information, completing a write operation.

[0113] In the above solution, when writing the update record into the second memory area, it needs to be written into the active sector of the second memory area, wherein the second memory area includes a plurality of sectors, each of which is used to store data.

[0114] The types of sectors include active sectors, which are sectors where data is currently being written. In addition to active sectors, there are also empty sectors and full sectors. Empty sectors are sectors where no data records are written at any empty addresses, and full sectors are sectors that are already full of data records and do not have empty addresses for writing new data records. When an active sector is filled with data, it becomes a full sector.

[0115] When the active sector is filled with data records, a sector needs to be re-determined from the empty sectors as the active sector to continue filling data records. In order to ensure that there is a certain amount of storage space, thereby maintaining the durability of the system, it is necessary to ensure that there is a certain number of empty sectors. Therefore, when the number of empty sectors is lower than a preset threshold, the memory controller is also used to perform sector compression on the current full sector and re-compress it into an empty sector to ensure the number of empty sectors.

[0116] When performing sector compression, if too much compressed data is recorded during each write operation, the write operation will take too long, so the compressed data should not be recorded too much during each write operation. However, if too little compressed data is recorded during each write operation, it may result in the failure to release empty sectors in time, resulting in no flash memory area being filled and no space to write new data; in order to solve this problem, more empty sectors need to be reserved, but too many empty sectors will affect the durability of the analog electrically erasable system.

[0117] Therefore, in order to solve the problem of balancing durability and write operation time, the embodiment of the present invention performs sector compression by dynamically adjusting the number of compressed valid data records.

[0118] Specifically, before the memory controller writes the address information of the first memory address and the first data information as an update record into the flash memory area, it needs to determine whether there is an active sector among all sectors of the flash memory area. When there is an active sector, the update record is directly written into the next empty address of the active sector; when there is no active sector, it is necessary to determine an active sector from the current multiple empty sectors and then write the update record into it.

[0119] After the sector status of the empty sector is changed to an active sector, the number of empty sectors in the flash memory area decreases, and it is determined whether the number of empty sectors in the flash memory area is less than a preset first threshold. When the number of empty sectors is less than the preset first threshold, it is necessary to trigger the execution of sector compression, determine a compressed sector from the full sectors of the flash memory area, and compress the valid data records in the compressed sector.

[0120] When it is determined that sector compression needs to be performed, it is further determined whether the number of empty sectors is less than a second threshold value. When the number of empty sectors is not less than the second threshold value, a first number of valid data records are compressed in the compressed sector; when the number of empty sectors is less than the second threshold value, a second number of valid data records are compressed in the compressed sector. The second threshold value is lower than the first threshold value, and the second number is less than the first number.

[0121] Optionally, when determining the compressed sector from the full sectors of the flash memory area, it is necessary to determine the full sector with the least number of erases among all the full sectors as the compressed sector, so as to ensure that the number of erases of each sector tends to be the same after multiple executions of sector compression, and there will be no damage caused by repeated erasures of a certain sector. When there are at least two full sectors with the least and the same number of erases, the full sector with the least valid data recorded is determined as the compressed sector, so as to ensure that executing sector compression can release more space.

[0122] The number of compression times of the sector and the number of valid data records stored in the compressed sector are both realized by the valid record number memory.

[0123] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0124] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this specification, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0125] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of this specification includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of this specification belong.

[0126] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0127] It should be noted that the terminals involved in the embodiments of this specification may include but are not limited to personal computers (Personal Computer; hereinafter referred to as: PC), personal digital assistants (Personal Digital Assistant; hereinafter referred to as: PDA), wireless handheld devices, tablet computers (Tablet Computer), mobile phones, MP3 players, MP4 players, etc.

[0128] In the embodiments provided in this specification, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0129] In addition, each functional unit in each embodiment of this specification may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0130] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform some steps of the method described in each embodiment of this specification.

[0131] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A data processing method for simulating an electrically erasable memory, characterized in that: The method comprises: In response to an access request, when the access request is a write request, writing first data information carried by the write request into a first memory area according to address information of a first memory address carried by the write request, and writing the address information of the first memory address and the first data information into a flash memory area as an update record; Determine whether there is a first valid data record corresponding to the update record in the flash memory area through the address record information stored in the second memory area; When it is determined that the first valid data record exists in the flash memory area, the first valid data record is set to be invalid, and the address record information is updated in the second memory area.

2. The method according to claim 1, characterized in that The address record information is each offset address of the flash memory area storing valid data records; The valid data record is a plurality of groups of address information and data information written in the flash memory area and not overwritten before the update record is written into the flash memory area, the address record information is respectively stored in each memory address of the second memory area, the memory address of the first memory area and the memory address of the second memory area are both physical addresses, and the memory address of the first memory area corresponds to the memory address of the second memory area one by one; Determining whether there is a first valid data record corresponding to the update record in the flash memory area through the address record information stored in the second memory area includes: Determine, by using the address information of the first memory address, whether an offset address of the flash memory area is stored in a corresponding second memory address in the second memory area; When the offset address is stored in the second memory address, it is determined that a first history record corresponding to the update record exists in the flash memory area.

3. The method according to claim 1, characterized in that The step of setting the first valid data record to invalid comprises: Determining the first valid data record stored in the flash memory area by using the address record information; The flag information in the first valid data record is changed to flag information indicating that the first valid data record is an invalid record.

4. The method according to claim 1, characterized in that: The updating of the address record information in the second memory area includes: The address information stored in the second memory address is changed to the offset address of the flash memory area storing the update record.

5. The method according to claim 1, characterized in that Before writing the address information of the first memory address and the first data information as an update record into the flash memory area, the method includes: Determining whether there is an active sector in the sectors of the flash memory area; When there is an active sector, writing the update record into an empty address of the active sector; When the active sector does not exist, determining the active sector from the empty sectors, and determining whether the number of the empty sectors in the flash memory area is less than a preset first threshold when the number of the empty sectors changes; When the number of empty sectors in the flash memory area is less than a preset first threshold, determining a compressed sector from the full sectors in the flash memory area; Determining whether the number of empty sectors in the flash memory area is less than a preset second threshold; When the number of empty sectors in the flash memory area is not less than the second threshold, compressing a first number of valid data records in the compressed sector; When the number of empty sectors in the flash memory area is less than the second threshold, compressing a second number of valid data records in the compressed sector; The second threshold is lower than the first threshold, and the second number is smaller than the first number.

6. The method according to claim 5, characterized in that Determining a compressed sector from the full sectors of the flash memory area includes: Determining the full sector with the least number of erases among all the full sectors as the compressed sector; When there are at least two full sectors with the least number of erase times, the full sector with the least number of valid data records is determined as the compressed sector.

7. An analog electrically erasable memory, characterized in that: include: A memory controller, a first memory area, a second memory area, and a flash memory area; The memory controller is configured to receive an access request sent by a processor, and when the access request is a write request, write the first data information carried by the write request into a first memory area according to the address information of the first memory address carried by the write request, and write the address information of the first memory address and the first data information into a flash memory area as an update record; Determine whether there is a first valid data record corresponding to the update record in the flash memory area through the address record information stored in the second memory area; When it is determined that the first valid data record exists in the flash memory area, the first valid data record is set to be invalid, and the address record information is updated in the second memory area.

8. The memory controller according to claim 7, wherein: The address record information is each offset address of the flash memory area storing valid data records; The valid data record is a plurality of sets of address information and data information written in the flash memory area before the update record is written into the flash memory area, the address record information is respectively stored in each memory address of the second memory area, the memory address of the first memory area and the memory address of the second memory area are both physical addresses, and the memory address of the first memory area corresponds to the memory address of the second memory area one by one; Determining whether there is a first valid data record corresponding to the update record in the flash memory area through the address record information stored in the second memory area includes: Determine, by using the address information of the first memory address, whether an offset address of the flash memory area is stored in a corresponding second memory address in the second memory area; When the offset address is stored in the second memory address, it is determined that a first valid data record corresponding to the update record exists in the flash memory area.

9. The memory controller according to claim 7, wherein: The step of setting the first valid data record to invalid comprises: Determining the first valid data record stored in the flash memory area by using the address record information; The flag information in the first valid data record is changed to flag information indicating that the first valid data record is an invalid record.

10. The memory controller according to claim 7, wherein: The updating of the address record information in the second memory area includes: The address information stored in the second memory address is changed to the offset address of the flash memory area storing the update record.

11. The analog electrically erasable memory according to claim 7, characterized in that: Also includes: Valid record number storage; The valid record number memory is used to count the number of valid data records in each sector of the flash memory area according to the control instruction of the memory controller.

12. The effective record number storage device according to claim 11, characterized in that: Before the memory controller writes the address information of the first memory address and the first data information into the flash memory area as an update record, the method includes: Determining whether there is an active sector in the sectors of the flash memory area; When there is an active sector, writing the update record into an empty address of the active sector; When the active sector does not exist, determining the active sector from the empty sectors, and determining whether the number of the empty sectors in the flash memory area is less than a preset first threshold when the number of the empty sectors changes; When the number of empty sectors in the flash memory area is less than a preset first threshold, determining a compressed sector from the full sectors in the flash memory area; Determining whether the number of empty sectors in the flash memory area is less than a preset second threshold; When the number of empty sectors in the flash memory area is not less than the second threshold, compressing a first number of valid data records in the compressed sector; When the number of empty sectors in the flash memory area is less than the second threshold, compressing a second number of valid data records in the compressed sector; The second threshold is lower than the first threshold, and the second number is smaller than the first number.

13. The memory controller according to claim 12, wherein: Determining a compressed sector from the full sectors of the flash memory area includes: Determining the full sector with the least number of erases among all the full sectors as the compressed sector; When there are at least two full sectors with the least number of erase times, the full sector with the least number of valid records is determined as the compressed sector.

14. The analog electrically erasable memory according to claim 7, characterized in that: The first memory area is a volatile random access memory ERAM, the second memory area is a volatile address random access memory ARAM, and the flash memory area is a non-volatile memory EFLASH.

15. A microprocessor chip comprising a processor and the analog electrically erasable memory according to any one of claims 7 to 14; The microprocessor chip is used to send access requests to the memory controller in the analog electrically erasable memory through the processor, and the access requests include read requests and write requests.

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