Chip, chip system, processor and computing device

Abstract

The invention provides a chip, a chip system, a processor and computing equipment. The chip comprises an exchange core grain used as a data routing node and / or a central controller; the at least one memory core particle is used for storing data; at least one computing core particle for computing data; wherein the exchange core particle comprises a bus and at least two core particle interfaces which are connected with each other through the bus; the exchange core particle is respectively interconnected with at least one memory core particle through at least one core particle interface, and is respectively interconnected with at least one calculation core particle through a first core particle interface; wherein the first core particle interface comprises at least two core particle interfaces except the core particle interface connected with at least one memory core particle. According to the scheme in the embodiment of the invention, the manufacturing cost, the expandability, the reusability and the flexible function of the chip can be balanced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a chip, a chip system, a processor, and a computing device. Background Art

[0002] Moore's Law drives computing performance by increasing the number of transistors at a constant cost per unit area. However, as transistor technology reaches single-digit nanometer nodes, manufacturing complexity slows down the reduction in transistor size and increases the cost of each transistor. In order to continue to increase the number of transistors without increasing manufacturing costs, multi-die packaging methods can be used. However, in the context of high performance and high integration requirements, chip design still faces the challenge of balancing manufacturing costs and flexible functions. Summary of the invention

[0003] In view of the shortcomings of existing methods, this application proposes a chip, a chip system, a processor and a computing device to solve the technical problems faced by chip design in related technologies in terms of how to balance manufacturing costs, scalability, reusability and flexible functions.

[0004] In a first aspect, an embodiment of the present application provides a chip, including: A switch core that acts as a data routing node and / or central controller; at least one memory chip for storing data; At least one computing core particle, used for computing data; Wherein, the switching core comprises a bus and at least two core interfaces interconnected by the bus; The switch core is interconnected with the at least one memory core through at least one core interface, and is interconnected with the at least one computing core through a first core interface; The first chip interface includes a chip interface among the at least two chip interfaces except the chip interface connected to the at least one memory chip.

[0005] In a second aspect, an embodiment of the present application provides a chip system, including: M chips as described in the first aspect; Among them, M chips are interconnected through the switching core particles included in each chip to form a two-dimensional topological structure, M is 2 to the power of N, and N is a positive integer.

[0006] In a third aspect, an embodiment of the present application provides a chip system, including: At least one chip unit, each chip unit comprising at least two chip systems of the two-dimensional topological structure as described in the second aspect; Among them, at least two chip systems of the two-dimensional topological structure form a three-dimensional mesh topological structure by interconnecting the chips in each chip system of the two-dimensional topological structure.

[0007] In a fourth aspect, an embodiment of the present application provides a processor, including: The chip according to the first aspect; or A chip system with a two-dimensional topological structure as described in the second aspect; or, A chip system with a three-dimensional mesh topology structure as described in the third aspect.

[0008] In a fifth aspect, an embodiment of the present application provides a computing device, comprising: a processor as described in the fourth aspect.

[0009] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include: The chip provided by the solution of the embodiment of the present application includes a switching core particle that serves as a data routing node and / or a central controller, which can work in conjunction with various computing core particles to build a high-performance, flexible and cost-effective core particle scalable system, thereby balancing the issues of chip manufacturing cost, reusability and flexible functions.

[0010] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which: Figure 1A is a schematic diagram of an exemplary core particle structure; Figure 1B is another exemplary schematic diagram of a core particle structure; Figure 2A A schematic diagram of the structure of a chip system provided in an embodiment of the present application; Figure 2B A schematic diagram of the structure of another chip system provided in an embodiment of the present application; Figure 3A A schematic diagram of the structure of a chip provided in an embodiment of the present application; Figure 3B A schematic diagram of the structure of another chip provided in an embodiment of the present application; Figure 3C A schematic diagram of the structure of another chip provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of another chip provided in an embodiment of the present application; Figure 5A schematic diagram of the structure of another chip system provided in an embodiment of the present application; Figure 6 A schematic diagram of the structure of another chip system provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of another chip system provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of another chip system provided in an embodiment of the present application; Fig. 9 A schematic diagram of the structure of another chip system provided in an embodiment of the present application; Fig.10 A schematic diagram of the structure of another chip system provided in an embodiment of the present application; Fig.11 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0012] It will be understood by those skilled in the art that, unless specifically stated, the "said" and "the" used herein may also include plural forms. It should be further understood that the wording "including" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may refer to the connection relationship between the element and the other element through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0013] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0014] A chiplet, or small chip, is a chip with independent functions that can be assembled into a complete system through advanced packaging technology.

[0015] Figure 1A Two core particles are shown connected directly to each other for data exchange. Figure 1B An IO chiplet is shown, which is connected to four or more chiplets using a specific SerDes or parallel connection protocol to form a larger computing system. These examples all describe 2D topologies using non-standard IO chiplets, making it difficult to scale the overall system bandwidth and computing power. None of them emphasize multi-die interconnect based on chiplet design. Most descriptions are generic and apply to specialized chiplet systems for specific companies or fields.

[0016] Therefore, an embodiment of the present application proposes a chip based on a standard switch chiplet, which can work together with various computing chiplets (for example, central processing units, artificial intelligence AI accelerators, and parallel video stream processors) to build a high-performance, flexible, and cost-effective chiplet scalable system.

[0017] In addition, the switch core can also be connected to a standard dynamic memory control core, so that the memory bandwidth can be expanded in a flexible and customization-friendly manner. The embodiment of the present application also proposes a 3D multi-core topology structure for multi-core and multi-chip connection.

[0018] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.

[0019] The present application provides the following solutions: 1. 3D multi-layered core-grain topology for large-scale computing systems in heterogeneous and homogeneous architectures.

[0020] 2. Various types of 2D core-grain topologies for heterogeneous and homogeneous architectures, which can be a subset of 3D core-grain topologies. The 2D core-grain topology is implemented based on standard switch cores and dynamic memory control cores.

[0021] 3. A standard switching core, used as the data routing point and central controller for the entire system.

[0022] 4. A standard, reusable dynamic memory control chiplet that works with the switch chiplet to expand bandwidth, where the dynamic memory control chiplet is used for memory access and data processing.

[0023] In some embodiments, 3D multi-layer core interconnect topology and various types of 2D core interconnect topology can be extended or modified according to different usage scenarios to meet various application requirements. The switching core and dynamic memory control core are designed to support the reusable and modular properties in the multi-core topology.

[0024] In the embodiments of the present application, all communication and control mechanisms are implemented based on common industry protocols, so that they can be applicable to different types of core particles.

[0025] The embodiments of the present application provide a low-latency and scalable bandwidth architecture by exchanging cores, which can be applied to various core dies in different usage scenarios such as automobiles, robots, and cloud servers.

[0026] Since existing chips are chip-level interconnected, they form a 2D topology on a two-dimensional PCB through external high-speed interfaces such as CXL and PCIe, as well as a logical 3D network, but cannot truly realize a physical 3D network. Therefore, when existing chips form 2D and 3D networks, their network architecture and interconnection rules are greatly differentiated, that is, the interfaces, architectures, protocols, etc. between 2D networks and 3D networks are diverse, resulting in poor reusability, and networking can only be done at the PCB board level. The solution of the embodiment of the present application is based on a reusable and flexible chiplet switch, as well as corresponding matching chiplets and a unified chiplet interface. It can build a 2D network inside the chip, or a 3D network through chip stacking packaging technology, that is, a 3D vertical network is built inside the chip, thereby truly realizing physical 3D network construction, and a low-cost logical 3D network can be built at the PCB level through external high-speed interfaces such as CXL and PCIe. Moreover, the flexible network architecture can support complex communication architectures with consistent and inconsistent data isolation.

[0027] After the existing chip is manufactured, the PCIe and CXL interfaces are fixed, and the maximum network carrying capacity is also fixed. If you want to expand the bandwidth and network scale, you need to redesign and produce the chip. The solution of the embodiment of the present application can interconnect the packaged chip layer (i.e., 2D network construction) through IO core particles or high-speed IO interfaces without redesigning the chip and manufacturing the chip, thereby flexibly expanding and shrinking the chip network scale. In addition, it is also compatible with existing chip-level interconnection solutions. Therefore, the solution of the embodiment of the present application can support both logical 3D networks and physical 3D networks.

[0028] The chip, chip system, processor and computing device proposed in the embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0029] In some embodiments, a chip is provided, such as Figure 3A As shown, the chip 10 includes: a switching core 11, at least one memory core 12, and at least one computing core 13, wherein the switching core is used as a data routing node and / or a central controller; at least one memory core is used to store data; and at least one computing core is used to calculate data. Optionally, the switching core includes a bus 110 and at least two core interfaces interconnected by the bus. The switching core is interconnected with at least one memory core 12 through at least one core interface 111, and is interconnected with at least one computing core 13 through a first core interface 112. Optionally, the first core interface includes a core interface of the at least two core interfaces except the core interface connected to at least one memory core.

[0030] In some embodiments, Figure 3A The chip 10 shown may also include at least one IO core. Among them, at least one IO core is used to transmit data. Optionally, the exchange core 11 is also interconnected with at least one IO core through a second core interface. The second core interface includes a core interface other than the core interface 111 connected to at least one memory core 12 and the core interface connected to at least one computing core 13 among the at least two core interfaces.

[0031] It should be noted that the second chip interface may be a part of the first chip interface.

[0032] It should be noted that the specific structure of the IO core particle can be found in the attached Figure 3C For the sake of brevity, it will not be described here.

[0033] It should be noted that the specific structure of the memory chip can be found in the attached Figure 3B or attached Figure 3C For the sake of brevity, it will not be described here.

[0034] In some embodiments, Figure 3A The switch core 11 shown may also include at least one IO interface. Wherein, at least one IO interface is used to transmit data. Optionally, as Figure 3B As shown, the IO interface may be a high-speed IO interface, but is not limited thereto.

[0035] Figure 3BA minimum system (corresponding to the chip 10 in the above text) consisting of a standard switching core (corresponding to the switching core 11 in the above text), a dynamic memory control core (corresponding to the memory core 12 in the above text) and other computing cores (corresponding to the computing core 13 in the above text) is shown. The standard core interface serves as the main data communication channel between cores, with multiple channels to meet bandwidth requirements. The protocol layer uses protocols such as AXI (Advanced eXtensible Interface, a bus protocol) or CHI (Coherent Hub Interface, an interconnection protocol) or ACE (Advanced Coherent Extensions, an interconnection protocol), and the link layer and PHY layer (Physical Layer, which is the physical layer in network communication and is responsible for data transmission) use UCIe / SerDes / HBI. The switching core can adopt an internal structure such as a mesh, ring or cross topology. The maximum core link between the computing chip and the switching core can be from 1 to 4.

[0036] Optionally, a large ARM computing system may include: switching core die and other computing dies (such as CPU die, GPU die, AI accelerator die or other accelerator die). As the central controller for system initialization, the switching core die can provide a communication strategy for processing memory data and control messages for core dies of different purposes. The switching core die can be developed independently of the computing core, reducing the design and architectural complexity of system control and memory access, enabling it to be expanded or reduced according to the computing density requirements in different scenarios.

[0037] Optionally, the switching chiplet may also include a high-bandwidth chiplet interface that can connect independent accelerators in accordance with the Advanced Microcontroller Bus Architecture protocol to support consistent and inconsistent data types in the physical layer, as well as general interconnect fast channels in the link and physical layers. The CPU chiplet Die can act as the main central computing unit in a large computing system, thereby achieving high performance in a multi-cluster topology. GPUs, AI accelerators, and other multi-purpose accelerator Dies can refer to the computing power in large computing systems and are combined in various ways according to different usage scenarios. The computing chiplet can access memory data, applications, and the main operating system running on the CPU chiplet through the hub system to manage and schedule jobs to each accelerator Die, such as: GPU Die with graphics rendering capabilities, AI accelerator Die with specific reasoning functions, etc.

[0038] Figure 3C Another minimum system consisting of a standard switching core, a dynamic memory control core, other computing cores, and an IO core is shown. Figure 3C The minimum system shown is compared to Figure 3B In the minimal system shown, the high-speed IO interface embedded in the standard switch core is replaced with a separate IO core.

[0039] Another standard reusable modular dynamic memory control core is designed to handle memory access and bandwidth allocation. Figure 4 As shown in FIG. 1 , if more dynamic memory control cores are connected to the switch core, the density and memory bandwidth of DRAM (dynamic random access memory) can be expanded. The maximum core link between the dynamic memory control core and the switch core can be set to 1 to 4.

[0040] Based on the same inventive concept, the embodiment of the present application further provides a chip system, which includes M such as Figure 3A or Figure 3B or Figure 3C or Figure 4 The chip shown in . Optionally, M chips are interconnected through the switch core particles included in each of the chips to form a two-dimensional topological structure. Wherein, M is 2 to the power of N, and N is a positive integer.

[0041] That is to say, the chip system with a two-dimensional topological structure in this embodiment may include 2, 4, 8, 16, etc. chips in the above embodiments.

[0042] In some embodiments, every two adjacent chips in the M chips are interconnected to form a two-dimensional topology structure through the third chip interface included in the respective switch chip 11. The third chip interface includes a chip interface that is not connected to at least one memory chip 12 and at least one computing chip 13 among at least two chip interfaces.

[0043] It should be noted that if the chip in this embodiment is Figure 3C In the chip shown, the third chip interface includes a chip interface among the at least two chip interfaces that is not connected to at least one memory chip 12, at least one computing chip 13, and at least one IO chip.

[0044] Optionally, the M chips include: a head chip and a tail chip, and each chip among the M chips, except the tail chip, corresponds to a next-level chip.

[0045] It should be noted that the M chips can be cascaded in a linear manner, but is not limited thereto. Optionally, when N is greater than or equal to 2, the M chips are divided into two groups, each group of chips is cascaded in a linear manner, and two chips at the same position in the two groups of chips are interconnected through the third chip interface included in their respective switching core particles 11.

[0046] For example, if N=2, then M=4. Assuming that the four chips are chips 1, 2, 3, and 4, chips 1, 2, 3, and 4 can be connected in sequence to form a two-dimensional topological structure. Chips 1 and 2 can also be connected to form chipset 1, chips 3 and 4 can be connected to form chipset 2, and then chipset 1 in chipset 1 is connected to chipset 3 in chipset 2, and chipset 2 in chipset 1 is connected to chipset 4 in chipset 2 to form a two-dimensional topological structure. It should be noted that the solution of the chip system with a two-dimensional topological structure in the embodiment of the present application is only described in the form of an example, and does not limit the embodiment of the present application.

[0047] In some embodiments, N can be 1, then M=2, and a chip system with a two-dimensional topological structure constructed by two chips can be as follows: Figure 6 or Figure 7 As shown, but not limited to this. Among them, Figure 6 Figure 1 shows a heterogeneous system based on standard switching chiplets and dynamic memory control chiplets. By extending the standard chiplet system, or what can be called the basic chiplet system (e.g. Figure 3B The system shown here allows for easy deployment of additional computing power. Figure 7 A homogeneous system based on standard switching core particles and dynamic memory control core particles is shown. By extending the standard core particle system (e.g. Figure 4 system shown), more memory bandwidth and density capabilities can be easily deployed.

[0048] It should be noted that Figure 6 and Figure 7 The basic core particle system in can also be as follows Figure 3C The chip shown.

[0049] In some embodiments, when N is greater than or equal to 2, each two adjacent chips in the M chips are interconnected through the third chip interface included in their respective switching chips to form a two-dimensional mesh topology. The third chip interface includes at least two chip interfaces that are not connected to at least one memory chip 12 and at least one computing chip 13. It should be noted that if the chip in this embodiment is as follows Figure 3C In the chip shown, the third chip interface includes a chip interface among the at least two chip interfaces that is not connected to at least one memory chip 12, at least one computing chip 13, and at least one IO chip.

[0050] In some embodiments, N can be 2, then M=4, and a chip system with a two-dimensional mesh topology structure constructed by four chips can be as follows: Figure 8 As shown, but not limited to. Figure 8 Another homogeneous or heterogeneous system based on standard switch core particles and dynamic memory control core particles is shown. According to the needs of users, the 2D core particle topology can be deployed in the computing system to provide more computing and memory bandwidth capabilities.

[0051] In some embodiments, when N is greater than or equal to 2, the chip system further includes a central computing core particle. Every two adjacent chips in every M / 2 chips are interconnected through the third core particle interface included in their respective switching core particles to form a chipset, and the two chipsets formed by the M chips are interconnected with the central computing core particle through the fourth core particle interface included in their respective switching core particles to form a two-dimensional mesh topology structure.

[0052] Optionally, the third chip interface includes a chip interface of at least two chip interfaces that is not connected to at least one memory chip 11 and at least one computing chip 12. The fourth chip interface includes a chip interface of at least two chip interfaces that is not connected to at least one memory chip 11 and at least one computing chip 12, and is different from the third chip interface.

[0053] Exemplarily, if N=3, then M=8. Assuming that the four chips are chips 1, 2, 3, 4, 5, 6, 7, and 8, the eight chips can be divided into two groups, and each group of chips is cascaded in a linear manner, that is, chips 1, 2, 3, and 4 can be connected in sequence to form chipset 1, and chips 5, 6, 7, and 8 can be connected in sequence to form chipset 2. Then, the four chips in chipset 1 and the four chips in chipset 2 are respectively connected to the central computing core particles to form a two-dimensional mesh topology. It should be noted that the scheme of the chip system with a two-dimensional mesh topology structure in the embodiment of the present application is only described in the form of an example, and does not limit the embodiment of the present application.

[0054] In some embodiments, N can be 2, then M=4, and a chip system with a two-dimensional mesh topology structure constructed by four chips and one central computing core particle can be as follows: Fig. 9 As shown, but not limited to. Fig. 9 A 2D core particle system based on a standard switching core particle and a dynamic memory control core particle is shown. The system can be homogeneous or heterogeneous. For example, a computing core particle is placed in the center of the system (which can be called a central computing core particle) and is set to be used by the CPU or other accelerators for shared use. Multiple direct memory access (DMA) devices are placed in the center of the chip for memory data transfer between quadrants.

[0055] In some embodiments, the M chips are 2 chips, and the chip system further includes: a central computing core particle, and the 2 chips are interconnected with the central computing core particle through the fourth core particle interface included in the respective exchange core particles to form a two-dimensional topological structure. The fourth core particle interface includes a core particle interface that is not connected to at least one memory core particle 12 and at least one computing core particle 13 among the at least two core particle interfaces.

[0056] It should be noted that if the chip in this embodiment is Figure 3C In the chip shown, the fourth chip interface includes a chip interface among the at least two chip interfaces that is not connected to at least one memory chip 12, at least one computing chip 13, and at least one IO chip.

[0057] In some embodiments, if N=1, then M=2, and in a chip system with a two-dimensional topology structure constructed by two chips and one central computing core particle, the two chips are interconnected with the central computing core particle respectively.

[0058] In some embodiments, when N is greater than or equal to 2, the chip system may further include M / 2 central computing core particles cascaded in a linear manner.

[0059] In this embodiment, every two adjacent chips in every M / 2 chips are interconnected through the third chip interface included in their respective switching cores to form a chipset; every two corresponding chips in the two chipsets formed by the M chips are interconnected with one of the M / 2 central computing cores through the fourth chip interface included in their respective switching cores to form a two-dimensional mesh topology structure.

[0060] Among them, the M / 2 central computing core particles may include: a head central computing core particle and a tail central computing core particle. Except for the tail central computing core particle, each central computing core particle in the M / 2 central computing core particles corresponds to a next-level central computing core particle. It should be understood that in this embodiment, two adjacent central computing core particles can be interconnected through their respective core particle interfaces.

[0061] Optionally, the third chip interface includes a chip interface of at least two chip interfaces that is not connected to at least one memory chip 11 and at least one computing chip 12. The fourth chip interface includes a chip interface of at least two chip interfaces that is not connected to at least one memory chip 11 and at least one computing chip 12, and is different from the third chip interface.

[0062] It should be noted that if the chip in this embodiment is Figure 3C For the chip shown, the third chip interface and the fourth chip interface are the chip interfaces among the at least two chip interfaces that are not connected to at least one memory chip 12, at least one computing chip 13, and at least one IO chip.

[0063] Exemplarily, if N=2, then M=4. Assuming that the four chips are chips 1, 2, 3, and 4, and the two central computing core particles are central computing core particles a and b, respectively, and central computing core particles a and central computing core particles b are interconnected through their respective core particle interfaces, then chips 1 and 2 can be connected to form chipset 1, chips 3 and 4 can be connected to form chipset 2, and then chipset 1 in chipset 1 and chipset 3 in chipset 2 are connected to central computing core particles a, and chipset 2 in chipset 1 and chipset 4 in chipset 2 are connected to central computing core particles b to form a two-dimensional mesh topology. It should be noted that the scheme of the chip system with a two-dimensional mesh topology structure in the embodiment of the present application is only described in the form of an example, and does not constitute a limitation on the embodiment of the present application.

[0064] In some embodiments, N can be 2, then M=4, and a chip system with a two-dimensional mesh topology structure constructed by four chips and two central computing core particles can be as follows: Fig.10 As shown, but not limited to. Fig.10 A hybrid 2D core-grain system based on standard switching core-grains and dynamic memory control core-grains is shown. The system can be homogeneous or heterogeneous. For example, two CPU core-grains are centrally allocated and have dedicated data exchange channels for cache consistency. AI-using acceleration chips are placed above and below, and consistency is not required except for the CPU chip. Consistent and non-consistent data services are clearly divided, which can improve robustness and the data transmission performance of the system.

[0065] Based on the same inventive concept, an embodiment of the present application further provides a chip system, including at least one chip unit, each chip unit including at least two chip systems of the two-dimensional topological structure described in any of the above embodiments.

[0066] Optionally, at least two chip systems with two-dimensional topological structures form a three-dimensional mesh topological structure by interconnecting chips in each chip system with two-dimensional topological structure.

[0067] In some embodiments, the chip system with a three-dimensional mesh topology structure can be as shown in the attached Figure 2A or attached Figure 2B shown, but not limited to.

[0068] That is to say, the chip system with a three-dimensional mesh topology structure in this embodiment may include 4, 8, 16, etc. chips in the above embodiments.

[0069] Figure 2AA high-performance computing system with a 3D core particle topology is shown. Every four switch core particles on the same plane form a dedicated chip layer. For example, switch core particles 00 to 03 form the upper chip layer 0, and switch core particles 10 to 13 form the lower chip layer 1. Each layer can contain multiple core particles and can act as an independent chip. In the 3D network architecture, the layers are connected through industry-standard high-speed peripheral devices (such as PCIe (Peripheral ComponentInterconnect express, a high-speed serial computer expansion bus standard) or CXL (Compute ExpressLink, a new high-speed interconnect technology) for logical 3D network construction, or through silicon vias (Through Silicon Via, TSV) through switch core particles for vertical physical 3D network connection.

[0070] Figure 2B A computing system with a larger 3D chiplet topology is shown. Different layers can be independent chips consisting of switch chiplets 00 to 07 and switch chiplets 10 to 17, respectively. Different layers can be logically connected to the 3D network through chiplet links such as UCIe (Universal Chiplet Interconnect Express), or HBI (High Bandwidth Interconnect), or SerDes (short for SERializer / DESerializer). During the stacking process of the 3D structure, the upper and lower layers communicate physically in the 3D network through high-speed input / output interfaces (HSIO) or through silicon vias (TSV).

[0071] In some embodiments, each two adjacent chip systems with two-dimensional topology structures in at least two chip systems with two-dimensional topology structures are interconnected through at least one IO interface included in the switch core particles of the respective chips to form a three-dimensional mesh topology structure.

[0072] In some embodiments, each two adjacent chip systems of two-dimensional topological structures in at least two chip systems of two-dimensional topological structures are interconnected through at least one IO chiplet included in each chip to form a three-dimensional mesh topological structure. Optionally, the chip system of the three-dimensional mesh topological structure in this embodiment can be as shown in the attached Figure 5 shown, but not limited to.

[0073] Figure 5A more detailed 3D coreparticle topology is shown. The upper and lower layers are composed of 8 switching coreparticles each, connected by coreparticle links. Each layer contains 4 dynamic memory control coreparticles. The upper and lower layers communicate through high-speed IO interfaces. Depending on the actual requirements of bandwidth and scenarios, the number of data channels between layers, that is, the links for communication between chips, can vary from 1*16 to 4*16.

[0074] Based on the same inventive concept, an embodiment of the present application provides a processor, which may include the chip in the above embodiment, or the chip system with a two-dimensional topological structure in the above embodiment, or the chip system with a three-dimensional topological structure in the above embodiment.

[0075] Based on the same inventive concept, an embodiment of the present application provides a computing device, which may include the processor in the above embodiment.

[0076] In some embodiments, Fig.11 As shown, the computing device may further include a memory 2003 communicatively connected to the processor 2001 , such as via a bus 2002 .

[0077] Processor 2001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof, including the chip or chip system described in any of the above embodiments. It may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 2001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0078] The bus 2002 may include a path to transmit information between the above components. The bus 2002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 2002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 9 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0079] The memory 2003 may be a ROM (Read-Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (random access memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read-Only Memory) or other optical disk storage, optical disk storage (including compressed optical disk, laser disk, optical disk, digital versatile disk, Blu-ray disk, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.

[0080] Optionally, the computing device 2000 may further include a communication unit 2004. The communication unit 2004 may be used to receive and send signals. The communication unit 2004 may allow the computing device 2000 to communicate with other devices wirelessly or by wire to exchange data. It should be noted that in actual applications, the communication unit 2004 is not limited to one.

[0081] Optionally, the computing device 2000 may further include an input unit 2005. The input unit 2005 may be used to receive input digital, character, image and / or sound information, or generate key signal input related to user settings and function control of the computing device 2000. The input unit 2005 may include, but is not limited to, one or more of a touch screen, a physical keyboard, a function key (such as a volume control key, a switch key, etc.), a trackball, a mouse, a joystick, a camera, a microphone, etc.

[0082] Optionally, the computing device 2000 may further include an output unit 2006. The output unit 2006 may be used to output or display information processed by the processor 2001. The output unit 2006 may include but is not limited to one or more of a display device, a speaker, a vibration device, and the like.

[0083] Although Fig.11 The computing device 2000 is shown with various devices, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or have instead.

[0084] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0085] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0086] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0087] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0088] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A chip, characterized in that: include: A switch core that acts as a data routing node and / or central controller; at least one memory chip for storing data; At least one computing core particle, used for computing data; Wherein, the switching core comprises a bus and at least two core interfaces interconnected by the bus; The switch core is interconnected with the at least one memory core through at least one core interface, and is interconnected with the at least one computing core through a first core interface; The first chip interface includes a chip interface among the at least two chip interfaces except the chip interface connected to the at least one memory chip.

2. The chip according to claim 1, characterized in that: The chip further includes: at least one IO chiplet for transmitting data, wherein: The switch core is also interconnected with the at least one IO core through a second core interface; The second core particle interface includes core particle interfaces other than the core particle interface connected to the at least one memory core particle and the core particle interface connected to the at least one computing core particle among the at least two core particle interfaces.

3. The chip according to claim 1, characterized in that: The switch core also includes at least one IO interface for transmitting data.

4. A chip system, characterized in that: include: M chips as claimed in any one of claims 1 to 3; Among them, M chips are interconnected through the switching core particles included in each chip to form a two-dimensional topological structure, M is 2 to the power of N, and N is a positive integer.

5. The chip system according to claim 4, characterized in that: Every two adjacent chips in the M chips are interconnected through the third core particle interface included in the respective switching core particles to form a two-dimensional topological structure; Wherein, the third chiplet interface includes a chiplet interface among the at least two chiplet interfaces that is not connected to the at least one memory chiplet and the at least one computing chiplet; The M chips include: a head chip and a tail chip. Except for the tail chip, each chip among the M chips corresponds to a next-level chip.

6. The chip system according to claim 4, characterized in that: When N is greater than or equal to 2, every two adjacent chips in the M chips are interconnected through the third chip interface included in their respective switching core particles to form a two-dimensional mesh topology structure; The third chip interface includes a chip interface of the at least two chip interfaces that is not connected to the at least one memory chip and the at least one computing chip.

7. The chip system according to claim 4, characterized in that: When N is greater than or equal to 2, the chip system further includes: a central computing core particle; Every two adjacent chips in every M / 2 chips are interconnected through the third chip interface included in the respective switch core particles to form a chipset; The two chip groups formed by the M chips are interconnected with the central computing core grain through the fourth core grain interface included in the respective switching core grains to form a two-dimensional mesh topology structure; Wherein, the third chiplet interface includes a chiplet interface among the at least two chiplet interfaces that is not connected to the at least one memory chiplet and the at least one computing chiplet; The fourth chip interface includes a chip interface of the at least two chip interfaces that is not connected to the at least one memory chip and the at least one computing chip, and is different from the third chip interface.

8. The chip system according to claim 4, characterized in that: The M chips are 2 chips, and the chip system further includes: a central computing core particle; The two chips are interconnected with the central computing core grain through the fourth core grain interface included in the respective exchange core grains to form a two-dimensional topological structure; The fourth chip interface includes a chip interface of the at least two chip interfaces that is not connected to the at least one memory chip and the at least one computing chip.

9. The chip system according to claim 4, characterized in that: When N is greater than or equal to 2, the chip system further comprises: M / 2 central computing core particles cascaded in a linear manner; Every two adjacent chips in every M / 2 chips are interconnected through the third chip interface included in the respective switch core particles to form a chipset; Each two chips corresponding to the two chips in the two chipsets formed by the M chips are interconnected with one of the M / 2 central computing core particles through the fourth core particle interface included in the respective switching core particles to form a two-dimensional mesh topology structure; The M / 2 center calculation core particles include: a head center calculation core particle and a tail center calculation core particle; among the M / 2 center calculation core particles, except for the tail center calculation core particle, each center calculation core particle corresponds to a next-level center calculation core particle; The third chiplet interface includes a chiplet interface of the at least two chiplet interfaces that is not connected to the at least one memory chiplet and the at least one computing chiplet; The fourth chip interface includes a chip interface of the at least two chip interfaces that is not connected to the at least one memory chip and the at least one computing chip, and is different from the third chip interface.

10. A chip system, characterized in that: include: At least one chip unit, each chip unit comprising at least two chip systems of a two-dimensional topological structure according to any one of claims 4 to 9; Among them, at least two chip systems of the two-dimensional topological structure form a three-dimensional mesh topological structure by interconnecting the chips in each chip system of the two-dimensional topological structure.

11. The chip system according to claim 10, characterized in that: Each two adjacent chip systems with two-dimensional topology structures in at least two of the chip systems with two-dimensional topology structures are interconnected through at least one IO interface included in the switching core particles of the respective chips to form a three-dimensional mesh topology structure.

12. The chip system according to claim 10, characterized in that: Each two adjacent chip systems with two-dimensional topology structures in at least two chip systems with two-dimensional topology structures are interconnected through at least one IO chip included in each chip to form a three-dimensional mesh topology structure.

13. A processor, characterized in that: include: The chip according to any one of claims 1 to 3; or, A chip system with a two-dimensional topological structure as claimed in any one of claims 4 to 9; or A chip system with a three-dimensional mesh topology structure as described in any one of claims 10-12.

14. A computing device, characterized in that include: The processor of claim 13.

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