Equal weight arbitration circuit

Abstract

The invention provides an equal-weight arbitration circuit which comprises a priority updating module and a request arbitration module, the priority updating module outputs ID signals corresponding to all paths of requests, after the mth path of request is successfully arbitrated, the priority of the mth path of request becomes the lowest, and for the rest n-1 paths of requests, if the priority is higher than the priority of the mth path of request, the mth path of request becomes the highest priority; if the priority is lower than the priority of the mth path of request, adding 1 to the priority of the mth path of request; the request arbitration module receives an arbitration request input signal and ID signals corresponding to all paths of requests output by the priority updating module, obtains a rearrangement request signal according to the arbitration request input signal and the ID signals corresponding to all paths of requests, and obtains a position signal of the controllable shift register corresponding to the highest priority request by using the rearrangement request signal; and an arbitration result signal and a shift control signal are obtained according to the position signal. The problem that an existing arbitration circuit is insufficient in expansibility is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an equal-weight arbitration circuit. Background Art

[0002] In logic circuit design, an arbitration circuit can receive multiple request signals and determine the priority of these request signals according to the sequence of the multiple request signals.

[0003] The commonly used arbitration circuit is the Round Robin arbitration circuit. However, although the Round Robin arbitration circuit has advantages in scalability and the characteristics that the circuit delay increases with the number of paths, it is insufficient in the realization of equal weight. The circuit structure based on historical value arbitration has advantages in equal weight, but it is insufficient in scalability and the characteristics that the circuit delay increases with the number of paths. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an equal-weight arbitration circuit to solve the problem of insufficient scalability of the existing arbitration circuit.

[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides an equal-weight arbitration circuit, the circuit comprising: a priority update module and a request arbitration module,

[0006] The priority updating module outputs an ID signal corresponding to each request, and includes n controllable shift registers, each of which stores an ID signal corresponding to one request, and the ID signal corresponding to each request is encoded using one-hot. The priorities of the ID signals stored in the n controllable shift registers decrease in sequence, and the priority of the ID signal stored in the first controllable shift register is the highest, and the priority of the ID signal stored in the nth controllable shift register is the lowest. After the mth request is successfully arbitrated, the priority of the mth request becomes the lowest. For the remaining n-1 requests, if their priority is higher than the priority of the mth request, their priority remains unchanged, and if their priority is lower than the priority of the mth request, their priority is increased by 1. When receiving a shift control signal, each controllable shift register shifts the request whose priority needs to be increased by 1, and the nth controllable shift register with the lowest priority receives the arbitration result signal;

[0007] The request arbitration module receives an arbitration request input signal and an ID signal corresponding to each request output by the priority update module, and obtains a rearrangement request signal after rearrangement according to the priority according to the arbitration request input signal and the ID signal corresponding to each request output by the priority update module, and obtains a position signal of a controllable shift register corresponding to the highest priority request using the rearrangement request signal, and then obtains the arbitration result signal and the shift control signal according to the position signal of the controllable shift register corresponding to the highest priority request;

[0008] The shift control signal and the arbitration request input signal are both n-bit binary codes, and n is a positive integer greater than or equal to 2, and m is a positive integer greater than or equal to 2 and less than or equal to n.

[0009] Optionally, the n controllable shift registers receive the shift control signal to perform shifting.

[0010] Optionally, when receiving the shift control signal, the method for each of the controllable shift registers to shift the request whose priority needs to be increased by 1 includes:

[0011] The n-bit binary code of the shift control signal corresponds one-to-one to the n controllable shift registers, and the shift control signal corresponding to the controllable shift register that needs to be shifted is 1, and the shift control signal corresponding to the controllable shift register that does not need to be shifted is 0, and each time the shift is made in the direction of higher priority, the nth controllable shift register with the lowest priority receives the arbitration result signal.

[0012] Optionally, the arbitration result signal is an n-bit one-hot code.

[0013] Optionally, the method of obtaining the reordering request signal after reordering according to the priority according to the arbitration request input signal and the ID signal corresponding to each request includes:

[0014] Performing AND operations on the arbitration request input signal and the ID signals corresponding to the requests stored in the n controllable shift registers to obtain n n-bit binary codes;

[0015] An OR operation is performed on the n bits of each binary code to obtain an n-bit rearrangement request signal.

[0016] Optionally, the method of obtaining the position signal of the controllable shift register corresponding to the highest priority request by using the rearrangement request signal includes:

[0017] An AND operation is performed on the n-bit rearrangement request signal and its own complement to obtain the position signal of the controllable shift register corresponding to the n-bit highest priority request.

[0018] Optionally, the method for obtaining the arbitration result signal according to the position signal of the controllable shift register corresponding to the highest priority request includes:

[0019] Expand each bit of the position signal of the controllable shift register corresponding to the n-bit highest priority request into the same n-bit signal, and perform AND operation with the ID signal corresponding to each request to obtain n n-bit binary codes;

[0020] Perform an OR operation on the n bits of each binary code to obtain the arbitration result signal.

[0021] Optionally, the method for obtaining the shift control signal according to the position signal of the controllable shift register corresponding to the highest priority request includes:

[0022] Performing an OR operation on the position signal of the controllable shift register corresponding to the highest priority request and the result of itself minus 1;

[0023] The result of the OR operation is inverted to obtain the n-bit shift control signal.

[0024] Optionally, the priority update module receives a driving clock signal, and the driving clock signal also drives the generation of the arbitration request input signal.

[0025] As described above, the equal-weight arbitration circuit of the present invention has a more balanced weight than the weight of the conventional Round Robin arbitration circuit, and is easier to expand into multiple paths than the conventional historical value-based arbitration circuit method, and the circuit delay will not increase significantly with the increase in the number of paths. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is an equal-weight arbitration circuit diagram of the present invention.

[0027] Figure 2 Shown is a circuit diagram of a priority update module of the present invention.

[0028] Figure 3 Shown is a circuit diagram of a request arbitration module of the present invention. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] See also Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0031] like Figure 1 As shown, this embodiment provides an equal-weight arbitration circuit, the circuit comprising: a priority update module and a request arbitration module,

[0032] The priority update module outputs an ID signal ID[n:1] corresponding to each request, and includes n controllable shift registers, each of which stores an ID signal ID[n:1] corresponding to one request, and the ID signal ID[n:1] corresponding to each request is encoded using one-hot encoding. The priorities of the ID signals ID[n:1] stored in the n controllable shift registers decrease in sequence, and the ID signal ID[n:1] stored in the first controllable shift register has the highest priority, and the ID signal ID[n:1] stored in the nth controllable shift register has the highest priority. The priority of the D signal ID[n:1] is the lowest. After the m-th request is successfully arbitrated, the priority of the m-th request becomes the lowest. For the remaining n-1 requests, if their priority is higher than the priority of the m-th request, their priority remains unchanged. If their priority is lower than the priority of the m-th request, their priority is increased by 1. When receiving the shift control signal EN[n:1], each of the controllable shift registers shifts the request whose priority needs to be increased by 1. The n-th controllable shift register with the lowest priority receives the arbitration result signal GRANT[n:1];

[0033] The request arbitration module receives the arbitration request input signal REQ[n:1] and the ID signal ID[n:1] corresponding to each request output by the priority update module, and obtains a reordering request signal req_valid[n:1] after reordering according to the priority according to the arbitration request input signal REQ[n:1] and the ID signal ID[n:1] corresponding to each request output by the priority update module, and obtains the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request by using the reordering request signal req_valid[n:1], and then obtains the arbitration result signal GRANT[n:1] and the shift control signal EN[n:1] according to the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request;

[0034] The shift control signal EN[n:1] and the arbitration request input signal REQ[n:1] are both n-bit binary codes, where n is a positive integer greater than or equal to 2, and m is a positive integer greater than or equal to 2 and less than or equal to n.

[0035] In this embodiment, the leftmost controllable shift register (that is, the nth controllable shift register) is used to store the request with the lowest priority, and the rightmost controllable shift register (that is, the first controllable shift register) is used to store the request with the highest priority.

[0036] Specifically, the priority updating module receives a driving clock signal CLK, and the driving clock signal CLK further drives the generation of the arbitration request input signal REQ[n:1].

[0037] Specifically, the n controllable shift registers receive the shift control signal EN[n:1] to perform shifting.

[0038] Specifically, when each of the controllable shift registers receives the shift control signal EN[n:1], the method for shifting the request that needs to be increased in priority by 1 includes: the n-bit binary code of the shift control signal corresponds one-to-one to the n controllable shift registers, and the shift control signal corresponding to the controllable shift register that needs to be shifted is 1, and the shift control signal corresponding to the controllable shift register that does not need to be shifted is 0, and each time the controllable shift register shifts in the direction of higher priority, the nth controllable shift register with the lowest priority receives the arbitration result signal.

[0039] In this embodiment, each shift toward the highest priority direction is that the ID signal IDm[n:1] stored in the mth controllable shift register is shifted to the m-1th controllable shift register.

[0040] Specifically, the arbitration result signal GRANT[n:1] is an n-bit one-hot code.

[0041] Specifically, the method for obtaining the reordering request signal req_valid[n:1] after reordering according to the priority based on the arbitration request input signal REQ[n:1] and the ID signal ID[n:1] corresponding to each request includes: performing an AND operation on the arbitration request input signal REQ[n:1] and the ID signal ID[n:1] corresponding to each request stored in n controllable shift registers to obtain n n-bit binary codes; and performing an OR operation on the n bits of each binary code to obtain an n-bit reordering request signal req_valid[n:1].

[0042] Specifically, the method of using the rearrangement request signal req_valid[n:1] to obtain the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request includes: performing an AND operation on the n-bit rearrangement request signal req_valid[n:1] and its own complement to obtain the position signal valid[n:1] of the controllable shift register corresponding to the n-bit highest priority request.

[0043] Specifically, it is characterized in that the method for obtaining the arbitration result signal GRANT[n:1] according to the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request includes: expanding each bit of the position signal valid[n:1] of the controllable shift register corresponding to the n-bit highest priority request into the same n-bit signal, and performing AND operations with the ID signal ID[n:1] corresponding to each request to obtain n n-bit binary codes; performing OR operations on the n bits of each binary code to obtain the arbitration result signal GRANT[n:1].

[0044] Specifically, the method for obtaining the shift control signal EN[n:1] according to the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request includes: performing an OR operation on the position signal valid[n:1] of the controllable shift register corresponding to the highest priority request and the result of subtracting 1 from itself; and inverting the result of the OR operation to obtain the n-bit shift control signal.

[0045] In this embodiment, it is assumed that there are 3 requests in total, that is, there are 3 controllable shift registers, REG_ID3[3:1], REG_ID2[3:1] and REG_ID1[3:1] represent the values ​​stored in each of the controllable shift registers, respectively representing the third request, the second request and the first request, the first request has the highest priority and the third request has the lowest priority, and REG_ID1[3:1]=3'b001, REG_ID2[3:1]=3'b010, REG_ID3[3:1]=3'b100. When the second and third requests arrive, the arbitration request input signal REQ[n]=3'b110 input by the request arbitration module, the authorization signal GRANT[n]=3'b010 output, the shift control signal EN[n]=3'b100 is generated, and output to the priority update module. Then, under the drive of the driving clock signal CLK, in the priority update module, REG_ID3[3:1] is updated to 3'b010, REG_ID2[3:1] is updated to 3'b100, and REG_ID1[3:1] maintains the original value 3'b001.

[0046] The shift request is a request output after the priority update module performs the shift, which are respectively represented as ID3[3:1], ID2[3:1] and ID1[3:1]. For the three signals, ID3[3:1] corresponds to the updated REG_ID3[3:1], and the value is 3'b010, ID2[3:1] is the updated REG_ID2[3:1], and the value is 3'b100, and ID1[3:1] corresponds to the original REG_ID1[3:1], and the value is 3'b00. 1. When the 1st and 3rd requests occur, the arbitration request input signal REQ[3:1] is 3'b101, ID3[3:1], ID2[3:1] and ID1[3:1] are respectively ANDed with REQ[3:1] to obtain three 3-bit binary codes, and each bit of each 3-bit binary code is ORed to obtain the reorder request signal req_valid[3:1], which has a value of 3'b011, indicating that the requests corresponding to ID2[3:1] and ID1[3:1] occur. The reorder request signal req_valid[3:1] is ANDed with its own complement to obtain the confirmation signal valid[3:1], which has a value of 3'b001, indicating that the request corresponding to ID1[3:1] is successfully arbitrated. The confirmation signal valid[3:1] performs an AND operation with ID3[3:1], ID2[3:1] and ID1[3:1] respectively, and then performs an OR operation on the AND operation result to obtain the one-hot code corresponding to the request of ID1[3:1], that is, the grant signal GRANT[3:1], whose value is 3'b001; at the same time, the confirmation signal valid[3:1] performs an OR operation with the result of itself minus one, and then the result of the OR operation is inverted to obtain the shift control signal EN[3:1], whose value is 3'b110, indicating that REG_ID 3[3:1] and REG_ID2[3:1] in the priority update circuit are shifted (moved to the right and stored) under the drive of the clock drive signal CLK, and at the same time, the grant signal GRANT[3:1] is stored in REG_ID3[3:1].

[0047] Specifically, the n controllable shift registers are arranged from left to right and respectively represent the number of requested ways.

[0048] Specifically, the priority of each request is stored in each of the controllable shift registers in an n-bit one-hot encoding.

[0049] In summary, the weight of the equal-weight arbitration circuit of the present invention is more balanced than that of the commonly used Round Robin arbitration circuit, and is easier to expand into multiple channels than the commonly used arbitration circuit based on historical values, and the circuit delay will not increase significantly with the increase in the number of channels. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0050] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An equal-weight arbitration circuit, characterized in that: The circuit comprises: a priority updating module and a request arbitration module, wherein the priority updating module outputs an ID signal corresponding to each request, and comprises n controllable shift registers, each of which stores an ID signal corresponding to one request, and the ID signal corresponding to each request is encoded using one-hot, and the priorities of the ID signals stored in the n controllable shift registers decrease in sequence, the ID signal stored in the first controllable shift register has the highest priority, and the ID signal stored in the nth controllable shift register has the lowest priority, and after the mth request is successfully arbitrated, the priority of the mth request becomes the lowest, and for the remaining n-1 requests, if their priority is higher than the priority of the mth request, their priority remains unchanged, and if their priority is lower than the priority of the mth request, their priority is increased by 1, and when receiving a shift control signal, each of the controllable shift registers shifts the request whose priority needs to be increased by 1, and the nth controllable shift register with the lowest priority receives the arbitration result signal; The request arbitration module receives an arbitration request input signal and an ID signal corresponding to each request output by the priority update module, and obtains a rearrangement request signal after rearrangement according to the priority according to the arbitration request input signal and the ID signal corresponding to each request output by the priority update module, and obtains a position signal of a controllable shift register corresponding to the highest priority request using the rearrangement request signal, and then obtains the arbitration result signal and the shift control signal according to the position signal of the controllable shift register corresponding to the highest priority request; The shift control signal and the arbitration request input signal are both n-bit binary codes, and n is a positive integer greater than or equal to 2, and m is a positive integer greater than or equal to 2 and less than or equal to n.

2. The equal-weight arbitration circuit according to claim 1, characterized in that: The n controllable shift registers receive the shift control signal to perform shifting.

3. The equal-weight arbitration circuit according to claim 2, characterized in that: The method in which each of the controllable shift registers shifts the request whose priority needs to be increased by 1 when receiving the shift control signal includes: The n-bit binary code of the shift control signal corresponds one-to-one to the n controllable shift registers, and the shift control signal corresponding to the controllable shift register that needs to be shifted is 1, and the shift control signal corresponding to the controllable shift register that does not need to be shifted is 0, and each time the shift is made in the direction of higher priority, the nth controllable shift register with the lowest priority receives the arbitration result signal.

4. The equal-weight arbitration circuit according to claim 1, characterized in that: The arbitration result signal is an n-bit one-hot code.

5. The equal-weight arbitration circuit according to claim 1, characterized in that: The method for obtaining the reordering request signal after reordering according to the priority according to the arbitration request input signal and the ID signal corresponding to each request includes: Performing AND operations on the arbitration request input signal and the ID signals corresponding to the requests stored in the n controllable shift registers to obtain n n-bit binary codes; An OR operation is performed on the n bits of each binary code to obtain an n-bit rearrangement request signal.

6. The equal-weight arbitration circuit according to claim 5, characterized in that: The method of obtaining the position signal of the controllable shift register corresponding to the highest priority request by using the rearrangement request signal comprises: An AND operation is performed on the n-bit rearrangement request signal and its own complement to obtain the position signal of the controllable shift register corresponding to the n-bit highest priority request.

7. The equal-weight arbitration circuit according to claim 6, characterized in that: The method for obtaining the arbitration result signal according to the position signal of the controllable shift register corresponding to the highest priority request includes: Expand each bit of the position signal of the controllable shift register corresponding to the n-bit highest priority request into the same n-bit signal, and perform AND operation with the ID signal corresponding to each request to obtain n n-bit binary codes; Perform an OR operation on the n bits of each binary code to obtain the arbitration result signal.

8. The equal-weight arbitration circuit according to claim 7, characterized in that: The method for obtaining the shift control signal according to the position signal of the controllable shift register corresponding to the highest priority request comprises: Performing an OR operation on the position signal of the controllable shift register corresponding to the highest priority request and the result of itself minus 1; The result of the OR operation is inverted to obtain the n-bit shift control signal.

9. The equal-weight arbitration circuit according to claim 1, characterized in that: The priority updating module receives a driving clock signal, and the driving clock signal further drives the arbitration request input signal.

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