CPU and CPU design method, device, equipment, medium and product

Abstract

The present application relates to a CPU and a CPU design method, device, equipment, medium and product, and in particular to the field of CPU technology. It includes: a plug-in pool and a processor core; wherein the processor core is used to control multiple sub-modules to execute instructions, process data and interrupts; the plug-in pool is used to manage the creation, execution order and resource allocation of multiple extended function plug-ins; multiple extended function plug-ins transmit data with the processor core through a plug-in interface; the plug-in interface includes a signal channel for inputting sub-module status information, and a data channel for outputting control instructions. The present application uses a plug-in hardware design method to enable different functions to be flexibly combined or replaced, thereby improving the flexibility, scalability and collaboration of the CPU design; when adding, removing or replacing extended function plug-ins, there is no need to modify the core source code, thereby reducing the complexity of the CPU design and improving reusability.

Description

Technical Field

[0001] The present application relates to the field of terminal technology, and in particular to a CPU and a CPU design method, device, equipment, medium and product. Background Art

[0002] With the continuous development of computer architecture, the design of CPU has evolved from the earliest simple architecture to today's highly complex and customized systems. Current CPU design methods, such as the bottom-up design method of hardware description language (HDL), use hardware description language (such as VHDL or Verilog) to start designing from the most basic modules such as logic gates and registers, and then gradually build more complex modules, such as arithmetic logic units such as adders and multipliers. These basic modules are combined to form the main components of the CPU, such as instruction decoders, register stacks, etc. Finally, these components are connected through data links and control signals to form a complete CPU.

[0003] However, when a CPU designed by this method is subsequently expanded or replaced with a module, it is usually necessary to modify the core code and perform a lot of design and verification work. In addition, the independence of each module is weak and the modules are tightly coupled, which means that any modification of any module will affect the stability and functional implementation of the entire design. In addition, the modules are not easily reusable in different projects. Therefore, the existing CPU design methods have problems with insufficient flexibility, scalability, reusability, and collaboration. Summary of the invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides a CPU and CPU design method, device, equipment, medium and product, which can enable different functions to be flexibly combined or replaced through a plug-in hardware design method, thereby improving the flexibility, scalability and collaboration of CPU design; when adding, removing or replacing extended function plug-ins, there is no need to modify the core source code, thereby reducing the complexity of CPU design and improving reusability.

[0005] In order to achieve the above purpose, the technical solutions provided by the embodiments of the present application are as follows:

[0006] In a first aspect, the present application provides a CPU, the CPU comprising: a plug-in pool and a processor core; wherein the processor core is used to control multiple sub-modules to execute instructions, process data and interrupts;

[0007] The plug-in pool is used to manage the creation, execution order and resource allocation of multiple extended function plug-ins; multiple extended function plug-ins transmit data with the processor core through the plug-in interface; the plug-in interface includes a signal channel for inputting sub-module status information and a data channel for outputting control instructions.

[0008] As an optional implementation in the embodiment of the present application, the plug-in pool is specifically used to: when the CPU starts, load the corresponding pre-selected extended function plug-in according to predefined parameters; wherein the first extended function plug-in obtains parameter information of the second extended function plug-in based on the shared database to collaboratively generate control instructions; the first extended function plug-in and the second extended function plug-in are any two of the extended function plug-ins.

[0009] As an optional implementation in the embodiment of the present application, the plug-in pool is specifically used to: when the second extended function plug-in sets the target parameter information through the shared database, control the first extended function plug-in to enter a blocking state and wait for the target parameter information to be set; after the target parameter information is set, control the first extended function plug-in to generate a control instruction according to the target parameter information.

[0010] As an optional implementation in the embodiment of the present application, the processor core is specifically used to: receive the control instruction output by the pre-selected extended function plug-in through the data channel; decode the control instruction to determine the instruction type of the control instruction; determine the sub-module corresponding to the instruction type to execute the control instruction to obtain sub-module status information; transmit the sub-module status information to the pre-selected extended function plug-in through the signal channel.

[0011] As an optional implementation in the embodiment of the present application, the plug-in pool is specifically used to control multiple functional plug-ins to dynamically release resources when the CPU enters a low power consumption mode.

[0012] In a second aspect, the present application provides a CPU design method, the method comprising: generating a hardware description of the CPU as described in the first aspect or any optional implementation manner thereof by using a high-level hardware description language SpinalHDL.

[0013] In a third aspect, the present application provides a CPU design device, comprising: a hardware generation module for generating a hardware description of the CPU as described in the first aspect or any optional embodiment thereof through a high-level hardware description language SpinalHDL.

[0014] In a fourth aspect, the present application provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the CPU design method as described in the second aspect is implemented.

[0015] In a fifth aspect, the present application provides a computer-readable storage medium, comprising: a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the CPU design method described in the second aspect is implemented.

[0016] In a sixth aspect, the present application provides a computer program product, including: the computer program product includes a computer program, and when the computer program runs on a computer, the computer implements the CPU design method as described in the second aspect.

[0017] Compared with the prior art, the technical solution provided by the embodiments of the present application has the following advantages:

[0018] The disclosed embodiments provide a CPU and a CPU design method, device, equipment, medium and product, wherein the CPU includes a processor core for controlling multiple submodules to execute instructions, process data and interrupts, and a plug-in pool for managing the creation, execution order and resource allocation of multiple extended function plug-ins, wherein multiple extended function plug-ins transmit data with the processor core through a plug-in interface, and the plug-in interface includes a signal channel for inputting submodule status information, and a data channel for outputting control instructions. Through the plug-in hardware design method, different functions can be flexibly combined or replaced, which improves the flexibility, scalability and collaboration of the CPU design; when adding, removing or replacing extended function plug-ins, there is no need to modify the core source code, which reduces the complexity of the CPU design and improves reusability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] Figure 1 A flowchart of a CPU design method provided in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of an assembly line provided for an embodiment of the present application;

[0023] Figure 3 A schematic diagram of the structure of a CPU design device provided in an embodiment of the present application;

[0024] Figure 4A schematic diagram of the structure of an electronic device described in an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the technical terms required to be used in the embodiments or the prior art description are briefly introduced below:

[0026] HDL is a programming language used to describe the function, structure, and behavior of electronic circuits (especially digital circuits). It allows engineers to design hardware in a way similar to software programming, rather than through the traditional way of drawing circuit diagrams. For example, when designing a complex microprocessor chip, engineers can use HDL to accurately describe the connection relationship and operation logic between various modules inside the chip (such as arithmetic logic units, registers, controllers, etc.). By using HDL to write circuit design codes, and then using Electronic Design Automation (EDA) tools, these codes can be converted into actual circuit layouts.

[0027] VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) is a strongly typed hardware description language based on IEEE standards. It has a rich language structure and supports hierarchical and modular design.

[0028] Verilog is a more flexible hardware description language that is closer to the C language style. It supports circuit descriptions at multiple levels of abstraction, including behavioral level, register transfer level (RTL), and gate level. For example, in behavioral level descriptions, procedural statements similar to those in software programming (such as always, initial) can be used to describe the dynamic behavior of the circuit.

[0029] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0030] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.

[0031] In order to solve some or all of the technical problems existing in the related art, an embodiment of the present application provides a CPU, which includes a processor core for controlling multiple sub-modules to execute instructions, process data and interrupts, and a plug-in pool for managing the creation, execution order and resource allocation of multiple extended function plug-ins, wherein multiple extended function plug-ins transmit data with the processor core through a plug-in interface, and the plug-in interface includes a signal channel for inputting sub-module status information, and a data channel for outputting control instructions. Through the plug-in hardware design method, different functions can be flexibly combined or replaced, which improves the flexibility, scalability and collaboration of the CPU design; when adding, removing or replacing extended function plug-ins, there is no need to modify the core source code, which reduces the complexity of the CPU design and improves reusability.

[0032] like Figure 1 As shown, Figure 1 A schematic diagram of the structure of a CPU provided in an embodiment of the present application, the CPU includes a processor core (Core) 101 and a plug-in pool (Plugin Pool) 102. Among them,

[0033] Processor core 101, used to control multiple submodules to execute instructions, process data and interrupt;

[0034] The plug-in pool 102 is used to manage the creation, execution order and resource allocation of multiple extended function plug-ins.

[0035] In the embodiment of the present application, multiple extended function plug-ins perform data transmission with the processor core 101 through a plug-in interface (Plugin Interface). The plug-in interface includes a signal channel for inputting submodule status information and a data channel for outputting control instructions.

[0036] The above embodiment makes the processor core 101 no longer directly implement various functions, but through plug-in design, multiple extended function plug-ins are used to implement extended functions in addition to the basic functions such as executing instructions, processing data and interrupting, and each extended function plug-in is uniformly managed by the plug-in pool. Therefore, the CPU function can be expanded by adding or replacing plug-ins without modifying the core logic, which improves the scalability and flexibility of the CPU; by defining the input and output of the plug-in interface, there is no need to manually control the timing, so that adding or replacing plug-ins does not affect the timing of other plug-ins, which facilitates flexible expansion of the CPU.

[0037] In the embodiment of the present application, multiple sub-modules of the processor core 101 transmit sub-module status information to the corresponding extended function plug-in through a signal channel; the extended function plug-in transmits control instructions to the processor core through a data channel.

[0038] In some embodiments, the processor core 101 includes sub-modules such as an instruction decoding module, a register file, an execution unit, and a memory interface to implement basic functions.

[0039] In some embodiments, the extended function plug-ins in the plug-in pool 102 include, but are not limited to, extended function components such as cache plug-ins, storage plug-ins, branch prediction plug-ins, multiplication and division plug-ins, and floating-point operation plug-ins. Exemplarily, the cache plug-in can be a cache cache, and the storage plug-in can be a tightly coupled memory (TCM). Different functions are integrated and implemented in a plug-in manner, and the extended function plug-ins negotiate with each other through the plug-in interface to ensure the compatibility and correctness of the functions. Each extended function plug-in supports the definition of input and output interfaces, logical functions, and the interaction method with the processor core.

[0040] In some embodiments, the plug-in pool 102 is specifically used to: when the CPU is started, load the corresponding pre-selected extended function plug-in according to predefined parameters, the pre-selected extended function plug-in includes but is not limited to the first extended function plug-in and the second extended function plug-in, wherein the first extended function plug-in obtains the parameters of the second extended function plug-in based on the shared database to collaboratively determine the control instruction. The pre-selected extended function plug-ins discover and register with each other through the plug-in interface.

[0041] When the CPU starts, the plug-in pool enters the initialization phase and starts loading extension plug-ins, specifically loading corresponding pre-selected extension plug-ins according to predefined parameters. Predefined parameters are predefined or configured parameters that are used to determine which extension plug-ins to load.

[0042] In the above embodiment, the shared database is a parameter database shared by multiple extended function plug-ins, which stores global parameter information or partial parameter information and supports dynamic writing or reading by each extended function plug-in. Exemplarily, the shared database stores parameter information such as instruction address width, virtual memory address width, and hit rate of branch prediction plug-ins.

[0043] Based on the above embodiment, when the second extended function plug-in sets the target parameter information through the shared database, the first extended function plug-in is controlled to enter a blocking state and wait for the target parameter information to be set. After the target parameter information is set, the first extended function plug-in is controlled to determine a control instruction according to the target parameter information.

[0044] Specifically, when the CPU starts, the corresponding first extended function plug-in and the second extended function plug-in are loaded according to the predefined parameters. At this time, if the second extended function plug-in is setting the target parameter information through the shared database, the plug-in pool 102 first controls the first extended function plug-in to enter a blocking state until the target parameter information is set, and then controls the first extended function plug-in to determine the control instruction according to the target parameter information. Thus, the dynamic collaboration of each extended function plug-in is realized through the shared database to complete complex functions. It can be understood that the first extended function plug-in determines the control instruction based on the target parameter information set by the second extended function plug-in, and the first extended function plug-in and the second extended function plug-in cooperate with each other through the shared database to achieve complex functions.

[0045] Exemplarily, the target parameter information may be an instruction address width. When the second extended function plug-in A sets the instruction address width through the shared database, the first extended function plug-in B enters a blocking state, waiting for the instruction address width to be set. When the instruction address width is set, the first extended function plug-in B recovers from the blocking state and determines the control instruction according to the instruction address width.

[0046] In the above embodiment, the extended function plug-in is executed as an independent fiber thread. The extended function plug-in can prevent its own execution until certain parameter information in the shared database is set by other plug-ins, thereby realizing refined thread control between plug-ins and enhancing parallel processing capabilities, so that different extended function plug-ins can achieve efficient dynamic collaboration based on the shared database. Different extended function plug-ins share a parameter database, which can enhance the collaboration capabilities between different plug-ins.

[0047] In some embodiments, when the CPU enters the working state, the extended function plug-in can execute its own functional logic and work in coordination with the processor core through the plug-in interface. For example, if the first extended function plug-in is a branch prediction plug-in, it will perform branch prediction operations, and if the second extended function plug-in is a cache plug-in, it will perform cache management operations; and it will work in coordination with the processor core through signal channels and data channels.

[0048] In some embodiments, the processor core is specifically used to: receive control instructions output by a pre-selected extended function plug-in through a data channel; decode the control instructions to determine the instruction type of the control instructions; determine the sub-module corresponding to the instruction type to execute the control instruction to obtain sub-module status information; and then transmit the sub-module status information to the pre-selected extended function plug-in through a signal channel.

[0049] There may be multiple sub-modules corresponding to the instruction type, and data is transferred between them through the pipeline API.

[0050] Optionally, when receiving control instructions output by the pre-selected extended function plug-in through the data channel, subsequent control instructions can be extracted in advance and placed in the pre-fetch queue, so that while some sub-modules are executing the current control instructions, the background continues to pre-fetch the next batch of control instructions. This can hide memory access delays, increase instruction acquisition speed, reduce the time waiting for instructions, and thus improve instruction execution efficiency. Instruction prefetching can ensure that each stage of the pipeline has sufficient instruction supply, avoid pipeline disconnection or pause due to untimely supply of operation instructions, and allow different stages to enter for processing in advance, further improving the overall performance of the CPU.

[0051] Optionally, after receiving the control instruction output by the pre-selected extended function plug-in through the data channel, the control instruction is cached. In this way, the control instruction can be quickly obtained directly from the cache without accessing the relatively slow memory, which improves the access speed and can speed up the instruction execution efficiency.

[0052] like Figure 2 As shown, Figure 2 The pipeline schematic diagram provided for the embodiment of the present application uses the following sub-modules or extended function plug-ins in each stage of the pipeline: branch target buffer (Branch Target Buffer, BTB), branch prediction plug-in (Global Shared Branch Predictor, Gshare), instruction decoder (Decoder), arithmetic logic unit (ALU), division operation plug-in (DIV), multiplication operation plug-in (MUL), register stack read (RF-read), register stack write (RF-write).

[0053] The above embodiments can be explained with reference to the five-stage pipeline. In the instruction fetch (IF) stage, the processor core extracts the control instruction, which is output to the processor core through the data channel by the pre-selected extended function component. It is configured according to the demand, and is provided with the instruction type, supports dynamic adjustment of the cache size or access strategy, and enhances the write back; in the instruction decode (ID) stage, the corresponding submodule is called according to the type of the control instruction, and the submodules transfer data through the pipeline API to realize dynamic adjustment of the data path. In the execution (EX) stage, the submodule can be dynamically configured according to the control instruction and execute the control instruction; in the memory access (MEM) stage, the submodule dynamically adjusts the cache size or access strategy according to the control instruction; in the write back (WB) stage, the submodule can realize the fast write back of the submodule status information according to the control instruction.

[0054] In the above embodiment, control instructions are transmitted and circulated in the processor core, and automatic control timing is achieved through the pipeline API, without the need for manual control of timing, making each stage of the pipeline more flexible. Based on the plug-in design, the adjustment of pipeline depth or structure can be achieved by configuring the plug-in or adjusting the execution order of instructions, without the need to manually modify the code logic; and the configuration of the plug-in or the modification of the execution order will not affect the timing of other extended function plug-ins.

[0055] In some embodiments, when the CPU enters a low power consumption mode, the plug-in pool controls multiple extended function plug-ins to dynamically release resources to save unnecessary resource consumption.

[0056] In summary, the embodiment of the present application provides a CPU, including a processor core for controlling multiple sub-modules to execute instructions, process data and interrupts, and a plug-in pool for managing the creation, execution order and resource allocation of multiple extended function plug-ins, wherein multiple extended function plug-ins transmit data with the processor core through a plug-in interface, and the plug-in interface includes a signal channel for inputting sub-module status information, and a data channel for outputting control instructions. In this way, the present application uses a plug-in hardware design method to enable different functions to be flexibly combined or replaced, thereby improving the flexibility, scalability and collaboration of the CPU design; when adding, removing or replacing extended function plug-ins, there is no need to modify the core source code, which reduces the complexity of the CPU design and improves reusability.

[0057] The embodiment of the present application provides a CPU design method, which can be executed by a CPU design device or an electronic device, wherein the device can be implemented by software and / or hardware and can generally be integrated into an electronic device. The method mainly includes: generating a hardware description of the CPU provided in the embodiment of the present application by using a high-level hardware description language SpinalHDL.

[0058] The method uses SpinalHDL to describe the CPU's processor core and plug-in pool, such as register files, etc. SpinalHDL is a modern hardware description language that emphasizes hardware design at a high level of abstraction, allowing developers to conceive and build hardware circuits like writing software.

[0059] SpinalHDL's static type checking and interface matching mechanisms ensure that the signals and data between the processor core and the plug-in can interact correctly, reduce the complexity of the design, improve design efficiency, and facilitate collaboration and code reuse between design teams. It supports dynamic configuration and updating of functions when the hardware is running. Multiple extended function plug-ins can access a shared database, which is conducive to communication and collaboration. Extended function plug-ins are controlled and managed through fiber threads, so as to more effectively manage parallel computing and reasonably allocate resources.

[0060] The plug-in design allows different functions to be dynamically integrated and flexibly combined, and can add, delete or replace CPU functions without modifying the core source code, reducing the complexity of CPU design. Extended function plug-ins share parameters, thereby reducing the duplication of design codes, reducing development time and maintenance costs, thereby improving design efficiency and reducing potential error risks.

[0061] A CPU design method provided in the embodiment of the present application can be implemented by a CPU design device or an electronic device, and the electronic device includes but is not limited to a personal computer, a laptop computer, a tablet computer, a smart phone, etc. The operating system of the electronic device may include Android (Android), a mobile operating system (iOS) developed by Apple, an operating system (Windows) developed by Microsoft Corporation of the United States, etc., and the embodiment of the present application is not limited to this. The electronic device can be run alone to implement the present application, or it can be connected to the network and implemented by interactive operations with other computer devices in the network. Among them, the network in which the electronic device is located includes but is not limited to the Internet, a wide area network, a metropolitan area network, a local area network, a virtual private network (Virtual Private Network, VPN) network, etc.

[0062] It should be noted that the protection scope of the CPU design method described in the embodiment of the present application is not limited to the execution order of the steps listed in this embodiment. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present application are included in the protection scope of the present application.

[0063] like Figure 3 As shown, Figure 3 A CPU design device provided in an embodiment of the present application includes: a hardware generation module 300, which is used to generate a hardware description of the CPU as described in any one of the above items through a high-level hardware description language SpinalHDL.

[0064] In summary, the embodiment of the present application provides a CPU design device, which can ensure that the signals and data between the processor core and the plug-in can interact correctly through the static type checking and interface matching mechanism of SpinalHDL, reduce the complexity of the design, improve the design efficiency, and facilitate the collaboration and code reuse between the design team. It supports dynamic configuration and updating of functions when the hardware is running.

[0065] For the specific definition of the CPU design device, please refer to the definition of the CPU design method above, which will not be repeated here. Each module in the above-mentioned CPU design device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0066] In one embodiment, the present application provides an electronic device, which may be a terminal, and its internal structure diagram may be as follows: Figure 4 As shown. The electronic device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the electronic device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, an operator network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a CPU design method is implemented. The display screen of the electronic device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic device can be a touch layer covered on the display screen, or a button, a trackball or a touch pad set on the housing of the electronic device, or an external keyboard, touch pad or mouse, etc.

[0067] Those skilled in the art will understand that Figure 4 The structure shown in the figure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the electronic device to which the scheme of the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0068] In one embodiment, the CPU design device provided by the present application can be implemented in the form of a computer program. The computer program can be Figure 4 The memory of the electronic device may store various program modules constituting the CPU design device, for example, Figure 3 The hardware generation module 300 shown is used to generate the hardware description of the CPU as described in any one of the above items by using the high-level hardware description language SpinalHDL. The computer program composed of each program module enables the processor to execute the steps in the CPU design method of each embodiment of the present application described in this specification.

[0069] In one embodiment, the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps in the CPU design method of each embodiment of the present application described in this specification are implemented.

[0070] When the processor in the electronic device provided by the present application executes a computer program, the hardware description of the CPU as described in any of the above items is generated through the high-level hardware description language SpinalHDL. Through the plug-in hardware design method, different functions can be flexibly combined or replaced, which improves the flexibility, scalability and collaboration of the CPU design; when adding, removing or replacing the extended function plug-in, there is no need to modify the core source code, which reduces the complexity of the CPU design and improves reusability.

[0071] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed, the steps in the CPU design method of each embodiment of the present application described in this specification are implemented.

[0072] When the computer program in the computer-readable storage medium provided by the present application executes the computer program, the hardware description of the CPU as described in any of the above items is generated through the high-level hardware description language SpinalHDL. Through the plug-in hardware design method, different functions can be flexibly combined or replaced, which improves the flexibility, scalability and collaboration of the CPU design; when adding, removing or replacing the extended function plug-in, there is no need to modify the core source code, which reduces the complexity of the CPU design and improves reusability.

[0073] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media that include computer-usable program code.

[0074] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0075] In the present application, the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0076] In this application, memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0077] In this application, computer-readable media includes permanent and non-permanent, removable and non-removable storage media. Storage media can be implemented by any method or technology to store information, and the information can be computer-readable instructions, data structures, modules of programs or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. According to the definition in this article, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0078] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0079] The above is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A CPU, characterized in that: include: Plug-in pool and processor core; where, The processor core is used to control multiple submodules to execute instructions, process data and interrupt; The plug-in pool is used to manage the creation, execution order and resource allocation of multiple extended function plug-ins; the multiple extended function plug-ins transmit data with the processor core through the plug-in interface; the plug-in interface includes a signal channel for inputting sub-module status information, and a data channel for outputting control instructions.

2. The CPU according to claim 1, characterized in that: The plug-in pool is specifically used for: When the CPU starts, the corresponding pre-selected extended function plug-in is loaded according to the pre-defined parameters; The first extended function plug-in obtains parameter information of the second extended function plug-in based on the shared database to collaboratively generate the control instruction; the first extended function plug-in and the second extended function plug-in are any two of the extended function plug-ins.

3. The CPU according to claim 2, characterized in that: The plug-in pool is specifically used for: When the second extended function plug-in sets the target parameter information through the shared database, controlling the first extended function plug-in to enter a blocking state, waiting for the target parameter information to be set; After the target parameter information is set, the first extended function plug-in is controlled to generate the control instruction according to the target parameter information.

4. The CPU according to claim 2, characterized in that: The processor core is specifically used for: Receiving a control instruction output by the preselected extended function plug-in through the data channel; Decoding the control instruction to determine the instruction type of the control instruction; Determine that a submodule corresponding to the instruction type executes the control instruction, and obtain status information of the submodule; The submodule status information is transmitted to the preselected extended function plug-in through the signal channel.

5. The CPU according to claim 1, characterized in that: The plug-in pool is specifically used for: When the CPU enters a low power consumption mode, the plurality of functional plug-ins are controlled to dynamically release resources.

6. A CPU design method, characterized in that: include: The hardware description of the CPU as claimed in any one of claims 1 to 5 is generated by a high-level hardware description language SpinalHDL.

7. A CPU design device, characterized in that: include: The hardware generation module is used to generate the hardware description of the CPU as described in any one of claims 1 to 5 by using the high-level hardware description language SpinalHDL.

8. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the CPU design method according to claim 6 when executed by the processor.

9. A computer-readable storage medium, characterized in that: include: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the CPU design method according to claim 6 is implemented.

10. A computer program product, characterized in that include: The computer program product includes a computer program, and when the computer program is run on a computer, the computer is caused to implement the CPU design method according to claim 6 .

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