Digital-to-analog conversion method based on improved binary gold washing algorithm optimization

Abstract

The invention discloses a digital-to-analog conversion method based on improved binary gold washing algorithm optimization. The method comprises the following steps: setting initial parameters; adopting and designing a binary method of a gold washing optimization algorithm and applying the binary method to the Uc-ReDAC model, and calculating a binary code corresponding to the target voltage; a dimension expansion strategy based on a dimension factor is adopted to expand the gold scrubber position matrix, and the dimension factor is utilized to enhance the influence of the current dimension on the binary position of the gold scrubber; designing a variable slope convergence factor based on an RC circuit time constant in the Uc-ReDAC model, and constraining the moving step length of the gold washing person through the factor; a gold scrubber position matrix dynamic updating strategy is adopted, a circle mapping random number generation method is adopted to expand a gold scrubber decimal position matrix, and binary codes meeting precision requirements are output. According to the method, the improved gold washing optimization algorithm is combined with the mathematical model of the unconstrained relaxation digital-to-analog converter, so that data conversion efficiency and accuracy can be ensured while data conversion is realized.

Description

Technical Field

[0001] The invention belongs to the field of digital-to-analog conversion, relates to digital-to-analog converter technology, and specifically relates to a digital-to-analog conversion method based on improved binary gold panning algorithm optimization. Background Art

[0002] Digital to Analog Converter (DAC) is one of the indispensable core components in modern electronic systems. It is widely used in many fields such as audio and video processing, communication systems, industrial automation, scientific measurement, medical equipment, power management and emerging technologies. With the popularization of digital signal processing technology, DAC enables digital systems to efficiently connect with analog devices by converting discrete digital signals into continuous analog signals. Therefore, the research on DAC is particularly important. With the development of DAC technology in recent years, DAC can be divided into many types according to different principles and application requirements, including resistor voltage divider type, current distribution type, weighted current type, integral type, charge distribution type, pulse width modulation type and hybrid DAC.

[0003] At present, it is an important research direction to integrate intelligent optimization algorithms into engineering applications and apply them to the field of DAC technology. Intelligent optimization algorithms are applied to DAC mathematical models to transform the optimization problem of the optimization algorithm into the problem of solving the DAC output voltage. This will greatly reduce the complexity of DAC while ensuring conversion time and accuracy.

[0004] Therefore, it is of great significance to combine the intelligent optimization algorithm with the DAC mathematical model to solve the optimization problem of binary coding in the model. Improving the DAC conversion rate and accuracy is an important topic in the field of digital-to-analog converter technology, and its research is of great significance. Summary of the invention

[0005] Purpose of the invention: In order to overcome the deficiencies in the prior art, a digital-to-analog conversion method based on an improved binary gold panning algorithm is provided, which combines the improved gold panning optimization algorithm with an unconstrained-Relaxation DAC (Uc-ReDAC) mathematical model to achieve data conversion while ensuring data conversion efficiency and accuracy.

[0006] Technical solution: To achieve the above purpose, the present invention provides a digital-to-analog conversion method based on an improved binary gold panning algorithm optimization, comprising the following steps:

[0007] S1: Set the initial parameters of the Uc-ReDAC model and algorithm;

[0008] S2: Adopt and design a binary method of gold panning optimization algorithm and use it in the Uc-ReDAC model to calculate the binary code corresponding to the target voltage;

[0009] S3: Adopt the dimension expansion strategy based on dimension factor to expand the gold digger position matrix, and use the dimension factor to enhance the influence of the current dimension on the binary position of the gold digger to ensure the correct movement of the gold digger;

[0010] S4: Design a variable slope convergence factor based on the RC circuit time constant in the Uc-ReDAC model, and use this factor to constrain the gold digger's moving step size;

[0011] S5: A dynamic update strategy for the gold digger position matrix is ​​adopted, and a circular mapping random number generation method is used to expand the gold digger decimal position matrix, and finally a binary code that meets the accuracy requirements is output.

[0012] Furthermore, the initial parameters in step S1 include the Uc-ReDAC resolution n, the minimum allowable error The number of gold diggers N, the maximum number of iterations M, and the upper and lower limits ub and lb of the gold digger search space.

[0013] Furthermore, the Uc-ReDAC model in step S2 is

[0014]

[0015] Among them, V C,n Represents the voltage across the capacitor at time nT, V C,0 Represents the initial voltage of the capacitor, V DD represents the power supply voltage of the RC circuit, T represents the system clock period, τ=RC represents the time constant, n represents the length of the binary sequence, b k represents the kth item of the binary sequence.

[0016] Furthermore, the binary method of the gold panning optimization algorithm in step S2 and the method used in the Uc-ReDAC model are:

[0017] Binarize the gold mining optimization algorithm. In the gold mining optimization algorithm, the gold diggers mainly determine the location of the gold mine through three steps: migration, collaboration, and gold mining. Unify the gold diggers' position updates into

[0018] x i+1 (t+1)=x i (t)+ε (2)

[0019] Among them, x i+1 、x iare the new and previous positions of the gold digger, respectively. ε is the step length of migration, collaboration, and gold digging. The position update is related to ε. The step length ε of the gold digger is mapped to [0,1], and the sigmoid function is

[0020]

[0021] When the step length ε of the gold digger is larger, the value of s(ε) is closer to 1; otherwise, the value is closer to 0; after mapping, the position of the gold digger is updated to

[0022]

[0023] If s(ε) is greater than the random number r, then x id The value of x is 1; otherwise, id The value of is 0, thus completing the gold digger's position update.

[0024] Furthermore, the dimension expansion strategy in step S3 includes: each row in the matrix represents a solution found by the algorithm, and only the solution that meets the accuracy requirement can be output, otherwise the matrix will continue to expand to a higher dimension;

[0025] Minimum allowable error of Uc-ReDAC model Determined by the model resolution,

[0026]

[0027] Where N is the resolution of Uc-ReDAC; P gd The optimal value found for the gold digger; V C,n is the voltage to be searched; is the minimum allowable error;

[0028] Despite the conditional dimensional expansion, the binary position update of the gold digger is random according to formula (1), resulting in an unsatisfactory output binary code length. Therefore, in formula (1), let V C,0 = 0, which is simplified to

[0029]

[0030] make Rewrite equation (6) as

[0031]

[0032] Among them, if b1=0, b1 is an invalid start bit, and the binary code valid start bit is b2; if b1=b2=0, b1 and b2 are invalid start bits, and the binary code valid start bit is b3.

[0033] Furthermore, in the dimension expansion strategy of step S3, the dimension expansion of the binary position matrix will be stopped only when there is a solution that meets the accuracy requirements in the binary position matrix of the gold digger; considering that the dimension change of the matrix can affect the current binary position of the gold digger, the dimension influence factor affecting the binary position of the gold digger is designed, and its calculation formula is:

[0034]

[0035] Among them, V DD Indicates the power supply voltage of the RC circuit; D max V is the resolution of the model DD The shortest length of the corresponding binary code; V C,n is the voltage to be searched; d is the current binary coding dimension;

[0036] At this time, the mapping formula of the gold digger's step length ε is

[0037]

[0038] Among them, ε is the step length of the gold digger;

[0039] In the Uc-ReDAC model, the shortest binary code bit corresponding to the target voltage cannot be calculated, but it can be calculated at the resolution of the model. DD The corresponding binary code has the shortest length D max ,When the dimension is expanded, the influence of the current dimension on the binary position of the gold digger can be increased to control the length of the binary code.

[0040] Furthermore, the variable slope convergence factor l in step S4 based on the RC circuit time constant in the Uc-ReDAC model * for

[0041]

[0042] Among them, α is the initial value of the factor change; β is the convergence coefficient; iter is the current iteration number of the algorithm, and T is the maximum iteration number.

[0043] Furthermore, when the gold digger's decimal position matrix is ​​expanded in dimension, the element values ​​of the newly expanded dimension are randomly generated. However, the traditional random number generation method may cause some random positions to aggregate, thereby affecting the performance of the algorithm. To address this problem, in step S5, when the decimal position matrix is ​​expanded in dimension, a random factor generated based on a circular mapping method is designed, and the calculation formula is:

[0044]

[0045] Among them, rand(j+1) is the currently generated random factor; α is the nonlinear degree factor; β is the driving factor.

[0046] Furthermore, in step S5, a random number generation method is adopted in which the circle mapping random number generation range decreases nonlinearly as the number of iterations increases; the gold digger decimal position update formula is:

[0047]

[0048] Among them, x id is the value of the ith gold digger in the dth dimension; iter is the number of iterations; rate is the contraction coefficient, which can be adjusted according to the actual search situation. The larger the value, the more obvious the contraction effect on the range of random number values; ub and lb are the upper and lower initial limits of the search space. As the number of iterations increases, the update range of the element values ​​in the newly expanded dimension of the gold digger decimal position matrix decreases nonlinearly, reducing the blindness of the algorithm in the later iterations and accelerating convergence.

[0049] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0050] 1. Mapping the moving step size in the GRO algorithm to realize the binary of the algorithm can better solve the optimization problem under the Uc-ReDAC model and improve the efficiency of the algorithm;

[0051] 2. A dimension expansion strategy based on dimension factor is proposed, which combines dimension change to influence the gold diggers, enhances the influence on the binary position change of the gold diggers, and further controls the binary code length;

[0052] 3. A variable slope convergence factor based on the time constant of the RC circuit is proposed. It changes nonlinearly according to the number of iterations to control the time for the gold digger to switch from global search to local search. At the same time, the time characteristics of the external RC circuit are taken into account to ensure the correctness of the output voltage value of UC-ReDAC.

[0053] 4. According to the characteristics of the Uc-ReDAC model and the characteristics of the GRO algorithm, a gold digger position matrix update strategy is proposed to improve the algorithm operation efficiency through synchronous update and ensure the correct operation of the algorithm;

[0054] 5. The algorithm provided by the present invention can be better applied to the Uc-ReDAC model. The binary code length corresponding to the search target voltage is short and the accuracy is high, which effectively reduces the code search time and can ensure data conversion efficiency and accuracy while realizing data conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a flow chart of the binary gold panning optimization algorithm of the present invention;

[0056] Figure 2 It is the structural diagram of Uc-ReDAC model;

[0057] Figure 3 Schematic diagram of the dimension expansion of the binary position matrix of the gold digger;

[0058] Figure 4 This is a schematic diagram of the dimension expansion of the improved binary position matrix of the gold digger;

[0059] Figure 5 The improved variable slope convergence factor function curve of the present invention is compared with the original convergence factor function;

[0060] Figure 6 It is a schematic diagram of the dynamic update of the position matrix of the present invention;

[0061] Figure 7 Update the range for the decimal position matrix elements;

[0062] Figure 8 The number of bits of binary coding for the 4-bit Uc-ReDAC model changes;

[0063] Fig. 9 The number of bits of binary coding for the 6-bit Uc-ReDAC model changes;

[0064] Fig.10 The number of bits of binary coding for the 8-bit Uc-ReDAC model changes;

[0065] Fig.11 The static parameter comparison chart of the two algorithms under 4-bit, 6-bit, and 8-bit Uc-ReDAC models. DETAILED DESCRIPTION

[0066] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0067] The present invention provides a digital-to-analog conversion method based on an improved binary gold panning algorithm optimization, referring to Figure 1 , which comprises the following steps:

[0068] S1: Set the initial parameters of the Uc-ReDAC model and algorithm;

[0069] Including Uc-ReDAC resolution n, minimum permissible error According to the model resolution n, the number of gold diggers N is 50, the maximum number of iterations M is set to 100, and the upper and lower limits ub and lb of the gold digger search space are set to 10 and -10 respectively;

[0070] S2: Adopt and design a binary method of gold panning optimization algorithm and use it in the Uc-ReDAC model to calculate the binary code corresponding to the target voltage;

[0071] The essence of Uc-ReDAC is to use the binary code generated by the optimization algorithm to charge and discharge the capacitor by controlling the three-state buffer, so as to generate the required analog voltage. The structure diagram of Uc-ReDAC is shown in Figure 2 As shown. The mathematical model expression of Uc-ReDAC is

[0072]

[0073] Among them, V C,n Represents the voltage across the capacitor at time nT, V C,0 Represents the initial voltage of the capacitor, V DD represents the power supply voltage of the RC circuit, T represents the system clock period, τ=RC represents the time constant, n represents the length of the binary sequence, b k represents the kth item of the binary sequence;

[0074] Binarize the gold mining optimization algorithm. In the gold mining optimization algorithm, the gold diggers mainly go through three steps: migration, collaboration, and gold mining to finally determine the location of the gold mine. Unify the gold diggers' position updates into

[0075] x i+1 (t+1)=x i (t)+ε (2)

[0076] Among them, x i+1 、x i are the new and previous positions of the gold digger, respectively. ε is the step length of migration, collaboration, and gold digging. The position update is related to ε. Map the step length ε of the gold digger to [0,1], and the sigmoid function is

[0077]

[0078] When the step length ε of the gold digger is larger, the value of s(ε) is closer to 1; otherwise, the value is closer to 0. After mapping, the position of the gold digger is updated to

[0079]

[0080] If s(ε) is greater than the random number r, then x id The value of x is 1; otherwise, idThe value of is 0, thus completing the gold digger's position update.

[0081] S3: Adopt the dimension expansion strategy based on dimension factor to expand the gold digger position matrix, and use the dimension factor to enhance the influence of the current dimension on the binary position of the gold digger to ensure the correct movement of the gold digger;

[0082] Dimension expansion methods such as Figure 3 As shown in the figure, the number of rows in the matrix represents the number of gold diggers, and the number of columns in the matrix represents the dimension of the gold diggers. In this matrix, each row represents the solution found by the algorithm. Only the solution that meets the accuracy requirements can be output, otherwise the matrix will continue to expand to higher dimensions. The minimum allowable error of the Uc-ReDAC model Determined by the model resolution,

[0083]

[0084] Where N is the resolution of Uc-ReDAC; P gd The optimal value found for the gold digger; V C,n is the voltage to be searched; is the minimum allowable error.

[0085] Despite the conditional dimensional expansion, the binary position update of the gold digger is random according to equation (1), resulting in an unsatisfactory output binary code length. Therefore, in equation (1), let V C,0 = 0, which is simplified to

[0086]

[0087] make Rewrite equation (6) as

[0088]

[0089] If b1=0, b1 is an invalid start bit, and the effective start bit of binary code is b2; if b1=b2=0, b1 and b2 are invalid start bits, and the effective start bit of binary code is b3. i1 ==1. The dimension of the improved binary position matrix of the gold digger is expanded as follows: Figure 4 shown.

[0090] In the dimension expansion strategy proposed by the present invention, the dimension expansion of the binary position matrix will be stopped only when there is a solution that meets the accuracy requirements in the binary position matrix of the gold digger. Considering that the dimension change of the matrix can affect the current binary position of the gold digger, the present invention designs a dimension influence factor that affects the binary position of the gold digger, and its calculation formula is:

[0091]

[0092] Among them, V DD Indicates the power supply voltage of the RC circuit; D max V is the resolution of the model DD The shortest length of the corresponding binary code; V C,n is the voltage to be searched; d is the current binary coding dimension. At this time, the mapping formula of the gold digger's step length ε is

[0093]

[0094] Among them, ε is the step length of the gold digger;

[0095] In the Uc-ReDAC model, the shortest binary code bit corresponding to the target voltage cannot be calculated, but it can be calculated at the resolution of the model. DD The corresponding binary code has the shortest length D max ,When the dimension is expanded, the influence of the current dimension on the binary position of the gold digger can be increased to control the length of the binary code.

[0096] S4: Design a variable slope convergence factor based on the RC circuit time constant in the Uc-ReDAC model, and use this factor to constrain the gold digger's moving step size;

[0097] In the gold mining optimization algorithm, the migration vector coefficient A1 is adjusted to determine whether the gold digger performs global search or local search. The calculation formula of A1 is:

[0098]

[0099] Wherein, l1 is the balance factor; r1 is a random number in the range of [0,1]. When |A1|≤1, the gold diggers reduce their migration and search for gold mines in a smaller local area. Since the value of |A1| changes with the change of l1, the change of l1 affects the search ability of the gold diggers. The present invention combines the charging and discharging process of the RC circuit in Uc-ReDAC to design a variable slope convergence factor l based on the time constant of the RC circuit. * Substituting l1, the calculation formula is

[0100]

[0101] Among them, α is the initial value of the factor change, which is 2 in this embodiment; β is the convergence coefficient, which is 0.5 in this embodiment; iter is the current iteration number of the algorithm, and T is the maximum iteration number.

[0102] When the maximum number of iterations is 250, the convergence factor change curve l when τ = 100ns * like Figure 5As shown. The fast decay in the early stage of iteration is conducive to the global search of the gold digger, and the slow decay in the later stage of iteration is conducive to the local search of the gold digger, thereby improving the search accuracy of the gold digger. In the Uc-ReDAC model, the larger the time constant is, the longer the charging and discharging time of the RC circuit is, and the longer the binary code is required to complete the charging. The convergence factor l proposed by the present invention is adopted. * Controlling the time for the gold digger to switch from global search to local search while taking into account the time characteristics of the external RC circuit ensures the correctness of the UC-ReDAC output voltage value.

[0103] S5: adopt a gold digger position matrix dynamic update strategy, use the circle mapping random number generation method to expand the gold digger decimal position matrix, and finally output the binary code that meets the accuracy requirements;

[0104] In the binarization process of the gold panning optimization algorithm, the gold panner's moving step length cannot be calculated using the gold panner's binary position. Therefore, the present invention designs a gold panner position matrix dynamic update strategy for obtaining the gold panner's moving step length. Figure 6 The dynamic update strategy of the gold digger position matrix is ​​described as follows: Process 1 represents the dynamic update of the gold digger binary position matrix, and process 2 represents the dynamic update of the gold digger decimal position matrix. In the dimension expansion strategy, as shown in process 1, it is stipulated that all element values ​​in the first dimension of the gold digger binary position matrix are 1, and when the dimension of the binary position matrix is ​​expanded, the position information of the new dimension is updated and generated by the decimal position information of the previous dimension in the decimal position matrix. In process 2, the algorithm randomly selects the migration, collaboration or gold panning update method to calculate the moving step length of the gold digger, and then uses the moving step length to calculate its binary position information. By analogy, the binary position matrix of the gold digger continues to expand in dimension until a binary code that meets the accuracy requirements appears in the updated binary position matrix of the gold digger, at which time the dimension expansion is stopped.

[0105] In the gold digger position matrix dynamic update strategy, when the gold digger's decimal position matrix is ​​expanded in dimension, the element value of the new expanded dimension is randomly generated. However, the traditional random number generation method may cause some random positions to aggregate, thus affecting the performance of the algorithm. In this regard, the present invention designs a random factor generated based on the circular mapping method when the decimal position matrix is ​​expanded in dimension. The calculation formula is:

[0106]

[0107] Wherein, rand(j+1) is the currently generated random factor; α is the nonlinear degree factor, which is 0.6 in this embodiment; β is the driving factor, which is 0.8 in this embodiment.

[0108] When the gold digger's decimal position matrix is ​​expanded in dimension, the use of a fixed range of circular mapping random number generation is not conducive to the gold digger's fine search of local areas in the later stages of iteration. Therefore, a random number generation method is adopted in which the range of circular mapping random number generation decreases nonlinearly with the increase in the number of iterations. The gold digger's decimal position update formula is:

[0109]

[0110] Among them, x id is the value of the ith gold digger in the dth dimension; iter is the number of iterations; rate is the contraction coefficient which can be adjusted according to the actual search situation. The algorithm of the present invention takes 0.01. The larger the value, the more obvious the contraction effect on the range of random number values; ub and lb are the upper and lower initial limits of the search space. As the number of iterations increases, the update range of the element values ​​in the newly expanded dimension of the gold digger's decimal position matrix dimension decreases nonlinearly, reducing the blindness of the algorithm iteration in the later stage and accelerating convergence. In the present invention, ub=10, lb=-10. As the number of iterations increases, the update range of the elements in the gold digger's decimal matrix becomes as follows: Figure 7 As shown, the shaded part is the value range of the elements in the gold digger's decimal position matrix.

[0111] In order to verify the effectiveness and effect of the method of the present invention, the following experiments and result analysis were performed in this embodiment:

[0112] The experimental computer is Intel(R) Core i7-8750H CPU@2.5GHz, 16G running memory; the operating system is Windows 11, and the programming environment is MATLAB R2021b. In order to test the performance of the algorithm of the present invention, the algorithm of the present invention, AP-BPSO and BPSO were simulated 10 times under the 4-bit Uc-ReDAC model and the 6-bit Uc-ReDAC model respectively. The experimental results were averaged, and the algorithm performance was evaluated by two indicators: the average number of bits of binary code generated and the algorithm search time. The average number of bits of binary code refers to the average number of bits of binary code that can represent each analog voltage under the model; the algorithm search time refers to the total time for the algorithm to output the binary code that can represent each analog voltage under the model. Finally, a comparison test of the number of bits of binary code generated by the three algorithms in the 4-bit Uc-ReDAC model, the 6-bit Uc-ReDAC model and the 8-bit Uc-ReDAC model was carried out, and the static parameters of the algorithm of the present invention and AP-BPSO under the 4-bit, 6-bit and 8-bit Uc-ReDAC models were compared.

[0113] In the experiment, the number of gold diggers in the algorithm of the present invention is 50, the maximum dimension of the gold diggers is 100, the maximum number of iterations is 100, and the random range of the initialization of the elements in the gold diggers' decimal position matrix is ​​[-10, 10]. The number of particles of AP-BPSO and BPSO is 50, the maximum dimension of the particles is 100, the maximum number of iterations of the particles is 100, the maximum and minimum values ​​of the inertia weight are 8 and 4 respectively, and the particle speed range is [-10, 10]. V in the 4-bit Uc-ReDAC, 6-bit Uc-ReDAC and 8-bit Uc-ReDAC models C,0 is 0V, the RC circuit time constant is 100ns, the clock period T is 10ns, and the power supply voltage V dd is 3.3V.

[0114] The average number of bits of binary code generated by the algorithm of the present invention and the other two algorithms and the algorithm search time under the 4-bit Uc-ReDAC and 6-bit Uc-ReDAC models are shown in Table 1. Since the BPSO algorithm does not converge to the optimal particle of the group, the binary numbers it generates will become more and more random as the iteration runs. C,n The binary encoding of will result in too long encoding bits and a long algorithm search time. The AP-BPSO algorithm adds an adaptive increment coefficient to the BPSO algorithm, thereby increasing the voltage V to be searched. C,n The value of has an impact on the particle position, which reduces the number of binary coding bits to a certain extent. However, the algorithm search time under the 6-bit Uc-ReDAC model is not significantly reduced compared with the BPSO algorithm.

[0115] Table 1

[0116]

[0117] The algorithm of the present invention generates a shorter binary code length and a faster search time under the 4-bit Uc-ReDAC model and the 6-bit Uc-ReDAC model. Compared with the AP-BPSO algorithm and the BPSO algorithm, the average number of bits of code under the 4-bit Uc-ReDAC model is shortened by 16.67% and 60%, and the search time is reduced by 47.31% and 79.22%, respectively. Under the 6-bit Uc-ReDAC model, the average number of bits of code is shortened by 52% and 57.14%, and the search time is reduced by 56.41% and 56.46%, respectively, indicating that the algorithm of the present invention has high performance under both models. The algorithm of the present invention binarizes the GRO algorithm, designs a dimension expansion strategy based on the dimension factor according to the characteristics of the algorithm itself and the law of the Uc-ReDAC model, and when the gold digger position matrix is ​​dimensionally expanded, the influence of the current dimension change on the binary position of the gold digger is added to enhance the directionality of the gold digger's movement; at the same time, in order to improve the search accuracy of the gold digger, the algorithm of the present invention adds a variable slope convergence factor based on the RC circuit time constant according to the Uc-ReDAC model. In combination with the above improvements, the binary position matrix of the gold diggers is conditionally expanded to reduce the number of binary coding bits as much as possible and improve the efficiency of the algorithm.

[0118] In the above two models, experiments were conducted on the changes in the number of binary code bits generated by the three algorithms, such as Figure 8 As shown in the figure, the algorithm generates a line graph of the change in the number of binary coded bits in the 4-bit Uc-ReDAC model. dd When the AP-BPSO algorithm generates binary code bits, the change is smoother than that of the BPSO algorithm. and The binary code bits generated by BPSO reached the maximum number of 100 and did not meet the accuracy requirement. The larger the target voltage is, the greater the change in the binary code bits is. The BPSO algorithm has no constraints on the position change of particles, and the randomness of the particle position is strong, resulting in a high probability of error when the search voltage is close to V dd The number of bits of the code generated by the algorithm of the present invention changes more slowly than that of the BPSO algorithm, but it is not much different from the AP-BPSO algorithm.

[0119] Fig. 9 The algorithm of the present invention generates a binary code bit change curve in the 6-bit Uc-ReDAC model. and When the binary code bit number generated by the BPSO algorithm reaches the maximum bit number of 100, and does not meet the accuracy requirement, as the resolution of the Uc-ReDAC model increases, the BPSO algorithm is unable to find the voltage close to V dd It is easier to fall into the global optimum when searching for When the target voltage is , the change of the binary code bit generated by the BPSO algorithm is larger than that of the other two algorithms. Compared with the AP-BPSO algorithm, the change of the binary code bit of the algorithm of the present invention is smaller and more obvious. The algorithm of the present invention not only meets the requirements in terms of accuracy, but also has obvious advantages in the number of binary code bits generated, the degree of change of the bit number, and the algorithm search time.

[0120] Fig.10 Extracted in 8-bit Uc-ReDAC model for three algorithms to The curve of the change of binary code bits under voltage. As the voltage to be searched increases, the 8-bit Uc-ReDAC model under the BPSO algorithm is searching for The binary code generated by the AP-BPSO algorithm has reached the maximum number of bits of 100 and does not meet the accuracy requirement. and When the maximum number of bits specified is 100, as the voltage to be searched increases and the model resolution improves, the number of bits of the binary code corresponding to the voltage to be searched will become larger and larger.

[0121] All target voltages searched in the 8-bit Uc-ReDAC model by the algorithm of the present invention do not exceed the specified maximum number of bits and meet the accuracy requirements. The algorithm of the present invention has obvious advantages over the other two algorithms in terms of the number of coding bits and the amplitude of the change in the number of coding bits. The present invention adds the influence of dimensional changes on the search direction of the gold digger, especially when the binary code corresponding to the voltage to be searched under the model is long, the dimensional influence factor will further strengthen the influence on the binary position of the gold digger, making the generated binary code as short as possible, and effectively improving the efficiency and running speed of the algorithm.

[0122] Fig.11 This is a static parameter comparison of the algorithm proposed in the present invention and the AP-BPSO algorithm under 4-bit Uc-ReDAC, 6-bit Uc-ReDAC and 8-bit Uc-ReDAC models. Fig.11 (a) and (b) are the integral nonlinearity (INL) and differential nonlinearity (DNL) of the two algorithms under the 4-bit Uc-ReDAC model; (c) and (d) are the comparison of INL and DNL of the two algorithms under the 6-bit Uc-ReDAC model; (e) and (f) are the comparison of INL and DNL of the two algorithms under the 8-bit Uc-ReDAC model. In (e) and (f), when the search voltage is close to V ddWhen , the static parameters of the 11-bit Uc-ReDAC model under the algorithm of the present invention are obviously better than those of the AP-BPSO algorithm.

[0123] The binary coded static parameters generated by the algorithm of the present invention and the AP-BPSO algorithm under the 4-bit Uc-ReDAC model, the 6-bit Uc-ReDAC model and the 8-bit Uc-ReDAC model are shown in Table 2. Under the 4-bit Uc-ReDAC model, the rms (DNL) of the algorithm of the present invention under the 4-bit Uc-ReDAC model is 0.355, which is slightly better than the AP-BPSO algorithm. The reason is that the model resolution is low and the two algorithms have limited searchable voltages. Under the 6-bit Uc-ReDAC model, the static parameters of the algorithm of the present invention are better than those of the AP-BPSO algorithm. In the 8-bit Uc-ReDAC model with higher resolution, the max (DNL) of the model under the algorithm of the present invention is reduced by 57.56%, the rms (DNL) is reduced by 18.87%, the max (INL) is reduced by 84.63%, and the rms (INL) is reduced by 39.26% compared with the AP-BPSO algorithm. The algorithm of the present invention adopts a variable slope convergence factor based on the time constant of the RC circuit during the optimization process. In the early stage of iteration, the convergence factor decreases rapidly, which is beneficial for the gold digger to perform global search. In the later stage of iteration, the convergence factor decreases slowly, which is beneficial for the gold digger to perform local search, thereby improving the search accuracy of the algorithm of the present invention, especially in the Uc-ReDAC model with higher resolution. Higher resolution means that more iterations are required when searching for a certain voltage, and the search accuracy of the algorithm of the present invention will be higher.

[0124] Table 2

[0125]

Claims

1. A digital-to-analog conversion method based on improved binary gold panning algorithm optimization, characterized in that: The steps include: S1: Set the initial parameters of the Uc-ReDAC model and algorithm; S2: Adopt and design a binary method of gold panning optimization algorithm and use it in the Uc-ReDAC model to calculate the binary code corresponding to the target voltage; S3: Adopt the dimension expansion strategy based on dimension factor to expand the gold digger position matrix, and use the dimension factor to enhance the influence of the current dimension on the binary position of the gold digger; S4: Design a variable slope convergence factor based on the RC circuit time constant in the Uc-ReDAC model, and use this factor to constrain the gold digger's moving step size; S5: A dynamic update strategy for the gold digger position matrix is ​​adopted, and a circular mapping random number generation method is used to expand the gold digger decimal position matrix, and finally a binary code that meets the accuracy requirements is output.

2. The digital-to-analog conversion method based on improved binary gold panning algorithm optimization according to claim 1, characterized in that: The initial parameters in step S1 include Uc-ReDAC resolution n, minimum allowable error The number of gold diggers N, the maximum number of iterations M, and the upper and lower limits ub and lb of the gold digger search space.

3. The digital-to-analog conversion method based on improved binary gold panning algorithm optimization according to claim 1, characterized in that: The Uc-ReDAC model in step S2 is: Among them, V C,n Represents the voltage across the capacitor at time nT, V C,0 Represents the initial voltage of the capacitor, V DD represents the power supply voltage of the RC circuit, T represents the system clock period, τ=RC represents the time constant, n represents the length of the binary sequence, b k represents the kth item of the binary sequence.

4. The digital-to-analog conversion method based on improved binary gold panning algorithm optimization according to claim 3 is characterized in that: The binary method of the gold panning optimization algorithm in step S2 and the method used in the Uc-ReDAC model are: Binarize the gold rush optimization algorithm. In the gold rush optimization algorithm, the gold diggers go through three steps: migration, collaboration, and gold rush, and finally determine the location of the gold mine. Unify the gold diggers' position updates into x i+1 (t+1)=x i (t)+ε (2) Among them, x i+1 、x i are the new and previous positions of the gold digger, respectively. ε is the step length of migration, collaboration, and gold digging. The position update is related to ε. The step length ε of the gold digger is mapped to [0,1], and the sigmoid function is After mapping, update the gold digger's position to If s(ε) is greater than the random number r, then x id The value of x is 1; otherwise, id The value of is 0, thus completing the gold digger's position update.

5. The digital-to-analog conversion method based on improved binary gold panning algorithm optimization according to claim 3 is characterized in that: The dimension expansion strategy in step S3 includes: each row in the matrix represents the solution found by the algorithm, and only the solution that meets the accuracy requirement can be output, otherwise the matrix will continue to expand to a higher dimension; Minimum allowable error of Uc-ReDAC model Determined by the model resolution, Where N is the resolution of Uc-ReDAC; P gd The optimal value found for the gold digger; V C,n is the voltage to be searched; is the minimum allowable error; In formula (1), let V C,0 = 0, which is simplified to make Rewrite equation (6) as Among them, if b1=0, b1 is an invalid start bit, and the binary code valid start bit is b2; if b1=b2=0, b1 and b2 are invalid start bits, and the binary code valid start bit is b3.

6. The digital-to-analog conversion method based on improved binary gold panning algorithm optimization according to claim 5, characterized in that: In the dimension expansion strategy of step S3, the dimension expansion of the binary position matrix will be stopped only when there is a solution that meets the accuracy requirements in the binary position matrix of the gold digger; considering that the dimension change of the matrix can affect the current binary position of the gold digger, the dimension influence factor affecting the binary position of the gold digger is designed, and its calculation formula is: Among them, V DD Indicates the power supply voltage of the RC circuit; D max V is the resolution of the model DD The shortest length of the corresponding binary code; V C,n is the voltage to be searched; d is the current binary coding dimension; At this time, the mapping formula of the gold digger's step length ε is Among them, ε is the step length of the gold digger.

7. The digital-to-analog conversion method based on improved binary gold panning algorithm optimization according to claim 6, characterized in that: The variable slope convergence factor l in step S4 is based on the RC circuit time constant in the Uc-ReDAC model. * for Among them, α is the initial value of the factor change; β is the convergence coefficient; iter is the current iteration number of the algorithm, and T is the maximum iteration number.

8. The digital-to-analog conversion method based on improved binary gold panning algorithm optimization according to claim 1, characterized in that: In step S5, when the decimal position matrix is ​​expanded in dimension, a random factor generated based on a circular mapping method is designed, and the calculation formula is: Among them, rand(j+1) is the currently generated random factor; α is the nonlinear degree factor; β is the driving factor.

9. The digital-to-analog conversion method based on improved binary gold panning algorithm optimization according to claim 8, characterized in that: In step S5, a random number generation method is adopted in which the range of random number generation for circular mapping decreases nonlinearly as the number of iterations increases; the gold digger decimal position update formula is: Among them, x id is the value of the ith gold digger in the dth dimension; iter is the number of iterations; rate is the shrinkage coefficient.

Images