Circuit grouping analysis method, system, terminal and medium based on graphic processing

Abstract

The present invention discloses a circuit grouping analysis method, system, terminal and medium based on graphic processing, which relates to the field of electronic design technology. The key points of the technical solution are: after parsing the PDF file, split it to obtain multiple circuit pictures, and perform binarization processing on the circuit picture to obtain a circuit image; use a recursive algorithm to seed fill the circuit image to obtain multiple circuit structures assigned different color labels, and each circuit structure is assigned a unique color label; obtain the center coordinates of each device schematic symbol from the design data, and map the center coordinates into pixels in the circuit image, and divide the two devices into the same device group when the color labels of the pixels corresponding to the two devices are the same; merge multiple device groups according to electrical rules to obtain functional groups; use multimodal large model technology to classify functional groups and device groups to obtain classification results. The present invention significantly improves the efficiency and accuracy of circuit grouping.

Description

Technical Field

[0001] The present invention relates to the field of electronic design technology, and more specifically, to a circuit grouping analysis method, system, terminal and medium based on graphic processing. Background Art

[0002] In large circuit diagrams, which usually contain a large number of components and connecting lines, it is very difficult to read and understand the entire circuit diagram directly. By grouping the circuit diagram, the complex circuit can be broken down into multiple relatively simple sub-circuits, each with a specific function or module, making the circuit diagram clearer and easier to understand.

[0003] Existing circuit grouping methods rely on manual operations, and there are mainly two forms: (1) Grouping based on hardware engineer attribute annotations: Hardware engineers add specific attributes to devices during the schematic drawing stage; then, layout tools automatically identify groups based on these attributes in the schematic; although this method uses the automatic identification function of the tool, the process of adding attributes by hardware engineers in the early stage still requires manual input. (2) Layout engineers manually identify groups: Layout engineers use schematics as a basis, rely on personal experience to manually judge and divide modules into groups; this method is too subjective, and the grouping results depend to a large extent on the engineer's experience level; in addition, inexperienced engineers may cause chaotic grouping and find it difficult to effectively analyze module functions, affecting the overall layout efficiency and quality.

[0004] Therefore, how to study and design a circuit grouping analysis method, system, terminal and medium based on graphics processing that can overcome the above-mentioned defects is a problem that we urgently need to solve. Summary of the invention

[0005] In order to address the deficiencies in the prior art, the purpose of the present invention is to provide a circuit grouping analysis method, system, terminal and medium based on graphics processing, which introduces a new set of graphics processing mechanisms and cutting-edge multimodal large model technology, and uses a recursive algorithm to fill adjacent areas until a boundary or an area that has been filled is encountered. It has the advantages of adapting to complex shapes and low space requirements. At the same time, in order to solve the problem that the device group grouping results are too small and circuits of the same module cannot be grouped together, multiple device groups are functionally merged according to electrical rules, which significantly improves the efficiency and accuracy of circuit grouping.

[0006] The above technical objectives of the present invention are achieved through the following technical solutions:

[0007] In a first aspect, a circuit grouping analysis method based on graphic processing is provided, comprising the following steps:

[0008] After parsing the PDF file, split it into multiple circuit pictures, and perform binary processing on the circuit pictures to obtain circuit images;

[0009] A recursive algorithm is used to seed fill the circuit image to obtain multiple circuit structures assigned different color labels, and each circuit structure is assigned a unique color label;

[0010] Obtaining the center coordinates of the schematic symbols corresponding to each device from the design data, and mapping the center coordinates into pixel points in the circuit image, and classifying the two devices into the same device group when the color labels of the pixel points corresponding to the two devices are the same;

[0011] Functionally merging the plurality of device groups according to electrical rules to obtain at least one functional group;

[0012] The multimodal large model technology is used to classify the functional groups and device groups to obtain the classification results.

[0013] Furthermore, the method further comprises:

[0014] Before performing seed filling on the circuit image, the circuit image is puffed.

[0015] Furthermore, the method further comprises:

[0016] A rectangular box is calculated based on the schematic symbol, and the rectangular box is filled when the seed is filled.

[0017] Furthermore, the process of functionally merging multiple device groups according to electrical rules is as follows:

[0018] Identify core components, and divide all component groups into a component group A that does not contain core components and a component group B that contains core components;

[0019] If device group A is connected to only one device group B, device group A and device group B are merged according to the connection relationship;

[0020] If device group A is connected to multiple device groups B, device group A is kept independent;

[0021] If device group A has no connection relationship with any device group B, device group A is kept independent.

[0022] Furthermore, the process of functionally merging multiple device groups according to electrical rules includes:

[0023] The functions of the device group A and the device group B are merged when they belong to the same circuit image.

[0024] Furthermore, the process of functionally merging multiple device groups according to electrical rules also includes:

[0025] When the device group A and the device group B belong to two different circuit images, their functions are merged.

[0026] Furthermore, the core device is the device with the most pins in the device group and the number of pins exceeds 4.

[0027] In a second aspect, a circuit grouping analysis system based on graphic processing is provided, the method being used to implement the circuit grouping analysis method based on graphic processing as described in any one of the first aspects, comprising:

[0028] The image processing module is used to parse the PDF file and split it into multiple circuit images, and perform binary processing on the circuit images to obtain circuit images;

[0029] A space partitioning module is used to perform seed filling on the circuit image using a recursive algorithm to obtain a plurality of circuit structures assigned with different color labels, and each circuit structure is assigned with a unique color label;

[0030] A positioning grouping module is used to obtain the center coordinates of the schematic symbols corresponding to each device from the design data, map the center coordinates into pixel points in the circuit image, and classify two devices into the same device group when the color labels of the pixel points corresponding to the two devices are the same;

[0031] A function merging module, used for merging functions of multiple device groups according to electrical rules to obtain at least one function group;

[0032] The classification processing module is used to classify the functional groups and device groups using the multimodal large model technology to obtain classification results.

[0033] In a third aspect, a computer terminal is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the circuit grouping analysis method based on graphic processing as described in any one of the first aspects is implemented.

[0034] In a fourth aspect, a computer-readable medium is provided, on which a computer program is stored, and the computer program is executed by a processor to implement the circuit grouping analysis method based on graphic processing as described in any one of the first aspects.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. The circuit grouping analysis method based on graphics processing provided by the present invention introduces a new set of graphics processing mechanisms and cutting-edge multi-modal large model technology, and uses a recursive algorithm to fill adjacent areas until a boundary or an area that has been filled is encountered. It has the advantages of adapting to complex shapes and low space requirements. At the same time, in order to solve the problem that the device group grouping result is too small and the circuits of the same module cannot be grouped together, multiple device groups are functionally merged according to electrical rules, which significantly improves the efficiency and accuracy of circuit grouping.

[0037] 2. The present invention can not only compress the circuit image by expanding the circuit image, so that the time cost of recursive generation is greatly reduced, but also eliminate the defects of some parts of the circuit image that are not tightly connected, effectively improving the efficiency and accuracy of circuit grouping;

[0038] 3. The present invention takes into account that the schematic symbols of devices such as capacitors and switches are usually not connected, and are easily divided into two categories when using the connected domain algorithm. The present invention calculates a rectangular box based on the schematic symbol, fills the rectangular box, and uses this rectangular box instead of the schematic symbol, effectively avoiding the occurrence of incorrect grouping of devices such as capacitors and switches. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0040] Figure 1 This is a flow chart of Embodiment 1 of the present invention;

[0041] Figure 2 This is a system block diagram of Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0043] Embodiment 1: A circuit grouping analysis method based on graphic processing is provided, such as Figure 1 As shown, the following steps are included:

[0044] S1: After parsing the PDF file, split it into multiple circuit pictures, and perform binary processing on the circuit pictures to obtain circuit images;

[0045] S2: Using a recursive algorithm to seed fill the circuit image, a plurality of circuit structures assigned with different color labels are obtained, and each circuit structure is assigned with a unique color label;

[0046] S3: obtaining the center coordinates of the schematic symbols corresponding to each device from the design data, and mapping the center coordinates into pixel points in the circuit image, and classifying the two devices into the same device group when the color labels of the pixel points corresponding to the two devices are the same;

[0047] S4: functionally merging the plurality of device groups according to electrical rules to obtain at least one functional group;

[0048] S5: Use multimodal large model technology to classify functional groups and device groups to obtain classification results.

[0049] In step S1, generally, the electronic design file contains multiple pages and is generally saved as a PDF file. Therefore, the present invention needs to parse the PDF file and split each PDF page into a circuit picture.

[0050] The circuit diagram in the split circuit image has certain auxiliary colors for circuit design, so the present invention performs binarization processing on the circuit image to obtain a circuit image containing only black and white colors.

[0051] In addition, the present invention performs expansion processing on the circuit image before seed filling. By performing expansion processing on the circuit image, not only can the circuit image be compressed, so that the time cost of recursive generation is greatly reduced, but also the defects of some parts of the circuit image that are not tightly connected can be eliminated, effectively improving the efficiency and accuracy of circuit grouping.

[0052] In step S2, the seed filling algorithm described in the present invention is a kind of connected domain algorithm, which uses a recursive algorithm to fill adjacent areas until a boundary or an already filled area is encountered, and has the advantages of adapting to complex shapes and low space requirements. At the same time, since the circuit image has been compressed in the preprocessing process, the time cost of recursion is greatly reduced. The compressed circuit image is seed filled, and each connected circuit structure obtained will be assigned the same label, that is, filled with the same color during the visualization process.

[0053] The present invention takes into account that the schematic symbols of devices such as capacitors and switches are usually not connected, and are easily divided into two categories when using a connected domain algorithm. To address this problem, the present invention calculates a rectangular box based on the schematic symbol, fills the rectangular box, and uses the rectangular box to replace the schematic symbol.

[0054] In step S3, although the circuit structure of the above-mentioned circuit image is assigned a label, it is unclear which label the specific device is. Therefore, the present invention also needs to obtain the center coordinates of the schematic symbol corresponding to the device from the design data, and then map the coordinates into pixel points in the circuit image, and then obtain the color of the corresponding pixel point. If the colors are the same, it is considered to be the same device group.

[0055] In step S4, in order to solve the problem that the above grouping results are too small and the circuits of the same module cannot be grouped together, such as the decoupling capacitor is divided into a group alone, and is not close to the power pins of the chip. The present invention introduces a new concept: a functional group, which represents a functional module, such as a Bluetooth module, which is composed of one or more device groups. A device group refers to a set of devices divided according to a schematic diagram. When designing a PCB, because there are a large number of devices, they will be grouped according to the schematic diagram first. We define the grouped set as a device group. When designing a PCB, a device refers to various electronic components and assemblies installed on a circuit board to achieve specific electrical or electronic functions.

[0056] In this embodiment, the process of functionally merging multiple device groups according to electrical rules is as follows: identifying core devices, dividing all device groups into device group A that does not contain core devices and device group B that contains core devices; if device group A is connected to only one device group B, then merging device group A and device group B according to the connection relationship; if device group A is connected to multiple device groups B, then keeping device group A independent; if device group A has no connection with all device groups B, then keeping device group A independent.

[0057] It should be noted that the process of merging functions of multiple device groups according to electrical rules includes merging functions when device group A and device group B belong to the same circuit image.

[0058] In addition, the process of merging functions of multiple device groups according to electrical rules also includes merging functions when device group A and device group B belong to two different circuit images.

[0059] The above two functional combinations are not contradictory. For example, the same circuit image may be combined for the first time, and then two different circuit images may be combined for the second time based on the first combination.

[0060] The present invention divides the device group into two categories according to whether it contains core devices. The definition of core devices is the device with the most pins in the device group, and the pins exceed 4. If no device in the device group meets the above conditions, it is considered that the device group does not have a core device.

[0061] In step S5, the present invention privatizes and deploys an open source big model and makes it into an intelligent agent; then, a prompt word is input into the big model, and the big model outputs the result in a fixed json format, and the json format is parsed to obtain a classification result.

[0062] For example, the prompt is "Output the type of the current module in json format", and the input circuit diagram is output as follows:

[0063] {

[0064] "circuit_type": "Key Input Module",

[0065] "components": {

[0066] "buttons": ["KEY1", "KEY2", "KEY3", "KEY4"],

[0067] "resistors": ["R12", "R13", "R14", "R15"],

[0068] "test_points": ["TP42", "TP43", "TP44", "TP45"],

[0069] "switches_or_relays": ["S2", "S3", "S4", "S5", "S6"],

[0070] "capacitors": ["C22", "C23", "C24", "C25", "C26"],

[0071] "reset_signal": "RST_N"

[0072] }

[0073] }.

[0074] Embodiment 2: A circuit grouping analysis system based on graphic processing is provided, which is used to implement the circuit grouping analysis method based on graphic processing as described in Embodiment 1, such as Figure 2 As shown, it includes an image processing module, a space division module, a positioning grouping module, a function merging module and a classification processing module.

[0075] Among them, the image processing module is used to parse the PDF file and split it into multiple circuit images, and binarize the circuit images to obtain circuit images; the space division module is used to use a recursive algorithm to seed the circuit image to obtain multiple circuit structures assigned different color labels, and each circuit structure is assigned a unique color label; the positioning grouping module is used to obtain the center coordinates of the schematic symbols corresponding to each device from the design data, and map the center coordinates into pixels in the circuit image, and divide the two devices into the same device group when the color labels of the pixels corresponding to the two devices are the same; the function merging module is used to merge the functions of multiple device groups according to electrical rules to obtain at least one function group; the classification processing module is used to classify the function groups and device groups using multimodal large model technology to obtain classification results.

[0076] The present invention also describes a computer terminal, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the circuit grouping analysis method based on graphic processing as described in Example 1 is implemented.

[0077] The present invention also describes a computer-readable medium on which a computer program is stored. The computer program is executed by a processor to implement the circuit grouping analysis method based on graphic processing as described in Example 1.

[0078] Working principle: The present invention introduces a new set of graphics processing mechanisms and cutting-edge multimodal large model technology, and uses a recursive algorithm to fill adjacent areas until it encounters a boundary or an area that has been filled. It has the advantages of adapting to complex shapes and low space requirements. At the same time, in order to solve the problem that the device grouping result is too small and the circuits of the same module cannot be grouped together, multiple device groups are functionally merged according to electrical rules, which significantly improves the efficiency and accuracy of circuit grouping.

[0079] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0080] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0081] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0082] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0083] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A circuit grouping analysis method based on graphic processing, characterized in that: The following steps are involved: After parsing the PDF file, split it into multiple circuit pictures, and perform binary processing on the circuit pictures to obtain circuit images; A recursive algorithm is used to seed fill the circuit image to obtain multiple circuit structures assigned different color labels, and each circuit structure is assigned a unique color label; wherein a rectangular box is calculated according to the schematic diagram symbol, and the rectangular box is filled during seed filling; Obtaining the center coordinates of the schematic symbols corresponding to each device from the design data, and mapping the center coordinates into pixel points in the circuit image, and classifying the two devices into the same device group when the color labels of the pixel points corresponding to the two devices are the same; Functionally merging multiple device groups according to electrical rules to obtain at least one functional group; wherein the process of functionally merging multiple device groups according to electrical rules is: identifying core devices, dividing all device groups into device group A without core devices and device group B containing core devices; if device group A is connected to only one device group B, merging device group A and device group B according to the connection relationship; if device group A is connected to multiple device groups B, keeping device group A independent; if device group A is not connected to all device groups B, keeping device group A independent; the process of functionally merging multiple device groups according to electrical rules includes: functional merging when device group A and device group B belong to the same circuit image; The multimodal large model technology is used to classify the functional groups and device groups to obtain the classification results.

2. A circuit grouping analysis method based on graphic processing according to claim 1, characterized in that: The method further includes: Before performing seed filling on the circuit image, the circuit image is puffed.

3. The circuit grouping analysis method based on graphic processing according to claim 1, characterized in that: The process of functionally merging multiple device groups according to electrical rules also includes: When the device group A and the device group B belong to two different circuit images, their functions are merged.

4. The circuit grouping analysis method based on graphic processing according to claim 1, characterized in that: The core device is the device with the most pins in the device group and more than 4 pins.

5. A circuit grouping analysis system based on graphics processing, characterized in that: The system is used to implement a circuit grouping analysis method based on graphic processing as described in any one of claims 1 to 4, comprising: The image processing module is used to parse the PDF file and split it into multiple circuit images, and perform binary processing on the circuit images to obtain circuit images; The space partitioning module is used to perform seed filling on the circuit image using a recursive algorithm to obtain multiple circuit structures assigned with different color labels, and each circuit structure is assigned with a unique color label; wherein a rectangular frame is calculated according to the schematic diagram symbol, and the rectangular frame is filled during seed filling; A positioning grouping module is used to obtain the center coordinates of the schematic symbols corresponding to each device from the design data, map the center coordinates into pixel points in the circuit image, and classify two devices into the same device group when the color labels of the pixel points corresponding to the two devices are the same; A function merging module is used to perform function merging on multiple device groups according to electrical rules to obtain at least one function group; wherein, the process of performing function merging on multiple device groups according to electrical rules is: identifying core devices, and dividing all device groups into device group A without core devices and device group B containing core devices; if device group A is connected to only one device group B, then merging device group A and device group B according to the connection relationship; if device group A is connected to multiple device groups B, then keeping device group A independent; if device group A is not connected to all device groups B, then keeping device group A independent; the process of performing function merging on multiple device groups according to electrical rules includes: merging functions when device group A and device group B belong to the same circuit image; The classification processing module is used to classify the functional groups and device groups using the multimodal large model technology to obtain classification results.

6. A computer terminal comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the circuit grouping analysis method based on graphics processing as described in any one of claims 1 to 4 is implemented.

7. A computer readable medium having a computer program stored thereon, characterized in that: The computer program is executed by a processor to implement a circuit grouping analysis method based on graphic processing as described in any one of claims 1 to 4.

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