A method and device for discrete event simulation time synchronization mechanism

Abstract

The present invention discloses a method and device for a discrete event simulation time synchronization mechanism, the method comprising: obtaining a discrete event set and simulation time synchronization mechanism information of a logical process; performing time synchronization on the nodes corresponding to the logical process; processing the simulation time synchronization mechanism information and the discrete event set of the logical process to obtain target simulation time synchronization mechanism information; judging whether all the discrete event information in the discrete event set has been executed to obtain a first judgment result; when the first judgment result is no, determining that the target simulation time synchronization mechanism information is the simulation time synchronization mechanism information, and executing the steps before the judgment; when the first judgment result is yes, ending the process. It can be seen that the present application is conducive to dynamically switching the time synchronization mechanism in the process of logically executing discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation.

Description

Technical Field

[0001] The present invention relates to the field of simulation, and in particular to a method and device for a discrete event simulation time synchronization mechanism. Background Art

[0002] The simulation logic process is highly dynamic, and it is difficult to determine in advance the scope of the logic process using conservative time synchronization mechanism and optimistic time synchronization mechanism. Dynamically switching the time synchronization mechanism according to application characteristics during runtime can maximize the performance of the simulation system. Therefore, it is necessary to study the logic process time synchronization mechanism determination strategy and dynamic switching strategy to provide support for the performance optimization of large-scale distributed parallel discrete event simulation. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a method and device for a discrete event simulation time synchronization mechanism, which is conducive to dynamically switching the time synchronization mechanism during the logical execution of discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation.

[0004] In order to solve the above technical problems, a first aspect of an embodiment of the present invention discloses a method for a discrete event simulation time synchronization mechanism, the method comprising:

[0005] S1, obtaining a discrete event set of a logic process and simulation time synchronization mechanism information; the discrete event set includes a plurality of discrete event information;

[0006] S2, performing time synchronization on the nodes corresponding to the logical process;

[0007] S3, processing the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set to obtain target simulation time synchronization mechanism information;

[0008] S4, determining whether all discrete event information in the discrete event set has been executed, and obtaining a first determination result;

[0009] When the first judgment result is no, determining that the target simulation time synchronization mechanism information is the simulation time synchronization mechanism information, and executing S3;

[0010] When the first judgment result is yes, the process ends.

[0011] As an optional implementation manner, in the first aspect of the embodiment of the present invention, the time synchronization of the nodes corresponding to the logical process includes:

[0012] S21, using the master node to send message information to the node corresponding to the logical process to obtain a first timestamp and a second timestamp;

[0013] S22, using the node corresponding to the logical process to send message information to the master node to obtain a third timestamp and a fourth timestamp;

[0014] S23, using a time synchronization calculation model, calculating and processing the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp to obtain a time synchronization difference;

[0015] The time synchronization calculation model is:

[0016]

[0017] Wherein, TB is the time synchronization difference, T1, T2, T3 and T4 are the first timestamp, the second timestamp, the third timestamp and the fourth timestamp respectively, θ1 and θ2 are the first deviation parameter and the second deviation parameter.

[0018] S24: Synchronize the time of the node corresponding to the logical process using the time synchronization difference.

[0019] As an optional implementation manner, in the first aspect of the embodiment of the present invention, the processing of the simulation time synchronization mechanism information of the logical process and the discrete event information in the discrete event set to obtain target simulation time synchronization mechanism information includes:

[0020] S31, obtaining a first time value;

[0021] S32, the number of associated events and the number of overflow events are both preset to 0;

[0022] S33, processing the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set to obtain an overflow result value;

[0023] S34, increasing the associated event number by 1; making the sum of the overflow event number and the overflow result value the updated overflow event number, and determining the updated overflow event number as the overflow event number;

[0024] S35, obtaining a second time value;

[0025] S36, determining whether the difference between the second time value and the first time value is greater than a preset time synchronization threshold, and obtaining a second determination result;

[0026] When the second judgment result is yes, time synchronization is performed on the node corresponding to the logical process, and S37 is executed;

[0027] When the second judgment result is no, executing S37;

[0028] S37, determining whether the difference between the second time value and the first time value is greater than a preset event overflow time threshold, and obtaining a third determination result;

[0029] When the third judgment result is yes, execute S38;

[0030] When the third judgment result is no, executing S33;

[0031] S38, calculating and processing the number of associated events and the number of overflow events to obtain an overflow event value;

[0032] S39 , analyzing and processing the simulation time synchronization mechanism information, the overflow event value, the preset first overflow threshold, and the preset second overflow threshold to obtain target simulation time synchronization mechanism information.

[0033] As an optional implementation manner, in the first aspect of the embodiment of the present invention, the processing of the simulation time synchronization mechanism information of the logical process and the discrete event information in the discrete event set to obtain an overflow result value includes:

[0034] S331, traverse the discrete event information in the discrete event set to obtain discrete event information to be processed; the discrete event information to be processed is the discrete event information with the smallest timestamp in the discrete event set;

[0035] S332, triggering the logic process to execute the discrete event information to be processed according to the simulation time synchronization mechanism information, and obtaining execution result information;

[0036] S333, determining whether the execution result information is consistent with the preset initiator information, and obtaining a fourth determination result;

[0037] When the fourth judgment result is yes, determining the overflow result value to be 0;

[0038] When the fourth judgment result is no, the overflow result value is determined to be 1.

[0039] As an optional implementation manner, in the first aspect of the embodiment of the present invention, the analyzing and processing of the simulation time synchronization mechanism information, the overflow event value, the preset first overflow threshold, and the preset second overflow threshold to obtain the target simulation time synchronization mechanism information includes:

[0040] S391, determining whether the overflow event value is less than the first overflow threshold, and obtaining a fifth determination result;

[0041] When the fifth judgment result is yes, determining the first simulation time synchronization mechanism information as the target simulation time synchronization mechanism information;

[0042] When the fifth judgment result is no, determining whether the overflow event value is greater than the second overflow threshold value to obtain a sixth judgment result;

[0043] When the sixth judgment result is yes, determining the second simulation time synchronization mechanism information as the target simulation time synchronization mechanism information;

[0044] When the sixth judgment result is no, executing S392;

[0045] S392, analyze and process the simulation time synchronization mechanism information, the overflow event value, the first simulation time synchronization mechanism information, the second simulation time synchronization mechanism information, the first overflow threshold and the second overflow threshold to obtain the target simulation time synchronization mechanism information.

[0046] As an optional implementation manner, in the first aspect of the embodiment of the present invention, the simulation time synchronization mechanism information, the overflow event value, the first simulation time synchronization mechanism information, the second simulation time synchronization mechanism information, the first overflow threshold and the second overflow threshold are analyzed and processed to obtain the target simulation time synchronization mechanism information, including:

[0047] S3921: Calculate the overflow event value, the first overflow threshold, and the second overflow threshold using an event overflow probability calculation model to obtain a first probability value and a second probability value.

[0048] The event overflow probability calculation model is:

[0049]

[0050] Wherein, P1 and P2 are the first probability value and the second probability value, YC is the overflow event value, DE and DY are the first overflow threshold and the second overflow threshold;

[0051] S3922: Analyze and process the simulation time synchronization mechanism information, the first simulation time synchronization mechanism information, the second simulation time synchronization mechanism information, the first probability value, and the second probability value to obtain the target simulation time synchronization mechanism information.

[0052] As an optional implementation manner, in the first aspect of the embodiment of the present invention, the analyzing and processing the simulation time synchronization mechanism information, the first simulation time synchronization mechanism information, the second simulation time synchronization mechanism information, the first probability value, and the second probability value to obtain the target simulation time synchronization mechanism information includes:

[0053] Determine whether the simulation time synchronization mechanism information is completely consistent with the first simulation time synchronization mechanism information, to obtain a seventh determination result;

[0054] When the seventh judgment result is yes, determining whether the first probability value is less than a preset first probability threshold, to obtain an eighth judgment result;

[0055] When the eighth judgment result is no, determining that the second simulation time synchronization mechanism information is the target simulation time synchronization mechanism information;

[0056] When the eighth judgment result is yes, determining the first simulation time synchronization mechanism information as the target simulation time synchronization mechanism information;

[0057] When the seventh judgment result is no, determining whether the second probability value is less than a preset second probability threshold; obtaining a ninth judgment result;

[0058] When the ninth judgment result is no, determining that the first simulation time synchronization mechanism information is the target simulation time synchronization mechanism information;

[0059] When the ninth judgment result is yes, the second simulation time synchronization mechanism information is determined to be the target simulation time synchronization mechanism information.

[0060] A second aspect of an embodiment of the present invention discloses a device for a discrete event simulation time synchronization mechanism, the device comprising:

[0061] An acquisition module is used to acquire a discrete event set of a logic process and simulation time synchronization mechanism information; the discrete event set includes a plurality of discrete event information;

[0062] A time synchronization module, used to synchronize the time of the nodes corresponding to the logical process;

[0063] a simulation time synchronization mechanism calculation module, configured to process the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set to obtain target simulation time synchronization mechanism information;

[0064] a discrete event determination module, configured to determine whether all discrete event information in the discrete event set has been executed, and obtain a first determination result;

[0065] When the first judgment result is no, determining that the target simulation time synchronization mechanism information is the simulation time synchronization mechanism information, and executing the simulation time synchronization mechanism calculation module;

[0066] When the first judgment result is yes, the process ends.

[0067] A third aspect of an embodiment of the present invention discloses a device for a discrete event simulation time synchronization mechanism, the device comprising:

[0068] processor;

[0069] a memory coupled to the processor and storing executable program code;

[0070] The processor calls the executable program code stored in the memory to execute part or all of the steps of the method for discrete event simulation time synchronization mechanism disclosed in the first aspect of the embodiment of the present invention.

[0071] The fourth aspect of an embodiment of the present invention discloses a computer-readable storage medium, which stores computer instructions. When the computer instructions are called, they are used to execute part or all of the steps of the method of discrete event simulation time synchronization mechanism disclosed in the first aspect of the embodiment of the present invention.

[0072] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0073] In an embodiment of the present invention, a discrete event set and simulation time synchronization mechanism information of a logic process are obtained; the discrete event set includes a plurality of discrete event information; time synchronization is performed on the nodes corresponding to the logic process; the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set are processed to obtain target simulation time synchronization mechanism information; it is determined whether all the discrete event information in the discrete event set has been executed to obtain a first judgment result; when the first judgment result is no, the target simulation time synchronization mechanism information is determined to be the simulation time synchronization mechanism information, and the steps before the judgment are executed; when the first judgment result is yes, the process is terminated. It can be seen that the present application is conducive to dynamically switching the time synchronization mechanism in the process of logically executing discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0075] Figure 1 A flowchart of a method for a discrete event simulation time synchronization mechanism disclosed in an embodiment of the present invention;

[0076] Figure 2 A schematic structural diagram of a device for a discrete event simulation time synchronization mechanism disclosed in an embodiment of the present invention;

[0077] Figure 3 This is a schematic structural diagram of another discrete event simulation time synchronization mechanism device disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0078] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0079] The terms "first," "second," and so on, in the description and claims of the present invention and the accompanying drawings are used to distinguish between different objects, not to describe a specific order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product, or device comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or device.

[0080] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0081] The present invention discloses a method and apparatus for a discrete event simulation time synchronization mechanism, which facilitates dynamic switching of the time synchronization mechanism during the logical execution of discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation. A detailed description is provided below.

[0082] Example 1

[0083] See also Figure 1 , Figure 1 This is a flow chart of a method for a discrete event simulation time synchronization mechanism disclosed in an embodiment of the present invention. Figure 1 The described method of discrete event simulation time synchronization mechanism is applied to a device of discrete event simulation time synchronization mechanism, such as a local server or cloud server for optimizing management of discrete event simulation time synchronization mechanism, and the embodiment of the present invention does not limit it. Figure 1 As shown, the discrete event simulation time synchronization mechanism method may include the following operations:

[0084] S1, obtaining a discrete event set of a logic process and simulation time synchronization mechanism information; the discrete event set includes a plurality of discrete event information;

[0085] It should be noted that the logical process runs on a node, which can be an independent server or a server network or server cluster composed of servers, including but not limited to a computer, a network host, a single network server, a set of multiple network servers, or a cloud server composed of multiple servers. Among them, a cloud server is composed of a large number of computers or network servers based on cloud computing.

[0086] It should be noted that, in this embodiment, there are multiple logical processes, one logical process runs on each node, each logical process includes a discrete event set and a simulation time synchronization mechanism information, and multiple logical processes coordinate together to complete the execution of parallel discrete events and exchange messages when necessary.

[0087] It should be noted that each logical process is performed according to all the steps in this embodiment to complete the overall discrete event task.

[0088] It should be noted that the simulation time synchronization mechanism information is the time mechanism used by the logic process during advancement. When the task starts, the simulation time synchronization mechanism information is set to the conservative time synchronization mechanism by default.

[0089] S2, performing time synchronization on the nodes corresponding to the logical process;

[0090] It should be noted that the above-mentioned time synchronization of the nodes corresponding to the logical process is to synchronize the operating system time on the node where the logical process runs. Specifically, tools such as NTP and Chrony can be used for synchronization, which is not limited in the embodiment of the present invention.

[0091] S3, processing the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set to obtain target simulation time synchronization mechanism information;

[0092] S4, determining whether all discrete event information in the discrete event set has been executed, and obtaining a first determination result;

[0093] When the first judgment result is no, determining that the target simulation time synchronization mechanism information is the simulation time synchronization mechanism information, and executing S3;

[0094] When the first judgment result is yes, the process ends.

[0095] It can be seen that the method of implementing the discrete event simulation time synchronization mechanism described in the embodiment of the present invention is conducive to dynamically switching the time synchronization mechanism during the process of logically executing discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation.

[0096] In an optional embodiment, the performing time synchronization on the nodes corresponding to the logical process includes:

[0097] S21, using the master node to send message information to the node corresponding to the logical process to obtain a first timestamp and a second timestamp;

[0098] It should be noted that the master node is a node set by the user and is used to synchronize the time of nodes corresponding to all logical processes. The present invention does not limit the specific setting method.

[0099] It should be noted that the first timestamp is the time on the master node when the master node sends the message information; the second timestamp is the time when the node corresponding to the logical process receives the message information sent by the master node.

[0100] S22, using the node corresponding to the logical process to send message information to the master node to obtain a third timestamp and a fourth timestamp;

[0101] It should be noted that the third timestamp is the time when the node corresponding to the logical process sends the message information; the fourth timestamp is the time on the master node when the master node receives the message information sent by the node corresponding to the logical process.

[0102] It should be noted that the message information in the above S21 and S22 are all UDP message information, and the message information includes the timestamp information of the sender when the sender sends the message information.

[0103] S23, using a time synchronization calculation model, calculating and processing the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp to obtain a time synchronization difference;

[0104] The time synchronization calculation model is:

[0105]

[0106] Wherein, TB is the time synchronization difference, T1, T2, T3 and T4 are the first timestamp, the second timestamp, the third timestamp and the fourth timestamp respectively, θ1 and θ2 are the first deviation parameter and the second deviation parameter.

[0107] It should be noted that the first deviation parameter and the second deviation parameter may be set by a user or obtained in other ways, and the embodiment of the present invention does not specifically limit them.

[0108] It should be noted that the average of the two time differences, T2-T1 and T3-T4, eliminates the error caused by the delay of a single timestamp. This symmetrical design improves the robustness of time synchronization. The introduction of the first and second offset parameters corrects for unavoidable systematic deviations in system hardware, transmission paths, or other factors, further improving synchronization accuracy.

[0109] Optionally, the value range of the first deviation parameter is [0.9, 1.1]. Such a range can cover common system hardware deviations and network fluctuations without causing error accumulation due to a large range. In addition, it can prevent excessive parameter deviation in abnormal situations and achieve a good balance between deviation correction and synchronization accuracy.

[0110] Optionally, the range of the second deviation parameter is [-5ms, 5ms], which is used to compensate for asymmetric deviation or static delay in the system and improve synchronization accuracy.

[0111] S24: Synchronize the time of the node corresponding to the logical process using the time synchronization difference.

[0112] It should be noted that the above time synchronization is performed by adding the current operating system time of the node corresponding to the logical process to the obtained time synchronization difference to obtain the updated current operating system time of the node corresponding to the logical process.

[0113] It can be seen that the method of implementing the discrete event simulation time synchronization mechanism described in the embodiment of the present invention is conducive to dynamically switching the time synchronization mechanism during the process of logically executing discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation.

[0114] In another optional embodiment, the processing of the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set to obtain target simulation time synchronization mechanism information includes:

[0115] S31, obtaining a first time value;

[0116] It should be noted that the first time value is the current operating system time of the node corresponding to the logical process.

[0117] S32, the number of associated events and the number of overflow events are both preset to 0;

[0118] S33, processing the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set to obtain an overflow result value;

[0119] S34, increasing the associated event number by 1; making the sum of the overflow event number and the overflow result value the updated overflow event number, and determining the updated overflow event number as the overflow event number;

[0120] S35, obtaining a second time value;

[0121] It should be noted that the second time value is the current operating system time of the node corresponding to the logical process.

[0122] S36, determining whether the difference between the second time value and the first time value is greater than a preset time synchronization threshold, and obtaining a second determination result;

[0123] It should be noted that the preset time synchronization threshold may be set by a user or obtained based on historical data, which is not limited in the embodiment of the present invention.

[0124] Exemplarily, the preset time synchronization threshold has a value range of [1, 10], in milliseconds.

[0125] When the second judgment result is yes, time synchronization is performed on the node corresponding to the logical process, and S37 is executed;

[0126] When the second judgment result is no, executing S37;

[0127] It should be noted that the above-mentioned time synchronization of the nodes corresponding to the logical process is consistent with the method in S2.

[0128] S37, determining whether the difference between the second time value and the first time value is greater than a preset event overflow time threshold, and obtaining a third determination result;

[0129] When the third judgment result is yes, execute S38;

[0130] When the third judgment result is no, executing S33;

[0131] S38, calculating and processing the number of associated events and the number of overflow events to obtain an overflow event value;

[0132] S39 , analyzing and processing the simulation time synchronization mechanism information, the overflow event value, the preset first overflow threshold, and the preset second overflow threshold to obtain target simulation time synchronization mechanism information.

[0133] It should be noted that the event overflow time threshold, the preset first overflow threshold, and the preset second overflow threshold may be set by the user or obtained based on historical data, and the embodiment of the present invention does not limit this.

[0134] Exemplarily, the value range of the event overflow time threshold is [1, 1000], in milliseconds, and the value ranges of the preset first overflow threshold and the preset second overflow threshold are [0.2, 0.5] and [0.5, 0.9] respectively.

[0135] It can be seen that the method of implementing the discrete event simulation time synchronization mechanism described in the embodiment of the present invention is conducive to dynamically switching the time synchronization mechanism during the process of logically executing discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation.

[0136] In yet another optional embodiment, the processing the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set to obtain an overflow result value includes:

[0137] S331, traverse the discrete event information in the discrete event set to obtain discrete event information to be processed; the discrete event information to be processed is the discrete event information with the smallest timestamp in the discrete event set;

[0138] It should be noted that each discrete event information in the discrete event set corresponds to a timestamp, and the timestamp indicates when the discrete event information is executed.

[0139] S332, triggering the logic process to execute the discrete event information to be processed according to the simulation time synchronization mechanism information, and obtaining execution result information;

[0140] It should be noted that the above-mentioned triggering operation can be triggered by the discrete event information previously executed in the said logical process, or it can be triggered when other logical processes in the entire discrete event task execute the discrete event information. The specific execution logic of the discrete event task is determined by the execution logic of the discrete event task, and the embodiment of the present invention does not make any specific limitations.

[0141] It should be noted that, when the execution of the discrete event information to be processed is triggered by the discrete event information previously executed in the logical process, it indicates that the initiator of the execution of the discrete event information to be processed is the logical process; when the execution of the discrete event information to be processed is triggered by the execution of discrete event information by other logical processes in the entire discrete event task, it indicates that the initiator of the execution of the discrete event information to be processed is other logical processes. At this time, information interaction occurs between the logical process corresponding to the discrete event information to be processed and the other logical processes.

[0142] It should be noted that the above logic process is executed according to the simulation time synchronization mechanism information when executing the discrete event information to be processed. In this embodiment, the simulation time synchronization mechanism information includes two types, conservative time synchronization mechanism and optimistic time synchronization mechanism.

[0143] It should be noted that the execution result information is the initiator information in the discrete event information to be processed obtained when the logic process executes the discrete event information to be processed. The specific acquisition method is not specifically limited in the embodiment of the present invention.

[0144] S333, determining whether the execution result information is consistent with the preset initiator information, and obtaining a fourth determination result;

[0145] It should be noted that the above-mentioned preset initiator information is the information of the logical process corresponding to the discrete event information to be processed. When the execution result information is consistent with the preset initiator information, it indicates that the execution of the discrete event information to be processed is initiated by the logical process corresponding to the discrete event information to be processed; when the execution result information is inconsistent with the preset initiator information, it indicates that the execution of the discrete event information to be processed is initiated by other logical processes.

[0146] When the fourth judgment result is yes, determining the overflow result value to be 0;

[0147] When the fourth judgment result is no, the overflow result value is determined to be 1.

[0148] It can be seen that the method of implementing the discrete event simulation time synchronization mechanism described in the embodiment of the present invention is conducive to dynamically switching the time synchronization mechanism during the process of logically executing discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation.

[0149] In an optional embodiment, the analyzing and processing the simulation time synchronization mechanism information, the overflow event value, the preset first overflow threshold, and the preset second overflow threshold to obtain target simulation time synchronization mechanism information includes:

[0150] S391, determining whether the overflow event value is less than the first overflow threshold, and obtaining a fifth determination result;

[0151] When the fifth judgment result is yes, determining the first simulation time synchronization mechanism information as the target simulation time synchronization mechanism information;

[0152] It should be noted that the first simulation time synchronization mechanism information is a conservative time synchronization mechanism.

[0153] When the fifth judgment result is no, determining whether the overflow event value is greater than the second overflow threshold value to obtain a sixth judgment result;

[0154] When the sixth judgment result is yes, determining the second simulation time synchronization mechanism information as the target simulation time synchronization mechanism information;

[0155] It should be noted that the second simulation time synchronization mechanism information is an optimistic time synchronization mechanism. When the sixth judgment result is no, execute S392;

[0156] It should be noted that, when the sixth judgment result is no, the following steps may be further performed to obtain the target simulation time synchronization mechanism information;

[0157] Step 1: determining whether the simulation time synchronization mechanism information is completely consistent with the first simulation time synchronization mechanism information, and obtaining a tenth determination result;

[0158] When the tenth judgment result is yes, using the first confidence calculation model, the overflow event value, the first overflow threshold, the second overflow threshold, the first confidence value and the second confidence value are calculated to obtain a third confidence value and a fourth confidence value;

[0159] The first confidence calculation model is:

[0160]

[0161] Wherein, C3 and C4 are the third confidence value and the fourth confidence value, C1 and C2 are the first confidence value and the second confidence value, YC is the overflow event value, DE and DY are the first overflow threshold and the second overflow threshold, α1 is the preset confidence update step size, and μ1 is the time synchronization mechanism influence weight;

[0162] It should be noted that the first confidence value, the second confidence value, and the time synchronization mechanism influence weight may be set by the user or obtained through other means, and the embodiment of the present invention does not specifically limit this.

[0163] It should be noted that the first confidence value and the second confidence value are set before the first use and will not be reset after setting.

[0164] Exemplarily, the initial values ​​of the first confidence value and the second confidence value are both 0.5.

[0165] It should be noted that the preset confidence update step size has a value range of [0.01, 0.02]. Optionally, the preset confidence update step size is 0.01, 0.02.

[0166] It should be noted that as overflow events occur and change in the system, the confidence value can be adjusted in real time to reflect the actual state of the current system.

[0167] It should be noted that when the simulation time synchronization mechanism information is completely consistent with the first simulation time synchronization mechanism information, the third confidence value is preferentially adjusted through the time synchronization mechanism influence weight to reduce the impact of time synchronization error on global consistency and enhance the consistency and stability of time synchronization.

[0168] When the tenth judgment result is no, using a second confidence calculation model, calculating the overflow event value, the first overflow threshold, the second overflow threshold, the first confidence value, and the second confidence value to obtain the third confidence value and the fourth confidence value;

[0169] The second confidence calculation model is:

[0170]

[0171] It should be noted that when the simulation time synchronization mechanism information is inconsistent with the first simulation time synchronization mechanism information, the fourth confidence value is preferentially adjusted through the time synchronization mechanism influence weight to improve the response speed and processing priority to dynamic overflow events, and prevent abnormal events from excessively interfering with system performance or priority allocation.

[0172] Step 2: Determine the third confidence value as the first confidence value; determine the fourth confidence value as the second confidence value;

[0173] Step 3: Determine whether the first confidence value is greater than the second confidence value, and obtain an eleventh determination result;

[0174] When the eleventh judgment result is yes, determining the first simulation time synchronization mechanism information as the target simulation time synchronization mechanism information;

[0175] When the eleventh judgment result is no, the second simulation time synchronization mechanism information is determined to be the target simulation time synchronization mechanism information.

[0176] S392, analyze and process the simulation time synchronization mechanism information, the overflow event value, the first simulation time synchronization mechanism information, the second simulation time synchronization mechanism information, the first overflow threshold and the second overflow threshold to obtain the target simulation time synchronization mechanism information.

[0177] It can be seen that the method of implementing the discrete event simulation time synchronization mechanism described in the embodiment of the present invention is conducive to dynamically switching the time synchronization mechanism during the process of logically executing discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation.

[0178] In an optional embodiment, the analyzing and processing of the simulation time synchronization mechanism information, the overflow event value, the first simulation time synchronization mechanism information, the second simulation time synchronization mechanism information, the first overflow threshold, and the second overflow threshold to obtain the target simulation time synchronization mechanism information includes:

[0179] S3921: Calculate the overflow event value, the first overflow threshold, and the second overflow threshold using an event overflow probability calculation model to obtain a first probability value and a second probability value.

[0180] The event overflow probability calculation model is:

[0181]

[0182] Wherein, P1 and P2 are the first probability value and the second probability value, YC is the overflow event value, DE and DY are the first overflow threshold and the second overflow threshold;

[0183] S3922: Analyze and process the simulation time synchronization mechanism information, the first simulation time synchronization mechanism information, the second simulation time synchronization mechanism information, the first probability value, and the second probability value to obtain the target simulation time synchronization mechanism information.

[0184] It can be seen that the method of implementing the discrete event simulation time synchronization mechanism described in the embodiment of the present invention is conducive to dynamically switching the time synchronization mechanism during the process of logically executing discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation.

[0185] In an optional embodiment, the analyzing and processing the simulation time synchronization mechanism information, the first simulation time synchronization mechanism information, the second simulation time synchronization mechanism information, the first probability value, and the second probability value to obtain the target simulation time synchronization mechanism information includes:

[0186] Determine whether the simulation time synchronization mechanism information is completely consistent with the first simulation time synchronization mechanism information, to obtain a seventh determination result;

[0187] When the seventh judgment result is yes, determining whether the first probability value is less than a preset first probability threshold, to obtain an eighth judgment result;

[0188] When the eighth judgment result is no, determining that the second simulation time synchronization mechanism information is the target simulation time synchronization mechanism information;

[0189] When the eighth judgment result is yes, determining that the first simulation time synchronization mechanism information is the target simulation time synchronization mechanism information

[0190] When the seventh judgment result is no, determining whether the second probability value is less than a preset second probability threshold; obtaining a ninth judgment result;

[0191] When the ninth judgment result is no, determining that the first simulation time synchronization mechanism information is the target simulation time synchronization mechanism information

[0192] When the ninth judgment result is yes, the second simulation time synchronization mechanism information is determined to be the target simulation time synchronization mechanism information.

[0193] It should be noted that this solution dynamically switches the simulation time synchronization mechanism under multiple judgment conditions. This allows the system to maintain the stability of time synchronization under various inconsistent or abnormal conditions. At the same time, by dynamically adjusting the time synchronization mechanism, the system can make the most appropriate response based on the current state of the overflow event.

[0194] It should be noted that based on the above evaluation of the first probability and the second probability, the system can provide a clear decision-making basis for each judgment step, ensuring that the selected synchronization mechanism is most in line with the current state, rather than a simple rule or assumption, thereby improving the accuracy of the decision-making. At the same time, it can predict the next time synchronization requirements based on the current probability distribution and make adjustments in advance.

[0195] It should be noted that the preset first probability threshold and the preset second probability threshold may be set by the user or obtained based on historical data, which is not limited in the embodiment of the present invention.

[0196] Exemplarily, the value range of the preset first probability threshold and the preset second probability threshold are both [0.1, 0.3].

[0197] It can be seen that the method of implementing the discrete event simulation time synchronization mechanism described in the embodiment of the present invention is conducive to dynamically switching the time synchronization mechanism during the process of logically executing discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation.

[0198] It should be noted that, in an embodiment of the present invention, an event rollback method is also provided. When the simulation time synchronization mechanism information is the second simulation time synchronization mechanism information, that is, the optimistic time synchronization mechanism, any optimistic time synchronization mechanism will cause state rollback. In order to adapt to the state rollback when an exception occurs in the optimistic time synchronization mechanism, a state vector mechanism is adopted. The so-called state vector (that is, the state buffer) provides N copy storage space for the data item. The N copies of the state variable S can be stored in S0, S1, ..., S N-1 When a logical process advances discrete event information based on an optimistic time synchronization mechanism, the state evolution process can be stored in the state vector. If a rollback is required, it can be done by moving the current pointer within a certain range.

[0199] Since the optimistic time synchronization mechanism has the risk of rollback and the state vector requires a large storage space, certain restrictions are imposed on the optimistic time advancement amplitude and state vector length, that is, a limited optimistic time synchronization mechanism is implemented.

[0200] The state vector has limited storage space, and there are still challenges with preservation and updating during different iterations. To achieve efficient access, batch serialization is adopted. That is, when the state vector reaches a certain "fill rate", the "old" state vector content is transferred to external storage space in batches.

[0201] Example 2

[0202] See also Figure 2 , Figure 2 This is a schematic diagram of the structure of a device for discrete event simulation time synchronization mechanism disclosed in an embodiment of the present invention. Figure 2 The discrete event simulation time synchronization mechanism described is applied to the discrete event simulation time synchronization mechanism optimization system, such as the local server or cloud server used for the discrete event simulation time synchronization mechanism, and the embodiment of the present invention does not limit it. Figure 2 As shown, the device of the discrete event simulation time synchronization mechanism includes:

[0203] An acquisition module 201 is configured to acquire a discrete event set of a logic process and simulation time synchronization mechanism information; the discrete event set includes information on a plurality of discrete events;

[0204] A time synchronization module 202 is used to synchronize the time of the nodes corresponding to the logical process;

[0205] A simulation time synchronization mechanism calculation module 203 is configured to process the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set to obtain target simulation time synchronization mechanism information;

[0206] The discrete event determination module 204 is configured to determine whether all discrete event information in the discrete event set has been executed, and obtain a first determination result;

[0207] When the first judgment result is no, determining that the target simulation time synchronization mechanism information is the simulation time synchronization mechanism information, and executing the simulation time synchronization mechanism calculation module 203;

[0208] When the first judgment result is yes, the process ends.

[0209] It can be seen that the device implementing the discrete event simulation time synchronization mechanism described in the embodiment of the present invention is conducive to dynamically switching the time synchronization mechanism during the process of logically executing discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation.

[0210] Example 3

[0211] See also Figure 3 , Figure 3 This is a schematic diagram of the structure of another discrete event simulation time synchronization mechanism disclosed in an embodiment of the present invention. Figure 3 The discrete event simulation time synchronization mechanism described is applied to the discrete event simulation time synchronization mechanism optimization system, such as the local server or cloud server used for the discrete event simulation time synchronization mechanism, and the embodiment of the present invention does not limit it. Figure 3 As shown, the device of the discrete event simulation time synchronization mechanism includes:

[0212] Processor 301;

[0213] A memory 302 coupled to the processor 301 and storing executable program code;

[0214] The processor 301 calls the executable program code stored in the memory 302 to execute part or all of the steps of the method for the discrete event simulation time synchronization mechanism described in the first embodiment.

[0215] It can be seen that the device implementing the discrete event simulation time synchronization mechanism described in the embodiment of the present invention is conducive to dynamically switching the time synchronization mechanism during the process of logically executing discrete events, thereby improving the performance of large-scale distributed parallel discrete event simulation.

[0216] Example 4

[0217] An embodiment of the present invention discloses a computer-readable storage medium storing computer instructions. When the computer instructions are called, they are used to execute some or all steps of the discrete event simulation time synchronization mechanism method described in embodiment 1.

[0218] Example 5

[0219] An embodiment of the present invention discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to enable a computer to execute some or all of the steps in the method of discrete event simulation time synchronization mechanism described in embodiment 1.

[0220] The system embodiments described above are merely illustrative. Modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules. They may be located in one place or distributed across multiple network modules. Some or all of these modules may be selected based on actual needs to achieve the objectives of this embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0221] Through the detailed description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus the necessary general hardware platform, or of course, by means of hardware. Based on this understanding, the above technical solution, in essence, or the portion that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, including a read-only memory (ROM), a random access memory (RAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0222] Finally, it should be noted that the method and device for a discrete event simulation time synchronization mechanism disclosed in the embodiments of the present invention are only preferred embodiments of the present invention, and are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for discrete event simulation time synchronization mechanism, characterized in that: The method comprises: S1, obtaining a discrete event set of a logic process and simulation time synchronization mechanism information; the discrete event set includes a plurality of discrete event information; S2, performing time synchronization on the nodes corresponding to the logical process; S3, processing the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set to obtain target simulation time synchronization mechanism information; S4, determining whether all discrete event information in the discrete event set has been executed, and obtaining a first determination result; When the first judgment result is no, determining that the target simulation time synchronization mechanism information is the simulation time synchronization mechanism information, and executing S3; When the first judgment result is yes, the process ends; The time synchronization of the nodes corresponding to the logical process includes: S21, using the master node to send message information to the node corresponding to the logical process to obtain a first timestamp and a second timestamp; S22, using the node corresponding to the logical process to send message information to the master node to obtain a third timestamp and a fourth timestamp; S23, using a time synchronization calculation model, calculating and processing the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp to obtain a time synchronization difference; The time synchronization calculation model is: Wherein, TB is the time synchronization difference, T1, T2, T3 and T4 are the first timestamp, the second timestamp, the third timestamp and the fourth timestamp respectively, θ1 and θ2 are the first deviation parameter and the second deviation parameter; S24: Synchronize the time of the node corresponding to the logical process using the time synchronization difference.

2. The method of discrete event simulation time synchronization mechanism according to claim 1, characterized in that: The processing of the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set to obtain target simulation time synchronization mechanism information includes: S31, obtaining a first time value; S32, the number of associated events and the number of overflow events are both preset to 0; S33, processing the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set to obtain an overflow result value; S34, increasing the associated event number by 1; making the sum of the overflow event number and the overflow result value the updated overflow event number, and determining the updated overflow event number as the overflow event number; S35, obtaining a second time value; S36, determining whether the difference between the second time value and the first time value is greater than a preset time synchronization threshold, and obtaining a second determination result; When the second judgment result is yes, time synchronization is performed on the node corresponding to the logical process, and S37 is executed; When the second judgment result is no, executing S37; S37, determining whether the difference between the second time value and the first time value is greater than a preset event overflow time threshold, and obtaining a third determination result; When the third judgment result is yes, execute S38; When the third judgment result is no, executing S33; S38, calculating and processing the number of associated events and the number of overflow events to obtain an overflow event value; S39 , analyzing and processing the simulation time synchronization mechanism information, the overflow event value, the preset first overflow threshold, and the preset second overflow threshold to obtain target simulation time synchronization mechanism information.

3. The method of discrete event simulation time synchronization mechanism according to claim 2, characterized in that: The processing of the simulation time synchronization mechanism information of the logic process and the discrete event information in the discrete event set to obtain an overflow result value includes: S331, traverse the discrete event information in the discrete event set to obtain discrete event information to be processed; the discrete event information to be processed is the discrete event information with the smallest timestamp in the discrete event set; S332, triggering the logic process to execute the discrete event information to be processed according to the simulation time synchronization mechanism information, and obtaining execution result information; S333, determining whether the execution result information is consistent with the preset initiator information, and obtaining a fourth determination result; When the fourth judgment result is yes, determining the overflow result value to be 0; When the fourth judgment result is no, the overflow result value is determined to be 1.

4. The method of discrete event simulation time synchronization mechanism according to claim 2, characterized in that: The analyzing and processing the simulation time synchronization mechanism information, the overflow event value, the preset first overflow threshold value, and the preset second overflow threshold value to obtain target simulation time synchronization mechanism information includes: S391, determining whether the overflow event value is less than the first overflow threshold, and obtaining a fifth determination result; When the fifth judgment result is yes, determining the first simulation time synchronization mechanism information as the target simulation time synchronization mechanism information; When the fifth judgment result is no, determining whether the overflow event value is greater than the second overflow threshold value to obtain a sixth judgment result; When the sixth judgment result is yes, determining the second simulation time synchronization mechanism information as the target simulation time synchronization mechanism information; When the sixth judgment result is no, executing S392; S392, analyze and process the simulation time synchronization mechanism information, the overflow event value, the first simulation time synchronization mechanism information, the second simulation time synchronization mechanism information, the first overflow threshold and the second overflow threshold to obtain the target simulation time synchronization mechanism information.

5. The method of discrete event simulation time synchronization mechanism according to claim 4, characterized in that: The analyzing and processing the simulation time synchronization mechanism information, the overflow event value, the first simulation time synchronization mechanism information, the second simulation time synchronization mechanism information, the first overflow threshold, and the second overflow threshold to obtain the target simulation time synchronization mechanism information includes: S3921: Calculate the overflow event value, the first overflow threshold, and the second overflow threshold using an event overflow probability calculation model to obtain a first probability value and a second probability value. The event overflow probability calculation model is: Wherein, P1 and P2 are the first probability value and the second probability value, YC is the overflow event value, DE and DY are the first overflow threshold and the second overflow threshold; S3922: Analyze and process the simulation time synchronization mechanism information, the first simulation time synchronization mechanism information, the second simulation time synchronization mechanism information, the first probability value, and the second probability value to obtain the target simulation time synchronization mechanism information.

6. The method of discrete event simulation time synchronization mechanism according to claim 5, characterized in that: The analyzing and processing the simulation time synchronization mechanism information, the first simulation time synchronization mechanism information, the second simulation time synchronization mechanism information, the first probability value, and the second probability value to obtain the target simulation time synchronization mechanism information includes: Determine whether the simulation time synchronization mechanism information is completely consistent with the first simulation time synchronization mechanism information, to obtain a seventh determination result; When the seventh judgment result is yes, determining whether the first probability value is less than a preset first probability threshold, to obtain an eighth judgment result; When the eighth judgment result is no, determining that the second simulation time synchronization mechanism information is the target simulation time synchronization mechanism information; When the eighth judgment result is yes, determining the first simulation time synchronization mechanism information as the target simulation time synchronization mechanism information; When the seventh judgment result is no, determining whether the second probability value is less than a preset second probability threshold; obtaining a ninth judgment result; When the ninth judgment result is no, determining that the first simulation time synchronization mechanism information is the target simulation time synchronization mechanism information; When the ninth judgment result is yes, the second simulation time synchronization mechanism information is determined to be the target simulation time synchronization mechanism information.

7. A device for discrete event simulation time synchronization mechanism, characterized in that: The device comprises: processor; a memory coupled to the processor and storing executable program code; The processor calls the executable program code stored in the memory to execute the method of discrete event simulation time synchronization mechanism according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and when the computer instructions are called, they are used to execute the method of discrete event simulation time synchronization mechanism according to any one of claims 1 to 6.

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