Radar seeker signal level model construction method, device, equipment and medium

Abstract

The embodiment of the present invention provides a radar seeker signal level model construction method, device, equipment and medium, which relates to the field of radar seeker signal processing technology. The method includes analyzing the radar seeker signal processing process, identifying the computationally intensive modules that can be processed in parallel; using the CUDA programming model, decomposing the identified computationally intensive modules into multiple threads; mapping the decomposed multiple threads to the parallel simulation architecture of the GPU, each thread corresponding to a stream processor; based on a preset thread scheduling strategy and a preset allocation strategy, allocating multiple threads to multiple stream processors of the GPU for parallel simulation execution, and completing the construction of the radar seeker signal level model. The scheme improves the computational efficiency of model construction and has high real-time performance.

Description

Technical Field

[0001] The present invention relates to the field of radar seeker signal processing technology, and in particular to a radar seeker signal level model construction method, device, equipment and medium. Background Art

[0002] With the continuous evolution of modern warfare, the real-time detection and tracking capability of radar seekers in the terminal stage of guidance has received increasing attention. Traditional radar seeker signal processing usually uses serial computing, which is inefficient and cannot meet real-time requirements. In addition, the programming model of traditional signal processing algorithms is complex and difficult to program, which brings many challenges to algorithm development and optimization. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a method for constructing a radar seeker signal level model to solve the technical problems of low computational efficiency and low real-time performance in the construction of radar seeker models in the prior art. The method includes: Analyze the radar seeker signal processing process and identify computationally intensive modules that can be parallelized; Using the CUDA programming model, the identified computationally intensive modules are decomposed into multiple threads; Map the decomposed multiple threads to the parallel simulation architecture of the GPU, with each thread corresponding to a stream processor; Based on a preset thread scheduling strategy and a preset allocation strategy, the multiple threads are allocated to multiple stream processors of the GPU for parallel simulation execution to complete the construction of the radar seeker signal level model.

[0004] The embodiment of the present invention also provides a radar seeker signal level model construction device to solve the technical problems of low computational efficiency and low real-time performance in radar seeker model construction in the prior art. The device includes: Identification module, used to analyze the radar seeker signal processing process and identify computationally intensive modules that can be processed in parallel; A decomposition module, for decomposing the identified computationally intensive module into multiple threads using a CUDA programming model; A mapping module is used to map the decomposed multiple threads to the parallel simulation architecture of the GPU, where each thread corresponds to a stream processor; The parallel execution module is used to allocate the multiple threads to multiple stream processors of the GPU for parallel simulation execution based on a preset thread scheduling strategy and a preset allocation strategy, so as to complete the construction of the radar seeker signal level model.

[0005] An embodiment of the present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, any of the above-mentioned radar seeker signal level model construction methods is implemented to solve the technical problems of low computational efficiency and low real-time performance in radar seeker model construction in the prior art.

[0006] An embodiment of the present invention also provides a computer-readable storage medium, which stores a computer program for executing any of the above-mentioned radar seeker signal level model construction methods to solve the technical problems of low computational efficiency and low real-time performance in radar seeker model construction in the prior art.

[0007] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of this specification include at least: analyzing the radar seeker signal processing process and identifying the computationally intensive modules that can be processed in parallel; using the CUDA programming model, decomposing the identified computationally intensive modules into multiple threads; mapping the decomposed multiple threads to the parallel simulation architecture of the GPU, each thread corresponding to a stream processor; based on the preset thread scheduling strategy and the preset allocation strategy, allocating multiple threads to multiple stream processors of the GPU for parallel simulation execution, and completing the construction of the radar seeker signal level model. This application utilizes the large-scale parallel computing capability of the GPU to effectively improve the real-time performance of the radar seeker signal processing and meet the real-time processing requirements in complex electromagnetic environments; by using the CUDA programming model to map the signal processing algorithm to the GPU parallel simulation architecture, the defect that the CPU serial processing method is difficult to transplant across platforms is overcome, and the versatility and promotion and application capabilities of the simulation algorithm are improved; by identifying the computationally intensive modules that can be parallelized and decomposing them into a large number of threads and allocating them to multiple stream processors of the GPU for parallel execution, the parallel computing advantages of the GPU are fully utilized to achieve the acceleration of signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0009] Figure 1 is a flow chart of a radar seeker signal level model construction method provided by an embodiment of the present invention; Figure 2 is a structural block diagram of a computer device provided by an embodiment of the present invention; Figure 3It is a structural block diagram of a radar seeker signal level model building device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0010] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0011] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0012] In an embodiment of the present invention, a method for constructing a radar seeker signal level model is provided, such as Figure 1 As shown, the method includes: Step S101, analyzing the radar seeker signal processing process to identify computationally intensive modules that can be processed in parallel; Step S102: using the CUDA programming model, decomposing the identified computationally intensive module into multiple threads; Step S103, mapping the decomposed multiple threads to the parallel simulation architecture of the GPU, where each thread corresponds to a stream processor; Step S104: Based on a preset thread scheduling strategy and a preset allocation strategy, the multiple threads are allocated to multiple stream processors of the GPU for parallel simulation execution to complete the construction of the radar seeker signal level model.

[0013] In this embodiment, the large-scale parallel computing capability of the GPU is utilized to effectively improve the real-time performance of the radar seeker signal processing and meet the real-time processing requirements in complex electromagnetic environments. The signal processing algorithm is mapped to the GPU parallel simulation architecture by adopting the CUDA programming model, thereby overcoming the defect that the CPU serial processing method is difficult to transplant across platforms, and improving the versatility and application capabilities of the simulation algorithm. By identifying parallelizable computing-intensive modules and decomposing them into a large number of threads and assigning them to multiple stream processors of the GPU for parallel simulation execution, the parallel computing advantages of the GPU are fully utilized to achieve acceleration of signal processing.

[0014] The CUDA (Compute Unified Device Architecture) programming model used in this embodiment is a parallel computing platform and application programming interface developed by NVIDIA, which allows developers to use the parallel computing capabilities of NVIDIA GPUs to perform general computing tasks.

[0015] In one embodiment, the step of analyzing the radar seeker signal processing process to identify computationally intensive modules that can be processed in parallel includes: Acquire multiple computing modules of the radar seeker signal processing process, wherein the computing modules include a signal generation module, a signal receiving module, a preprocessing module, a pulse compression module, a Doppler processing module, a constant false alarm rate detection module, and a target tracking module; Conduct data independence evaluation, repeated calculation mode evaluation, and calculation intensity evaluation for each calculation module to obtain a comprehensive evaluation result for each calculation module; Based on the comprehensive evaluation result, a computationally intensive module that can be processed in parallel is identified among the plurality of computational modules.

[0016] In specific implementation, for each computing module of the radar seeker signal processing process, the signal generation module is used to generate a radar transmission signal (such as a linear frequency modulation signal), the signal receiving module is used to receive the echo signal reflected by the target; the preprocessing module is used to filter and denoise the echo signal, the pulse compression module is used to improve the distance resolution through matched filtering; the Doppler processing module is used to extract the target speed information through FFT; the constant false alarm rate detection module is used to detect the target through algorithms such as constant false alarm rate (CFAR); the target tracking module is used to track and predict the trajectory of the detected target. In this embodiment, by analyzing the calculation process of each calculation module, a computationally intensive module that can be processed in parallel is obtained, which provides a basis for subsequent parallel computing using GPU.

[0017] Specifically, this embodiment comprehensively evaluates the computationally intensive modules that can be used for parallel processing through three aspects: data independence evaluation, repeated computing pattern evaluation, and computational intensity evaluation. By evaluating data independence, it is possible to determine which computing modules can run independently without relying on the data of other computing modules, thereby identifying modules suitable for parallel processing, which helps to improve the overall computing efficiency of the system; repeated computing pattern evaluation can help identify which modules have redundant calculations, thereby optimizing the utilization of computing resources and reducing unnecessary computing overhead; computational intensity evaluation helps to identify which modules are computationally intensive, so that these modules can be optimized, such as using more efficient algorithms or hardware acceleration to improve overall computing efficiency. By combining the results of these three evaluations, the computing characteristics of each computing module can be fully understood, so that more reasonable parallelization decisions can be made, ensuring that the system can maximize performance improvements during parallel processing.

[0018] In specific implementation, performance analysis tools (such as cProfile) are used to measure the computational intensity of each computing module; code review or static analysis tools (such as SonarQube) are used to identify repeated computing patterns; and data flow analysis tools (such as Apache NiFi) are used to evaluate data independence. The calculation of the comprehensive evaluation results can be carried out using comprehensive analysis and weighted methods, which is explained below with a specific example. Assign weights to the three evaluation dimensions of data independence, repeated computing mode and computing intensity respectively, and calculate a comprehensive score based on the weights to represent the comprehensive evaluation result. For example, the weight of data independence is 40%, the weight of computing intensity is 40%, and the weight of repeated computing mode is 20%. Then formulate a scoring standard for each dimension (such as 0-10 points): data independence: the higher the score, the more independent the module; computing intensity: the higher the score, the greater the amount of module calculation; repeated computing mode: the lower the score, the less redundant calculation of the module; then calculate the comprehensive score of each computing module based on the weights and scores of each dimension, the comprehensive score = (data independence score × weight) + (computational intensity score × weight) + (repeated computing mode score × weight); finally, sort or classify the computing modules based on the comprehensive score, and then identify the computing-intensive modules suitable for parallelization (for example, computing modules with a comprehensive score greater than a threshold or the first preset computing modules in the sorting are computing-intensive modules).

[0019] In one embodiment, in addition to using a data flow analysis tool (such as Apache NiFi) to evaluate data independence, in order to further improve the evaluation accuracy, the data independence evaluation is also proposed, including: Obtaining input data and output data of the computing module; The input data and the output data are fuzzified by using a fuzzy system and mapped to a fuzzy space, a correlation index between the input data and the output data is calculated in the fuzzy space, and the correlation between the input data and the output data is determined according to the correlation index; When the correlation is greater than a preset threshold, the data independence of the calculation module is evaluated using a BP neural network model according to the correlation.

[0020] In specific implementation, the input data and output data are fuzzified through the fuzzy system and mapped from exact values ​​to fuzzy space. The purpose of fuzzification is to convert data into fuzzy sets in order to better handle uncertainty and nonlinear relationships. Specifically, fuzzy logic toolboxes such as Fuzzy Logic Toolbox in MATLAB or scikit-fuzzy in Python are used to implement fuzzification, and membership functions such as triangular membership functions or Gaussian membership functions are used to map data to fuzzy space.

[0021] In the fuzzy space, the correlation index between the input data and the output data is calculated, which can be a fuzzy correlation coefficient or a fuzzy similarity. The correlation index is used to quantify the dependency between the input data and the output data. Specifically, the calculation formula of the fuzzy correlation coefficient is as follows: , in, is the membership degree of the input data, is the membership degree of the output data, and n is the number of data.

[0022] The strength of the correlation between the input data and the output data is determined based on the calculated correlation index. If the correlation index is high, it means that there is a strong dependency between the input data and the output data; otherwise, the dependency is weak.

[0023] If the correlation index is greater than the preset threshold (for example, 0.7), it means that there is a strong dependency between the input data and the output data, and the data independence needs to be further evaluated. Specifically, the BP (back propagation) neural network model is used to train the neural network with the input data and the output data as training data; the data independence of the computing module is evaluated through the output results of the neural network. For example: if the neural network can accurately predict the output data, it means that there is a strong dependency between the input data and the output data, and the data independence of the module is low; if the prediction result of the neural network is poor, it means that the dependency between the input data and the output data is weak, and the data independence of the module is high.

[0024] In this embodiment, by processing data through a fuzzy system, the nonlinear relationship and uncertainty between input data and output data can be better captured, thereby improving the accuracy of correlation evaluation; fuzzy processing can reduce the impact of data noise and outliers on the evaluation results, making the evaluation process more robust; the BP neural network can learn the complex dependencies between input data and output data, and is suitable for evaluating computing modules with nonlinear characteristics; and through the combination of correlation indicators and neural network models, the data independence of the computing modules can be scientifically quantified, providing a reliable basis for parallel decision-making. This method not only improves the accuracy and robustness of the evaluation, but also supports automated processing, and is suitable for performance optimization of complex systems.

[0025] In one embodiment, the purpose of repeated computing pattern evaluation of a computing module is to identify whether there are redundant calculations or repeated operations in the module, so as to optimize computing efficiency, mainly including static code analysis, dynamic runtime analysis, data flow analysis, cache and reuse inspection.

[0026] For static code analysis, the source code of the calculation module is analyzed to identify potential repeated calculation patterns; loops, recursions, function calls and other structures are checked to find the possibility of repeated calculations. In this embodiment, static code analysis tools (such as SonarQube, Clang Static Analyzer) or built-in analysis functions of IDE are used.

[0027] For dynamic runtime analysis, when the computing module is running, its execution process is monitored, and the number of function calls, the number of computing task executions, etc. are recorded; repeated calculations are detected through Python's cProfile performance analysis tool.

[0028] For data flow analysis, analyze the input and output data of the computing module to check whether the same input data is processed multiple times; identify redundant calculations through the data flow graph (Data Flow Graph), and use data flow analysis tools such as LLVM and Apache NiFi. In the data flow graph, if multiple nodes are found to process the same input data, there may be repeated calculations.

[0029] For cache and reuse checks, check whether the computing module fully utilizes the cache mechanism to avoid repeated calculations. For example, use cache analysis tools (such as Valgrind and Perf) to check whether intermediate results are cached and reused.

[0030] In this embodiment, identifying repetitive computing patterns helps to optimize algorithm design and select more efficient computing strategies; highly repetitive computing patterns usually have high data parallelism, and the GPU can process a large amount of data at the same time, giving full play to its parallel computing advantages; after migrating repetitive computing tasks to the GPU, the response speed of the radar seeker model can be significantly improved, and the real-time performance of the calculation can be improved.

[0031] In one embodiment, in addition to using a performance analysis tool (such as cProfile) to measure the computational intensity of each computing module, in order to further improve the evaluation accuracy, it is also proposed that the computational intensity evaluation includes: Calculate the theoretical total number of floating-point operations according to the specific operations of the calculation module; Using CUDA Event to measure the actual execution time of the computing module; The theoretical total number of floating-point operations is divided by the actual execution time to obtain the number of floating-point operations per unit time, and the number of floating-point operations per unit time is used as the computational intensity of the computational module.

[0032] Specifically, use CUDA Event to measure the actual execution time, including: Run the computing module on the GPU and use CUDA Event to record its start and end time; Record the event with cudaEventRecord() and ensure the event is completed with cudaEventSynchronize(); Use cudaEventElapsedTime() to calculate the actual execution time (in milliseconds); Divide the theoretical total number of floating-point operations by the actual execution time to get the number of floating-point operations per unit time. This value reflects the computational intensity of the computing module.

[0033] In this embodiment, by calculating the number of floating-point operations (FLOPS) per unit time, the computational density of the computing module can be quantified, providing a scientific basis for performance optimization; by comparing theoretical FLOPs and actual FLOPS, the computing efficiency of the GPU can be evaluated and performance bottlenecks can be identified; modules with high computational density are usually more suitable for parallel processing, and the evaluation results provide guidance for parallel optimization; by measuring the actual execution time, performance problems of the computing module (such as memory access latency, unbalanced computing load) can be identified and targeted optimization can be performed. Therefore, by calculating the computational density of each computing module, not only the computing performance is quantified, but also an important basis for algorithm optimization, resource allocation, and parallelization decisions is provided, thereby significantly improving system efficiency and performance.

[0034] In one embodiment, the computationally intensive module includes a pulse compression module, a Doppler processing module, and a constant false alarm rate detection module. The calculation formula for the theoretical total floating-point operation times of the pulse compression module is: ; The calculation formula of the theoretical total floating point operation times of the Doppler processing module is: ; The calculation formula of the theoretical total floating point operation times of the constant false alarm rate detection module is: ; Wherein, TotalFLOPs is the theoretical total number of floating-point operations, N is the length of the one-dimensional fast Fourier transform or the inverse fast Fourier transform in the pulse compression module, S is the signal length of the matched filter in the pulse compression module, X and Y are the length and width of the two-dimensional fast Fourier transform in the Doppler processing module, U and V are the height and width of the input data of the constant false alarm rate detection module, and K and L are the height and width of the sliding window of the constant false alarm rate detection module.

[0035] In one embodiment, the use of the CUDA programming model to decompose the identified computationally intensive module into multiple threads includes: For the pulse compression module, the echo signal of the pulse compression module is divided into multiple segments according to a preset time period, and a first CUDA kernel function is written. The multiple segments of echo signals are distributed to multiple threads through the first CUDA kernel function, and each thread is responsible for processing a segment of echo signal; wherein the first CUDA kernel function is defined using the global keyword, and by calculating the starting position of the signal processed by each thread, it is ensured that each thread accesses the data in the time period corresponding to it; For the Doppler processing module, the input signal of the Doppler processing module is divided into multiple subsets according to the number of Doppler frequency points, and the cuFFT library in CUDA is used as the second CUDA kernel function. In the process of creating an FFT plan, the batch size is set to 1, so that each subset is respectively assigned to a thread, and multiple threads perform cuFFT operations in parallel; For the constant false alarm rate detection module, the input signal of the constant false alarm rate detection module is divided into multiple subsets according to the number of sampling points, and a third CUDA kernel function is written. By calculating each thread ID, each subset is assigned to a thread respectively, and multiple threads calculate the background noise level of each sampling point in parallel. By judging whether the background noise level exceeds a threshold, it is confirmed whether the sampling point is a target point.

[0036] In this embodiment, by dividing different computationally intensive modules into multi-threaded modules, the processing speed of the computationally intensive modules can be significantly improved, and efficient parallel computing can be achieved; through reasonable task division and memory management strategies, the computing resources of the GPU are maximized; and the ability of the radar seeker signal-level model to process large-scale data is enhanced, making it more suitable for radar signal processing scenarios with high real-time and accuracy requirements.

[0037] In one embodiment, the preset thread scheduling strategy includes: allocating multiple threads to multiple stream processors of the GPU in sequence according to thread ID order, and using GPGPU as a coprocessor; The preset allocation strategy includes: implementing overall scheduling and reallocation of register resources when GPGPU executes branch instructions according to different register reallocation strategies, and expanding the register group of active threads or the first-level cache by reallocating the register group of idle threads; when expanding the register group of active threads, the idle register groups are broken up and reorganized, and the register resources are evenly distributed to each active register group according to the number of active register groups to achieve the expansion of the register group.

[0038] In specific implementation, based on the preset thread scheduling strategy, multiple threads are sequentially assigned to different stream processors of the GPU in the order of thread IDs. This sequential assignment helps to maintain a balanced distribution of tasks and avoid the situation where some stream processors are overloaded while other stream processors are idle. For the overall scheduling and reallocation of register resources, identify idle threads: determine which threads are currently idle, and the register groups of these threads can be reallocated; expand the register group or first-level cache of active threads: reallocate the register group resources of idle threads to active threads to increase their available registers or expand the capacity of the first-level cache.

[0039] In this embodiment, tasks are allocated in sequence according to the order of threads to ensure balanced distribution of tasks; Resource allocation strategy: According to different register reallocation strategies, the register resource management of GPGPU when executing branch instructions is optimized to improve the execution efficiency of active threads. Register group expansion: By breaking up and reorganizing the idle register groups, resources are evenly distributed to each active register group to achieve register group expansion, thereby further improving computing performance.

[0040] In one embodiment, the method further comprises: System integration: module integration, integrating signal generation, processing, detection and other modules into a unified system; designing user interface to facilitate parameter setting and result viewing; Testing and verification: Conduct unit tests on each module to ensure correct functionality; conduct overall system tests to verify whether performance meets requirements; evaluate system performance, including processing speed, accuracy, and resource consumption; Documentation and Maintenance: Write detailed documentation, including design, implementation, testing, and maintenance instructions; regularly maintain and update the system to fix problems and optimize performance.

[0041] In this embodiment, a computer device is provided, such as Figure 2 As shown, it includes a memory 201, a processor 202, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, any of the above-mentioned radar seeker signal level model construction methods is implemented.

[0042] Specifically, the computer device may be a computer terminal, a server or a similar computing device.

[0043] In this embodiment, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program for executing any of the above-mentioned radar seeker signal level model construction methods.

[0044] Specifically, computer-readable storage media include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer-readable storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable storage media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0045] Based on the same inventive concept, a radar seeker signal level model construction device is also provided in an embodiment of the present invention, as described in the following embodiments. Since the principle of solving the problem by the radar seeker signal level model construction device is similar to that of the radar seeker signal level model construction method, the implementation of the radar seeker signal level model construction device can refer to the implementation of the radar seeker signal level model construction method, and the repeated parts will not be repeated. As used below, the term "unit" or "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceived.

[0046] Figure 3 is a structural block diagram of a radar seeker signal level model building device according to an embodiment of the present invention, such as Figure 3 As shown, it includes: an identification module 301, a decomposition module 302, a mapping module 303 and a parallel execution module 304. The structure is described below.

[0047] An identification module 301 is used to analyze the radar seeker signal processing process and identify computationally intensive modules that can be processed in parallel; A decomposition module 302 is used to decompose the identified computationally intensive module into multiple threads using a CUDA programming model; A mapping module 303 is used to map the decomposed multiple threads to the parallel simulation architecture of the GPU, where each thread corresponds to a stream processor; The parallel execution module 304 allocates the multiple threads to multiple stream processors of the GPU for parallel simulation execution based on a preset thread scheduling strategy and a preset allocation strategy, thereby completing the construction of the radar seeker signal level model.

[0048] In one embodiment, the identification module 301 is further used to: Acquire multiple computing modules of the radar seeker signal processing process, wherein the computing modules include a signal generation module, a signal receiving module, a preprocessing module, a pulse compression module, a Doppler processing module, a constant false alarm rate detection module, and a target tracking module; Conduct data independence evaluation, repeated calculation mode evaluation, and calculation intensity evaluation for each calculation module to obtain a comprehensive evaluation result for each calculation module; Based on the comprehensive evaluation result, a computationally intensive module that can be processed in parallel is identified among the plurality of computational modules.

[0049] In one embodiment, the identification module 301 is further used to: Obtaining input data and output data of the computing module; The input data and the output data are fuzzified by using a fuzzy system and mapped to a fuzzy space, a correlation index between the input data and the output data is calculated in the fuzzy space, and the correlation between the input data and the output data is determined according to the correlation index; When the correlation is greater than a preset threshold, the data independence of the calculation module is evaluated using a BP neural network model according to the correlation.

[0050] In one embodiment, the identification module 301 is further used to: Calculate the theoretical total number of floating-point operations according to the specific operations of the calculation module; Using CUDA Event to measure the actual execution time of the computing module; The theoretical total number of floating-point operations is divided by the actual execution time to obtain the number of floating-point operations per unit time, and the number of floating-point operations per unit time is used as the computational intensity of the computational module.

[0051] In one embodiment, the identification module 301 is further used to: The computationally intensive module includes a pulse compression module, a Doppler processing module and a constant false alarm rate detection module. The calculation formula for the theoretical total floating-point operation times of the pulse compression module is: ; The calculation formula of the theoretical total floating point operation times of the Doppler processing module is: ; The calculation formula of the theoretical total floating point operation times of the constant false alarm rate detection module is: ; Wherein, TotalFLOPs is the theoretical total number of floating-point operations, N is the length of the one-dimensional fast Fourier transform or the inverse fast Fourier transform in the pulse compression module, S is the signal length of the matched filter in the pulse compression module, X and Y are the length and width of the two-dimensional fast Fourier transform in the Doppler processing module, U and V are the height and width of the input data of the constant false alarm rate detection module, and K and L are the height and width of the sliding window of the constant false alarm rate detection module.

[0052] In one embodiment, the decomposition module 302 is further used to: For the pulse compression module, the echo signal of the pulse compression module is divided into multiple segments according to a preset time period, and a first CUDA kernel function is written. The multiple segments of echo signals are distributed to multiple threads through the first CUDA kernel function, and each thread is responsible for processing a segment of echo signal; wherein the first CUDA kernel function is defined using the global keyword, and by calculating the starting position of the signal processed by each thread, it is ensured that each thread accesses the data in the time period corresponding to it; For the Doppler processing module, the input signal of the Doppler processing module is divided into multiple subsets according to the number of Doppler frequency points, and the cuFFT library in CUDA is used as the second CUDA kernel function. In the process of creating an FFT plan, the batch size is set to 1, so that each subset is respectively assigned to a thread, and multiple threads perform cuFFT operations in parallel; For the constant false alarm rate detection module, the input signal of the constant false alarm rate detection module is divided into multiple subsets according to the number of sampling points, and a third CUDA kernel function is written. By calculating each thread ID, each subset is assigned to a thread respectively, and multiple threads calculate the background noise level of each sampling point in parallel. By judging whether the background noise level exceeds a threshold, it is confirmed whether the sampling point is a target point.

[0053] In one embodiment, the parallel execution module 304 is further used to: The preset thread scheduling strategy includes: allocating multiple threads to multiple stream processors of the GPU in sequence according to thread ID order, and using GPGPU as a coprocessor; The preset allocation strategy includes: implementing overall scheduling and reallocation of register resources when GPGPU executes branch instructions according to different register reallocation strategies, and expanding the register group of active threads or the first-level cache by reallocating the register group of idle threads; when expanding the register group of active threads, the idle register groups are broken up and reorganized, and the register resources are evenly distributed to each active register group according to the number of active register groups to achieve the expansion of the register group.

[0054] The embodiment of the present invention achieves the following technical effects: analyzing the radar seeker signal processing process, identifying the computationally intensive modules that can be processed in parallel; using the CUDA programming model, decomposing the identified computationally intensive modules into multiple threads; mapping the decomposed multiple threads to the parallel simulation architecture of the GPU, each thread corresponding to a stream processor; based on the preset thread scheduling strategy and the preset allocation strategy, allocating multiple threads to multiple stream processors of the GPU for parallel simulation execution, and completing the construction of the radar seeker signal level model. This application utilizes the large-scale parallel computing capability of the GPU to effectively improve the real-time performance of the radar seeker signal processing and meet the real-time processing requirements in complex electromagnetic environments; by using the CUDA programming model to map the signal processing algorithm to the GPU parallel simulation architecture, the defect that the CPU serial processing method is difficult to transplant across platforms is overcome, and the versatility and promotion and application capabilities of the simulation algorithm are improved; by identifying the computationally intensive modules that can be parallelized, and decomposing them into a large number of threads and allocating them to multiple stream processors of the GPU for parallel execution, the parallel computing advantages of the GPU are fully utilized to achieve the acceleration of signal processing.

[0055] Obviously, those skilled in the art should understand that the modules or steps of the above-mentioned embodiments of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. In this way, the embodiments of the present invention are not limited to any specific combination of hardware and software.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for constructing a radar seeker signal level model, characterized in that: include: Analyze the radar seeker signal processing process and identify computationally intensive modules that can be parallelized; Using the CUDA programming model, the identified computationally intensive modules are decomposed into multiple threads; Map the decomposed multiple threads to the parallel simulation architecture of the GPU, with each thread corresponding to a stream processor; Based on a preset thread scheduling strategy and a preset allocation strategy, the multiple threads are allocated to multiple stream processors of the GPU for parallel simulation execution to complete the construction of the radar seeker signal level model.

2. The radar seeker signal level model construction method according to claim 1, characterized in that: The step of analyzing the radar seeker signal processing process and identifying computationally intensive modules that can be processed in parallel includes: Acquire multiple computing modules of the radar seeker signal processing process, wherein the computing modules include a signal generation module, a signal receiving module, a preprocessing module, a pulse compression module, a Doppler processing module, a constant false alarm rate detection module, and a target tracking module; Conduct data independence evaluation, repeated calculation mode evaluation, and calculation intensity evaluation for each calculation module to obtain a comprehensive evaluation result for each calculation module; Based on the comprehensive evaluation result, a computationally intensive module that can be processed in parallel is identified among the plurality of computational modules.

3. The radar seeker signal level model construction method as claimed in claim 2, characterized in that: The data independence assessment includes: Obtaining input data and output data of the computing module; The input data and the output data are fuzzified by using a fuzzy system and mapped to a fuzzy space, a correlation index between the input data and the output data is calculated in the fuzzy space, and the correlation between the input data and the output data is determined according to the correlation index; When the correlation is greater than a preset threshold, the data independence of the calculation module is evaluated using a BP neural network model according to the correlation.

4. The radar seeker signal level model construction method as claimed in claim 2, characterized in that: The computational intensity assessment includes: Calculate the theoretical total number of floating-point operations according to the specific operations of the calculation module; Using CUDA Event to measure the actual execution time of the computing module; The theoretical total number of floating-point operations is divided by the actual execution time to obtain the number of floating-point operations per unit time, and the number of floating-point operations per unit time is used as the computational intensity of the computational module.

5. The radar seeker signal level model construction method as claimed in claim 4, characterized in that: The computationally intensive module includes a pulse compression module, a Doppler processing module and a constant false alarm rate detection module. The calculation formula for the theoretical total floating-point operation times of the pulse compression module is: ； The calculation formula of the theoretical total floating point operation times of the Doppler processing module is: ； The calculation formula of the theoretical total floating point operation times of the constant false alarm rate detection module is: ； Wherein, TotalFLOPs is the theoretical total number of floating-point operations, N is the length of the one-dimensional fast Fourier transform or the inverse fast Fourier transform in the pulse compression module, S is the signal length of the matched filter in the pulse compression module, X and Y are the length and width of the two-dimensional fast Fourier transform in the Doppler processing module, U and V are the height and width of the input data of the constant false alarm rate detection module, and K and L are the height and width of the sliding window of the constant false alarm rate detection module.

6. The radar seeker signal level model construction method according to claim 5, characterized in that: The CUDA programming model is used to decompose the identified computationally intensive modules into multiple threads, including: For the pulse compression module, the echo signal of the pulse compression module is divided into multiple segments according to a preset time period, and a first CUDA kernel function is written. The multiple segments of echo signals are distributed to multiple threads through the first CUDA kernel function, and each thread is responsible for processing a segment of echo signal; wherein the first CUDA kernel function is defined using the global keyword, and by calculating the starting position of the signal processed by each thread, it is ensured that each thread accesses the data in the time period corresponding to it; For the Doppler processing module, the input signal of the Doppler processing module is divided into multiple subsets according to the number of Doppler frequency points, and the cuFFT library in CUDA is used as the second CUDA kernel function. In the process of creating an FFT plan, the batch size is set to 1, so that each subset is respectively assigned to a thread, and multiple threads perform cuFFT operations in parallel; For the constant false alarm rate detection module, the input signal of the constant false alarm rate detection module is divided into multiple subsets according to the number of sampling points, and a third CUDA kernel function is written. By calculating each thread ID, each subset is assigned to a thread respectively, and multiple threads calculate the background noise level of each sampling point in parallel. By judging whether the background noise level exceeds a threshold, it is confirmed whether the sampling point is a target point.

7. The radar seeker signal level model construction method according to claim 1, characterized in that: The preset thread scheduling strategy includes: allocating multiple threads to multiple stream processors of the GPU in sequence according to thread ID order, and using GPGPU as a coprocessor; The preset allocation strategy includes: implementing overall scheduling and reallocation of register resources when GPGPU executes branch instructions according to different register reallocation strategies, and expanding the register group of active threads or the first-level cache by reallocating the register group of idle threads; when expanding the register group of active threads, the idle register groups are broken up and reorganized, and the register resources are evenly distributed to each active register group according to the number of active register groups to achieve the expansion of the register group.

8. A radar seeker signal level model construction device, characterized in that: include: Identification module, used to analyze the radar seeker signal processing process and identify computationally intensive modules that can be processed in parallel; A decomposition module, for decomposing the identified computationally intensive module into multiple threads using a CUDA programming model; A mapping module is used to map the decomposed multiple threads to the parallel simulation architecture of the GPU, where each thread corresponds to a stream processor; The parallel execution module is used to allocate the multiple threads to multiple stream processors of the GPU for parallel simulation execution based on a preset thread scheduling strategy and a preset allocation strategy, so as to complete the construction of the radar seeker signal level model.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the radar seeker signal level model construction method described in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program for executing the radar seeker signal level model building method according to any one of claims 1 to 7.

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