Data acquisition system verification and analysis method and system
By adopting FPGA-based data acquisition cache system and simulation verification methods in multi-channel data acquisition systems, the problem of difficulty in detecting internal data changes in existing systems is solved, and development efficiency and system performance are improved.
Patent Information
- Application Number
- CN202510038955.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-10
- Publication Date
- 2025-04-04
AI Technical Summary
The existing multi-channel data acquisition system is difficult to effectively detect internal data changes, resulting in low development efficiency, high cost and long R&D time.
The FPGA-based data acquisition and cache system is used to simulate verification and debug through the simulation software Modelsim and FPGA embedded logic analyzer, to build a laboratory hardware board test environment, verify the data acquisition, cache and transmission process, and perform comparison and analysis.
It realizes detection of the operating status of the internal signals and registers of FPGA, improves development efficiency, reduces development costs and cycles, and effectively verifies the performance of the data acquisition system.
Smart Images
Figure CN119761277A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of data acquisition system verification, and in particular relates to a data acquisition system verification and analysis method and system. Background Art
[0002] In recent years, data acquisition systems have widely tested data from industrial sites, national defense construction, scientific research and other fields. With the continuous development of sensor technology and communication technology, the number of data sampling channels is increasing. At the same time, the system also puts forward higher requirements for data sampling accuracy and synchronization.
[0003] Through the above analysis, the problems and defects of the existing technology are: the existing multi-channel data acquisition system cannot effectively detect the changes in internal data, has low development efficiency, high development cost and long development cycle time. Summary of the invention
[0004] In order to overcome the problems existing in the related art, the disclosed embodiments of the present invention provide a data acquisition system verification and analysis method and system, which specifically relates to an overall verification and integration method of a data acquisition cache system based on FPGA, and uses laboratory hardware boards to build a test environment to verify the entire process of data acquisition, caching and transmission, and compare and analyze the data processing results.
[0005] The technical solution is as follows: A data acquisition system verification and analysis method, comprising the following steps: S1, use the simulation software Modelsim and FPGA embedded logic analyzer to simulate, verify and debug each sub-module of the system; S2, after the simulation and debugging are passed, the test environment is built using the laboratory hardware board through the overall system verification and integration method to verify the entire process of data collection, caching and transmission, and compare and analyze the data processing results; S3, based on the comparative analysis results, obtain the operating status of each signal and register inside the FPGA, and obtain the change information of the internal data of the FPGA through the embedded logic analyzer.
[0006] Further, in step S2, the method for overall system verification and integration includes: The first step is to write the testbensh file to apply stimulus to the top layer of the DDR3 SDRAM cache controller, and test the running status of each signal of the DDR3 SDRAM controller in the Modelsim software. After the test is correct, write the Verilog HDL code of the serial port RX and TX ends, load it into the entire DDR3 SDRAM controller project, and continuously send bit data through the serial port host computer software to analyze whether the host computer receives the same bit data as the sending end; The second step is to write testbensh to apply stimulus to the top layer of the Gigabit Ethernet receiver, and detect the operating status of each signal of the Gigabit Ethernet receiver controller in the Modelsim software. After the test is correct, connect the board to the PC through the network cable, and use the embedded logic analyzer Debug ila in the code design software to analyze the information that the FPGA can receive the garbage packets sent by the PC; The third step is to write testbensh according to the data framing sequence of the Gigabit Ethernet transmitter framing module to apply stimulus to the top layer of the Gigabit Ethernet transmitter, and detect whether the Gigabit Ethernet transmitter controller sends according to the framing sequence in the Modelsim software. After the test is correct, write the cyclic data stimulus testbensh, and use Modelsim to detect whether the packet header and data can be sent cyclically; The fourth step is to use Verilog HDL inside the FPGA to generate a gray image information data source, connect the image data source to the HDMI transmitter, and use the embedded logic analyzer Debug ila in the code design software to detect whether the status of each RGB signal at the FPGA HDMI transmitter is R=G=B; The fifth step is to introduce the test board, use Verilog HDL inside the test board FPGA to generate a gray image information data source, connect the image data source to the test board HDMI transmitter controller, and connect it to the HDMI receiver interface controller of the motherboard to be tested through the HDMI transmitter port, and use the embedded logic analyzer Debug ila inside the code design software to detect whether the status of each RGB signal at the FPGA HDMI receiver is R=G=B; Step 6: Introduce a monocular camera and connect it to the DVP interface. Combine it with the tested DDR3 SDRAM controller and Gigabit Ethernet transmitter controller to collect video information through host computer detection. Step 7: Send the network downloaded video through the HDMI host computer, connect the PC to the HDMI receiver, and combine the tested DDR3 SDRAM controller and HDMI transmitter controller to detect whether the host computer receives the original video source data information; In the eighth step, a monocular camera is introduced and connected to the DVP interface. The DDR3 SDRAM controller, grayscale conversion, denoising, background overlay preprocessing module and Gigabit Ethernet transmitter controller that have been tested are combined to detect the collected video information through the host computer, and the image processing results are compared and analyzed. In the ninth step, a binocular camera is introduced and connected to the DVP interface, and the image scaling effect is tested in conjunction with the tested DDR3 SDRAM controller, image scaling preprocessing module, HDMI transmitter, and display.
[0007] In the first step, 1024 8-bit data are continuously sent through the serial port host computer software to detect whether the host computer receives the same 1024 8-bit data as the sender; Based on the implemented DDR3 SDRAM read-write controller, write a test script to test the functional files of the entire project.
[0008] Writing a test script to test the functional files of the entire project specifically includes: testbensh is a test script written in which Wr_req and Rd_req are used as input signals of the top module. It is simulated through the Modelsim software to verify the correctness of the entire project file. The input stimulus signal required by the top module is generated in the written test script, and the top module is instantiated into the test script. Modelsim is run for simulation detection.
[0009] Furthermore, in the second step, the code design software uses Vivado 2016.4 version; Based on the already implemented Gigabit Ethernet receiver controller, the receiver and transmitter are verified by writing test scripts for simulation or using the internal logic analyzer for debugging.
[0010] During the verification of the receiving end, after completing the test data source module, the ODDR module is also written to convert the single-edge 8-bit data sampling into double-edge 4-bit data sampling, simulating the RGMII interface between the PHY chip and the FPGA; in this process, the clock and reset signals of the test data source module are provided by the module under test.
[0011] Further, in the third step, when the connection establishment function of the receiving end is normal, a test script is written for the sending end to test at the same time, and the written test script data source is cyclically sent according to the framing order of the Gigabit Ethernet sending end data, and the sending end function module of the sending end receives the data according to the framing order of the test data source, including the preamble, MAC address, packet type and data packet information; When the test script data source cyclically sends multiple packets of data according to the Gigabit Ethernet transmitter data framing sequence, a data flag of 8'h00 is added before each packet of data. The transmitter normally receives the flag 8'h00 and the data, and the enable signal is normally pulled low or high.
[0012] Furthermore, in the fourth step, based on the already implemented HDMI transmitter controller, a graphic data generation module is written inside the FPGA. The graphic data generation module is used to generate information of a gray image, convert the continuous 24-bit image information into RGB three-way pixel information after passing through the VGA control module, and convert the 8-bit pixel into 10-bit pixel data. The status of the three signals r_10bit, g_10bit and b_10bit are captured through the embedded logic analyzer Debug ila inside the FPGA.
[0013] In the fifth step, based on the already implemented HDMI transmitter controller, the verified HDMI transmitter module, vga_data_gen and vga control module are transplanted into the FPGA of the test board, and the HDMI receiver module to be verified is transplanted into the FPGA of the main board. The embedded logic analyzer Debug ila inside the FPGA is used to detect the R, G, and B pixel information converted by the HDMI receiver.
[0014] Further, in step S3, obtaining the operating status of each signal and register inside the FPGA based on the comparison and analysis results includes: Step 1: When there is a new test data source request, the frame sequence generated by the test data source is converted into an RGB pixel model, that is, the frame sequence is divided into a timing pre-domain T and a bit pixel adjustment domain H; then the frame sequence is forwarded to the conflict attack detection module, and it is determined whether the frame sequence of the new test data source itself belongs to the test data source type that generates a conflict attack. If so, step 2 is executed, otherwise step 3 is executed; Step 2: Take out an undetected frame sequence from the new test data source, and take out an undetected frame sequence from the existing frame sequence of the test data source in the network to proceed to step 4. If all frame sequences have been detected, proceed to step 3. Step 3: Take out an undetected frame sequence from the new test data source, and take out an undetected frame sequence from other deployed test data sources to execute step 4. If all frame sequences have been detected, execute step 8. Step 4: record the two frame sequence timing pre-orders as Tn and To, the bit pixel adjustment domains as Hn and Ho, and the priorities as Un and Uo; then separate the timing pre-orders and generate four new frame sequences E1, E2, E3, and E4. The timing pre-orders of these four frame sequences are T1=Tn-To, T2=To-Tn, T3=To∩Tn, and T4=Tn∩To; the bit pixel adjustment domains are H1=Hn, H2=Ho, H3=Ho, and H4=Hn; Step 5: Check the content after spatial separation. If T3 and T4 are not empty sets and the actions corresponding to H3 and H4 are different, it is determined to be a conflicting attack and step 7 is executed; otherwise, it is determined to be no conflicting attack and step 6 is executed; Step 6: Determine whether this step is jumped from step 2. If yes, return to step 2; otherwise, return to step 3. Step 7, eliminating the frame sequence that resists the attack; Step eight, configure the frame sequence that does not conflict with the attack into the network to deploy a new test data source.
[0015] After completing the separation of the space in step 4, execute step 5; wherein Tn-To represents the remaining space after removing To from space Tn, To-Tn represents the remaining space after removing Tn from space To, To∩Tn represents the part where To and Tn spaces intersect, and Tn∩To represents the part where Tn and To spaces intersect; The step seven comprises: The first step is to determine the priority of the test data source corresponding to the two frame sequences. The priority is divided according to the test data source type: security test data source, general test data source. The security test data source has the highest priority. The general test data source is divided into two categories: one is related to the register, and the other is not related to the register. The test data source not related to the register generally belongs to the configuration test data source in the network, and is given a higher priority than the test data source related to the register; if the test data source types are the same, the priority is set according to the specific type of the test data source; The second step is to eliminate the conflicting attack frame sequence with a low priority. If Un>Uo, eliminate the frame sequence E3, otherwise eliminate the frame sequence E4. The frame sequence conflict attack elimination is completed, and return to step six.
[0016] Another object of the present invention is to provide a data acquisition system verification and analysis system, the system comprising: Sub-module simulation verification and debugging module, used to simulate, verify and debug each sub-module of the system using simulation software Modelsim and FPGA embedded logic analyzer; The system overall verification and integration module is used to verify the entire process of data acquisition, caching and transmission through the system overall verification and integration method after simulation and debugging, and to compare and analyze the data processing results by using the laboratory hardware board to build a test environment; The data operation status and change acquisition module is used to obtain the operation status of each signal and register inside the FPGA based on the comparative analysis results, and to obtain the change information of the internal data of the FPGA through the embedded logic analyzer.
[0017] Combining all the above technical solutions, the beneficial effects of the present invention are as follows: the multi-channel data acquisition verification system developed by the present invention can effectively detect the data accuracy of the analog unit by synchronous sampling and data comparison with the signal acquisition unit, and realize the performance verification of the signal acquisition unit, which has a high value of engineering test data source. After the development of each module of the system is completed, each sub-module needs to be debugged and verified to meet the functional requirements of the system. The modular function design and implementation of the present invention are as follows: Figure 2 The FPGA development process shown in the figure is carried out, and the code design is completed in the development environment of Vivado 2016.4. The tool used for behavioral level simulation is Modelsim, a tool promoted by Model Company. Compared with other simulation tools, Modelsim has fast simulation speed and high simulation accuracy. In the board-level debugging stage, the FPGA embedded logic analyzer Debug ila IP core is used. The Bitstream after comprehensive implementation needs to be burned into the FPGA through the jtag download method, so as to detect the operating status of each signal and register inside the FPGA. The embedded logic analyzer is used to detect the changes in internal data to improve the development efficiency and reduce the development cost and cycle. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure; Figure 1 is a flow chart of a data acquisition system verification and analysis method provided by an embodiment of the present invention; Figure 2 It is a principle diagram of a data acquisition system verification and analysis method provided by an embodiment of the present invention; Figure 3 It is a method flow chart of overall verification and integration of the data acquisition system verification and analysis method provided by an embodiment of the present invention; Figure 4 A framework diagram of the entire project in which a test script is written for the present invention to test the functional files of the entire project; Figure 5 This is a schematic diagram of the receiving end test solution of the present invention; Figure 6 The test script data source is written for the present invention to perform cyclic transmission effect diagram according to the framing order of the Gigabit Ethernet transmitting end data; Figure 7 For the present invention, a diagram data generation module diagram is written inside the FPGA; Figure 8 This is a schematic diagram of the verification scheme of the present invention; Fig. 9This is a rendering of the 24-bit RGB pixel information sent by the test board and converted by the HDMI receiving end. DETAILED DESCRIPTION
[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific implementation disclosed below.
[0020] Embodiment 1, the data acquisition system verification and analysis method provided by the embodiment of the present invention includes: S1, use the simulation software Modelsim and FPGA embedded logic analyzer to simulate, verify and debug each sub-module of the system; S2, after the simulation and debugging are passed, the test environment is built using the laboratory hardware board through the overall system verification and integration method to verify the entire process of data collection, caching and transmission, and compare and analyze the data processing results; S3, based on the comparative analysis results, obtain the operating status of each signal and register inside the FPGA, and obtain the change information of the internal data of the FPGA through the embedded logic analyzer.
[0021] For example, Figure 2 This is the principle of the data acquisition system verification and analysis method provided by the embodiment of the present invention.
[0022] Example 2, as another embodiment of the present invention, Figure 3 As shown, the method for overall system verification and integration in the data acquisition system verification and analysis method provided by the embodiment of the present invention includes: The first step is to write the testbensh file to stimulate the top layer of the DDR3 SDRAM cache controller, and test the running status of each signal of the DDR3 SDRAM controller in the Modelsim software. After the test is correct, write the Verilog HDL code for the serial port RX and TX ends, load it into the entire DDR3 SDRAM controller project, and continuously send 1024 8-bit data through the serial port host software to detect whether the host computer receives the same 1024 8-bit data as the sending end.
[0023] In addition, based on the implemented DDR3 SDRAM read / write controller, a test script is written to test the functional files of the entire project. The framework of the entire project is as follows Figure 4As shown in the figure, the dotted line represents the entire project file, testbensh represents the written test script, Wr_req and Rd_req are used as the input signals of the top module, and the simulation is performed through the Modelsim software to verify the correctness of the entire project file. The input stimulus signal required by the top module is generated in the written test script, and the top module is instantiated into the test script, and Modelsim is run for simulation detection.
[0024] In the second step, write testbensh to apply stimulus to the top layer of the Gigabit Ethernet receiver, and detect the operating status of each signal of the Gigabit Ethernet receiver controller in the Modelsim software. After the test is correct, connect the board to the PC through a network cable, and use the embedded logic analyzer Debug ila in Vivado 2016.4 (code design software) to detect whether the FPGA can receive the garbage packets sent by the PC.
[0025] In addition, based on the already implemented Gigabit Ethernet receiver controller, the receiver and transmitter are verified by writing test scripts for simulation or using the internal logic analyzer for debugging.
[0026] For the receiving end test solution Figure 5 As shown, since the Ethernet receiving end is a dual-edge sampling design of the RGMII interface, after completing the test data source module, the ODDR module should also be written to convert the single-edge 8-bit data sampling into dual-edge 4-bit data sampling, so as to simulate the RGMII interface between the PHY chip and the FPGA. In this process, the clock and reset signals of the test data source module are provided by the module under test.
[0027] The third step is to write testbensh according to the data framing sequence of the Gigabit Ethernet transmitter framing module to apply stimulus to the top layer of the Gigabit Ethernet transmitter, and use the Modelsim software to detect whether the Gigabit Ethernet transmitter controller sends according to the framing sequence. After the test is correct, write the cyclic data stimulus testbensh and use Modelsim to detect whether the packet header and data can be sent cyclically.
[0028] When the receiving end establishes a normal connection function, the sending end also needs to write a test script for testing. The data source of the written test script needs to be sent cyclically according to the framing order of the Gigabit Ethernet sending end data, such as Figure 6 As shown, the transmitting end functional module can receive the data in the framing order sent by the test data source, such as the preamble, MAC address, packet type, and other data packet information.
[0029] When the test script data source cyclically sends multiple packets of data according to the Gigabit Ethernet transmitter data framing order, a data flag of 8'h00 is added before each packet of data. The transmitter receives the flag 8'h00 and the data normally, and the enable signal is also pulled low or high normally. Therefore, the transmitter function verification is passed.
[0030] The fourth step is to use Verilog HDL inside the FPGA to generate a gray image information data source, connect the image data source to the HDMI transmitter, and use the embedded logic analyzer Debug ila in Vivado 2016.4 to detect whether the status of each RGB signal at the FPGA HDMI transmitter is R=G=B.
[0031] In addition, based on the already implemented HDMI transmitter controller, such as Figure 7 As shown in the figure, a picture data generation module is written inside the FPGA. The main function of the picture data generation module is to generate information of a gray image. The continuous 24-bit picture information is converted into RGB three-way pixel information after passing through the VGA control module. In order to maintain the balance of DC, the 8-bit pixel is converted into 10-bit pixel data. The status of the three signals r_10bit, g_10bit and b_10bit are captured through the embedded logic analyzer Debug ila inside the FPGA.
[0032] The fifth step is to introduce the test board and use Verilog HDL inside the test board FPGA to generate a gray image information data source. The image data source is connected to the test board HDMI transmitter controller, and then connected to the HDMI receiver interface controller of the motherboard to be tested through the HDMI transmitter port. The embedded logic analyzer Debug ila inside Vivado 2016.4 is used to detect whether the status of each RGB signal at the FPGA HDMI receiver is R=G=B.
[0033] In addition, based on the already implemented HDMI transmitter controller, the verification scheme is as follows Figure 8 As shown, the verified HDMI transmitter module, vga_data_gen and vga control module are transplanted into the FPGA of the test board, and the HDMI receiver module to be verified is transplanted into the FPGA of the main board. The embedded logic analyzer Debug ila inside the FPGA is used to detect the R, G, and B pixel information converted by the HDMI receiver.
[0034] like Fig. 9 It is shown that the 24-bit RGB pixel information sent by the test board and then converted by the HDMI receiving end can be received normally, and R=G=B, that is, the gray picture information sent by the test, which has been verified to be correct by the test.
[0035] In the sixth step, a monocular camera is introduced and connected to the DVP interface. The video information is collected through host computer detection in combination with the tested DDR3 SDRAM controller and Gigabit Ethernet transmitter controller.
[0036] Step 7: Send the network downloaded video through the HDMI host computer, connect the PC to the HDMI receiver, and combine the tested DDR3 SDRAM controller and HDMI transmitter controller to detect whether the host computer receives the original video source data information.
[0037] In the eighth step, a monocular camera is introduced and connected to the DVP interface. The DDR3 SDRAM controller, grayscale conversion, denoising, background overlay preprocessing modules and Gigabit Ethernet transmitter controller that have been tested are combined to detect the collected video information through the host computer and compare and analyze the image processing results.
[0038] In the ninth step, a binocular camera is introduced and connected to the DVP interface, and the image scaling effect is tested in conjunction with the tested DDR3 SDRAM controller, image scaling preprocessing module, HDMI transmitter, and display.
[0039] By executing the above nine steps, the functional testing and verification of each sub-module of the system can be completed.
[0040] Embodiment 2, as a further preferred embodiment of the present invention, in step S3, obtaining the operating status of each signal and register inside the FPGA based on the comparison and analysis results includes: Step 1: When there is a new test data source request, the frame sequence generated by the test data source is converted into an RGB pixel model, that is, the frame sequence is divided into a timing pre-domain T and a bit pixel adjustment domain H; then the frame sequence is forwarded to the conflict attack detection module, and it is determined whether the frame sequence of the new test data source itself belongs to the test data source type that generates a conflict attack. If so, step 2 is executed, otherwise step 3 is executed; Step 2: Take out an undetected frame sequence from the new test data source, and take out an undetected frame sequence from the existing frame sequence of the test data source in the network to proceed to step 4. If all frame sequences have been detected, proceed to step 3. Step 3: Take out an undetected frame sequence from the new test data source, and take out an undetected frame sequence from other deployed test data sources to execute step 4. If all frame sequences have been detected, execute step 8. Step 4: record the two frame sequence timing pre-orders as Tn and To, the bit pixel adjustment domains as Hn and Ho, and the priorities as Un and Uo; then separate the timing pre-orders and generate four new frame sequences E1, E2, E3, and E4. The timing pre-orders of these four frame sequences are T1=Tn-To, T2=To-Tn, T3=To∩Tn, and T4=Tn∩To; the bit pixel adjustment domains are H1=Hn, H2=Ho, H3=Ho, and H4=Hn; Step 5: Check the content after spatial separation. If T3 and T4 are not empty sets and the actions corresponding to H3 and H4 are different, it is determined to be a conflicting attack and step 7 is executed; otherwise, it is determined to be no conflicting attack and step 6 is executed; Step 6: Determine whether this step is jumped from step 2. If yes, return to step 2; otherwise, return to step 3. Step 7, eliminating the frame sequence that resists the attack; Step eight, configure the frame sequence that does not conflict with the attack into the network to deploy a new test data source.
[0041] After completing the separation of the space in step 4, execute step 5; wherein Tn-To represents the remaining space after removing To from space Tn, To-Tn represents the remaining space after removing Tn from space To, To∩Tn represents the part where To and Tn spaces intersect, and Tn∩To represents the part where Tn and To spaces intersect; The step seven comprises: The first step is to determine the priority of the test data source corresponding to the two frame sequences. The priority is divided according to the test data source type: security test data source, general test data source. The security test data source has the highest priority. The general test data source is divided into two categories: one is related to the register, and the other is not related to the register. The test data source not related to the register generally belongs to the configuration test data source in the network, and is given a higher priority than the test data source related to the register; if the test data source types are the same, the priority is set according to the specific type of the test data source; The second step is to eliminate the conflicting attack frame sequence with a low priority. If Un>Uo, eliminate the frame sequence E3, otherwise eliminate the frame sequence E4. The frame sequence conflict attack elimination is completed, and return to step six.
[0042] The present invention provides a method for detecting and eliminating frame order conflict attacks between multiple test data sources in a software-defined network, which models frame order conflict attacks between multiple test data sources in a software-defined network, and then detects and eliminates frame order conflict attacks; it can be used for monitoring and managing upper-layer test data sources in a software-defined network. The controller implemented in the present invention adopts a simple optimal strategy, that is, from all strategies in the buffer pool, selects the strategy with the highest priority marked as valid strategy; during platform verification, the present invention also simply detects the frame sequence of the FPGA firewall test data source to verify the correctness and feasibility of the solution.
[0043] The present invention has good versatility and models the frame sequence of the test data source. It can detect frame sequence conflict attacks in the flow table in the switch, frame sequence conflict attacks in the firewall test data source, frame sequence conflict attacks between the firewall test data source frame sequence and the switch flow table, and frame sequence conflict attacks between other test data sources. The present invention is easy to implement and does not adopt complex algorithms. The existing software-defined network controller software can directly add new functional modules, that is, the conflict attack detection and elimination module can be added to the control module, so as to detect the test data source in the network in real time and ensure the normal function of the network.
[0044] Embodiment 3, the present invention provides a data acquisition system verification and analysis system, the system comprising: Sub-module simulation verification and debugging module, used to simulate, verify and debug each sub-module of the system using simulation software Modelsim and FPGA embedded logic analyzer; The system overall verification and integration module is used to verify the entire process of data acquisition, caching and transmission through the system overall verification and integration method after simulation and debugging, and to compare and analyze the data processing results by using the laboratory hardware board to build a test environment; The data operation status and change acquisition module is used to obtain the operation status of each signal and register inside the FPGA based on the comparative analysis results, and to obtain the change information of the internal data of the FPGA through the embedded logic analyzer.
[0045] After the data acquisition system completes the FPGA digital logic circuit design of all modules, the designed logic circuit needs to be debugged, verified and integrated. The present invention uses the simulation software Modelsim and the FPGA embedded logic analyzer to simulate, verify and debug each submodule of the system. After the simulation and debugging are passed, a method for overall system verification and integration is proposed, and a test environment is built using laboratory hardware boards to verify the entire process of data acquisition, caching and transmission, and the data processing results are compared and analyzed. This verification method can detect the operating status of each signal and register inside the FPGA, and detect the changes in internal data by means of an embedded logic analyzer, which improves development efficiency and reduces development costs and cycles.
[0046] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered within the protection scope of the present invention.
Claims
1. A data acquisition system verification and analysis method, characterized in that: The method includes: S1, using the simulation software Modelsim and FPGA embedded logic analyzer, simulate and verify and debug each sub-module of the system; S2, after the simulation and debugging are passed, the test environment is built using the laboratory hardware board through the overall system verification and integration method to verify the entire process of data collection, caching and transmission, and compare and analyze the data processing results; S3, based on the comparative analysis results, obtain the operating status of each signal and register inside the FPGA, and obtain the change information of the internal data of the FPGA through the embedded logic analyzer.
2. The data acquisition system verification and analysis method according to claim 1, characterized in that: In step S2, the method for overall system verification and integration includes: The first step is to write the testbensh file, apply stimulus to the top layer of the DDR3 SDRAM cache controller, and test the running status of each signal of the DDR3 SDRAM controller in the Modelsim software. After the test is correct, write the Verilog HDL code of the serial port RX and TX ends, load it into the entire DDR3 SDRAM controller project, and continuously send bit data through the serial port host computer software to analyze whether the host computer receives the same bit data as the sending end; The second step is to write testbensh to apply stimulus to the top layer of the Gigabit Ethernet receiver, and detect the operating status of each signal of the Gigabit Ethernet receiver controller in the Modelsim software. After the test is correct, connect the board to the PC through the network cable, and use the embedded logic analyzer Debug ila in the code design software to analyze the information that the FPGA can receive the garbage packets sent by the PC; The third step is to write testbensh according to the data framing sequence of the Gigabit Ethernet transmitter framing module to apply stimulus to the top layer of the Gigabit Ethernet transmitter, and detect whether the Gigabit Ethernet transmitter controller sends according to the framing sequence in the Modelsim software. After the test is correct, write the cyclic data stimulus testbensh, and use Modelsim to detect whether the packet header and data can be sent cyclically; The fourth step is to use Verilog HDL inside the FPGA to generate a gray image information data source, connect the image data source to the HDMI transmitter, and use the embedded logic analyzer Debug ila in the code design software to detect whether the status of each RGB signal at the FPGA HDMI transmitter is R=G=B; The fifth step is to introduce the test board, use Verilog HDL inside the test board FPGA to generate a gray image information data source, connect the image data source to the test board HDMI transmitter controller, and connect it to the HDMI receiver interface controller of the motherboard to be tested through the HDMI transmitter port, and use the embedded logic analyzer Debug ila inside the code design software to detect whether the status of each RGB signal at the FPGA HDMI receiver is R=G=B; Step 6: Introduce a monocular camera and connect it to the DVP interface. Combine it with the tested DDR3 SDRAM controller and Gigabit Ethernet transmitter controller to collect video information through host computer detection. Step 7: Send the network downloaded video through the HDMI host computer, connect the PC to the HDMI receiver, and combine the tested DDR3 SDRAM controller and HDMI transmitter controller to detect whether the host computer receives the original video source data information; In the eighth step, a monocular camera is introduced and connected to the DVP interface. The DDR3 SDRAM controller, grayscale conversion, denoising, background overlay preprocessing module and Gigabit Ethernet transmitter controller that have been tested are combined to detect the collected video information through the host computer, and the image processing results are compared and analyzed. In the ninth step, a binocular camera is introduced and connected to the DVP interface, and the image scaling effect is tested in conjunction with the tested DDR3 SDRAM controller, image scaling preprocessing module, HDMI transmitter, and display.
3. The data acquisition system verification and analysis method according to claim 2, characterized in that: In the first step, 1024 8-bit data are continuously sent through the serial port host computer software to detect whether the host computer receives the same 1024 8-bit data as the sender; Based on the implemented DDR3 SDRAM read / write controller, write a test script to test the functional files of the entire project; Writing a test script to test the functional files of the entire project specifically includes: testbensh is a test script written in which Wr_req and Rd_req are used as input signals of the top module. It is simulated through the Modelsim software to verify the correctness of the entire project file. The input stimulus signal required by the top module is generated in the written test script, and the top module is instantiated into the test script. Modelsim is run for simulation detection.
4. The data acquisition system verification and analysis method according to claim 2, characterized in that: In the second step, based on the already implemented Gigabit Ethernet receiver controller, the receiver and transmitter are verified by writing test scripts for simulation or using the internal logic analyzer for debugging. During the verification of the receiving end, after completing the test data source module, the ODDR module is also written to convert the single-edge 8-bit data sampling into double-edge 4-bit data sampling, simulating the RGMII interface between the PHY chip and the FPGA; in this process, the clock and reset signals of the test data source module are provided by the module under test.
5. The data acquisition system verification and analysis method according to claim 2, characterized in that: In the third step, when the connection establishment function of the receiving end is normal, a test script is written for the sending end to test at the same time. The data source of the written test script is cyclically sent according to the framing order of the Gigabit Ethernet sending end data, and the sending end function module of the sending end receives the data according to the framing order of the test data source, including the preamble, MAC address, packet type and data packet information; When the test script data source cyclically sends multiple packets of data according to the Gigabit Ethernet transmitter data framing sequence, a data flag of 8'h00 is added before each packet of data. The transmitter normally receives the flag 8'h00 and the data, and the enable signal is normally pulled low or high.
6. The data acquisition system verification and analysis method according to claim 2, characterized in that: In the fourth step, based on the already implemented HDMI transmitter controller, a graphic data generation module is written inside the FPGA. The graphic data generation module is used to generate information of a gray image, convert the continuous 24-bit image information into RGB three-way pixel information after passing through the VGA control module, and convert the 8-bit pixel into 10-bit pixel data. The status of the three signals r_10bit, g_10bit and b_10bit are captured through the embedded logic analyzer Debug ila inside the FPGA.
7. The data acquisition system verification and analysis method according to claim 2, characterized in that: In the fifth step, based on the already implemented HDMI transmitter controller, the verified HDMI transmitter module, vga_data_gen and vga control module are transplanted into the FPGA of the test board, and the HDMI receiver module to be verified is transplanted into the FPGA of the main board. The embedded logic analyzer Debug ila inside the FPGA is used to detect the R, G, and B pixel information converted by the HDMI receiver.
8. The data acquisition system verification and analysis method according to claim 2, characterized in that: In step S3, obtaining the operating status of each signal and register inside the FPGA based on the comparison and analysis results includes: Step 1: When there is a new test data source request, the frame sequence generated by the test data source is converted into an RGB pixel model, that is, the frame sequence is divided into a timing pre-domain T and a bit pixel adjustment domain H; then the frame sequence is forwarded to the conflict attack detection module, and it is determined whether the frame sequence of the new test data source itself belongs to the test data source type that generates a conflict attack. If so, step 2 is executed, otherwise step 3 is executed; Step 2: Take out an undetected frame sequence from the new test data source, and take out an undetected frame sequence from the existing frame sequence of the test data source in the network to proceed to step 4. If all frame sequences have been detected, proceed to step 3. Step 3: Take out an undetected frame sequence from the new test data source, and take out an undetected frame sequence from other deployed test data sources to execute step 4. If all frame sequences have been detected, execute step 8. Step 4: record the two frame sequence timing pre-orders as Tn and To, the bit pixel adjustment domains as Hn and Ho, and the priorities as Un and Uo; then separate the timing pre-orders and generate four new frame sequences E1, E2, E3, and E4. The timing pre-orders of these four frame sequences are T1=Tn-To, T2=To-Tn, T3=To∩Tn, and T4= Tn∩To; the bit pixel adjustment domains are H1=Hn, H2=Ho, H3=Ho, and H4=Hn; Step 5: Check the content after spatial separation. If T3 and T4 are not empty sets and the actions corresponding to H3 and H4 are different, it is determined to be a conflicting attack and step 7 is executed; otherwise, it is determined to be no conflicting attack and step 6 is executed; Step 6: Determine whether this step is jumped from step 2. If yes, return to step 2; otherwise, return to step 3. Step 7, eliminating the frame sequence that resists the attack; Step eight, configure the frame sequence that does not conflict with the attack into the network to deploy a new test data source.
9. The data acquisition system verification and analysis method according to claim 8, characterized in that: In step 4, after completing the separation of the space, execute step 5; wherein Tn-To represents the space remaining after removing To from space Tn, To-Tn represents the space remaining after removing Tn from space To, To∩Tn represents the part where the To and Tn spaces intersect, and Tn∩To represents the part where the Tn and To spaces intersect; In step 7, the frame sequence that resists the attack is eliminated, including: The first step is to determine the priority of the test data source corresponding to the two frame sequences. The priority is divided according to the test data source type: security test data source, general test data source. The security test data source has the highest priority. The general test data source is divided into two categories: one is related to the register, and the other is not related to the register. The test data source not related to the register generally belongs to the configuration test data source in the network, and is given a higher priority than the test data source related to the register. If the test data sources are of the same type, the priority is set according to the specific type of the test data source; The second step is to eliminate the conflicting attack frame sequence with a low priority. If Un>Uo, eliminate the frame sequence E3, otherwise eliminate the frame sequence E4. The frame sequence conflict attack elimination is completed, and return to step six.
10. A data acquisition system verification and analysis system, characterized in that: The system implements the data acquisition system verification and analysis method according to any one of claims 1 to 9, and the system comprises: Sub-module simulation verification and debugging module, used to simulate, verify and debug each sub-module of the system using simulation software Modelsim and FPGA embedded logic analyzer; The system overall verification and integration module is used to verify the entire process of data acquisition, caching and transmission through the system overall verification and integration method after simulation and debugging, and to compare and analyze the data processing results by using the laboratory hardware board to build a test environment; The data operation status and change acquisition module is used to obtain the operation status of each signal and register inside the FPGA based on the comparative analysis results, and to obtain the change information of the internal data of the FPGA through the embedded logic analyzer.